High Power, Low Voltage GaN Converter Design for Hybrid … · 2019. 8. 6. · GaN has huge...

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Johannes Burkard, Jürgen BielaLaboratory for High Power Electronic Systems, ETH Zurich

26.03.2019 1

High Power, Low Voltage GaN Converter Design for Hybrid Distribution Transformer

Johannes Burkard

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High share of distributed generation

Increased controllability necessary

Hybrid transformer = LFT + PE converter PE: dynamic control of V, P, Q,… Fractional conv. rating: high η

26.03.2019Johannes Burkard 2

Introduction

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Performance: GaN vs. Si

Design of GaN half-bridge cell

Measurements results

Electrical / thermal / mechanical integration

Conclusion


Outline

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Prototype specifications Rated power 100kVA VMV, VLV 20kVRMS, 400VRMS Controllability ±10% VLV, P & Q

Converter specifications Rated power 10kVA Conv. topology 2-level VSI back-to-back VSer, ILV 23V, 145ARMS Semiconductor 100V GaN switches DC-link 60V, 2mF (foil caps.) Cooling Free convection


Prototype Specifications

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Modeling of switching losses crucial

Spice model Device model from manufacturer Parasitic inductance approximated from dimensions Antiparallel diodes Separate on/off gate resistances Sweep half-bridge current Iout = -75A …75A


Performance Comparison: Si vs. GaN

𝐿𝐿𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 ≈ µ0µ𝑅𝑅ℎ𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙�𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑤𝑤𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙

= 600pH for GaN

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Different RDS,on & Rth: Direct comparison not reasonable! Holistic system optimization


Performance Comparison: Simulated Switching Energies

VDS 100 V 100 V 100 V

ID 120 A 300 A 48 A

RDS,on 2.3 mΩ 1.5 mΩ 4 mΩ

QRR 287 nC 316 nC 0

VGS -20...20 V -20...20 V -4...6 V

Vth 2.2…3.8 V 2.2…3.8 V 0.8…2.5 V

Heat extraction Case/tab PCB Die, top side

LS, LD ≈ 5-10 nH ≈ 1-3 nH ≈ 100-200 pH

RthJ-H 1.8 K/W 3.5 K/W 11.3 K/W

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Performance Comparison: Pareto Optimizations

η-ρ pareto optimization for one side of the back-to-back converter Complete 3Φ, 10kVA converter design (filter, heat sink) Semiconductor + inductor losses (HF + LF) Degrees of freedom Type of switch Number of parallel switches Npar = 0…60 Switching frequency fsw = 5…120kHz Inductor current ripple ΔiL = 4…20%

: 15kHz, 6 parallel, 98,9%, 1.1kW/l

: 25kHz, 5 parallel, 99.2%, 1.5kW/l

: 50kHz, 20 parallel, 99.4%, 2.4kW/l

- 25% losses- 38% volume

How to optimally realize?


Parallelization of GaN Switches

Concepts for paralleling Individual output inductor ( 1 & 2 ) Transient current sharing uncritical Mechanically complex

Common output inductor for Ncell switches ( 3 & 4 ) Requires synchr. swichting common gate driver 4


Supply High-Side Gate Drive

Half-bridge: bootstrap convenient

GaN: high gate leakage current Discharges CBS

AC application: Low duty-cycles inevitable

Example: 4 x half-bridge EPC2032 with driver LMG1205 CBS to limit vBS > 4V (+15% cond. losses!) Int. bootstrap diode CBS ≥ 680µF Ext. bootstrap diode CBS ≥ 188µF Isol. supply CBS = 1µF, vBS = 4.65V ( +DC/DC conv.)

IG,leak (typ.) 1nA 10nA 1mA


Parallelization of GaN Switches

Oscillation of parallel switches Differences in LCSI, LG, LD & Vth Inhomogenous transient current distribution Small CGS & large transconductance Prone to oscillation

Miller turn-on During dv/dt event: iDG partially charges vGS Effective internal driver pull-down Ncell· Rint Prone to Miller turn-on


Realised Cell Design

Star-shaped design based on [1] 4 x half-bridge EPC2032, LMG1205 driver Separate output inductor per cell Paralleling of cells 70ARMS, 100Apeak Isolated high-side supply 6 layer PCB, filled & capped vias

4x EPC2001 in parallel, 35ARMS

[1] EPC - Efficient Power Conversion, Development Board EPC9013 - Quick Start Guide.


Realised Cell Design

Star-shaped design based on [1] 4 x half-bridge EPC2032, LMG1205 driver Separate output inductor per cell Paralleling of cells 70ARMS, 100Apeak Isolated high-side supply 6 layer PCB, filled & capped vias High currents: Two layers VDC+ and VDC- Minimize coupling to Vsw: Cut-outs Gate/power loops close on adjacent layers


Measurement Setup

Half-bridge cell in buck operation VDC = 60 V, Iout = 0…100A, pulsed operation Optically isol. high-side measurement, BW: 500 MHz Minimize measurement loop inductance! Two different designs 1 : Basic design 2 : Bipolar gate voltages, reduced LG, LCSI

Vary RG,on, RG,off, T

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Measurement Results

Oscillation of parallel switches Occur during turn-on of high-side switch Increase for increasing Iout Opposed vgs osc. of parallel switches Circulating iD,circ Increase RG,off to dampen iG,cric Alternative: Diodes in gate path



Measurement Results

Temperature dependency of the oscillation Increasing temperature Less oscillation Theory: Decreasing transconductance Lower positive feedback


Measurement Results

Miller turn-on Minimize RG,off for low-impedance turn-off path Increase RG,on for lower dv/dt Bipolar gate voltages advisable: Design 2

In contrary to damping of oscillations!

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GaN Cell Design Guidelines

Recommendation Symmetrical layout (LCSI!) Minimal RG,off avoiding oscillations Minimal RG,on avoiding Miller turn-on Alternatively: diodes in gate path Bipolar gate voltages Good thermal coupling of parallel switches (Vth(T)!) Isol. supply for high-side gate drive

Realized cells Design 1 : RG,off = 1 Ω, RG,on = 60 Ω Design 2 : vGS = -1 V / 4 V, RG,off = 1 Ω, RG,on = 20 Ω



Integrating Half-Bridge Cell into Converter

Electrical integration Symmetrical placement inductor connector Multiple PCB layers for low conduction losses

Thermal integration Gap pad as thin as possible Equalize tolerances Recesses in heat sink

Mechanical integration Avoid tilt of switches Homogenous pressure distribution Metal plate & spacers Decouple mechanical loading from stiff inductor connectors


Conclusion

GaN has huge potential: - 25% losses, - 38% volume compared to Si (HSOF)

GaN is especially beneficial for hard-switched low voltage applications

High output currents: Parallelization inevitable

Main challenges Parallelization (PCB layout & gate drive) Integration

To fully exploit potential: integrated FET & driver and higher current ratings

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ETH ZurichJohannes BurkardLaboratory for High Power Electronic Systems (HPE)Physikstrasse 38092 Zurich

+41 44 632 75 [email protected]


Contact Information

mailto:[email protected]

High Power, Low Voltage GaN Converter Design for Hybrid Distribution TransformerIntroductionOutlinePrototype SpecificationsPerformance Comparison: Si vs. GaNPerformance Comparison: Simulated Switching EnergiesPerformance Comparison: Pareto OptimizationsParallelization of GaN SwitchesSupply High-Side Gate DriveSupply High-Side Gate DriveSupply High-Side Gate DriveSupply High-Side Gate DriveParallelization of GaN SwitchesRealised Cell DesignRealised Cell DesignMeasurement SetupMeasurement ResultsMeasurement ResultsMeasurement ResultsMeasurement ResultsMeasurement ResultsGaN Cell Design GuidelinesIntegrating Half-Bridge Cell into ConverterIntegrating Half-Bridge Cell into ConverterIntegrating Half-Bridge Cell into ConverterConclusionContact Information

High Power, Low Voltage GaN Converter Design for Hybrid … · 2019. 8. 6. · GaN has huge...

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