High Performance ADCs for 5G · Wu, ISSCC 2016 4 GS/s 56dB SNDR 300mW Case study: Industry...

High Performance ADCs for 5G

Benjamin Hershberg

imec, Leuven, Belgium

5G NR FR2:ADC REQUIREMENTS

Benjamin Hershberg High Performance ADCs for 5G 2 of 60

5G Bandwidth Specs

◼ Channel: 50MHz, 100MHz, 200MHz, 400MHz

◼ Max. Aggregation: 800MHz

◼ Widest Band: 3.25GHz (24.25GHz – 27.50GHz)

◼ Agg. 28GHz Bands: 5.25GHz (24.25GHz – 29.50GHz)

...and need >1.5x more bandwidth to relax anti-alias filter.

5G Modulation Specs

◼ QPSK, 16 QAM, 64 QAM, 256 QAM

◼ Future: 1024 QAM

5G NR FR2: 3GPP specs


[3GPP, 2019]

Translation into ADC specs depends heavily on system-level choices

◼ Receiver chain SNR budget

◼ % of standard supported

Let’s see what we can do across the large range of likely 5G ADC specs:

◼ Resolution: 7 – 13 bits

◼ Speed: 400 MS/s – 12 GS/s

◼ Linearity: 65 dB – 85 dB SFDR

(needs to cover Mobile-Terminal, Base-Station, etc...)

5G NR FR2: ADC specs


CH

AN

NEL

AG

G.

CH

AN

NEL

BAN

D

5G NR FR2: ADC SoTA


[Murmann, 2019]

Linearity SoTA


[Murmann, 2019]CH

AN

NEL

AG

G.

CH

AN

NEL

BAN

D

SFDR/THD specs can be harder than SNR specs!

◼ Noise power gets spread across large bandwidth

◼ Distortion power remains concentrated at specific frequencies

Linearity considerations


dB

fS1/2

dB

fS2/2

dB

freqfS1/2 fS2/2

Continuous-time input spectrum:

Low speed ADC after sampling:

High speed ADC after sampling:

Beamforming requires many ADCs

◼ Power efficiency

◼ Area efficiency

Reconfigurability

◼ Large variation in required performance depending on mode (e.g. 50MHz vs. 800MHz BW)

More considerations


Vaz

ISSCC

2017

Devarajan

ISSCC

2017

Straayer

ISSCC

2016

Wu

ISSCC

2016

Ali

VLSI 2016

Architecture Pipe-SAR Pipeline Pipeline Pipeline Pipeline

Sampling rate [Gsps] 4 10 4 4 5

Technology [nm] 16 28 65 16 28

ENOB Nyquist [bit] 9.2 8.8 8.9 9.0 9.3

SFDR Nyquist [dB] 67.0 64 64.0 68.0 70

Power [mW] 513 2900 2214 300 2300

FoMWalden [fJ/c.step] 214 631 1130 145 709

FoMSchreier [dB] 153 147 145 154 148

Area [mm²] 1.04 20.2 11.0 0.34 14.4

Industry SoTA

500mW 4GS/s ADC in 0.5mm2

x 128 element digital beam-forming= 64 Watts= 64 mm2

An industrial solution today:

Case Study: MIMO Transceiver


[Jann ISSCC 2019]

◼ First fully-integrated 5G TRX

Modest ADC specs

◼ 400 MS/s

◼ 7.7 ENOB

◼ ...but ADC is still biggest slice of RX power!

Many ADCs

High speed (400MS/s - 12GS/s)

Medium resolution (7 - 13b)

High linearity (65dB - 85dB)

Low power

Low area

Conclusions: 5G NR FR2 requirements


Industry SoTA can meet these specs...

...but not necessarily with acceptable power / area.

☺

GETTING TO GIGA-SAMPLE SPEEDS


Two possible strategies:

1. Fast single-channel

Practical technology speed limits

Many clocking overheads don’t scale w/ clock

Limited architecture choices

Giga-samples: how do we get there?


2 GS/sVIN

Two possible strategies:

1. Fast single-channel

Practical technology speed limits

Many clocking overheads don’t scale w/ clock

Limited architecture choices

2. Interleave several slower channels

Interleave errors (spurs)

Easy to correct: Offset, Gain

Hard to correct: Skew, Bandwidth

Larger input load to drive

Larger area



2 GS/sVIN100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/s

100 MS/sVIN

Combine both strategies

◼ First: maximize channel speed

◼ Then: interleave as necessary



2 GS/sVIN1 GS/s

1 GS/sVIN

Core mission statement:

Maximize per-channel speed!

Pipelining

◼ Appears in all medium/high resolution giga-sample ADCs

◼ Break task into smaller pieces

◼ Pass incomplete result along for more processing

Minimize # of operations in critical timing path

◼ Sample

◼ Quantize

◼ Amplify

Pipelining


Stage 2Stage 1 Stage 3 Stage 4 Backend

3 3 3 3 4

VIN

Time Alignment & Digital Error Correction12

DOUT

3b flash sub-ADC

3

T/H Σ x4

3b sub-DAC

VIN VRES

DOUT

Example 3b/stage Pipelined ADC

• 2b/stage of quantization• 1b/stage of redundancy (error correction)

Case study: Deep Pipeline


1.5b/stage Flash ADC Quantizer

☺ Fast! Minimum set of actions per stage

Many stages / residue amplifiers

[Wu, ISSCC 2016]

System 4 GS/s

Channel 1 GS/s

SNDR 56 dB

SFDR 68 dB

Power 300 mW

FoMW 146 fJ/cs

Case study: Pipelined SAR


SAR as a sub-ADC

☺ Fewer stages / amplifiers

☺ Power efficient sub-ADC

Slower channel speed

[Vaz, ISSCC 2017]

System 4 GS/s

Channel 500 MS/s

SNDR 57 dB

SFDR 67 dB

Power 513 mW

FoMW 214 fJ/cs

16nm

Area = 1mm2

Fast frontend, slower backend

☺ Fast frontend minimizes interleave factor

☺ Interleaved SARs improve backend efficiency

Frontend amplifiers still power-hungry

Case study: Hybrid Pipeline


[Brandolini, JSSC 2015]

System 5 GS/s

Channel 2.5 GS/s

SNDR 52 dB

SFDR 58 dB

Power 150 mW

FoMW 96 fJ/cs

AMPLIFICATION: THE HIDDEN BOTTLENECK


Pipelining requires passing along analog residues

To go high speed, you need good amplifiers!

Amplification


Stage 2Stage 1 Stage 3 Stage 4 Backend

3 3 3 3 4

VIN

Time Alignment & Digital Error Correction12

DOUT

3b flash sub-ADC

3

T/H Σ x4

3b sub-DAC

VIN VRES

DOUT

Class-A opamps in nanoscale CMOS

Not enough voltage headroom

Poor efficiency / technology scaling

Requires a special high-voltage supply

Eliminates all hope of high efficiency

But lacking better options, this is still what many in industry use...

Case study: Industry Gigasample ADCs


[Ali, JSSC 2014]

2.5V

Wu, VLSI 2013

◼ 5.4GS/s

◼ 52dB SNDR

◼ 500mW

Brandolini, JSSC 2015

◼ 5GS/s

◼ 52dB SNDR

◼ 150mW

Wu, ISSCC 2016

◼ 4 GS/s

◼ 56dB SNDR

◼ 300mW



• All 3 ADCs use the same residue amplifier on 1.8V

• Core circuits on 1.4V/0.4V

[Wu, VLSI 2013]

Fs 5.4 GS/s

SNDR 52 dB

Power 500 mW


Fs 5 GS/s

SNDR 52 dB

Power 150 mW

[Wu, ISSCC 2016]

Fs 4 GS/s

SNDR 56 dB

Power 300 mW

Wu, VLSI 2013

◼ 5.4GS/s

◼ 52dB SNDR

◼ 500mW

Wu, ISSCC 2016

◼ 4 GS/s

◼ 56dB SNDR

◼ 300mW

Brandolini, JSSC 2015

◼ 5GS/s

◼ 52dB SNDR

◼ 150mW



8 high-performance amps

2 high-performance amps

2 high-performance amps14 low-performance amps

[Wu, VLSI 2013]

Fs 5.4 GS/s

SNDR 52 dB

Power 500 mW


Fs 5 GS/s

SNDR 52 dB

Power 150 mW

[Wu, ISSCC 2016]

Fs 4 GS/s

SNDR 56 dB

Power 300 mW

Amplification: The Hidden Bottleneck


Architectural Freedom

Calibration Complexity

Power Efficiency

Linearity

Performance

Input Swing

High Voltage Supply

Amplifier Bottleneck

Architectural Freedom

Output Swing

Class-A opamps will never be good in scaled CMOS

◼ Severely constrains ADC design freedoms

◼ 2010’s were the era of the (amplifier-less) SAR ADC

A new approach is needed!

Conclusions: Amplifier Bottleneck


EMERGING AMPLIFICATION SOLUTIONS


Open loop

Gm-C integrator

Gm-R amplifier

◼ Charge-pump based

Feedback

Ring amplifier

◼ Zero-crossing based circuit

◼ Charge-steering amplifier

◼ Digital amplifier

Emerging Amplification Solutions


Found in state-of-the-art Gigasample ADCs

Amplifier Wishlist


Basic idea: Integrate current GmVRES onto load capacitor

☺ Fast (open-loop)

☺ Fully dynamic (switchable)

☺ Inherent filtering (sinc)

☺ Good efficiency

Poor linearity

Small input swing

Small output swing

Sensitive to jitter

Sensitive to PVT

Gm-C integrator


GmVRES

ΦA

VRES

ΦR

VOUT

CLGm

ΦA

tR tA

VO

UT

time

Gm · taCL

AV =

Case Study: Gm-C Integrator


Channel:

Gm-C:

[Vaz, ISSCC 2017]

System 4 GS/s

Channel 500 MS/s

SNDR 57 dB

SFDR 67 dB

Power 513 mW

FoMW 214 fJ/cs

Tunable integration time:

Gm-R amplifier


Basic idea: RC settle voltage GmVRESRL across load capacitor

☺ Even faster! (no pre-clearing)


☺ Good efficiency

Moderate PVT sensitivity

Poor linearity

Small input swing

Small output swing

tA

VO

UT

time

GmVRESVRES VOUT

CLGm

ΦA

RL

AV = Gm · RL

Case study: Gm-R Amplifier


[Jiang, ISSCC 2019]

System 1 GS/s

Channel 1 GS/s

SNDR 60 dB

SFDR 75 dB

Power 8 mW

FoMW 9 fJ/cs

Current SoTA for single-channel gigasample ADCs

CLOAD

OUTmINp

feedback

VDZ

Ring Amplifier


Basic idea: Start in a high efficiency but unstable state and then dynamically stabilize with large-signal feedback

[Hershberg, JSSC 2012]

☺ High efficiency

☺ High speed

☺ Wide output swing

☺ Excellent linearity

☺ Scales with digital


Moderate PVT sensitivity [Lagos, JSSC 2019]

[Lim, JSSC 2015 (1)]

Ring Amplifier


CLOAD

OUTmINp

feedback

VDZ

p1

p2

p3

p2

Transient, large signal paradigm

The AC view

◼ Make p1 & p2 as fast as possible

Ring Amplifier


CLOAD

OUTmINp

feedback

VDZ

p1

p2

p3

p2


The AC view


◼ Dynamically reduce p3

Ring Amplifier


CLOAD

OUTmINp

feedback

VDZ

p1

p2

p3

p2


The AC view


◼ Dynamically reduce p3

◼ ring oscillator → ring amplifier

Ring Amplifier


CLOAD

OUTmINp

feedback

VDZp3

VOV

VOV


The DC / transient view

◼ VOV initially maximum

Slew-rate at theoretical max. ☺

Ring Amplifier



The DC / transient view

◼ VOV initially maximum

Slew-rate at theoretical max. ☺

◼ VOV dynamically reduced to adjust P3

Reduces VDSAT → swing/linearity ☺

Increases ro → gain/linearity ☺

Reduces gm → noise filtering ☺

CLOAD

OUTmINp

feedback

VDZp3

VOV

VOV

[Hershberg, ISSCC 2019 (1)]

System 3.2 GS/s

Channel 800 MS/s

SNDR 63 dB

SFDR 80 dB

Power 61.3 mW

FoMW 19 fJ/cs

Case study: Ring Amplifier


VDD

DZP

EN

DZN

VSS

EN_i

EN_i

EN

EN

OUTm

INp

VDD

DZP

EN

DZN

VSS

EN_i

EN_i

EN

EN

OUTp

INm

EN

VDDEN

Vs2p2

Vs2m2

Vs2p1

Vs2m1

VDD

VSS

MCM2

OUTp

B1

CFB

CSMALLCBIG

ENCSENSE

EN_i

EN_iEN_i

Trapped Charge CMFB

Dz_nmos[7:0]7

VDD DZN

EN

Dz_pmos[7:0]7

VSS DZP

EN

Trapped-Charge Bias Control

CFBOUTm

CSENSE

MCM1

Order-of-magnitude improvement in SoTA

36 ringamps in system

◼ Bottleneck solved?

Option 1: Design with extra margin

☺ Calibration free

Requires some sacrifice in speed

Still can achieve SoTA performance

◼ 3 stage ringamp [Lim, JSSC 2015 (2)]

◼ 4 stage ringamp [Lim, VLSI 2017]

Ringamp Robustness Techniques


[Lim, JSSC 2015]

Option 2: Use background tracking or calibration techniques

☺ Optimum performance

Extra analog/digital complexity

Ringamp Robustness Techniques


AOL

β

+IN OUTX+ -

+‒

v/σ

PIP

ELINE

B

ACK

END

“bin” 1

“bin” N

estimator equations

𝐷 𝑉𝑥

𝐷 𝑉𝑥 𝐷 𝑉𝑜𝑢𝑡

bias control

VCM

v/σ factor estimation

1σ = 0.3 mV

𝑆𝐷𝑅

mean erfinv x

mean erfinv x

mean erfinv x

mean erfinv x

cal ADC

mux

demux

𝐴 𝑂𝐿

𝑆𝐷𝑅 𝑉𝑂𝑈𝑇 ,𝑉𝑋

𝐴𝑂𝐿 𝑉𝑂𝑈𝑇 ,𝑉𝑋


Open-loop where it makes sense

◼ E.g. for very fast amplification

Ringamps for everything else

◼ Any input swing, any output swing

◼ Any resolution, any speed

◼ All circuits: ADC, VGA, Filter, PLL, etc.

Conclusion: Emerging Amplification


GmVRESVRES VOUT

CLGm

ΦA

RL

CLOAD

OUTmINp

feedback

VDZ

DESIGNING FORRECONFIGURABILITY


Wide range of channel bandwidths and modulations:

5G Bandwidth Specs

◼ Channel: 50MHz, 100MHz, 200MHz, 400MHz

◼ Max. Aggregation: 800MHz

◼ Widest Band: 3.25GHz (24.25GHz – 27.50GHz)

◼ Agg. 28GHz Bands: 5.25GHz (24.25GHz – 29.50GHz)

5G Modulation Specs

◼ QPSK, 16 QAM, 64 QAM, 256 QAM

◼ Future: 1024 QAM

➔ A reconfigurable multi-standard ADC is a clear advantage

5G NR FR2 specs revisited


Run-time

Speed

◼ Resolution

Design-time

Architecture

ADC Reconfigurability


= most relevant for 5G

Speed Reconfigurability


Motivation: constant power efficiency

2 ingredients required

◼ Event-driven control (clocking)

◼ Fully-dynamic power consumption

Fully-dynamic = no static power

“Next-gen” amplifiers support this

◼ Gm-C

◼ Gm-R

◼ Ringamp

Speed Reconfigurability


Ringamp with power-gating function

[Lagos, JSSC 2019]

Conventional: Synchronous 2-phase non-overlapping clock tree

◼ Simple & effective at lower speeds

◼ But many hidden drawbacks at high speed

With improvements in amplification tech., clocking becomes the new bottleneck

Event-Driven Control: Deep Pipeline


Phase 1 delayed

Phase 2 delayed

Phase 1

Phase 2

cINpSTG1

INm

c

Local Clkgen

STG2

Local Clkgen

STG3

Local Clkgen

STG4

Local Clkgen

STG5

Local Clkgen

STG6

Local Clkgen

BACKEND

Local Clkgen

c

master clock

Global Clkgen

[Lagos, CICC 2017]

Local “Stage Control Units” connected by inter-stage control busses

◼ Communication

◼ Driving local circuits

☺ Correct-by-construction

☺ Minimal global routing

☺ Interleaving advantages

☺ Less sampling jitter

☺ Faster (less timing overhead)




VCM

1.5bsub-ADC

DOUT[1:0]

subRingamp+

-Ringamp+

-

sub-ADC latch

sample REQ sample REQ

1.5bsub-DAC

track N

track early N

flush REQ

stagecontrol

unittrack early N+1 (ACK)track early N (ACK)

flush ACK

stagecontrol

unit

STAGE N+1STAGE N

VCM

STAGE N-1

amplify N

sub-ADC latch

flush ACKcINp STG1

1.5b

CU=64fF

STG21.5b

CU=32fF

c

master clock

BACKEND1.5b + 3b

CU=32fF

STG31.5b

CU=32fF

STG41.5b

CU=32fF

STG51.5b

CU=32fF

STG61.5b

CU=32fF

STG71.5b

CU=32fF

INm

c

Internal “chain-reaction” of processing is independent of external clock rate

◼ 1MS/s same as 1GS/s

☺ Enables fully-dynamic operation

☺ Auto maximizes track time

☺ Removes many leakage issues




trackquantize

amplify track

trackquantize

amplify track

. . . .

. . . .

trackquantize

amplify

Conventional

clkmax

clkmax / 2

trackquantize

amplify track

trackquantize

amplify track

. . . .

. . . .

trackquantize

amplifyclkmax

clkmax / 2

Event-driven

Analog data enters Analog data exits

Analog data enters Analog data exits

window expands

constant

☺ More efficient (less power)

☺ Reconfigurable behavior

☺ No limit to # of clocks/phases

Must be careful about deadlocks

Validation effort increased




** Sneak Peek! **

General-purpose solution

◼ Discrete-time comparator-based

[Kull, JSSC 2013]

◼ Can sub-divide into dirty/clean replicas for low-noise and high-accuracy

☺ Low power

☺ General purpose

Still requires some decap area

Fully Dynamic Reference Regulation


c

c

master clock

INm

c

INp

c

VREFP ext. c

VCM ext. c

VREFM ext.

VREFP dirtyVREFP cleanVCMVREFM dirtyVREFM clean

reference regulator

BACKEND1.5b + 3b

CTOT=256fF

STG11.5b

CTOT=256fF

STG21.5b

CTOT=128fF

STG31.5b

CTOT=128fF

STG41.5b

CTOT=128fF

STG51.5b

CTOT=128fF

STG61.5b

CTOT=128fF

STG71.5b

CTOT=128fF

Deep pipeline with dirty/clean reference replicas:

VDD

precharge_i

CP

VSS

precharge

CM

Charge source / sink

CR

VREF_extprecharge

+

replica out

connect

connect_i

Discrete-time regulation circuit:

Design-time circuit re-use

◼ Faster time-to-market

◼ Less manpower

Simple, low resolution stages

◼ Use “cheap” high performance amplifiers

◼ Can simply “chain” together using asynchronous, event-driven control protocols

Architecture Reconfigurability


STG21.5b

CU = 128fF

STG31.5b

CU = 64fF

STG41.5b

CU = 32fF

BACKEND9b

CU = 32fF

Inventory of low-resolution, fully-dynamic building blocks

BACKEND9b

CU = 32fF

9

c

VINSTG31.5b

CU = 64fF

c

clk

2c

STG41.5b

CU = 32fF

2DOUT

13b ADC (x4)for Base-station Applications[Hershberg, ISSCC 2019 (1)]

STG11.5b

CU = 200fF

BACKEND9b

CU = 32fF

9

c

VIN STG21.5b

CU = 128fF

STG31.5b

CU = 64fF

c

clk

2 2 2c

STG11.5b

CU = 200fF

STG41.5b

CU = 32fF

2DOUT

11b ADCfor Mobile-terminal Applications[Hershberg, ISSCC 2019 (2)]

Easily adapted to many resolution &

speed requirements

SUMMARY & CONCLUSION


Final Summary


1 GS/s

1 GS/s

1 GS/s

1 GS/s

1 GS/s

VIN

For best performance at high speeds:

First maximize the per-channel speed...

...then interleave as necessary

Final Summary


1 GS/s

Pipelining can maximize the per-channel speed

BACKEND9b

CU = 32fF

9

c

VIN STG21.5b

CU = 128fF

STG31.5b

CU = 64fF

c

clk

2 2 2c

STG11.5b

CU = 200fF

STG41.5b

CU = 32fF

2DOUT

But it isamplifier intensive!

Luckily, new amplification techniques

are now available

CLOAD

OUTmINp

feedback

VDZ

Ringamp

Final Summary


ADC Reconfigurability

Run-time

Constant energy per conversion for multi-standard use Asynchronous-

event driven timing control

Fully dynamic power use

Design-time

Building block reuse for reduced

design effort

Enablers:

Closing the Gap


Industry SoTA R&D SoTA

Top Level

CH0

CH1

DOUT[N:0]

CH2

CH3

D0[N:0]

D1[N:0]

D2[N:0]

D3[N:0]

CLKIN

controller mux

BU

F

VINBUF

Vaz

ISSCC

2017

Devarajan

ISSCC

2017

Straayer

ISSCC

2016

Wu

ISSCC

2016

Ali

VLSI 2016

Architecture Pipe-SAR Pipeline Pipeline Pipeline Pipeline

Sampling rate [Gsps] 4 10 4 4 5

Technology [nm] 16 28 65 16 28

ENOB Nyquist [bit] 9.2 8.8 8.9 9.0 9.3

SFDR Nyquist [dB] 67.0 64 64.0 68.0 70

Power [mW] 513 2900 2214 300 2300

FoMWalden [fJ/c.step] 214 631 1130 145 709

FoMSchreier [dB] 153 147 145 154 148

Area [mm²] 1.04 20.2 11.0 0.34 14.4

Hershberg

ISSCC

2019

Architecture Pipeline

Sampling rate [Gsps] 3.2

Technology [nm] 16

ENOB Nyquist [bit] 10.0

SFDR Nyquist [dB] 73.3

Power [mW] 61

FoMWalden [fJ/c.step] 19

FoMSchreier [dB] 166

Area [mm²] 0.194

Coming soon, to a product near you...

References (1)


3GPP, 2019 3GPP, “5G NR release 15”, 2019. [Online]. Available: https://www.3gpp.org/release-15

Ali, JSSC 2014A. M. A. Ali et al., "A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration," in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2857-2867, Dec. 2014.

Brandolini, JSSC 2015M. Brandolini et al., "A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2922-2934, Dec. 2015.

Hershberg, ISSCC 2019 (1)B. Hershberg et al., "3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 58-60.

Hershberg, ISSCC 2019 (2)B. Hershberg et al., "3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 68-70.

Hershberg, JSSC 2012B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita and U. Moon, "Ring Amplifiers for Switched Capacitor Circuits," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2928-2942, Dec. 2012.

Jann, ISSCC 2019B. Jann et al., "21.5 A 5G Sub-6GHz Zero-IF and mm-Wave IF Transceiver with MIMO and Carrier Aggregation," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 352-354.

Jiang, ISSCC 2019W. Jiang, Y. Zhu, M. Zhang, C. Chan and R. P. Martins, "3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA,

Kull, JSSC 2013L. Kull et al., "A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec. 2013.

References (2)


Lagos, CICC 2018J. Lagos, B. Hershberg, E. Martens, P. Wambacq and J. Craninckx, "A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, 2018, pp. 1-4.

Lagos, JSSC 2019J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq and J. Craninckx, "A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 54, no. 3, pp. 646-658, March 2019.

Lim, JSSC 2015 (1)Y. Lim and M. P. Flynn, "A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 50, no. 10, pp. 2331-2341, Oct. 2015.

Lim, JSSC 2015 (2)Y. Lim and M. P. Flynn, "A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2901-2911, Dec. 2015.

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