Design and Development of a One Gigasample per Second Radar Data

Acquisition System

By Ryan EakinOctober 29, 2001

System Motivation/Background

Traditional Coherent Radar

Transmitter

Receiver

DirectDigital

Synthesis

DivideByN

Coherent PRF PulseTransmit Blanking

90°PhaseShifter

2 Channel (Low Bandwidth)Data Acquistition System

Coherent PRF Pulse

Sensitivity TimeControl

Coherent PRF PulseReference

Clock

I

Q

Traditional Radar Problems

• Analog components cannot be precisely characterized and are non-ideal– Characteristics change with temperature

• Analog components add:– noise– Harmonics

• All of these result in degraded system performance

Digital RF Radar System

Receiver

Transmitter

ArbitraryWaveformGenerator

Coherent PRF Pulse

Transmit Blanking

2 Channel (High Bandwidth)Data Acquistition System

Coherent PRF Pulse

ReferenceClock

HighGain

LowGain

Blanking

Blanking

Advantages of Digital RF Radar

• All mixers are eliminated from the system• Increased ADC bandwidth eliminates IQ

downconversion– Allows STC to be replaced with 2 fixed gain amps

• Amplifiers/antennas/filters can be compensated for digitally for a more ideal system response

Acquisition System Design

RSL Digital RF System Block Diagram

Universal RadarTiming System

A/D ConvertorCards

Computer

1 GHz Sine Wave Clock

Timing Signals

Timing Signals

2 Channel Outputs

1 GHz Clocks

28 Bit Data Bus

Radar Analog Section

DDS

TX Antenna

RX Antenna

DSP AveragingCards

MUX Card

RS 232 Link

Int Count

Acquisition System Specifications

• 4 8-bit channels• 1 GS/s maximum sampling rate • 2.2 GHz analog bandwidth to allow direct

digitization of RF signals• Input clock 1 GHz sine wave drive• Performs coherent averaging adjustable from 1 to

65,535

A/D Channel Overview

MAX 104ADC

Analog Input

BUSA

BUSB

2-8 BitChannels500 MHz

8:64 Demux

16-8 BitChannels

(62.5 MHz)

62.5 MHz100 MHzPeak

Multiplexer

ADC Card To MUX Card

Timing System

Averaging Card

Acquire Data SignalsADC Sync SignalADC Clock

8:64 Demux

32 bit FIFO 200 MHz DSP 32 bit FIFO

32 bit FIFO 200 MHz DSP 32 bit FIFO

32 bit FIFO 200 MHz DSP 32 bit FIFO

32 bit FIFO 200 MHz DSP 32 bit FIFO

Sync

Sync

100 MHzPeak 20 MHz

Peak 32 Bits

ADC Card Detailed Diagram

MAX 104A/D Converter

Analog Input

BUSA

BUSB

2-8 BitChannels500 MHz

TimingSystem

ADC Sync SignalADC Clock

4:32 Demux

Sync

4:32 Demux

4:32 Demux

4:32 Demux1:4

PECLSplitter

1:4PECL

Splitter

Clock

ToDemux

16-8 BitChannels62.5 MHz

Clock

Data

Clock

Data

Clock

Data

Clock

Data

272 Pin,2mm

Connector

ADC Synchronization for Coherency

ADC Synchronization for Coherency

• Without synchronization, system coherency is lost• Synchronization is made complex because of

pipelined devices• Synchronizing to a 1-GHz clock requires a 400 ps

“window” on the sync pulse

1 GS/s ADC Card

1 GS/s ADC Card

ADC Card PCB Specs

• ADC card• 6 layers using Rogers 4000 RF board material.• High resolution (5 mil line/spacing).• 6 ICs, 150 Resistors, 100 Capacitors.• Thermal Vias.

PCB Tangential Loss

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.05

0.1

0.15

0.2

0.25

Frequency (GHz)

Los

s (d

B)

FR-4 Rogers 4403

Coupled Differential Lines

11 mils 11 mils

8 milsEr = 3.17 Er = 3.17

18 mils8 mils

Coupled-Differential Microstrip Normal Microstrip

18 mils24 mils

ADC Card PCB Stackup

70 mils

Prepreg Rogers 4403, 8 mil, Er=3.17

0.5oz

0.5 oz

0.5 oz

0.5 oz

1.0 oz

1.0 oz

Core Rogers 4003, 20 mil, Er=3.4.

Prepreg Rogers 4403, 8 mil, Er=3.17

Prepreg Rogers 4403, 8 mil, Er=3.17

Core Rogers 4003, 20 mil, Er=3.4

Averaging Card Diagram

16-8 BitChannels

(62.5 MHz)

100 MHzPeak

Multiplexer

To MUX CardAveraging Card

32 bit FIFO 200 MHz DSP 32 bit FIFO

32 bit FIFO 200 MHz DSP 32 bit FIFO

32 bit FIFO 200 MHz DSP 32 bit FIFO

32 bit FIFO 200 MHz DSP 32 bit FIFO

100 MHzPeak 20 MHz

Peak

32 Bits

4 Samples

4 Samples

4 Samples

4 Samples

IntegrationCounter

AcquireControl

AcquireSignal

IntegrationComplete

AcquireSignal

Busy/Don't Acquire

FromADCCard

ToMUXCard

Averaging Card Specifications

• 4 32-bit inputs, multiplexed 32 bit output• Utilizes 200 MHz TI DSPs (1,600 MIPS)• 133 MHz input FIFOs• Designed to process 8,000 samples/channel at 30

kHz PRF (goal not met)• Averages selectable from 1 to 65,535 in

increments of 1

Averaging Card PCB

PCB Specifications

• 6 layer standard FR-4 board.• High resolution (4 mil line width/spacing).

• Created manufacturability issues• 34 ICs, 600 resistors, 328 capacitors.• Components on both sides.

Packaging Technologies

• A key feature of the design is the use of Ball Grid Array (BGA) packaging technology

• Tiny balls of solder attach the bottom of the IC directly to the circuit board

• Increases pin density and performance

BGA Mounting

Averaging Card Design Problem

• Ultra fine pitch (0.8 mm) BGA resulted in the following manufacturing problems:– Required 4/4 mil PCB width/spacing and tiny

vias resulting in low PCB yields– Devices did not solder correctly and board

operation was intermittent.• Wide pitch BGA (1.27 mm) on the ADC card was

easy to design and manufacture

Universal Radar Timing System

• Stand alone radar timing system in 19” enclosure.• Computer or manual control.• Accepts input clock from 100 MHz to 2.3 GHz.

1 GHz SineWave (2.3 GHz

Max)

500

MH

z

250

MH

z

125

MH

z

62.5

MH

z

Mezzanine Card

1 G

Hz

Differential ECL SingleTTL

Main Card

Microcontrollerwith Display/keypad

RS 232 InputFrom

Computer

PRF

PRF ClockECL/TTL

PRF(6 Outputs)

Adjustable Delay/WidthChannels (9 Outputs)

ExternalPRF/SingleShot

Microcontroller Bus

Radar Timing

30 us3 6 9 12 15 18 21 24 270

Transmit

2 to 10 us

200 ns

7 us

7 us

Channel 1 Receive Channel 2 Receive

PRF Variable from 30 to 100 us

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 us

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 us

Timing System Specifications

• Sine wave clock input• 2.3 GHz maximum input frequency• Generates radar PRF signal (1 kHz minimum, 16 ns steps)• Generates 9 adjustable timing “windows”• Outputs divided versions of input clock• Signals edges must be adjustable to a 400 ps window

• Required for ADC sync signal•Accomplished with ECL technology

Mezzanine Card Diagram

Divider1 GHz Sine

1 GHz PECL

500 MHz PECL

ClockInput

ClockFanout

ClockFrequency

Divider

250 MHz PECL

125 MHz PECL

62.5 MHz PECL

250 MHzPECL Output

62.5 MHzTTL

Output

PECL to

TTL

125 MHzPECL

Output

PRFGenerator

Clock To Main Card

1 GHzPECL

Output

DAQ USE ONLY

500 MHzPECL

Output

Single ShotGenerator

Single ShotDebouncedTTL Input

Single Shot/Repetitive

Select

PRF to Main Card

Microntroller Bus

Mezzanine Card

Mezzanine Card (in system)

Mezzanine Card PCB Specifications

• 6 layers using Rogers 3000 RF board material• 22 ICs, 40 Resistors, 100 Capacitors• Measured power consumption: 10W (2A @ 5V)

Main Card Diagram

Fanout Buffer

PulseDelayAdjust

Pulse Width Adjust

PulseDelayAdjust

Pulse Width Adjust

PulseDelayAdjust

Pulse Width Adjust

PulseDelayAdjust

Pulse Width Adjust

PRFOutput(PECL)

PulseDelayAdjust

Pulse Width Adjust

PulseDelayAdjust

Pulse Width Adjust

PulseDelayAdjust

Pulse Width Adjust

ADCSync

Signals

CH2

CH3

CH4

CH1

TransmitBlanking

CH1Receiver Blanking

TransmitAmplifierBlanking

CH2Receiver Blanking

Extra

PRFOutput(TTL)

Flip Flop

FlipFlopped

PRF(TTL)

PulseDelayAdjust

Pulse Width Adjust

PulseDelayAdjust

Pulse Width Adjust

PRFPulseInput

CH2

CH3

CH4

CH1

4AcquisitionChannels

5 RadarChannels

Main Card PCB

Main Card Finished PCB

Main Card PCB Specifications

• 8 layers using standard FR-4 material.• 155 ICs, 224 resistors, 420 capacitors.• Components on both sides.• Blind vias to maximize density• Measured power consumption: 54W (10.7A @ 5V)

Timing System

LCD Front Panel

Multiplexer Card

Multiplexer Card Diagram

DAQ Channel 1

DAQ Channel 2

DAQ Channel 3

DAQ Channel 4

Multiplexer

DIOHandshaking

Control

DIO 20MHzClock

DIO 32-bitConnector

ErrorSummation

LEDInterface

20 MHz ClocksTo DAQ Channels

Clock, Ack, Req Signals

Error Signals FromDAQ Channels

32

32

32

32

32

2

Multiplexer Card Specifications

• Converts 4 32-bit channels into a single 32-bit channel

• Provide handshaking with computer DIO card (NI DIO 32HS)

• Operates at 20 MHz (80 Mbyte/s peak rate)• Consolidates 8 error signals into 2 signals for

computer link

Finished Multiplexer Card

Multiplexer Card PCB Specs

• 4 layer FR-4, 2 signal layers• Board routed using an autorouter

User Interface Software

• Labview used to create acquisition software– Provides graphical programming environment– DIO low level routines pre-written– RS 232 low level routines pre-written

GUI Front Panel

System Performance/Results

ADC Performance

0 500 1000 1500 2000 2500-7

-6

-5

-4

-3

-2

-1

0

1

Frequency (MHz)

AD

C I

nput

Los

s (d

B)

DatasheetMeasured

System Time Domain Output

System Frequency Domain Output

Performance Summary

• ADC analog input was verified to operate over 2.2 Ghz• System capture and record was verified• ADC SFDR was measured to be 63 dB (62-69 dB

datasheet)• System throughput to the drive: 1.3 Mbyte/s• Coherent averaging demonstrated but malfunctioning

average card prevented adequate testing• Timing system operated to 2.3 Ghz• Averaging card maximum PRF is 10 kHz

Project Summary

• 4 of 5 circuit boards work at or above requirements

• Timing system is complete and validated • Averaging card needs additional development

work• Labview software is ~90% complete (pending

average card work)

The End?