EE143 – Ali Javey

Section 12: Intro to Devices

Extensive reading materials on reserve, includingRobert F. Pierret, Semiconductor Device Fundamentals

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Bond Model of Electrons and Holes Silicon crystal in

a two-dimensionalrepresentation.

S i S i S i

S i S i S i

S i S i S i

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

When an electron breaks loose and becomes a conduction electron, a hole is also created.

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Semiconductors, Insulators, and Conductors

• Totally filled bands and totally empty bands do not allow current flow. (Just as there is no motion of liquid in a totally filled or totally empty bottle.)

• Metal conduction band is half-filled.• Semiconductors have lower EG’s than

insulators and can be doped

E c

Ev

Eg =1.1 eV

E c

E g = 9 eV empty

Si, Semiconductor SiO2

, insulator Conductor

E cfilled

Top of conduction band

E v

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-

+ Top of valence band

Bottom of conduction band

electron

hole

Energy gap=1.12 eV

n (electron conc)= p (hole conc) = ni

Intrinsic Carriers

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Dopants in Silicon

Si Si Si

Si Si

Si Si Si

Si Si Si

Si Si

Si Si Si

As B

As, a Group V element, introduces conduction electrons and creates N-type silicon,B, a Group III element, introduces holes and creates P-type silicon,

and is called an acceptor.

and is called a donor.

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Ionized

Donor

IonizedAcceptor

Immobile Chargesthey DO NOTcontribute to current flow with electric field is applied. However, they affect the local electric field

Hole

Electron

Mobile Charge Carriers they contribute to current flow with electric field is applied.

Types of charges in semiconductors

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Fermi Function–The Probability of an Energy State Being Occupied by an Electron

f(E)

0.5 1

Ef

Ef – kT

Ef – 2kT

Ef – 3kT

Ef + kT

EfEf + 2kT

Ef + 3kT

E

kTEE feEf /)(1

1)( Ef is called the Fermi energy or

the Fermi level.

kTEE feEf )( kTEE f

kTEE feEf 1)( kTEE f

Boltzmann approximation:

kTEE feEf )(

kTEE feEf 1)(

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Electron and Hole Concentrations

Remember: the closer Ef moves up to Ec, the larger n is; the closer Ef moves down to Ev , the larger p is.

For Si, Nc = 2.81019cm-3 and Nv = 1.041019 cm-3 .

kTEEc

CFeNn /)(

kTEEv

FVeNp /)(

Nc is called the effectivedensity of states.

Nv is called the effectivedensity of states of the valence band.

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Shifting the Fermi Level

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n: electron concentration (cm-3)

p : hole concentration (cm-3)

ND: donor concentration (cm-3)

NA: acceptor concentration (cm-3)

1) Charge neutrality condition: ND + p = NA + n

2) Law of Mass Action : n p = ni2

Assume completely ionized to form ND

+ and NA

-

Quantitative Relationships

What happens when one doping

species dominates?

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I. (i.e., N-type)

If ,

II. (i.e., P-type)

If ,

ad NNn

nnp i2

iad nNN

ad NN dNn di Nnp 2 and

ida nNN da NNp pnn i

2

da NN aNp ai Nnn 2 and

General Effects of Doping on n and p

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• When an electric field is applied to a semiconductor, mobile carriers will be accelerated by the electrostatic force. This force superimposes on the random thermal motion of carriers:

E.g. Electrons drift in the direction opposite to the E-field

Current flows

Average drift velocity = | v | = ECarrier mobility

12

3

45

electron

E

123

4

5

electron

E =0

Carrier Drift

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• Mobile carriers are always in random thermal motion. If no electric field is applied, the average current in any direction is zero.

• Mobility is reduced by

1) collisions with the vibrating atoms

“phonon scattering”

2) deflection by ionized impurity atoms “Coulombic scattering”

-

Si

-

As+

-B-

-

Carrier Mobility

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1E14 1E15 1E16 1E17 1E18 1E19 1E20

0

200

400

600

800

1000

1200

1400

1600

Holes

Electrons

Mo

bili

ty (

cm2 V

-1 s

-1)

Total Impurity Concenration (atoms cm-3)Na + Nd (cm-3)

impurityphonon

impurityphonon

111

111

Total Mobility

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Jp,drift = qpv = qppE

Jn,drift = –qnv = qnnE

Jdrift = Jn,drift + Jp,drift = E =(qnn+qpp)E

conductivity of a semiconductor is = qnn + qpp

Resistivity, = 1/

Conductivity and Resistivity

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N-type

P-type

= 1/

DOPA

NT D

ENSI

TY c

m-

3

RESISTIVITY

( cm)

Relationship between Resistivity and Dopant Density

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• Rs value for a given conductive layer (e.g. doped Si, metals) in IC or MEMS technology is used– for design and layout of resistors

– for estimating values of parasitic resistance in a device or circuit

W

LR

Wt

LR s

tRs

Rs is the resistance when W = L (in ohms/square)

if is independent of depth x

V

+_

L

tW

I

Material with resistivity

V

+_

L

tW

I

Material with resistivity

V

+_

L

tW

I

Material with resistivity

Sheet Resistance

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Particles diffuse from higher concentration to lower concentration locations.

Diffusion Current

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dx

dnqDJ ndiffusionn ,

dx

dpqDJ pdiffusionp ,

D is called the diffusion constant. Signs explained:

n p

x x

Diffusion Current

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Generation/Recombination Processes

Recombination continues until excess carriers = 0.Time constant of decay is called recombination lifetime

EE143 – Ali Javey

Continuity Equations• Combining all the carrier actions:

• Now, by the definition of current, we know:

• Since a change in carrier concentration must occur from a net current

• Therefore, we can compactly write the continuity equation as:

otherstn

GthermalRtn

difftn

drifttn

tn

NqzJ

y

J

xJ

qdifftn

drifttn JNzNyNx

11 )(

othertp

GthermalRtp

Pqtp

othertn

GthermalRtn

Nqtn

J

J

1

1

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A PN junction is present in almost every semiconductor device.

N-type

P-type

Donors

V

I

Reverse bias Forward bias

N P

V

I

diodesymbol

– +

PN Junctions

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N-region P-region(a)

(b)

(c)

(d)

Depletionlayer

Neutral P-region

NeutralN-region

Ef

n 0 and p 0in the depletion layer

Ec

Ef

Ev

Ec

Ev

Ef

Ec

Ev

Ef

Ev

Ec

Energy Band Diagram and Depletion Layer

2lni

adbi

n

NN

q

kT

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Qualitative Electrostatics

Band diagram

Built in-potential

From =-dV/dx

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On the P-side of the depletion layer, = –qNa

On the N-side, = qNd

(a)

N P

Nd

Na

D eple tion La yer N e utral R egi on

–xn

0 xp

(b)

x x

p

–xn

(c)

qNd

–qNa

x

E

–xn xp

(d)

(f)

Ec

Ef

Ev

bi , built-in potential

P N

0

–xn

xp

x

bi

(e)

N eut ra l Re gion

V

s

aqNdxd

E

E

)()( 1 xxqN

CxqN

x p

s

a

s

a E

)()( n

s

d xxqN

x E

Depletion-Layer Model

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Effect of Bias on Electrostatics

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Current Flow - Qualitative

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dep

depir τ

WqnAII 0

)1(0 kTVqeII

an

n

dp

pi NL

D

NL

DAqnI 2

0

PN Diode IV Characteristics

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MOS: Metal-Oxide-Semiconductor

SiO2

metalgate

Si body

Vg

SiO2

gate

P-body

Vg

N+N+

MOS capacitor MOS transistor

MOS Capacitors

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MOS Band Diagram –

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E0 : Vacuum levelE0 – Ef : Work functionE0 – Ec : Electron affinitySi/SiO2 energy barrier

sMfbV

SiO2

=0.95 eV

9 eV

Ec, Ef

Ev

Ec

Ev

Ef

3.1 eV qs= Si + (Ec–Ef) qM Si

E0

3.1 eV

Vfb

N+ -poly-Si P-body

4.8 eV

=4.05eV

Ec

Ev

SiO2

Flat-band Condition and Flat-band Voltage

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Biasing Conditions

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Biasing Conditions (2)

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Depletion and the Depletion Width• The charge within the depletion

region is:

• Poisson’s equation reduces to:

• Integrating twice gives:

• Or:

S iO2

gate

P-Si body

+ + + + + +

- - - - - - - V

Vg > V

fb

(a)

Ec,Ef

Ev

Ec

Ef Ev

(b)

M O S

qVg

depletion

region

qs

Wde p - - - - - - - depletion layer charge, Q

de p

qVox

- - --

AqN

WxqN

dx

d

Si

A

Si

0

2

2W

qN

Si

AS

A

SSi

qNW

2

EE143 – Ali Javey

S iO2

gate

P-Si body

+ + + + + +

- - - - - - - V

Vg > V

fb

(a)

Ec,Ef

Ev

Ec

Ef Ev

(b)

M O S

qVg

depletion

region

qs

Wde p - - - - - - - depletion layer charge, Q

de p

qVox

- - --

Surface Depletion

ox

ssasfboxsfbg C

qNVVVV

2

ox

ssa

ox

depa

ox

dep

ox

sox C

qN

C

WqN

C

Q

C

QV

2

EE143 – Ali Javey

threshold of inversion

threshold : ns = Na

(Ec–Ef)surface= (Ef – Ev)bulk

A=B, and C = D

i

aBst n

N

q

kTln22

i

a

a

v

i

vbulkvf

gB n

N

q

kT

N

N

q

kT

n

N

q

kTEE

Eq lnlnln|)(

2

Ec ,Ef

M O S

Ev

Ef

Ei

Ec

A

B

C = q

Ev

D

qVg = qVt

st

Threshold Condition and Threshold Voltage

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oxsfbg VVVV

ox

BsaBfbt C

qNVV

222

Threshold Voltage

Bst 2

ox

stssubstfbt C

qNVV

||2

+ : N-type device, – : P-type device

Summarizing both polarities:

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• Past VT, the depletion width no longer grows

• All additional voltage results in inversion layer charge

SiO2

gate

P-Si su bstrat e

++++ ++++++

V

Vg > Vt

(a)

Ec,Ef

Ev

Ec

Ef

Ev

(b)

M O S

qVg

- - - - - ---

-

- - - - - - -

-

- - --

Qde p

Qinv

a

stsdmaxdep qN

WW2

Strong Inversion–Beyond Threshold

)( tgoxinv VVCQ

EE143 – Ali Javey

s

2B

V f b Vt

Vg

accumulation depletion inversion

Wdep

Wdmax

Vfb Vt

Vg

accumulation dep let ion inversion

s)1/2

Wdm ax

= (2s2 qa

Review : Basic MOS Capacitor Theory

EE143 – Ali Javey

Qdep

= q NaW

dep

0

Vfb

Vt

Vg

accumulation depletion inversion

–q Na

Wdep

Qinv

Vfb

Vt

V g

accumulation depletion inversion

slope = C ox

(a)

(b)

Qacc

Vf b

Vt

Vg

accumulation depletion inversion

(c)

– q NaW

dm ax

slope = C ox

Qs

0

Vf b

Vt

Vg

accumulation regime

depletion regime

inversion regime

Qinv

slope = Cox

total substrate charge, Qs

invdepaccs QQQQ

Review : Basic MOS Capacitor Theory

EE143 – Ali Javey

depox CCC

111

sa

fbg

ox qN

VV

CC )(211

2

C

V f b Vt

Cox

accumulation depletion inversion

Vg

Quasi-Static CV Characteristics

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Qualitative MOSFET Operation

Depletion Layer

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Channel Length Modulation

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MOSFET I-V Characteristics – A 1st attempt

The Square Law Theory

• Current in the channel should be mainly drift-driven

• The current is:

dy

dnqnqJ nnN

dy

dQZ

dxyxndy

dqZ

dzdxJI

Nn

yx

n

NyD

c

)(

0

),(

EE143 – Ali Javey

MOSFET I-V Characteristics – A 1st attempt• But, current is constant through the channel:

• We know the inversion layer charge:

• Accounting for the non-uniformity:

D

D

V

NnD

V

NnD

L

D

dQL

ZI

dQZLIdyI

0

00

)( TGoxinv VVCQ

)()( TGoxinv VVCyQ

TG

DsatDDDTGoxnD VV

VVVVVVC

L

ZI

0

2

2

EE143 – Ali Javey

MOSFET I-V Characteristics – A 1st attempt• Past pinch-off, the drain current is constant

• So:

• Now, in the pinched-off region:

DsatVVDVVD IIIDsatDDsatD

,,

TGDsat

DsatTGoxinv

VVV

VVVCyQ

0)()(

2

2Dsat

DsatTGoxnD

VVVVC

L

ZI

22 TGoxnD VVC

L

ZI

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N-channel MOSFET

Layout (Top View)

4 lithography steps are required: 1. active area 2. gate electrode 3. contacts 4. metal interconnects

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1) Thermal oxidation (~10 nm “pad oxide”)

2) Silicon-nitride (Si3N4) deposition by CVD (~40nm)

3) Active-area definition (lithography & etch)

4) Boron ion implantation (“channel stop” implant)

Simple NMOS Process Flow

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5) Thermal oxidation to grow oxide in “field regions”

6) Si3N4 & pad oxide removal

7) Thermal oxidation (“gate oxide”)

8) Poly-Si deposition by CVD

9) Poly-Si gate-electrode patterning (litho. & etch)

10) P or As ion implantation to form n+ source and drain regions

Top view of masks

Simple NMOS Process Flow

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11) SiO2 CVD

12) Contact definition (litho. & etch)

13) Al deposition by sputtering

14) Al patterning by litho. & etch to form interconnects

Top view of masks

Simple NMOS Process Flow