EE143 F2010 Final Exam Review EE143 LABee143/fa10/lectures/Lec_27.pdf · Professor N Cheung, U.C....

Professor N Cheung, U.C. Berkeley

Final Exam ReviewEE143 F2010

1

EE143 LAB

1



2

EE143 Equipment in Cory 218



3

Si wafer

Processing

Steps

Guidelines for Process Integration

* A sequence of Additive and Subtractive steps with lateral patterning

• Watch out for materials compatibility issues (e.g. temperature limit)

• Planarity is desirable for lithography, etching, and thin-film deposition

• Whenever possible, use self-aligned structures



4

0200400600800

100012001400

Resi

st E

xposu

re

Resi

st S

pin-o

n

Resi

st B

ake

Evap

oratio

n Deposi

tion

Sputt

ering D

epositio

nCVD

Ion Im

planta

tion

Post

Impla

ntatio

n Anneal

Therm

al O

xidat

ion

Dopan

t Diff

usion

Epi

Pro

ce

ss

Te

mp

era

ture

in

C

Resist

Reflow

Al-Si Eutectic (560C)

Si Melting

Point (1412C)

Processing Temperature and Material Failure Temperature



5

Self-Aligned Silicide Process (SALICIDE) using Ion

Implantation and Metal-Si reaction

n+n+

TiSi2 (metal)poly-gate

*Process Flow:

Show Process Description and Cross-sections



6

A Generic

CMOS Process

P-well CMOS



7

Layout Design Rules

•Understand the

meaning of the

boundaries

•Use EE143 design rule

values

•Actual layout may look

different from

conceptual layout when

rule values are applied

•Change of design rules

values will need

understanding of device

structures/technology

•(qualitative)“conceptual layout”



8

Summary : Parameters Affecting VT

6

7

n+

Na

VB

5

1

2

4

3

Dopant implant near Si/SiO2 interface

fOX Q& M

xox

VCQn n+

VG-VB= FMS+ Vox +VSi



9

Accumulation

Depletion

Inversion

Vox = Qa/Cox

VSi ~ 0

Vox =qNaxd/Cox

VSi = qNaxd2/(2s)

Vox = [qNaxdmax+Qn]/Cox

VSi = qNaxdmax2/(2s)

= 2|FF|

Voltage drop = area under E-field curve

* For simplicity, dielectric constants assumed to be same for oxide and Si in E-field sketches



10

+ Qf or Qox

B threshold implant

As or P threshold implant

Xox increases

Xox increases

FM increases

FM decreases

|VCB| increases

|VCB| increases



11

DSDS

TGOXn

D VV

VVCL

WI

2

For VD < VDsat

22

TGOXn

DsatD VVCL

WII

For VD > VDsat

Note: VDsat = VG - VT

MOSFET I-V Characteristics



12

Small Signal Capacitance C ( Q/VG)

*p-type substrateCox



13

Typical Thin Film stress : 108 to 5x1010

dynes/cm2 (107 dyn/cm2 = 1 MPa)

Radius of Curvature of warpage

“Stoney Equation”

r = Es ts

2

( 1- )s 6 f tf



14

MEMS Process Flow Example:

to form a hollow cantilever beam



15

MEMS- IC Integration

Example of MEMS-first approach



16

Thermal Oxidation Model

CG

Cs

Co

Ci

X0x

stagnant

layerSiO2 Si

F1 F2 F3

gas

transport

flux

diffusion

flux

through SiO2

reaction

flux

at interface

Note

Cs Co



17

CVD Deposition Rate [Grove Model]

F

F

3

1

kTE

os

G

ekk

hD

F1F3

Si

film

= thickness of stagnant layer

31 FF

D [ CG - CS] /

kS CS



18

Ion Implantation

C(x)Cp

0.61 Cp

Rp

Rpx=0x

straggleallongitudinR

rangeprojectedR

eCpxC

p

p

R

Rx

p

p

2

2

2

CB

xj

Implantation Damage

random scattering path

deeper

penetration

Si Crystal

random scattering path

deeper

penetration

Si Crystal

Ion Channeling



19

T(t)

time

i

ieffective DtDt

BudgetThermal

)()(

well

drive-in

step

S/D

Anneal

step

For a complete process flow, only those steps with high Dt

values are important

Examples: Well drive-in and S/D

annealing steps



20



21

point

best

off

Depth of Focus (DOF)



22

01020304050

6070

8090

100120140160

0 1 2 3

Lateral position x ( in um)

Ph

oto

n e

ne

rgy d

os

e

(mJ

/cm

2)

Any dose < 20mJ/cm2 will work


01020304050

6070

8090

100120140160

0 1 2 3


Ph

oto

n e

ne

rgy d

os

e

(mJ

/cm

2)



Positive Resist

00.10.20.30.40.50.60.70.80.9

1

1 10 100 1000

Exposure energy dose (mJ/cm2)

No

rmal

ized

rem

ian

ing

th

ickn

ess

aft

er d

evelo

pm

ent

Resist cross-section after development

0

0.1

0.20.30.4

0.5

0.6

0.70.8

0.9

1

0 1 2 3


Mo

rma

liz

ed

re

sis

t

thic

kn

es

s

Resist cross-section after development

0

0.1

0.20.30.4

0.5

0.6

0.70.8

0.9

1

0 1 2 3


Mo

rma

liz

ed

re

sis

t

thic

kn

es

s

Past Exam Question

Answer



23

Worst-Case Design Considerations for Etching

step

Substrate

step height

variation

variation

of film

thickness

across wafer

etching mask

can be eroded

during

film

etchingMask

film



24

effect

Control

variable

Effect of RIE process variables on etching characteristics



Multilevel Metallization

Interconnect

Via



26

Electromigration Issues

EE143 F2010 Final Exam Review EE143 LABee143/fa10/lectures/Lec_27.pdf · Professor N Cheung, U.C....

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