EE 5340 Semiconductor Device Theory Lecture 23 - Fall 2010

EE 5340Semiconductor Device TheoryLecture 23 - Fall 2010

Professor Ronald L. [email protected]

http://www.uta.edu/ronc

L23 10Nov2010 2

Gummel-Poon Staticnpn Circuit Model

C

E

B

B’

ILC

ILEIBF

IBRICC - IEC = {IS/QB}*

{exp(vBE/NFVt)-exp(vBC/NRVt)}

RC

RE

RBB

IntrinsicTransistor

L23 10Nov2010 3

Gummel Poon npnModel Equations

IBF = ISexpf(vBE/NFVt)/BF

ILE = ISEexpf(vBE/NEVt)

IBR = ISexpf(vBC/NRVt)/BR

ILC = ISCexpf(vBC/NCVt)

QB = (1 + vBC/VAF + vBE/VAR )

{½ + ¼ + (BFIBF/IKF + BRIBR/IKR)}

L23 10Nov2010 4

Charge componentsin the BJT **From Getreau, Modeling the

Bipolar Transistor, Tektronix, Inc.

L23 10Nov2010 5

Gummel PoonBase ResistanceIf IRB = 0, RBB = RBM+(RB-RBM)/QB

If IRB > 0RB = RBM + 3(RB-RBM)(tan(z)-z)/(ztan2(z))

[+iB/(IRB)]1/2-

(/)(iB/IRB)1/2z =

From An Accurate Mathematical Model for the Intrinsic Base Resistance of Bipolar Transistors, by Ciubotaru and Carter, Sol.-St.Electr. 41, pp. 655-658, 1997.

RBB = Rbmin + Rbmax/(1 + iB/IRB)RB

L23 10Nov2010 6

BJT CharacterizationForward GummelvBCx= 0 = vBC + iBRB - iCRC

vBEx = vBE +iBRB +(iB+iC)RE

iB = IBF + ILE =

ISexpf(vBE/NFVt)/BF

+ ISEexpf(vBE/NEVt)

iC = FIBF/QB =

ISexpf(vBE/NFVt)/QB

+

-

iC RC

iB

RE

RB

vBEx

vBC

vBE

++

-

-

L23 10Nov2010 7

Ideal F-G DataiC and iB (A)

vs. vBE (V)

N = 1 1/slope = 59.5 mV/dec

N = 2 1/slope = 119 mV/dec

BJ T I (A) vs. Vbe (V) for the G-P model Forward Gummel configuration (Vbcx=0)

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

0.0 0.2 0.4 0.6 0.8

I c

I b

L23 10Nov2010 8

BJT CharacterizationReverse Gummel

+

-

iE

RC

iB

RE

RB

vBCxvBC

vBE

++

-

-

vBEx= 0 = vBE + iBRB - iERE

vBCx = vBC +iBRB +(iB+iE)RC

iB = IBR + ILC =

ISexpf(vBC/NRVt)/BR

+ ISCexpf(vBC/NCVt)

iE = RIBR/QB =

ISexpf(vBC/NRVt)/QB

L23 10Nov2010 9

Ideal R-G DataiE and iB (A)

vs. vBE (V)

N = 1 1/slope = 59.5 mV/dec

N = 2 1/slope = 119 mV/dec

BJ T I (A) vs. Vbe (V) for the G-P model Forward Gummel configuration (Vbcx=0)

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

0.0 0.2 0.4 0.6 0.8

I c

I b

Ie

L23 10Nov2010 10

Ideal 2-terminalMOS capacitor/diode

x

-xox

0SiO2

silicon substrate

Vgate

Vsu

b

conducting gate,area =

LW

tsub

0y

L

L23 10Nov2010 11

Band models (approx. scale)

Eo

Ec

Ev

qox

~ 0.95 eV

metal silicon dioxide

p-type s/c

qm= 4.1 eV for Al

Eo

EF

m

EFp

Eo

Ec

Ev

EFi

qs,p

qSi= 4.05e

VEg,ox

~ 8 eV

L23 10Nov2010 12

Flat band condition (approx. scale)

Ec,Ox

Ev

Al SiO2p-Si

q(m-ox)= 3.15 eV

EF

m EFp

Ec

Ev

EFi

q(ox-Si)=3.1eV

Eg,ox

~8eV

cond band-flat for

VVV8.0

V

eV8.0EE

Then

eV85.0EE

If

sg

MS

fpfmFB

fpfm

fpc

qfp= 3.95e

V

L23 10Nov2010 13

Equivalent circuitfor Flat-Band• Surface effect analogous to the

extr Debye length = LD,extr = [Vt/(qNa)]1/2

• Debye cap, C’D,extr = Si/LD,extr

• Oxide cap, C’Ox = Ox/xOx

• Net C is the series comb

Oxextr,Dtot 'C1

'C1

'C1

C’Ox

C’D,extr

L23 10Nov2010 14

Accumulation for Vgate< VFB

SiO2

p-type Si

Vgate<

VFB

Vsub = 0

EOx,x<0

x

-xox

0

tsu

b

x,OxSi

Ox

Si

SiSix,OxOx

Ox

Oxx,Ox

E31

E

39.37.11

EE

0xV

E

holes

L23 10Nov2010 15

Accumulationp-Si, Vgs < VFBFig 10.4a*

L23 10Nov2010 16

Equivalent circuitfor accumulation• Accum depth analogous to the

accum Debye length = LD,acc = [Vt/(qps)]1/2

• Accum cap, C’acc = Si/LD,acc



Oxacctot 'C1

'C1

'C1

C’Ox

C’acc

L23 10Nov2010 17

Depletion for p-Si, Vgate> VFB

SiO2

p-type Si

Vgate>

VFB

Vsub = 0

EOx,x> 0

x

-xox

0

tsu

b

x,OxSi

Ox

Si

SiSix,OxOx

Ox

Oxx,Ox

E31

E

39.37.11

EE

0xV

E

Acceptors

Depl Reg

L23 10Nov2010 18

Depletion forp-Si, Vgate> VFBFig 10.4b*

L23 10Nov2010 19

Equivalent circuitfor depletion• Depl depth given by the usual

formula = xdepl = [2Si(Vbb)/(qNa)]1/2

• Depl cap, C’depl = Si/xdepl



Oxdepltot 'C1

'C1

'C1

C’Ox

C’depl

L23 10Nov2010 20

Inversion for p-SiVgate>VTh>VFB

Vgate>

VFB

Vsub = 0

EOx,x> 0

inversion for

threshold above

E Induced

depletes 0

E Induced

0xV

E

Si

Si

Ox

Oxx,Ox

Acceptors

Depl Reg

e- e- e- e- e-

L23 10Nov2010 21

Inversion for p-SiVgate>VTh>VFBFig 10.5*

L23 10Nov2010 22

Approximation concept“Onset of Strong Inv”• OSI = Onset of Strong Inversion occurs

when ns = Na = ppo and VG = VTh

• Assume ns = 0 for VG < VTh

• Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh

• Cd,min = Si/xd,max for VG > VTh

• Assume ns > 0 for VG > VTh

L23 10Nov2010 23

MOS Bands at OSIp-substr = n-channelFig 10.9*

L23 10Nov2010 24

Equivalent circuitabove OSI• Depl depth given by the maximum

depl = xd,max = [2Si|2p|/(qNa)]1/2

• Depl cap, C’d,min = Si/xd,max



Ox,mindtot 'C1

'C1

'C1

C’Ox

C’d,min

L23 10Nov2010 25

MOS surface states**p- substr = n-channel

VGS s Surf chg Carr Den

VGS < VFB < 0 s < 0 Accum. ps > Na

VGS = VFB < 0 s = Neutral ps = Na

VFB < VGS s > 0 Depletion ps < Na

VFB < VGS < VTh s = |p| I ntrinsic ns = ps = ni

VGS < VTh s > |p| Weak inv ni< ns < Na

VGS = VTh s = 2|p| O.S.I . ns = Na

L23 10Nov2010 26

References

* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.

**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986

EE 5340 Semiconductor Device Theory Lecture 23 - Fall 2010

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