ECE 4510/5530Microcontroller Applications

Week 7

Dr. Bradley J. BazuinAssociate Professor

Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences

ECE 2510 2

Lab 6 & 7 Element

• uCOS-II

• SPI and ADC/DAC– SPI and ADC discussed last week

uCOS-IIby Micrium http://micrium.com/

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uCOS-II Real Time OS

• Seehttp://micrium.com/?wpdmdl=366&

• Review in class– Jean J. Labrosse, The 10-Minute Guide to RTOS, Application Note

AN-1004, Micriμm, Inc., 2001.– Jean.Labrosse@Micrium.com– www.Micrium.com

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SERIAL PERIPHERAL INTERFACE (SPI)

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Data Transfer Example

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Chip Select: enable target device for transferSerial Clock: fast clock from master for synchronous data transfersMOSI: master output, slave input (simultaneous transfer with MISO)MISO: slave output, master input (simultaneous transfer with MOSI)• Typically, the first 8-bits are an address and/or command from master to slave and

subsequent 8-bit transfers are data.

AD5678 Digital-to-Analog

FEATURES– Low power octal DAC with– Four 16-bit DACs and Four 12-bit DACs– 14-lead/16-lead TSSOP– On-chip 1.25 V/2.5 V, 5 ppm/°C reference– Power down to 400 nA @ 5 V, 200 nA @ 3 V– 2.7 V to 5.5 V power supply– Guaranteed monotonic by design– Power-on reset to zero scale– 3 power-down functions– Hardware LDAC and LDAC override function– CLR function to programmable code– Rail-to-rail operation

APPLICATIONS– Process control– Data acquisition systems– Portable battery-powered instruments– Digital gain and offset adjustment– Programmable voltage current sources– Programmable attenuators

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SPI Programming Sequence

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Example DAC AD5678 dac.h

/** Bazuin DAC header file for AD5678* Last Modified: B. Bazuin 3/3/2009*/

// Public Function Prototypesextern void dac_init(void);extern void dac_output(char dac_channel, unsigned intvoltage);

// SPI port interface macros#define dac_select P3OUT &= ~DAC_nCS#define dac_deselect P3OUT |= DAC_nCS

// Command Definitions

#define write_input_reg 0x00#define update_dac_reg 0x01#define write_update_input_reg 0x02#define write_update_dac 0x03#define power_dac 0x04#define clear_code_reg 0x05#define ldac_reg 0x06#define reset 0x07#define internal_ref_reg 0x08

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// Address Commands/*A3 A2 A1 A0 Description0 0 0 0 DAC A (16 bits) pin 40 0 0 1 DAC B (16 bits) pin 130 0 1 0 DAC C (12 bits) pin 50 0 1 1 DAC D (12 bits) pin 120 1 0 0 DAC E (12 bits) pin 60 1 0 1 DAC F (12 bits) pin 110 1 1 0 DAC G (16 bits) pin 70 1 1 1 DAC H (16 bits) pin 101 1 1 1 All DACs*/

#define dac_a 0x00#define dac_b 0x10#define dac_c 0x20#define dac_d 0x30#define dac_e 0x40#define dac_f 0x50#define dac_g 0x60#define dac_h 0x70#define dac_all 0xF0

Example DAC AD5678 dac.c

void dac_output(char dac_channel, unsigned int voltage) // output voltage to Channael A{

char msnib;char midbyte;char lsnib;

msnib = (voltage>>12) & 0x0F;midbyte = (voltage>>4) & 0xFF;lsnib = (voltage<<4) & 0xF0;dac_select; spi0_transmit(0x03); // DB31-C0: write to and update Channel Aspi0_transmit(dac_channel | msnib); // A3-D12: channel A: transmit the first two bits of the voltagespi0_transmit(midbyte); // D11-D4: transmit the next bytespi0_transmit(lsnib); // D3-DB0: transmit the last four bits + X'sdac_deselect; // SYNC (active low) is required to go high for at least 15ns

}

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Example DAC AD5678 dac.cvoid dac_init() //initialize DAC1{

// the following commands enable the use of internal reference (~2.5V)// alternatively, if an external reference, does not require an initialization.

dac_select; spi0_transmit(reset); // DB31-C0: reset command spi0_transmit(0x00); // A3-D12 spi0_transmit(0x00); // D11-D4spi0_transmit(0x00); // D3-DB0: externalreferencedac_deselect; // SYNC (active low) is required for >= 15ns

dac_select; spi0_transmit(internal_ref_reg); // DB31-C0: internal reference for Channel A spi0_transmit(0x00); // A3-D12spi0_transmit(0x00); // D11-D4

// spi0_transmit(0x01); // D3-DB0: internal reference - ONspi0_transmit(0x00); // D3-DB0: externalreferencedac_deselect; // SYNC (active low) is required for >= 15ns

//LDAC internal or exrternal updatingdac_select; spi0_transmit(ldac_reg); // DB31-C0: internal reference spi0_transmit(0x00); // A3-D12spi0_transmit(0x00); // D11-D4

// spi0_transmit(0x00); // All channels use external LDACspi0_transmit(0xFF); // All channels use immediately update, LDAC#=0 dac_deselect; // SYNC (active low) is required for >= 15ns

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//Power up/down functionsdac_select; spi0_transmit(power_dac); // DB31-C0: internal reference spi0_transmit(0x00); // A3-D12

// spi0_transmit(0x03); // Tri-state power down modespi0_transmit(0x00); // power up modespi0_transmit(0xFF); // All channels imm. power up/down dac_deselect; // SYNC (active low) >= 15ns

//Clear Code Function to start at 0x0000dac_select; spi0_transmit(clear_code_reg); // DB31-C0: internal reference spi0_transmit(0x00); // A3-D12spi0_transmit(0x00); // power up modespi0_transmit(0x00); // 0-0x0000, 1-0x8000, 2-0xFFFF, 3- nopdac_deselect; // SYNC (active low) >= 15ns

}

Digital-to-Analog Converter

FEATURES• Micropower—100 uA• Single-Supply—2.7 V to 5.5 V Operation• Compact 1.75 mm Height SO-8 Package

and 1.1 mm Height TSSOP-8 Package• AD7390—12-Bit Resolution• SPI and QSPI Serial Interface Compatible

with Schmitt Trigger InputsAPPLICATIONS

• Automotive 0.5 V to 4.5 V Output Span Voltage

• Portable Communications• Digitally Controlled Calibration

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AD7390 DAC

• Note: LDn appears to be is backwards?! High SPI Shift/Low Update ADC Out

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Data Sheet Notes for Analog

• The AD7390 should be powered directly from the system• power supply. This arrangement, shown in Figure 6, employs an LC filter and

separate power and ground connections to isolate the analog section from the logic switching transients.

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Analog 5V Supply

Typical Application

Twelve data bits are required to load a value into the AD7390. • If more than 12 bits are

transmitted before the load LD input goes high, the extra (i.e., the most-significant) bits are ignored.

• Thus, the μC sends 16 bits to the DAC instead of 12 bits. The AD7390 will only respond to the last 12 bits clocked into the SDI input.

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5.2 DVout

Warning: Pin out is wrong!

1 and 3 swapped

Correct Device Pin Out

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Programming Notes

• For Clearing– LDn held high while CLRn transitions high to low and low to high– tCLRW > 15 nsec

• For loading– LDn low causes the DAC to be loaded with the value in the shift register.– tLDW > 30 nsec for 3 V

(suggestion hold low when not programming or clearing)– Data is loaded MSB first with last 12-bits being DAC value to output (zero fill first

4 bits). – Max clock width high and low is 50 nsec.

Therefore, max clock rate 10 MHz.

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Example DAC AD7390

void dac_output(unsigned int voltage) // output voltage{

char ms_byte;char ls_byte;

ms_byte = (voltage>>8) & 0x0F; // Shift 16-bit value to 8 lsbs, and upper 4 bitsls_byte = (voltage) & 0xFF; // Convert 16-bit to 8 bitdac_select; spi0_transmit( ms_byte ); // D11-D8: transmit the most sig. bytespi0_transmit( ls_byte ); // D7-DB0: transmit the least sig. bytedac_deselect;

}

void dac_clear(void) // zero output voltage{

dac_select; // LDn goes high dac_clear_select; // CLRn goes lowasm(“nop”); // clock cycle delay for clearingdac_clear_deselect // CLRn returns highdac_deselect; // LDn returns low

}

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