ECE 4510/5530 Microcontroller Applications Chapter 6bazuinb/ECE4510/Ch06.pdf · 2013-01-23 · ECE...

ECE 4510/5530Microcontroller Applications

Chapter 6

Dr. Bradley J. BazuinAssociate Professor

Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences

ECE 4510/5530

2

Chapter 6

• Resets• Interrupts• Differences between • Interrupt/Reset Handlers

– Interrupt Service Routines

• Clock and Reset Block• Low Power Modes• COP watchdog timer

ECE 2510 3

What is a Reset?

• Hardware Reset– All hardware and software placed in the initial, default state.

• All registers and values reset to default conditions.• Assume RAM contains random binary values or is unchanged.

(If the power goes off, memory can change, if not, it stays the same.)– Activated by: Power turning on or reset pin on microcontroller

• Software Reset– Restart or reinitialize software without resetting the hardware

• Hardware memory are not changed except under program control, hardware peripheral registers may be “protected”.

• Registers/memory not initialized or used by the software are likely to remain unchanged.

– Activated by: a software command or, if programmed and enabled, a non-maskable interrupt pin … often called NMI(for us, the XIRQ can be used for this task if enabled)

ECE 2510 4

What is an Interrupt?

• An interrupt is a special event that requires the CPU to stop normal program execution and perform some “service related to the event”. – Examples of interrupts include I/O completion, timer time-out,

illegal opcodes, arithmetic overflow, divide-by-0, etc.– For most PCs, an interrupt is caused by a real-world event or by

something going wrong.– In most “real-time” signal processing almost all events drive

interrupts and interrupts are prioritized so the most important interrupt is worked on first.

• Interrupt sources– External: an external pin or level causes the interrupt– Internal: an internal microcontroller peripheral device or CPU

operation causes the interrupt– Software: the swi assembly language instruction is an interrupt

ECE 4510/5530

5

Reset Features

• The initial values of some CPU registers, flip-flops, and the control registers in I/O interface chips must be established in order for the computer to function properly.– The reset mechanism establishes these initial conditions for the

computer system.

• There are at least two types of resets: power-on reset and manual reset. – The power-on reset establishes the initial values of registers and

I/O control registers.– The manual reset without power-down allows the computer to get

out of most error conditions if hardware doesn’t fail.

• A reset is nonmaskable. After a reset, the CPU always starts at a defined address.

ECE 4510/5530

6

Hardware vs. Software Reset

• Hardware Resets are caused due to physical hardware conditions. (e.g. power-on, reset pin activated)– All processor register defaults set, all initialization performed

• Software Resets– Often associated with activation of a non-maskable interrupt

(NMI)– May not reset processor hardware, such as registers or peripherals.– May be used to stop a program and restart the operating system or

CPU monitor or Software (like D-Bug12).

ECE 2510 7

Interrupts

• Interrupts Features– Respond to real time hardware, “software events”, or program

software initiated interrupts.– Software errors can cause software interrupts,

usually referred to as a trap or a fault• Illegal instruction, illegal memory address, etc. • (advanced memory management page fault or segmentation fault)

– SWI is a software interrupt • Transfers program execution to D-Bug12

– Activated by: software or IRQ pin if enabled or a peripheral device hardware interrupt if enabled.

– Software interrupts happen at defined times in code execution– Hardware interrupts happen at random times during code execution

ECE 4510/5530

Functions of Interrupts

• Performing time-critical operations or applications– Real-time data sample systems– Power failure

• Coordinating I/O activities and preventing CPU from being tied up

• Providing a graceful way to handle or exit from errors• Reminding the CPU to perform routine tasks

– Time-of-Day– Health check and status– Other Periodic Functions– Task Switching for a multitasking operating system

ECE 4510/5530

9

Example of Real-Time Code Flow

• Sequential Code with Infinite Loop– Process as time is available

• Interrupts that must be immediately processed

External Interrupt Priority

Interrupt 1

Int 1 Process

Set Int 1 Flag

RTI

Interrupt 2

Int 2 Process

Set Int 2 Flag

RTI

Interrupt M

Int M Process

Set Int M Flag

RTI

ECE 4510/5530

10

Multi-tasking Operating Systems

• Modern computer systems consists of multiple application programs in the memory– CPU time is divided into many short time slots of 10 to 20ms– Multitasking operating systems assign a program to be executed

for one time slot– At end of a time slot or when program is waiting for the

completion of an I/O operation, the operating system takes over and assigns another program for execution

• This technique is called multi-tasking and dramatically improve the CPU performance

• This multi-tasking technique is implemented by using periodic timer interrupts

ECE 4510/5530

Basics of Interrupts (1 of 5)

• Interrupt priority– Allow multiple pending interrupt requests– Resolve the order of service for multiple pending interrupts

• Interrupt maskability– Interrupts that can not be ignored by the CPU are called

nonmaskable interrupts. (An NMI is usually the highest priority interrupt).

– Interrupts that can be ignored by the CPU are called maskable interrupts.

– A maskable interrupt must be enabled before it can interrupt the CPU and must be disabled when it is not allowed to interrupt the CPU.

– An interrupt is enabled by setting an enable/disable bit or flag.

ECE 4510/5530


• Interrupt service– CPU executes a program called the interrupt service routine.– A complete interrupt service cycle includes

1. Saving the program counter value in the stack2. Saving the CPU status (including the CPU status register and some

other registers) in the stack3. Identifying the cause of interrupt4. Resolving the starting address of the corresponding interrupt service

routine (ISR)5. Executing the interrupt service routine6. Restoring the CPU status and the program counter from the stack7. Restarting the interrupted program

– An ISR often looks exactly like a subroutine call, except that it is called due to an interrupt.

ECE 4510/5530


• Interrupt vector– Starting address of the interrupt service routine

• Interrupt vector table– A table where all interrupt vectors are stored

• Methods of determining interrupt vectors– Predefined locations (Microchip PIC18, 8051 variants)– Fetching the vector from a predefined memory location (HCS12)– Executing an interrupt acknowledge cycle to fetch a vector number

in order to locate the interrupt vector (68000 and x86 families)

ECE 4510/5530


• Steps required for interrupt programming– Step 1. Initializing the interrupt vector table– Step 2. Writing the interrupt service routine– Step 3. Enabling the desired interrupts at the appropriate location

in the system code.

• The overhead of interrupts– Saving and restoring of CPU status and other registers. (HCS12

needs to save all CPU registers).– Execution time of instructions of the interrupt service routine.

• Overhead time required to enter and exit an ISR– The execution of the return-from-interrupt (RTI) instruction that

will restore all the CPU registers.

ECE 4510/5530


• Nasty details when using interrupts– Interrupt happen at random times that may not be predictable.

• Plan for the worst– Microprocessors should cleanly transition from normal operation to the

interrupt• They typically finish the instruction they are executing and save the

address of next instruction in stack so that it can resume the program later.– Microprocessor needs to identify the cause of the interrupt before it can

take appropriate action. This is built into the microprocessor hardware.– Interrupts will force the microprocessor to stop executing an

application program briefly• What is the application priority as compared to the interrupt?

– Interrupts if they return should resume the previous application code as though nothing happened (registers, CCR, etc.).

Important Interrupt Concepts

• Enabling and Disabling Interrupts– The programmer can let them happen or not– Typically global and local enables (one or all and then one each)– Typically the “interrupt status” can be checked even when not

enabled (polling is when software checks for “events”

• Pending interrupt– An interrupt waiting to happen

• Nested interrupts– When an interrupt is allowed to occur while the software is

executing another interrupt– Typically, interrupts are disabled automatically while an interrupt

is being serviced … waiting interrupts are “pending”.

ECE 2510 16

Using Interrupts

• Initialize the interrupting function and set the local interrupt enable bit– clear pending interrupts if possible

• Make sure a valid interrupt service routine (ISR) exists• Make sure the system can find the ISR code

– A ISR address table is often used for defined types of interrupts– Also called an interrupt vector (IV) table (address of address)

• When ready, set the global interrupt enable– Pending interrupts will immediately be serviced– Interrupt ISR will start where the IV says, even if you forgot to

define where in the IVECE 2510 17

ECE 4510/5530

18

Major Interrupt Issues

• Maskable/Non-Maskable Interrupts• Interrupt Priority• Interrupt Service• Interrupt Vector• Interrupt Programming• Interrupt Overhead

ECE 4510/5530

19

Maskable Interrupt Operation

• Program can request the CPU to service or ignore a maskable interrupt by setting or clearing an enable bit– When an interrupt is enabled, the CPU will respond to it– When an interrupt is disabled, the CPU will ignore it

• An interrupt is said to be pending when active but not yet serviced by the CPU

• Pending interrupt may or may not be serviced depending on whether or not they have priority and are enabled

• Computer system normally provides a global (all maskable interrupts) and local interrupt masking capability

ECE 2510 20

Maskable Interrupt Operation

• Program can request the CPU to service or ignore a maskable interrupt by setting or clearing an enable bit– When an interrupt is enabled, the CPU will respond to it– When an interrupt is disabled, the CPU will ignore it

• Multiple level masks (both enabled to operate):– Global enable bit

• all local interrupts are enabled or disabled– Local enable bit

• each interruptible function has an enable/disable bit

• HC12 also has a special XIRQ interrupt

ECE 4510/5530

21

NMI and the HC12

• The XIRQ input is an updated version of the NMI input found on earlier generations of MCUs.– Non-maskable interrupts are often used to deal with major system failures, such

as loss of power.– However, enabling non-maskable interrupts before a system is fully powered

and initialized can lead to spurious interrupts. The X bit provides a mechanism for enabling non-maskable interrupts after a system is stable.

– By default, the X bit is set to 1 during reset. As long as the X bit remains set, interrupt service requests made via the XIRQ pin are not recognized. An instruction must clear the X bit to enable non-maskable interrupt service requests made via the XIRQ pin. Once the X bit has been cleared to 0, software cannot reset it to 1 by writing to the CCR. The X bit is not affected by maskable interrupts.

b7 b6 b5 b4 b3 b2 b1 b0

S X H I N Z V C The CCR

ECE 2510 22

Enabling the XIRQ pin Interrupt

• After Reset, the X status bit is set to 1• To allow XIRQ based “non-maskable interrupts” set the bit

to 0

ANDCC #$BF ;AND CCR with 1011 1111 or $BF

Also needed: interrupt vector and XIRQ ISR

b7 b6 b5 b4 b3 b2 b1 b0

S X H I N Z V C The CCR

Initially off, manually turned on

ECE 2510 23

XIRQ and the CCR X Bit

• When an XIRQ interrupt occurs after non-maskable interrupts are enabled, both the X bit and the I bit are set automatically to prevent other interrupts from being recognized during the interrupt service routine. – The mask bits are set after the registers are pushed onto the stacked, but

before the interrupt vector is fetched.– Normally, a return-from-interrupt (RTI) instruction at the end of the

interrupt service routine restores register values that were present before the interrupt occurred.

• Since the CCR is stacked before the X bit is set, the RTI normally clears the X bit, and thus re-enables non-maskable interrupts. – It is possible to manipulate the stacked value of X so that X is set after an

RTI, but there is no software method to reset X (and disable XIRQ) once X has been cleared.

Interrupts are disabled once an interrupt occurs and an

ISR begins

ECE 4510/5530

24

Global Interrupt Mask

• When none of the interrupts are desirable, the processor can disable all the interrupts by clearing the global interrupt enable bit.

• CCR bit I is the global interrupt mask bit– The I bit enables and disables maskable interrupt sources. – By default, the I bit is set to 1 during reset. – An instruction must clear the I bit to enable maskable interrupts. – While the I bit is set, maskable interrupts can become pending and

are remembered, but operation continues uninterrupted until the I bit is cleared.

b7 b6 b5 b4 b3 b2 b1 b0

S X H I N Z V C

ECE 4510/5530

25

Enabling Global Interrupt

• After Reset, the I status bit is set to 1• To allow interrupts (except NMI) set the bit to 0

ANDCC #$EF ; AND CCR with 1110 1111 or $EForCLI ; Clear interrupt mask bitAlso needed:

lower level interrupt enables, interrupt vectors, and ISRs

• To disable interrupts reset the bit to 1ORCC #$10 ; OR CCR with 0001 0000 or $10orSEI ; Set interrupt mask bit

The CCRb7 b6 b5 b4 b3 b2 b1 b0

S X H I N Z V C

ECE 2510 26

CCR: I Mask Bit

• When an interrupt occurs after interrupts are enabled, the I bit is automatically set to prevent other maskable interrupts during the interrupt service routine. – The I bit is set after the registers are stacked, but before the first

instruction in the interrupt service routine is executed.– Normally, an RTI instruction at the end of the interrupt service

routine restores register values that were present before the interrupt occurred.

• Interrupts can be re-enabled by clearing the I bit within the service routine– implementing a nested interrupt management scheme requires

great care and seldom improves system performance.

Interrupt Hints

• At the beginning of the program, execute an “SEI”– Insure that interrupts will not occur during initialization. – You will be initializing peripherals and enabling the local interrupt

bits. So the global bit keeps them from occuring.

• When initialization is complete, enable interrupts “CLI”– Typically just prior to starting the main programming loop

• Try never to use nested interrupts– To perform nested interrupts, you must execute a CLI inside the

ISR that can be nested– If priority/time is a problem, for non-critical interrupts immediately

set flags and return … thereby spending as little time as possible in the ISR.

ECE 2510 27

ECE 4510/5530

28

Individual Interrupt Mask Bits

• The processor can selectively enable certain interrupts while at the same time disable other undesirable interrupts– When an interrupt is undesirable it can be disabled while at the

same time allowing other interrupt sources to be serviced by the processor

• This is achieved by providing each interrupt source an enable bit in addition to the global interrupt mask– These bits are defined as part of the on-chip peripheral devices and

parallel I/O ports– Example: the IRQ pin

• Bit 6 of the INTCR or IRQCR register (Addr. $001E) must be set

ECE 4510/5530

29


• Maskable Interrupts• Interrupt Priority• Interrupt Service• Interrupt Vector• Interrupt Programming• Interrupt Overhead

ECE 4510/5530

30

Interrupt Priority

• Controller may supports multiple interrupt sources at the same time– It is possible that several interrupts would be pending at the same

time– CPU has to decide which interrupt to service during this situation– Solution to this situation is to prioritize the interrupts

• Interrupt with highest priority receives service before interrupts at lower priorities– Many microcontrollers prioritize interrupts in hardware.

In the HC12, interrupt priority is based on the higest interrupt vector address

– For those microcontrollers that do not prioritize interrupts, software can be written to handle certain interrupts before others.

ECE 2510 31

Interrupt Vector Table (1 of 2)

ResetsSWIsXIRQ

Priority

IRQ

Peripheral Interrupts

ECT

SPI

SCI

Ports

ECE 2510 32

Interrupt Vector Table (2 of 2)Priority

Peripheral Interrupts

Ports

SPI

ECE 4510/5530

33

HCS12 Priority

• The priority and vector addresses of all HCS12 interrupts are listed in Table 6.1 on p. 228.

• To raise a one maskable interrupt source to the highest maskable interrupt priority, write the low byte of the vector address of this interrupt to the HPRIO register (Addr. $001F).

PSEL5 PSEL4 PSEL3 PSEL2 PSEL1PSEL7 PSEL6 07 6 5 4 3 2 1 0

Figure 6.1 Highest priority I interrupt register

$001F

ECE 4510/5530

34



ECE 4510/5530

35

Interrupt Service

• CPU provides service to an interrupt by executing a program called an interrupt service routine (ISR)– The ISR begins at predefined address locations– The HCS12 has a predefined location for each interrupt where the

address of the ISR can be found. This is called an interrupt vector.

• After providing service to an interrupt, the CPU must resume normal program execution– It achieves this by saving the program counter and the CPU status

information before executing the interrupt service routine and then restoring the saved program counter and CPU status before exiting the interrupt service routine.

ECE 4510/5530

36

Interrupt Service

• Interrupt service cycle involves1. Saving the program counter value in the stack2. Saving the CPU status (including the CPU status register and

some other registers) in the stack3. Identifying the source of the interrupt4. Resolving the starting address of the corresponding interrupt

service routine5. Executing the interrupt service routine6. Restoring CPU status from the stack7. Restoring the CPU status and the program counter from the stack8. Resuming the interrupted program

ECE 4510/5530

37

ISR Starting Address or Vector

• The term interrupt vector refers to the starting address of the interrupt service routine

• Different processors use varying ways to determine the interrupt vector1. Predefined locations (Microchip PIC18, 8051 variants)2. Executing an interrupt acknowledge cycle to fetch a vector

number in order to locate the interrupt vector (68000 and x86 families)

3. Fetching the vector from a predefined memory location (HCS12)

ECE 4510/5530

38

Interrupt Acknowledge(68000 and x86 families)

• Execute an interrupt acknowledge cycle to fetch a vector number in order to locate the interrupt vector– During the interrupt acknowledge cycle, the microprocessor

performs a read bus cycle, and the external I/O device that requested the interrupt places a number on the data bus to identify itself

– This number is called the interrupt vector number– CPU can figure out the starting address of the interrupt service

routine by using this number– Freescale 68000 and intel x86 family supports this method

ECE 4510/5530

39

Predefined ISR Locations(Microchip PIC18, 8051 variants)

• Predefined ISR locations, where the starting address of the service routine is predefined when the microcontroller is designed– Processor uses a table to store all the interrupt service routines– Ex: Intel 8051 microcontrollers– Each interrupt is allocated same number of bytes to hold its service

routine– Each routine is allocated eight words– If routine requires more than eight words, the solution is to place a

jump instruction in the predefined location to jump to the actual service routine

ECE 4510/5530

40

Interrupt Vector(HCS12)

• Fetch the interrupt vector from a predefined memory location– In this approach, the interrupt vector of each interrupt source is

stored at a predefined location in the interrupt vector table– The microprocessor or microcontroller can access it directly to

obtain the interrupt vector– HCS12 and most other freescale microcontrollers use this approach

ECE 4510/5530

41

Interrupt Vector Addresses

No CCR Mask$FFFE, $FFFF Power-On (POR) or External Reset$FFFC, $FFFD Clock Monitor Reset$FFFA, $FFFB Computer Operating Properly

Reset(COP Watchdog Timer Reset)$FFF8, $FFF9 Unimplemented Instruction Trap$FFF6, $FFF7 Software Interrupt Instruction (SWI)

X-bit CCR Mask$FFF4, $FFF5 XIRQ Pin

I-bit CCR Mask$FFF2, $FFF3 IRQ Pin$FFC0–$FFF1 Device-Specific Interrupt Sources

See Table 6.1 on p. 268 for a complete list

ECE 2510 42

Interrupts using D-Bug12

• D-Bug12 contains default interrupt handlers for all of the implemented MC9S12DP256 interrupt vectors. – However, to allow a programmer to utilize peripherals in an interrupt driven

manner, a RAM based interrupt vector table is provided by D-Bug12. Each of the 64 entries in the table consists of a two byte address with the table beginning at $3E00.

– Initially, all entries in the table have an address of $0000. Storing a value other than $0000 in any of the RAM interrupt vector table entries causes execution of the interrupt service routine pointed to by the address when an associated interrupt occurs.

• If an unmasked interrupt occurs and a table entry contains the default address of $0000, program execution is returned to D-Bug12 where a message is displayed indicating the source of the interrupt and displays the CPU registers at the point where the program was interrupted.

ECE 4510/5530

43

D-Bug12 RAM Based Interrupts

• Figure 4 shows the correspondence between the interrupt source and the two byte RAM interrupt vector. – SCIO will be ignored,

it is used by D-Bug12

• Use these addresses instead of those previously presented …

From: Reference Guide For D–Bug12 Version 4.x.x

ECE 4510/5530

44



ECE 2510 45

Example of Real-Time Code Flow

• Sequential Code with Infinite Loop– Process as time is available

• Interrupts that must be immediately processed

External Interrupt Priority

Interrupt 1

Int 1 Process

Set Int 1 Flag

RTI

Interrupt 2

Int 2 Process

Set Int 2 Flag

RTI

Interrupt M

Int M Process

Set Int M Flag

RTI

ECE 2510 46

Example “Software” Radio(like a cellular telephone)

• Digital Signal Processing Section– Other blocks are RF, analog, discrete digital, or …

ECE 2510 47

Example Software Radio DSP Code

Based on TI TMS320C6701 Processor Audio example

• Squares are hardware peripherals, either embeeded in the processor or discrete ICs

• ISRs are interrupt service routines

– Handle real-time data block movements

• Red receiver to audio• Orange Mic to transmit

Audio Line-In

AudioLine-Out

Audio Codec

DDR DXR

DMA0

McBSP0 Serial Port

AudioDMA ISR

Receiver DDC Output

TransmitDUC Input

DDR DXR

DMA1

McBSP1Serial Port

BasebandDMA ISR

Demodulation

Audio In Memory

Audio Out Memory

BasebandIn

Memory

BasebandOut

Memory

ModulationCommand and Control

Display and Status

Main Program Loop Routines

Watch Dog Timeout

Watch Dog ISR

InAudio In Audio out Out

ECE 2510 48

Interrupt Routine Programming

• Interrupt programming deals with how to provide service to the interrupt. Three steps are involved in interrupt programming:– Step 1a. Set the interrupt vector table with the ISR start address.

• Maybe be performed automatically using assembler/compiler directives.

– Step 1b. Initializing the peripheral hardware involved.– Step 2. Writing the interrupt service routine.– Step 3. Enabling the desired interrupts at the appropriate

location in the system code.

ECE 2510 49

Interrupt Programming: Step 1a

• Step1a:– Initialize the interrupt vector table– This step is not needed for microprocessors that have predefined

interrupt vectors, but we need to do it!– Two methods to initialize the interrupt vector table

• Can be done using the .org assembler directive• By loading the start address of ISR into index register and storing it

into the Debug-12 interrupt vector table memory

• Step 1b:– Initialize peripherals that will be used

• I/O port directions, levels, etc.

ECE 2510 50

Interrupt Programming: Step 1 Example

Ex: • Method1 (may cause ICC12 size problems)

.org $xxxx ; xxxx is the vector table addressInterrupt_vector: .word ISR_1 ; store the starting address of

; interrupt service routine 1– The above instruction stores the start address of interrupt service

routine by name ISR_1 into the interrupt vector table address specified by the .org assembler directive

• Method2ldx #ISR_1 ; Load start address of interrupt service routine to

; index register Xstx $xxxx ; Store the start address to the interrupt vector table

; address specified

ECE 4510/5530

51

Interrupt Programming: Step 2

• Step2:– Write the interrupt service routine– Interrupt service routine should be as short as possible– For some interrupts, the service routine may only output a message

to indicate that something unusual has occurred

• An ISR is similar to the subroutine– An ISR uses a return from interrupt (RTI) instead of return from

subroutine (RTS) instruction

• Execution of the RTI instruction will automatically restore all the CPU registers.– Interrupts automatically push and pull register and status values

ECE 4510/5530

52

Interrupt programming: Step 2 Example

Ex:IRQ_ISR:

ldaa #$55adda $1032staa PortArti

• This service routine adds $55 to the contents of address $1032 and writes the result to PORTA (Addr. $0000) whenever a particular interrupt occurs

• Execution of the RTI instruction will return CPU control to the new address

ECE 4510/5530

53

Interrupt Programming:Step 3

• Enable the interrupts to be serviced– Interrupts can be enabled by clearing the global interrupt mask– Set the local interrupt enable bits in the I/O control registers

• One common mistake is forgetting to enable interrupts when writing interrupt driven applications!

• Commands:SEI instruction for disabling the global interrupt maskCLI instruction for clearing the global interrupt mask

ECE 2510 54

• Find new PC• Push Y• Push X• Push D• Push CCR• Set I bit in CCR

– Disable I interrupts

• Set X bit in CCR– Disable XIRQ

interrupt

Interrupt Execution

ECE 4510/5530

55

• The stack order on entry of an interrupt– The HCS12 saves all CPU registers on an interrupt.– The order of saving CPU registers is shown below.

• The RTI instruction– RTI is used to terminate interrupt service routines.– RTI will restore CPU registers from the stack.– The HCS12 will continue to execute the interrupted program unless there

is another pending interrupt.

.

Figure 6 .3 Stack o rde r o n entry to inte rrupts

re turn address

[Y]

[X]

[B]

[A]

[CCR] SP

SP + 1

SP + 2SP + 3

SP + 5

SP + 7

Stack after an Interrupt

Return.L

Return.H

Y.H

Y.L

Return Address

Protect Y

Initial SP

X.H

X.LProtect X

A or D.H

B or D.LProtect D=A:B

CCRProtect CCRPost Int SP(9 bytes)

1,SP

0,SP

2,SP

3,SP

5,SP

7,SP

ECE 4510/5530

56

Interrupt Stack Memory Layout

ECE 4510/5530

57



ECE 2510 58

When Does the MCU Recognize Interrupt Requests?

• The MCU recognizes the interrupt request when it completes the execution of the current instruction unless the current instruction is a fuzzy logic instruction. For fuzzy logic instructions, the HCS12 recognizes the interrupt immediately.– Once enabled, an interrupt request can be recognized at any time

after the I mask bit is cleared

• Before HCS12 starts to service an interrupt, it will set the I mask to disable other maskable interrupts

• when CPU begins to service an interrupt, the instruction queue is refilled, return address is calculated and contents of all CPU registers (except Stack Pointer) are saved onto the stack

ECE 2510 59

Overhead of Interrupt Start

• Although interrupt mechanism provides many advantages, it also involves some overhead

• The overhead of HCS12 interrupt includes:– Saving CPU registers including A, B, X, Y and CCR and fetching

the interrupt vector takes at least 9E cycles– RTI instruction restores all the CPU registers that have been stored

in the stack by the CPU during the interrupt takes from 8 to 11E clock cycles (based on whether a new interrupt is pending)

• Execution time of the interrupt service routine depends on the type and the number of instructions in the service routine

• Total overhead is thus at least 17E clock cycles, which amounts to almost 0.7 μsec for a 24MHz E-clock

ECE 2510 60

Return From Interrupt (RTI)

RTI Instruction:• RTI instruction is used to terminate interrupt service routines• RTI is an 8-cycle instruction when no other interrupt is pending and a

11-cycle instruction when other interrupt is pending• In either case first 5 cycles are used to restore the CCR, B:A, X, Y and

the return address from the stack• HCS12 then clears the I mask to enable further maskable interrupts• If no interrupt is pending, three program words are fetched to fill the

instruction queue from the area of return address and processing proceeds from there

ECE 2510 61

Pending Interrupt Requests

• If another interrupt is pending after registers are restored– A new vector is fetched– Stack pointer is adjusted to point at the CCR value that was just

recovered (SP=SP-9)– This makes it appear that registers are stacked again– Then three program words are fetched to refill the instruction

queue, starting at the address the vector points to– Processing then continues with execution of the instruction that is

now at the head of the queue

ECE 4510/5530

62

Interrupts in EVB Mode

• D-Bug12 contains default interrupt handlers for all of the implemented MC9S12DP256 interrupt vectors. – However, to allow a programmer to utilize peripherals in an interrupt

driven manner, a RAM based interrupt vector table is provided by D-Bug12. Each of the 64 entries in the table consists of a two byte address with the table beginning at $3E00.

• Initially, all entries in the table have an address of $0000. Storing a value other than $0000 in any of the RAM interrupt vector table entries causes execution of the interrupt service routine pointed to by the address when an associated interrupt occurs. – If an unmasked interrupt occurs and a table entry contains the default

address of $0000, program execution is returned to D-Bug12 where a message is displayed indicating the source of the interrupt and displays the CPU registers at the point where the program was interrupted.

ECE 4510/5530

63






SPECIFIC INTERRUPT ELEMENTS

ECE 4510/5530

64

ECE 4510/5530

65

External (IRQ) interrupt

• IRQ pin the only external maskable interrupt signal available in the HCS12

• IRQ interrupt pin can be edge- triggered (falling edge) or level-triggered (low) signal

• The triggering method is selected by programming the IRQE bit of the “Interrupt Control register” (IRQCR)

• The IRQ pin interrupt has a local enable bit IRQEN bit, which is bit6 of the IRQCR (location $001E)

ECE 4510/5530

66

External (IRQ) Interrupt

• IRQCR Register

ECE 4510/5530

67

Making IRQ Level-sensitive

• Pros– Multiple interrupt sources can be tied to this pin. Whenever one of

the interrupt sources that are tied to the IRQ pin is low, an interrupt request will be detected by the HCS12

• Cons– Need to make sure that the IRQ signal has become inactive before

the IRQ service routine is complete if there is only one interrupt request pending.

ECE 4510/5530

68

Making IRQ Edge-sensitive

• Pros– Advantage of making the IRQ interrupt edge-sensitive (falling

edge) is that the user does not need to concern about the assertion time of the IRQ signal

• Cons– This approach is not appropriate in a noisy environment– Any noise spikes could generate an undesirable interrupt request

on the IRQ pin

ECE 2510 69

External IRQ Example

Ex: • Assume that the IRQ pin of HCS12 is connected to a 1-Hz

digital waveform and PortB is connected to eight LED’s. • Write a program to configure PortB for output and enable

the IRQ interrupt• Write the service routine for the IRQ interrupt• Service routine for the IRQ interrupt should simply

increment a counter and output it to PortB (a parallel port on the microprocessor)

ECE 2510 70

External IRQ Example Steps

• Step1: Write ISR start address into the IRQ vector address• Step2: Configure PortB as output port• Step3: Disable global maskable interrupt pin• Step4: Enable IRQ interrupt, by enabling the local interrupt

in the interrupt register• Step5: Enable global maskable interrupts• Step6: Develop the interrupt service routine

ECE 2510 71

Using IRQ: Code (1 of 2)

.area prog(abs)PortB = $01DDRB = $03 ; DDRB is the data direction registers for PORTB to

; configure a I/O pin for output (1) or input (0), write a 1 or 0 to; the corresponding bit in the data direction register

IRQCR = $1E ;Defined as INTCR in Register definition file.text_main::

sei ; set interrupt mask (insure ints off)lds #$3C00 ; load the stack pointerldx #IRQ_isr ;Load start addr of ISRstx $3E72 ;Store in the vector locationldaa #$FF ;set PortB as output portstaa DDRBldaa #$00staa PortB ;Initial output to the port

ECE 2510 72

Using IRQ: Code (2 of 2)

ldaa #$C0staa IRQCR ; falling edge external interrupt enablecli ; clear interrupt mask to enable I interrupts

End: nop ; do nothingnopbra End

.org $1400IRQ_isr:

inc 1,SP ; increment A reg in interrupt stackstaa PortB ; let the PortB outputs be the A reg valuerti

ECE 2510 73

External IRQ Example C Code (1 of 2)

#include <hc12def.h>#include <mc9s12dp512.h> //header file to be includedchar i = 0;

main() {

asm(“sei”); // insure that INTs are offDDRB = 0xFF; // initialize port DDRPORTB = i; // provide an initial output valueINTCR = 0xC0; // setup and enable IRQasm(“cli”); // enable INTswhile() {asm(“nop”); // do nothing}

}

ECE 2510 74

External IRQ Example C Code (2 of 2)

// The ISR code with pragma so an RTI is used for returning#pragma interrupt_handler IRQ_isr void IRQ_isr (void) {

i = i+1;PORTB = i;

}

// Make sure the address of the ISR is in the Int Vector Table#pragma abs_address:0x3E72 void (*ISR_VECTOR[]) () = {IRQ_isr}; #pragma end_abs_address

ECE 2510 75

Non Maskable Interrupts

• Three interrupts are available in this category– XIRQ pin– SWI instruction– Unimplemented opcode trap

ECE 2510 76

Non Maskable (XIRQ)

• XIRQ Pin Interrupt Non Maskable interrupt– Disabled during a system reset and upon entering the service

routine of another XIRQ interrupt.

• If X bit in the CCR sets, XIRQ pin is disabled

• After system initialization, software can clear X bit of the CCR register to enable the XIRQ interrupt using

andcc #$BF ; anding CCR register instruction– Software cannot reset the X bit from 0 to 1 once it has been

cleared, and hence the interrupt requests made via the XIRQ pin become non maskable

ECE 2510 77

Non Maskable SWI & Opcode Trap

• Unimplemented Opcode Trap:– If HCS12 attempts to execute one of the unused opcodes, an

unimplemented opcode trap occurs

• Software Interrupt Instruction (SWI):– Execution of the SWI instruction causes an interrupt without an

interrupt request signal– SWI is not inhibited by the global mask bits in the CCR– SWI instruction is commonly used in the debug monitor to

implement breakpoints and to transfer control from a user program to the debug monitor

CLOCK AND RESET GENERATOR

ECE 4510/5530

78

ECE 4510/5530

79

Microcontroller Clocks

• Welcome to hardware …

• Typical microcontrollers have multi-function clock generation circuitry. Built in user flexibility …– On IC clock generation– External input clock ports– External crystal connections for clocks– Clock rate multiplication/division circuits (PLL or counters)– Low power allowances (slow or stop the clock)– Special operation during power-on reset and hardware reset– Periodic clock based interrupts (watchdog timer)– And more …..

ECE 4510/5530

80

Clock and Reset Generation Block (CRG) (1 of 2)

ECE 4510/5530

81

Clock and Reset Generation Block (CRG) (2 of 2)

• CRG generates the clock signals required by the HCS12 instruction execution and all peripheral operations.– The clock signal has the form of square waveform.

• Crystal oscillators are often used to generate clock signals.– The crystal oscillator output is sinusoidal wave and must be squared up

before it can be used. The HCS12 has an internal circuit to do this square up operation.

– The CRG block also has a PLL circuit that can multiply the frequency of the incoming clock signal.

• The CRG can also accept an external oscillator (square waveform). – The XCLKS signal must be tied low (for MC9S12DP256B) in order to

use external clock signal.

ECE 4510/5530

82

CRG Configuration Registers

CRG Block User Guide V02.07, Doc. Number S12CRGV2/D

ECE 4510/5530

83

MC9S12DP256B Device User Guide

MC9S12DP256B Device User Guide V02.15, Doc. Number 9S12DP256BDGV2/D

ECE 4510/5530

84

Phaselockloop

1

0

1

0

Clockmonitor

Oscillator OSCCLK

PLLCLK

PLLSEL or SCM

SCM

clockphase

generator2

WAIT,STOP

wait(RTIWAI),stop(PSTP,PRE)

RTI enable

RTI

COP

wait (COPWAI),stop(PSTP, PCE)

COP enable

wait (SYSWAI),stop

stop (PSTP)

wait (CWAI,SYSWAI)stop

Coreclock

Busclock

oscillatorclock

oscillatorclock (pseudo stopmode)

extal

xtal

gatingcondition

= clock gate

Figure 6.15 HCS12 clock generation circuit

SYSCLK

Choice of Clock Source (1 of 3)

E-Clock

Real Time Interrupt

Comp. Operating Properly

ECE 4510/5530

85


• The user can choose between using the external crystal or oscillator to produce the clock signal.– The external crystal is connected between the EXTAL and XTAL

pins and needs an on-chip oscillator circuitry to square it up.– The external clock source provided by the oscillator is connected

to the EXTAL pin and has a 2.5V peak-to-peak magnitude for D family.

• The XCLKS signal must be grounded to select the external clock signal.

ECE 4510/5530

86

Crystal or External Clock Connection


ECE 4510/5530

87


• The output from the OSC module in Figure 6.4 may bypass or go through the PLL circuit.– The PLL circuit has the capability to multiply incoming signal

frequency and stabilize its output signal frequency.

• Either the OSCCLK or the PLLCLK can be chosen as the SYSCLK which will be divided by 2 to derive the bus clock to control the instruction execution and peripheral operation. (E-clock from timing).

ECE 4510/5530

88

Phase Lock Loops

• A Phase Lock Loop is capable of providing an integer change up or down in the clock rate input to the PLL– A voltage controlled oscillator is used


ECE 4510/5530

89

(SYNR + 1)PLLCLK = 2 OSCCLK ----------------------- (6.1)

(REFDV + 1)

Phase Locked Loop (PLL) (1 of 5)

• The frequency of the PLLCLK is controlled by registers synthesizer (SYNR) and reference divide (REFDY) using the following equation:

NOTE: PLLCLK must not exceed the maximum operating system frequency.

Maximum bus frequency is 25 MHz.

Therefore, maximum PLLCLK is 50 MHz.

The lab modules use a 16 MHz external crystal, PLLCLK of 48 MHz, and

E-clock (bus frequency) of 24 MHz.

ECE 4510/5530

90

PLL Rate Registers

• SYNR: 0 to 63• REFDV: 0 to 15

1612min OSCCLKPLLCLK

1642max OSCCLKPLLCLK


ECE 4510/5530

91

PLL Control Register (1)

• Read: anytime• Write: refer to each bit for individual write conditions• CME — Clock Monitor Enable Bit

– 1 = Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock Mode.

– 0 = Clock monitor is disabled.• PLLON — Phase Lock Loop On Bit

– 1 = PLL is turned on. If AUTO bit is set, the PLL will lock automatically.– 0 = PLL is turned off.

• AUTO — Automatic Bandwidth Control Bit– 1 = Automatic Mode Control is enabled and ACQ bit has no effect.– 0 = Automatic Mode Control is disabled and the PLL is under software control, using ACQ bit.

• ACQ — Acquisition Bit– 1 = High bandwidth filter is selected.– 0 = Low bandwidth filter is selected.


ECE 4510/5530

92

PLL Control Register (2)

• PRE — RTI Enable during Pseudo Stop Bit– 1 = RTI continues running during Pseudo Stop Mode.– 0 = RTI stops running during Pseudo Stop Mode.

• PCE — COP Enable during Pseudo Stop Bit– 1 = COP continues running during Pseudo Stop Mode– 0 = COP stops running during Pseudo Stop Mode

• SCME — Self Clock Mode Enable Bit– 0 = Detection of crystal clock failure causes clock monitor reset .– 1 = Detection of crystal clock failure forces the MCU in Self Clock Mode


ECE 4510/5530

93

CRG Clock Selection (1)

Read: anytimeWrite: refer to each bit for individual write conditions• PLLSEL — PLL Select Bit

– 1 = System clocks are derived from PLLCLK.– 0 = System clocks are derived from OSCCLK.

• PSTP — Pseudo Stop Bit– This bit controls the functionality of the oscillator during Stop Mode.– 1 = Oscillator continues to run in Stop Mode (Pseudo Stop). The oscillator amplitude is reduced.– 0 = Oscillator is disabled in Stop Mode.

• SYSWAI — System clocks stop in Wait Mode Bit– 1 = In Wait Mode the system clocks stop.– 0 = In Wait Mode the system clocks continue to run.

• ROAWAI — Reduced Oscillator Amplitude in Wait Mode Bit.– 1 = Reduced oscillator amplitude in Wait Mode.– 0 = Normal oscillator amplitude in Wait Mode.


ECE 4510/5530

94

CRG Clock Selection (2)

• PLLWAI — PLL stops in Wait Mode Bit– 1 = PLL stops in Wait Mode.– 0 = PLL keeps running in Wait Mode.– If PLLWAI is set, the CRG will clear the PLLSEL bit before entering Wait Mode. The PLLON bit

remains set during Wait Mode but the PLL is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be set manually in case PLL clock is required.

– While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting Wait Mode.

• CWAI — Core stops in Wait Mode Bit– 1 = Core clock stops in Wait Mode.– 0 = Core clock keeps running in Wait Mode.

• RTIWAI — RTI stops in Wait Mode Bit– 1 = RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode.– 0 = RTI keeps running in Wait Mode.

• COPWAI — COP stops in Wait Mode Bit– 1 = COP stops and initializes the COP dividers whenever the part goes into Wait Mode.– 0 = COP keeps running in Wait Mode.


ECE 4510/5530

95

movb #2,SYNR ; set SYNR to 2movb #0,REFDV ; set REFDV to 0movb #$80,CRGSEL ; enable PLL, keep SYSCLK running in wait mode,

; keep RTI, COP, PLL & core running in wait modemovb #$60,PLLCTL ; disable clock monitor, enable PLL, set automatic

; bandwidth control, disable RTI & COP in pseudo stop

Phase Locked Loop Example 6.2

• Example 6.2 There is a system that derives its bus clock from the PLL circuit and an external clock of 8 MHz is selected. The desired bus clock is 24 MHz. Write an instruction sequence to perform the desired configuration.– Solution:

• The frequency of OSCCLK is 8 MHz.– The XCLKS pin must be grounded to select oscillator as clock source.

• Make the SYSCLK frequency 48 MHz.• 48 MHz = 2 8 MHz [SYNR + 1] /[REFDV + 1]

– One solution is to set SYNR and REFDV to 2 and 0, respectively.

ECE 4510/5530

96

movb #5,SYNR ; set SYNR to 5movb #0,REFDV ; set REFDV to 0movb #$80,CRGSEL ; enable PLL, keep SYSCLK running in wait mode,

; keep RTI, COP, PLL & core running in wait modemovb #$60,PLLCTL ; disable clock monitor, enable PLL, set automatic

; bandwidth control, disable RTI & COP in pseudo stop

Phase Locked Loop Example 6.3

• Example 6.3 There is a system that uses a 4 MHz crystal oscillator to derive a 24 MHz bus clock. Write an instruction sequence to perform the required configuration.– Solution:

• The OSCCLK and PLLCLK frequencies are 4 MHz and 48 MHz, respectively.

– The XCLKS pin must be pulled to high to select external crystal to generate clock signals

• 48 MHz = 2 4 MHz [SYNR + 1] /[REFDV + 1] • One solution is to set SYNR and REFDV to 5 and 0, respectively.

ECE 4510/5530

97

CRG and PLL Status


• RTIF — Real Time Interrupt Flag– 1 = RTI time-out has occurred.– 0 = RTI time-out has not yet occurred.

• PORF — Power on Reset Flag– 1 = Power on reset has occurred.– 0 = Power on reset has not occurred.

• LOCKIF — PLL Lock Interrupt Flag– 1 = LOCK bit has changed.– 0 = No change in LOCK bit.

• LOCK — Lock Status Bit– 1 = PLL VCO is within the desired tolerance of the target frequency.– 0 = PLL VCO is not within the desired tolerance of the target frequency.

ECE 4510/5530

98

CRG and PLL Status

• TRACK — Track Status Bit– 1 = Tracking mode status.– 0 = Acquisition mode status.

• SCMIF — Self Clock Mode Interrupt Flag– 1 = SCM bit has changed.– 0 = No change in SCM bit.

• SCM — Self Clock Mode Status Bit– 1 = MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from

PLLCLK running at its minimum frequency fSCM.– 0 = MCU is operating normally with OSCCLK available.


ECE 4510/5530

99

Clock Monitor

• The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay so that it can operate without any MCU clocks. – If no OSCCLK edges are detected within this RC time delay, the clock

monitor indicates failure which asserts self clock mode or generates a system reset depending on the state of SCME bit.

– If the clock monitor is disabled or the presence of clocks is detected no failure is indicated.

• The clock monitor function is enabled/disabled by the CME control bit. (PLLCTL)– If no OSCCLK edges are detected within the RC time delay, the clock

monitor may reset the MCU if the CME bit in the PLLCTL register is set to 1.

– The SCME bit of the PLLCTL register must be cleared to 0 for clock monitor to work.

ECE 4510/5530

100

Real-time interrupt (RTI) (1 of 3)

• The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the RTICTL ($003B) register. – The RTI runs with a gated OSCCLK. At the end of the RTI time-out

period the RTIF flag is set to one and a new RTI time-out period starts immediately.

• A write to the RTICTL register restarts the RTI time-out period.– If the PRE bit is set, the RTI will continue to run in Pseudo-Stop Mode.

(in PLLCTL)

• The RTI interrupt is enabled by the interrupt enable register (CRGINT).

ECE 4510/5530

101

RTI Counter Chain


102112122132142152162

161 to

Note: OSCCLK not SYSCLK and not E-Clock

ECE 4510/5530

102

RTI Control Register (RTICTL)

• RTR[6:4] — Real Time Interrupt Prescale Rate Select Bits– These bits select the prescale rate for the RTI. See Table 3-2.

• RTR[3:0] — Real Time Interrupt Modulus Counter Select Bits– These bits select the modulus counter target value to provide additional

granularity


Addr: $003B

ECE 4510/5530

103

RTI RatesTable 6.4 RTI interrupt period (in units of OSCCLK cycle)

RTR[3:0] RTR[6:4]000(off)

001(210)

010(211)

011(212)

100(213)

101(214)

110(215)

111(216)

0000 (1)0001(2)0010 (3)0011 (4)0100 (5)0101 (6)0110 (7)0111 (8)1000 (9)1001 (10)1010 (11)1011 (12)1100 (13)1101 (14)1110 (15)1111 (16)

off*off*off*off*off*off*off*off*off*off*off*off*off*off*off*off*

210

2210

3210

4210

5210

6210

7210

8210

9210

10210

11210

12210

13210

14210

15210

16210

211

2211

3211

4211

5211

6211

7211

8211

9211

10211

11211

12211

13211

14211

15211

16211

212

2212

3212

4212

5212

6212

7212

8212

9212

10212

11212

12212

13212

14212

15212

16212

213

2213

3213

4213

5213

6213

7213

8213

9213

10213

11213

12213

13213

14213

15213

16213

214

2214

3214

4214

5214

6214

7214

8214

9214

10214

11214

12214

13214

14214

15214

16214

215

2215

3215

4215

5215

6215

7215

8215

9215

10215

11215

12215

13215

14215

15215

16215

216

2216

3216

4216

5216

6216

7216

8216

9216

10216

11216

12216

13216

14216

15216

16216

ECE 4510/5530

104

CRG Interrupt Enable Register (CRGINT)

• RTIE — Real Time Interrupt Enable Bit.– 1 = Interrupt will be requested whenever RTIF is set.– 0 = Interrupt requests from RTI are disabled.

• LOCKIE — Lock Interrupt Enable Bit– 1 = Interrupt will be requested whenever LOCKIF is set.– 0 = LOCK interrupt requests are disabled.

• SCMIE — Self Clock Mode Interrupt Enable Bit– 1 = Interrupt will be requested whenever SCMIF is set.– 0 = SCM interrupt requests are disabled.


Addr: $0038

ECE 4510/5530

105

Initialize RTI Code (1)

.area prog(abs)RTICTL = $003B ;RTICTL register addressCRGINT = $0038 ;CRGINT register addressRTIIV = $3E70 ;RTI D-Bug12 Interrupt Vector address

.text_main::

ldx #RTI_isr ;Load start addr of ISRstx RTIIV ;Store in the vector locationldaa #$1F ;RTI Rate is 16 x 2^10 * OSCClock

; OSCclock = 16 MHz (?)staa RTICTL ; approximately 1.024 msec

ECE 4510/5530

106

Initialize RTI Code (2)sei ; set interrupt maskldaa CRGINToraa #$80 ; set the RTIE interruptstaa CRGINT cli ; clear interrupt mask

End: Nop ; infinite loopbra End

.org $1600RTI_isr:

nop ; interrupt routine here…rti

ECE 4510/5530

107

The RTI as a Watchdog Timer

• Important control information:A write to the RTICTL register restarts the RTI time-out period.

• Therefore, for real-time processing, make the RTI time greater than the maximum time that is takes one of the infinite software loops – Include all possible times: loop code, interrupt ISR code and time

• At the end of every loop, re-write the RTICTL register

• If the RTI interrupt occurs, the software broke!– The RTI ISR should be an error recovery routine.

ECE 4510/5530

108

Computer Operating Properly (COP) Circuit

• COP is a free running watchdog timer and allows the user to determine whether the application software operates properly.

– The COP is a timer circuit that will time out if it is not rearmed within a preset time limit.

– The COP will reset the MCU when it times out and the user would know if the software operated properly.

– The time out period of the COP is controlled by the COPCTL register.

• The application software must include an instruction sequence to prevent the COP from timing out when this is enabled.

• To prevent the COP from timing out for applications that uses COP function, write $55 and then $AA into the ARMCOP register.

ECE 4510/5530

109

COP Counter Chain


142

162182

202

222

232

242


ECE 4510/5530

110

COP Control Register (COPCTL)

• WCOP — Window COP Mode Bit– When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A

write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts and the user must wait until the next window before writing to ARMCOP.

– 1 = Window COP operation– 0 = Normal COP operation

• RSBCK — COP and RTI stop in Active BDM mode Bit– 1 = Stops the COP and RTI counters whenever the part is in Active BDM mode.– 0 = Allows the COP and RTI to keep running in Active BDM mode.

• CR[2:0] — COP Watchdog Timer Rate select– These bits select the COP time-out rate. The COP time-out period is OSCCLK period divided

by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register.


Addr: $003C

ECE 4510/5530

111

COP Watchdog Timer Rates

• For a 16 MHz OSCCLK these correspond to approximately:– 1.02 msec– 4.09 msec– 16.4 msec– 65.5 msec– 262 msec– 524 msec– 1049 msec


ECE 4510/5530

112

ARM COP Register

• When the COP is disabled (CR[2:0] = "000") writing to this register has no effect.

• When the COP is enabled by setting CR[2:0] nonzero, the following applies:– Writing any value other than $55 or $AA causes a COP reset. – To restart the COP time-out period you must write $55 followed by a write of $AA.

Other instructions may be executed between these writes but the sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.

– Sequences of $55 writes or sequences of $AA writes are allowed. – When the WCOP bit is set (COPCTL), $55 and $AA writes must be done in the last

25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset.


Addr: $003F

ECE 4510/5530

113

Initialize COP Code

.area prog(abs)COPCTL = $003C ;COPCTL register addressARMCOP = $003F ;ARMCOP register address

.text_main::

ldaa #$55 ; execute this code t0 insure the staa ARMCOP ; COP is reset to start ldaa #$AA ; the COP timeoutstaa ARMCOPldaa #$07 ;COP Period is 2^24 / OSCClock

; OSCclock = 48 MHzstaa COPCTL ; approximately 349 msec

; the COP is running, so be careful

ECE 4510/5530

114

Running COP CodeMainLoop: ; infinite loop

….….

ldaa #$55 ; execute this code once per loopstaa ARMCOP ; the loop should take longer than ldaa #$AA ; the COP timeoutstaa ARMCOP

bra MainLoop

Note: The COP Interrupt Vector ($FFFA,$FFFB) is not supported by D-Bug12, Therefore, using the COP may cause your code to return control to D-Bug12, but I haven’t tried it!

ECE 4510/5530

115

Lower Power Mode

• It is desirable to minimize power consumption when the MCU is not busy performing useful operations.

• The execution of the WAI instruction places the HCS12 MCU in wait mode and reduces power consumption significantly.– In wait mode, CPU clocks are stopped, but clock signals for peripheral

functions continue to run.

• The CPU leaves the wait mode when one of more of the following events occur:– Maskable interrupts that are not disabled.– Nonmaskable interrupts– Resets

• Reset is not the best way to get out of wait state because it will restart everything and takes longer to resume normal operation.

ECE 4510/5530

116

Stop-Standby Mode

• Stop mode is entered when the MCU executes the STOP instruction. When this instruction is executed, the MCU enters standby mode.– The STOP instruction has no effect if the S flag of the CCR register is 1.

• In stop mode, all clock signals in the MCU are stopped.

• Asserting the RESET, IRQ, or XIRQ signal ends the standby mode.

ECE 4510/5530

117

Resets

• There are four sources of reset:– Power-on (POR) and low-voltage detector (LVD) reset– RESET pin– COP reset– Clock monitor reset

ECE 4510/5530

118

Power-on Reset

• The HCS12 has a circuit to assert reset when the VDD supply to the MCU has reached a certain level.

• The CRG module performs a quality check on the incoming clock signal as soon as a power-on reset is triggered.

• The CRG module will release the reset signal only when the clock check is successful.

ECE 4510/5530

119

IN

GND

RESET

To RESETof HCS12

VDD

MC34064

VDD

4.7

1

3

Figure 6.18 A typical external reset circuit

manual reset

4.7

4.7

2F

External Reset

• The RESET pin allows the user to reset the MCU.

• The MCU can differentiate the external and internal reset signals.

• When the power supply drops to a certain level, it may corrupt the EEPROM.

– It is desirable to have a circuit that can detect this situation and asserts a reset to the MCU.

• The Motorola MC34064 is a chip that can detect low voltage on power supply and reset the CPU.

• An external reset circuit incorporating an MC34064 is shown.

ECE 4510/5530

120

Table 6.5 HCS12 Mode Selection

BKGD MODB MODA Mode

00001111

00110011

01010101

Special single chipSpecial expanded narrow

Special peripheralSpecial expanded wide

Normal single chipNormal expanded narrow

Reserved (forced to peripheral)Normal expanded wide

Port A

general-purpose I/OADDR[15:8]DATA[7:0]ADDR/DATAADDR/DATAGeneral-purpose I/OADDR[15:8]DATA[7:0]--ADDR/DATA

Port B

general-purpose I/OADDR[7:0]ADDR/DATAADDR/DATAGeneral-purpose I/OADDR[7:0]--ADDR/DATA

HCS12 Operation Modes

• The HCS12 can operate in eight different operation modes.• The states of MODC, MODB, and MODA pins are latched

to determine the MCU operation modes.– Expanded modes allow the user to access external memory where

single chip modes do not.– In expanded modes, Port A and B become the time-multiplexed

address and data port.

ECE 4510/5530

121

Timing Example

• Software Loop• RTI Interrupt

ECE 4510/5530

122

End of Chap 6 Material

• And now for an RTI timing example

ECE 4510/5530

123

LED Time Displays

• The hardware module in the lab can implement a Modulo-256 counter that updates the count onto an LED module every 100 ms. The assembly program to implement the Modulo256 counter and the 100 ms delay is given on the following pages.

• Use a microcontroller with a clock oscillator (OSCCLK) of 8.000 MHz, an internal core clock (PLLCLK=SYSCLK) of 48.000 MHz and a bus clock (E-clock) of 24.000 MHz (note that 8.000 x 3/2 = 24.000).

ECE 4510/5530

124

Init., Outer Loop, LED Write.area program(abs)PTT = $0240DDRT = $0242

.text_main::

lds #$3C00ldaa #$FFstaa DDRT ; Set Port T as Output Portldaa #$00staa PTT ; write $00 to Port T

Loop:ldx #$Xcnt ; 2E, Load X register with count

Loop1:ldy #$Ycnt ; 2E, Load Y register with countjsr Delay2msec ; 4E (used inside delay loop)dbne X, Loop1 ; 3E/1Einca ; 1E, Increment Accumulator Astaa PTT ; 2Ebra Loop ; 3E

ECE 4510/5530

125

Outer Loop Timing Estimate

• Assuming a 2 msec subroutine, 50 x 2 msec = 100 msec.• Therefore, assume an Xcnt of 50 and adjust as needed.

• If Xreg=50 and Tinner is 2 msec, what is the error

000,000,24

321121322 reg

reginner

XXTTime

000,000,246

000,000,245

regreginner

XXTTime

sec67.10000,000,24

256000,000,24

6000,000,24

5

regX

Error

ECE 4510/5530

126

Delay 2 msec Code

Delay2msec: ; The jsr is 4E prior to this statementpshy ; 2Epuly ; 3Enop ; 1Enop ; 1Enop ; 1Enop ; 1Edbne Y, Delay2msec ; 3E/1Erts ; 5 E

JSR Loop: loop taken = 2+3+1+1+1+1+3=12, loop not taken = 2+3+1+1+1+1+1 = 10

1000

2_

5101124

RateClockEY

Time reg

ECE 4510/5530

127

Delay 2 msec Computation

• E-Clock Rate is 24,000,000 Hz

1000

2000,000,24

5101124

regY

Time

000,2421000

000,000,2425112

regY

000,412

000,2421

regY

999,3regY

sec208sec2

000,000,245112

nmY

Time reg

ECE 4510/5530

128

Combining Inner and Outer(to achieve 100 msec delay)

• Combining with Yreg=3999 and Xreg=50

000,000,24

5112 reg

inner

YT

000,000,24

6000,000,24

5000,000,24

5112

reg

regreg X

XY

Time

000,000,246

000,000,245

regreginner

XXTTime

000,000,24

6000,000,24112

regreg XYTime

sec250000,000,4

1000,000,24

6 nError

ECE 4510/5530

129

Using the Real-time interrupt (RTI)

• The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. – The RTI runs with a gated OSCCLK. At the end of the RTI time-out

period the RTIF flag is set to one and a new RTI time-out period starts immediately.

– If the PRE bit is set, the RTI will continue to run in Pseudo-Stop Mode. (in PLLCTL)

• A write to the RTICTL register restarts the RTI time-out period.

• The RTI interrupt is enabled by the interrupt enable register (CRGINT).

ECE 4510/5530

130

RTI Counter Chain


102112122132142152162

161 to


ECE 4510/5530

131

Replacing with an RTI

• Determine the interrupt vector to be set.– $3E70 from D-Bug12 on next page

• Initialize the appropriate peripheral registers– RTICTL

• Write the ISR– Coding with functional modifications

• Enable the interrupts prior to the main programming loop– SEI– CRGINT– CLI

ECE 4510/5530

132






ECE 4510/5530

133

RTI Count

• Determine the required count to generate 2 msec.– OSCCLK=16.000 MHz

000,12

000,000,16

Count000,32Count

Use 1 and 2^15 (actual 2.048 msec)

Count 16000

RTR(3:0) log2 Ceil(log2) RTI Count error Floor(log2) RTI Count error1 16000.00 13.97 14 16384 -2% 13 8192 49%2 8000.00 12.97 13 16384 -2% 12 8192 49%3 5333.33 12.38 13 24576 -54% 12 12288 23%4 4000.00 11.97 12 16384 -2% 11 8192 49%5 3200.00 11.64 12 20480 -28% 11 10240 36%6 2666.67 11.38 12 24576 -54% 11 12288 23%7 2285.71 11.16 12 28672 -79% 11 14336 10%8 2000.00 10.97 11 16384 -2% 10 8192 49%9 1777.78 10.80 11 18432 -15% 10 9216 42%

10 1600.00 10.64 11 20480 -28% 10 10240 36%11 1454.55 10.51 11 22528 -41% 10 11264 30%12 1333.33 10.38 11 24576 -54% 10 12288 23%13 1230.77 10.27 11 26624 -66% 10 13312 17%14 1142.86 10.16 11 28672 -79% 10 14336 10%15 1066.67 10.06 11 30720 -92% 10 15360 4%16 1000.00 9.97 10 16384 -2% 9 8192 49%

ECE 4510/5530

134

RTI RatesTable 6.4 RTI interrupt period (in units of OSCCLK cycle)

RTR[3:0] RTR[6:4]000(off)

001(210)

010(211)

011(212)

100(213)

101(214)

110(215)

111(216)

0000 (1)0001(2)0010 (3)0011 (4)0100 (5)0101 (6)0110 (7)0111 (8)1000 (9)1001 (10)1010 (11)1011 (12)1100 (13)1101 (14)1110 (15)1111 (16)

off*off*off*off*off*off*off*off*off*off*off*off*off*off*off*off*

210

2210

3210

4210

5210

6210

7210

8210

9210

10210

11210

12210

13210

14210

15210

16210

211

2211

3211

4211

5211

6211

7211

8211

9211

10211

11211

12211

13211

14211

15211

16211

212

2212

3212

4212

5212

6212

7212

8212

9212

10212

11212

12212

13212

14212

15212

16212

213

2213

3213

4213

5213

6213

7213

8213

9213

10213

11213

12213

13213

14213

15213

16213

214

2214

3214

4214

5214

6214

7214

8214

9214

10214

11214

12214

13214

14214

15214

16214

215

2215

3215

4215

5215

6215

7215

8215

9215

10215

11215

12215

13215

14215

15215

16215

216

2216

3216

4216

5216

6216

7216

8216

9216

10216

11216

12216

13216

14216

15216

16216

ECE 4510/5530

135

RTI Control Register (RTICTL)

• RTR[6:4] — Real Time Interrupt Prescale Rate Select Bits– These bits select the prescale rate for the RTI. See Table 3-2.

• RTR[3:0] — Real Time Interrupt Modulus Counter Select Bits– These bits select the modulus counter target value to provide additional

granularity• Therefore, for RTICTL with 1 and 2^15

– 1 RTR[3:0] = 0000– 2^14 RTR[6:4] = 110– RTICTL = 0 110 0000 = $60


ECE 4510/5530

136

CRG Interrupt Enable Register (CRGINT)


• RTIE — Real Time Interrupt Enable Bit.– 1 = Interrupt will be requested whenever RTIF is set.– 0 = Interrupt requests from RTI are disabled.

• LOCKIE — Lock Interrupt Enable Bit– 1 = Interrupt will be requested whenever LOCKIF is set.– 0 = LOCK interrupt requests are disabled.

• SCMIE — Self Clock Mode Interrupt Enable Bit– 1 = Interrupt will be requested whenever SCMIF is set.– 0 = SCM interrupt requests are disabled.

• RTI Interrupt Enable - CRGINT Register– CRGINT = 1 00 0 00 0 0 = $80

ECE 4510/5530

137

RTI Timer Code (1).area prog(abs)PTT = $0240 ; Port address for Port TDDRT = $0242 ; DDR for Port TCRGFLG = $0037 ; Register addressCRGINT = $0038 ; Register addressRTICTL = $003B ; Register addressXcount = 50 ; Outer Loop Count value.org 1100OuterCount: .byte Xcount ; global outer loop count addressLedValue .byte 0 ; global value of the LED.text_main::

ldx #RTI_isr ;Load start address of ISRstx $3E70 ;Store in the RTI vector locationldaa #$FF ;set Port T as output portstaa DDRTldaa LedValue ; set the initial LED valuestaa PTTldaa #$60 ;set RTICTLstaa RTICTLsei ; set interrupt mask (redundant)ldaa CRGINToraa #$80 ; set the RTIE interruptstaa CRGINT cli ; clear interrupt mask (global int enable)

ECE 4510/5530

138

Main Loop and ISR Code (2)

mainloop: nop ; provide some instructions that can be interruptednopbra mainloop

.org $1500RTI_isr:

lda CRGFLG ; The RTI Int Flag must be resetoraa #$80 ; Writing a 1 to bit 7 resets RTIFstaa CRGFLG ;lda OuterCount ; Load outer count valuedeca ; decriment the counterbeq LedChange ; change the LEDstaa OuterCount ; save the new count valuerti ; return from interrupt

LedChange :lda #Xcount ; restore outer loop countstaa OuterCount ; save the new count valuelda LedValue ; load the current LED byteinca ; increment staa LedValue ; store the new LED value to memorystaa PTT ; write the new LED value to the LEDsrti ; return from interrupt

ECE 4510/5530 Microcontroller Applications Chapter 6bazuinb/ECE4510/Ch06.pdf · 2013-01-23 · ECE...

Documents

Transcript of ECE 4510/5530 Microcontroller Applications Chapter 6bazuinb/ECE4510/Ch06.pdf · 2013-01-23 · ECE...