ECE 4510/5530Microcontroller Applications

Chapter 9Serial Communication Interface

Dr. Bradley J. BazuinAssociate Professor

Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences

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Chapter 9

• Serial Communication Interface (SCI)– Simple ASCII serial transmission– EIA-232 or RS-232

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Memory Addresses

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Adapt9S12DP512 I/O Pins

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Why Serial Communication?

• Parallel data transfer requires many I/O pins. This requirement prevents the microcontroller from interfacing with as many devices as desired in the application.

• Many I/O devices do not have high enough data rate to justify the use of parallel data transfer.

• Data synchronization for parallel transfer is difficult to achieve over a long distance. This requirement is one of the reasons that data communications are always using serial transfer.

• Consider cost … fewer wires or traces

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What is SCI?

• An interface designed to transfer data only in asynchronous mode that utilizes the EIA-232 standard.

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Asynchronous Serial Data Communication

• It is often used for data communication between a DTE and a DCE with or without a modem.– DTE stands for data terminal equipment and can be either a computer or a

terminal.– DCE stands for data communication equipment. A modem is a DCE.

• A basic data communication link is shown.

• There are three kinds of data communication links:– Simplex link (one way)– Half-duplex link (one way at a time)– Full-duplex link (both ways simultaneously)

DTE DTEDCE DCE

Computeror terminal

Computeror terminal

Modem Modem

Communication link

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(a) Point-to-point Station Station

M aster

Slave 1 Slave 2 Slave n......

(b) M ulti-drop

Figure 9P .2 Po int-to -point and multi-drop communication links

Types of Communication Link Configuration

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The RS232 Standard

• Was the most widely used physical level interface for data communication– Specifies 25 interchange circuits for DTE/DCE use– Was established in 1960 by Electronics Industry Association (EIA)– Was revised into RS232C in 1969– Was revised into RS232D in 1987– Was revised to RS232E in 1991/1992 and

renamed as EIA/TIA-232-E– It has been superseded by TIA-232-F (Sept 1997)

• Four aspects: electrical, functional, procedural, and mechanical

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The EIA-232E Electrical Specifications (1 of 3)

• The interface is rated at a signal rate of < 20 kbps.– The signal can transfer correctly within 15 meters.

• Voltage of Physical Layer Output– The maximum driver output voltage (with circuit open) is -25 V to

+25 V.– The minimum driver output voltage (loaded output) is -25 V to -5

V and +5 V to +25 V.– The minimum driver output resistance when power is off is 300 .

• Voltage of Physical Layer Input– The receiver input voltage range is -25 V to +25 V.– The receiver output is high when input is open circuit.– A voltage more negative than -3 V at the receiver input is

interpreted as a logic 1.– A voltage more positive than +3 V at the receiver input is

interpreted as a logic 0.

The EIA-232E Electrical Specifications (2 of 3)

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Table 9 .1 Func tio ns o f EIA-2 3 2 -E s ignals

P in N o . C irc uit D e sc riptio n

1 - Shie ld2 B A Transmitted da ta3 B B R e ce ive d da ta4 C A /C J R e quest to send/rea dy for rece iving1

5 C B C lea r to send6 C C D C E rea dy7 A B Signa l common8 C F R e ce ive d line signa l de tec tor9 - (re se rved for te sting)10 - (re se rved for te sting)11 - unassigne d3

12 SC F/C I Sec ondary re ce ive d line signa l de tec tion/da ta ra te se le c tor (D C E source )2

13 SC B Sec ondary c le a r to send14 SB A Sec ondary tra nsmitted da ta15 D B Transmitte r s igna l e le me nt timing (D C E sourc e )16 SB B Sec ondary re ce ive d da ta17 D D R e ce ive r signa l e lement timing18 LL Loca l loopbac k19 SC A Sec ondary re quest to send20 C D D TE rea dy21 R L/C G R e mote loopbac k/signa l qua lity de tec tor22 C E R ing indica tor23 C H /C I D a ta s igna l ra te se lec tor (D TE/D C E sourc e )2

24 D A Transmitte r s igna l e le me nt timing (D TE source )25 TM Test mode

1. W hen ha rdw a re flow control is required, c ircuit C A may ta ke on the func tiona lity of c ircuit C J. This is one c ha nge from the former EIA -232.2. For designs using inte rc ha nge c irc uit SC F, inte rchange c ircuits C H and C I a re a ssigne d to pin 23. If SC F is not use d, C I is a ssigned to pin 12.3. P in 11 is unassigned. It w ill not be a ssigned in future ve rsions of EIA -232. H ow e ver, in inte rna tiona l s tanda rd ISO 2110, this pin is a ssigne d to se le c t transmit freque ncy.

The EIA-232E Electrical Specifications (3 of 3)

25 pin definition

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Signal Name

Protective groundTransmitted dataReceived dataRequest to sendClear to sendData set readySignal groundCarrier detectReservedReserved

Secondary carrier detectSecondary clear to send

Secondary transmitted dataTransmit clock

Secondary received dataReceiver clock

UnassignedSecondary request to send

Data terminal readySignal quality detect

Ring indicatorData rate selectTransmit clock

Unassigned

Signal Name SignalDirection

Bothto DCEto DTEto DCEto DTEto DTEBoth

to DTE

to DTEto DTE

Both

to DCEto DTE

SignalDirection

to DTEto DTE

to DCEto DCEto DTEto DTE

to DCE

Figure 9.1 EIA-232-E connector and pin assignment

123456789

10111213

141516171819202122232425

Unassigned

EIA-232-E Mechanical Specification (1 of 2)

• Specifies a 25-pin connector (DB25)• Specifies exact dimensions of each pin

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EIA-232-E Mechanical Specification (2 of 2)

• Only a small subset of the 25 pins are actually used in most data communications.

• Nine-pin is introduced to reduce the size and cost of the connector. (DB9 )

Old back panel PC Com port connectors

Another connector was the old PC mouse and keyboard circular connectors.

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EIA-232-E Procedural Specification (1 of 2)

• Define the sequence of events that occurs during data transmission.

• Examples: Case 1. Two DTEs connected via a point-to-point link using a modem

• Signal ground (GND) – (Voltage reference for other pins)• Transmitted data (Tx) – (output from uP, serial data transmission)• Received data (Rx) – (input to uP, serial data received)Hardware Handshaking• Request to send (RTS) – (output from uP, connect to CTS if not used)• Clear to send (CTS) – (input to uP, connect to RTS if not used)State of the DTEs and what the “line” is doing• Data set ready (DSR) – (input to uP, set high if not used)• DTE Ready (DTR) – (output from uP, pair with DSR, set high if not used)• Carrier detect (CD) – (input to uP, the phone/modem is ringing)• Ring Indicator (RI) – (input to uP, the phone is ringing , not required)

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TxDRxDCD

CTS

DSRGND

RTS

TxDRxDCDCTS

DSRGND

RTS

Computer(DTE)

Modem(DCE)

TxDRxDCD

CTS

DSRGND

RTS

TxDRxDCDCTS

DSRGND

RTS

Direct link

Computer(DTE)

Modem(DCE)

Figure 9.2 Point-to-point asynchronous connection

EIA-232-E Procedural Specification (2 of 2)

Null modem cable: Computer to Computer

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Local Remote1. DCE asserts DSR

2. DTE asserts RTS

3. DCE asserts CTS

4. DTE starts to senddata (to local DCE)

5. DCE sends out a carrier and then themodulated data 6. DCE asserts CD

7. DTE waits for arrival of data

8. DCE sends outdemodulatedreceived data

9. DTE receivesdemodulated data

Time

Sequence of Events Occurred During Data Transmission Over Dedicated Link

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EIA-232-E Procedural Specification Example 2 (1 of 2)

• Case 2. Two DTEs (data terminal equipment) exchange data through a public phone line. EIA-232-E signals involved:– Signal ground (GND)– Transmitted data (Tx)– Received data (Rx)– Request to send (RTS)– Clear to send (CTS)– Data set ready (DSR)– Carrier detect (CD)– Data terminal ready (DTR)– Ring indicator (RI)

• The signal DTR is used by the DTE to indicate its intention to make a call or accept a call.

• The signal RI is used by the DCE to indicate that there is an incoming call.

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TxDRxD

RICD

CTSRTSDSRDTRGND

TxDRxDRICDCTSRTSDSRDTRGND

TxDRxD

RICD

CTSRTSDSRDTRGND

TxDRxDRICDCTSRTSDSRDTRGND

Phone line

Computer(DTE)

Computer(DTE)

Modem(DCE)

Modem(DCE)

Figure 9.3 Asynchronous connection over public phone line

EIA-232-E Procedural Specification Example 2 (2 of 2)

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Local Remote (receiving side)

time

Connection establishment phase

(transmission side)

1. DTE asserts DTR

2. DCE dials the phone number 3. DCE detects the ring

and asserts RI4. DTE asserts DTR

to accept the call

5. DCE sends out acarrier and asserts DSR6. DCE asserts DSR

and CD and also sends out a carrierfor full duplex operation

7. DCE asserts CD(full duplex operation)

Sequence of Events During Data Transmission Over Public Phone Line (1 of 2)

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Local Remote (receiving side)(transmission side)

time

Data transmissionphase

1. DTE asserts RTS

2. DCE asserts CTS

3. DTE sends outdata to DCE 4. DCE modulates data

and sends it out 5. DCE demodulates data and forwards the data to DTE 6. DTE receives data

Disconnectionphase

1. DTE drops RTS2. DCE drops CTS

and drops the carrier 3. DCE deassertsCD & DSR

4. DTE deasserts DTR

Sequence of Events During Data Transmission Over Public Phone Line (2 of 2)

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Data Format for Asynchronous Data Communication

• Data is transmitted character by character bit-serially.• A character consists of

– one start bit (0)– 7 to 8 data bits (often, an ASCII character plus a parity bit)– an optional parity bit– one, or one and a half, or two stop bits (1)– least significant bit is transmitted first– most significant bit is transmitted last

Note: Transceivers invert the signal to the appropriate logical and voltage levels of the physical layer.

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Example: How to Detect the Arrival of Start Bit

• Use a clock signal with frequency at least 16 times that of the data rate to sample the RxD signal.

• When the RxD pin is idle (high) for at least three sampling times and a falling edge follows, the SCI circuit checks the third, fifth, and seventh samples after the first sample. If the majority of them are low, then the start bit is considered detected.

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Example: How to Determine the Logic Value of a Data Bit

• Use a clock signal with frequency at least 16 times that of the data rate to sample the incoming data.

• Take the majority function of the eighth, ninth, and tenth samples. If the majority of them are 1s, then the logic value is determined to be 1.

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0 1 1 0 0 11 1 10

( a) o utput wave fo rm o n m ic ro c o ntro l le r in te r f ac e

0 1 1 1 0 0 0 1 10

(b) o utput wave fo r m o n E IA- 2 3 2 -E in te r f ac e

F igure 9 .6 D ata fo rm at fo r le t te r g

Example 9.1

• Sketch the output of the letter g when it is transmitted using the format of one start bit, 8 data bit, and 1 stop bit.

• Solution:– The ASCII code of letter g is $67 or %01100111. This code will be

followed by a stop bit. The output from the DTE should be:

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Data Transmission Errors

• Framing error– A character is not properly framed by a stop bit

• Receiver overrun– One or more characters received, but not read by the CPU

• Parity error– Odd number of bits change value

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Figure 9.7 Null Modem connection

Signal Name

FG (frame ground)TD (transmit data)RD (receive data)RTS (request to send)CTS (clear to send)SG (signal ground)DSR (data set ready)CD (carrier detect)DTR (data terminal ready)DTR (data terminal ready)

DB25 pin DB9 pin

DTE 1 DTE 2

DB9 pin DB25 pinSignal Name

12345768

2020

-327856144

-238754416

132547

202086

FGRDTDCTSRTSSG

DTRDTRCDDSR

Null Modem Connection

Null modem cable: Computer to Computer

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The HCS12 SCI Subsystem (1 of 3)

• An HCS12 device may have one or two serial communication interface. These two SCI interfaces are referred to as SCI0 and SCI1. – Use the data format of one start, eight or nine data bits, and one stop bit. The

collection of the start bit, eight or nine data bits, and the stop bit is called a frame.– The SCI function supports parity checking. This option requires the use of 9-bit

data format. • One SCI channel uses two signal pins from Port S.

– SCI0 shares the use of PS0 (RxD0) and PS1 (TxD0)– SCI1 shares the use of PS2 (RxD1) and PS3 (TxD1).

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The HCS12 SCI Subsystem (2 of 3)

• The SCI has the capability to send break to attract the attention of the other party of communications.– A break is defined as the transmission or reception of logic 0 for a frame or longer

time.• The SCI supports hardware parity for transmission and reception.• The SCI supports idling line and address mark wakeup, which is useful in

multi-drop environment to reduce the software overhead.

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SCI data register

Receive shift register

Receive and wake up control

BAU

Dge

nera

tor

16 Data format control

Transmit control

Transmit shift register

SCI data register

Busclock

RxDInterrupt

generation

Interruptgeneration

IdleIRQ

RDRF/ORIRQ

TDREIRQ

TCIRQ

ORI

NG

IRQto CPU

TxD

Figure 9.8 HCS12 SCI block diagram

Status Register 1

Status Register 2

The HCS12 SCI Subsystem (3 of 3)

Registers Outlined in red

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SCI Registers• Baud Rate Registers – sets the serial bit rate• SCI Control Register 1 – general set-up• SCI Control Register 2 – interrupt and other enables• SCI Status Register 1 – important operation bits• SCI Status Register 2 – additional status bits• SCI Receive Data Register – input register when data has been received• SCI Transmit Data Register – output register when data is to be sent

• D-Bug12 initializes all the registers so ECE2510 does not have to.In ECE4510 you will have to do this!

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7 6 5 4 3 2 1 0

reset: 0 0 0 0 0 0 0 0

SBR12 SBR11 SBR10 SBR90 0 0 SBR8

Figure 9.9 SCI baud rate control register

7 6 5 4 3 2 1 0

0 0 0 0 0 1 0 0

SBR4 SBR3 SBR2 SBR1SBR7 SBR6 SBR5 SBR0

(a) SCI baud rate control register high (SC0BDH/SC1BDH)

(b) SCI baud rate control register low (SC0BDL/SC1BDL)

reset:

Baud Rate Generation (1 of 2)

• The HCS12 SCI module uses a 13-bit counter to generate this clock signal.

• The baud rate generator divides down the E clock to derive the clock signal for reception and transmission.

• The user writes an appropriate value into the SCIxBDH and SCIxBDL (x = 0 or 1) register pair to set the baud rate.

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Table 9.2 Baud rate generationDesired SCIbaud rate

Baud rate divisor forfE = 24 MHz

Baud rate divisor forfE = 16 MHz

3006001200240048009600

14,40019,20038,400

5000250012506253131561047839

33331667833417208104695226

Baud Rate Generation (2 of 2)

• The 13-bit value to be written into the baud rate generator register is the rounding of the following expression:

RateBaudfSBR ClkE _16

Baud Rate Counter

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E-Clock24000000

Desired Rate Ratio Remainder Use Actual Rate Error300 80000 5000 5000 300.00 0.000%600 40000 2500 2500 600.00 0.000%

1200 20000 1250 1250 1200.00 0.000%4800 5000 312.5 312 4807.69 -0.160%4800 5000 312.5 313 4792.33 0.160%9600 2500 156.25 156 9615.38 -0.160%

14400 1666.666667 104.1666667 104 14423.08 -0.160%19200 1250 78.125 78 19230.77 -0.160%28800 833.3333333 52.08333333 52 28846.15 -0.160%38400 625 39.0625 39 38461.54 -0.160%57600 416.6666667 26.04166667 26 57692.31 -0.160%

115200 208.3333333 13.02083333 13 115384.62 -0.160%

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7 6 5 4 3 2 1 0

reset: 0 0 0 0 0 0 0 0

M WAKE ILT PELOOPS SCISWAI RSRC P T

Figure 9.10 SCI control register 1 (SC0CR1/SC1CR1)

LOOPS: Loop select bit 0 = loop operation disabled 1 = loop operation enabledSCISWAI: SCI stop in wait mode 0 = SCI enabled in wait mode. 1 = SCI disabled in wait mode.RSRC: Receiver source bit When LOOPS = 1, the RSRC bit determines the source for the receiver shift register 0 = receiver input connected to the transmitter internally (not TxD pin). 1 = receiver input connected extrenally to the transmitted (TxD pin)M: Data format mode bit 0 = one start bit, eight data bits, one stop bit 1 = one start bit, nine data bits, one stop bitWAKE: Wakeup condition bit 0 = idle line wakeup 1 = address mark wakeup (last data bit set)ILT: Idle line type bit 0 = idle character bit count begins after start bit 1 = idle character bit count begins after the stop bitPE: parity enable bit 0 = parity disabled 1 = parity enabledPT -- parity type bit (for both transmit and receive) 0 = even parity selected 1 = odd parity selected

The SCI Control Registers (1 of 2)

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7 6 5 4 3 2 1 0

valueafter reset 0 0 0 0 0 0 0 0

ILIE TE RE RWUTIE TCIE RIE SBK

Figure 9.11 SCI control register 2 (SC0CR2/SC1CR2)

TIE: Transmit interrupt enable bit 0 = TDRE interrupt disabled 1 = TDRE interrupt enabled.TCIE: Transmit complete interrupt enable bit 0 = TC interrupt disabled 1 = TC interrupt enabledRIE: Receiver full interrupt enable bit 0 = RDRF and OR interrupts disabled 1 = RDRF and OR interrupt enabledILIE: Idle line interrupt enable bit 0 = IDLE interrupt disabled 1 = IDLE interrupt enabledTE: Transmitter enable bit 0 = transmitter disabled 1 = transmitter enabledRE: Receiver enable 0 = receiver disabled 1 = receiver enabledRWU: Receiver wakeup bit 0 = normal SCI receiver 1 = enables the wakeup function and inhibits further receiver interrupts. Normally, hardware wakes up the receiver by automatically clearing this bit.SBK: Send break bit 0 = no break characters 1 = generate a break code, at least 10 or 11 contiguous 0s. As long as SBK remains set, the transmitter sends 0s.

The SCI Control Registers (2 of 2)

D-Bug12 sets these in order to function

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SCI Status Registers (1 of 2)

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7 6 5 4 3 2 1 0

reset: 0 0 0 0 0 0 0 0

0 0 BK13 TXDIR0 0 0 RAF

Figure 9.14 SCI status register 2 (SCI0SR2/SCI1SR2)

BK13: Break transmit character length 0 = Break character is 10- or 11-bit long 1 = Break character is 13- or 14-bit longTXDIR: transmit pin data direction in single-wire mode 0 = TxD pin to be used as an input in single-wire mode 1 = TxD pin to be used as an output in single-wire modeRAF: receiver active flag RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 = no reception in progress 1 = reception in progress

SCI Status Registers (2 of 2)

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Character Transmission

• The block diagram of the SCI transmitter is shown in Figure 9.12.• To transmit a character from the SCI module, the user writes the data

bits into the SCIxDRH and SCIxDRL registers.– The data bits in SCIxDRH and SCIxDRL registers will be transferred to

the transmit shift register and shifted out serially from the TxD pin.• Each time the SCI transfers data from the buffer SCIxDRH/L to the

transmit shift register, it also sets the TDRE flag in the SCIxSR1 register.– The setting of the TDRE flag indicates that the MCU can write new data

into the SCI data register. • When the transmit shift register is not transmitting data, the TxD signal

goes to idle state.– When both the transmit data registers and shift register are empty, the TC

flag in the SCIxSR1 register is set to 1. – An interrupt may be requested to the MCU if the TDRE or TC flag is set

to 1.

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BAUD dividerBusclock

SBR12-SBR0

16 SCI Data Register

H 8 7 6 5 3 2 1 0 L

STO

P

STA

RT

M

T8

Paritygeneration

PEPT

Transmitter control

load

from

SC

IDR

Shift

ena

ble

prea

mbl

e (a

ll on

es)

Brea

ks (a

ll 0s

)TE SBKTDRE

TIE

TCTCIE

TDRE interrupt request

TC interrupt request

LoopControl

LoopsRSRC

To RxD

TxD

Figure 9.12 SCI transmitter block diagram

Internal Bus

MSB

4

Transmitter Block Diagram

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Send Break Characters

• A break character is represented by eight or nine logic 0 data bits depending on the character data length.

• Whenever one party in the data communications discovers an error, it can send break characters to discontinue the communication and start over again.

• To send break characters, the user sets the SBK bit in the SCIxCR1 register to 1.

• As long as the SBK bit is 1, the transmitter logic continuously sending out the break character.

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Idle Characters

• An idle character contains all 1s and has no start, stop, or parity bit.

• Depending on the character data length, an idle character can be eight or nine 1s.

• If the TE bit in the SCIxCR2 register is cleared during a transmission, the TxD signal becomes idle after the completion of the transmission in progress.

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Character Reception (1 of 2)

• The block diagram of the SCI receiver is shown in Figure 9.15.

• The SCI receiver can handle either 8- or 9-bit characters. – When receiving 9-bit data, the R8 bit of the SCIxDRH register

holds the ninth bit. – During an SCI reception, the receive shift register shifts in a frame

from the RxD pin.

• After a complete frame is shifted into the receive shift register, the data portion of the frame is transferred to the SCI data register. The receive data register full flag (RDRF) in the SCIxSR1 register is set to 1.

• An interrupt for RDRF may be requested to the MCU if it is enabled.

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BAUD dividerBusclock

SBR12-SBR0 SCI Data Register

H 8 7 6 5 3 2 1 0 L

STO

P

STA

RT

PEPT

IDLEILIE

RIE

IDLE interrupt request

RDRF/OR interrupt request

Figure 9.15 SCI receiver block diagram

Internal Bus

11-bit receive shift register

4

FENFPE

RWUWakeup

logic

Paritychecking

R8

RDRFOR

All

ones

MSB

WAKEILT

M

RERAF

Datarecovery

RxD

Loopcontrol

FromTxD

LOOPSRSRC

Character Reception (2 of 2)

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Transmitter

Receiver

TxD

RxD

Figure 9.16 Single-wire operation

Single-Wire Operation

• In this operation, the RxD pin is disconnected from the SCI module.• The SCI module uses the TxD pin for both receiving and transmitting

as illustrated in Figure 9.16. This is commonly called Loop-Back– Single-wire operation is enabled by setting the LOOPS and the RSRC bits

in the SCIxCR1 register.– Setting the LOOPS bit disables the path from the RxD pin to the receiver.

Setting the RSRC bit connects the receiver input to the output of the TxD pin driver.

– Both transmitter and receiver must be enabled.• The TXDIR bit determines whether the TxD pin is going to be used as

an input (TXDIR = 0) or output (TXDIR = 1) in this mode of operation.

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Flow Control of UART in Asynchronous Mode

• The SCI module will transmit data as fast as the baud rate allows.– In some circumstances, the software may not be able to read data as fast as the data

is received.– There is a need for the MCU to tell the transmitting device to suspend transmission

of data temporarily.– Similarly, the HCS12 may need to be told to suspend transmission temporarily.

This is done by flow control.• There are two common methods of flow control: XON/XOFF and hardware.

– XON/XOFF is implemented completely in software, but requires a full-duplex communication.

– When incoming data needs to be suspended, an XOFF byte is transmitted back to the other device that is transmitting.

– To start the other device transmitting again, an XON character is transmitted.– The XON and XOFF characters have the ASCII code of 0x11 and 0x13,

respectively.• Hardware flow control requires the use of extra signals. Generally, an input

pin of the transmitter is controlled by the receiver. – Before transmitting any character, the transmitter needs to test the flow control

input pin.

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movb #$00,SC0BDH ; set up baud ratemovb #156,SC0BDL ; “movb #$4C,SC0CR1 ; select 8 data bits, address mark wakeupmovb #$0C,SC0CR2 ; enable transmitter and receiver

• Write an instruction sequence to configure the SCI0 0 to operate with the following parameters:

– 9600 baud (E clock is 24 MHz)– One start bit, 8 data bits, one stop bit – No interrupt– Address mark wakeup– Disable wakeup initially– Long idle line mode– Enable transmit and receive– No loop back– Disable parity checking

• Solution: The following instruction sequence will configure the SCI0 properly:

Example 9.2: configure the SCI0 0

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Interfacing SCI with EIA-232-E

• The SCI uses 0 V and 5 V to represent 0 and 1.– The EIA-232 signal Tx cannot be driven by the SCI TxD signal without

translation. The EIA-232 signal Rx cannot drive the SCI RxD signal without translation.

– Voltage level translation is required for the SCI signals to drive and be driven by the EIA-232 signals.

• Examples of EIA-232 driver chips include: – LT1080/1081 from Linear technology – ST232 from SGS Thompson – ICL232 from Intersil – MAX232 from MAXIM – DS14C232 from National Semiconductor – These chips are pin-compatible.

• The DS14C232 from National Semiconductor will be used in the following illustration.

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+5 V

+5 V EIA-232-Eoutputs

EIA-232-Einputs

TTL/CMOSinputs

TTL/CMOSinputs

TTL/CMOSoutputs

TTL/CMOSoutputs

Figure 9.18 Pin assignments and connections of the DS14C232

10

11

12

9

15

8

13

7

14

R2IN

R1IN

5K

5K

T1IN

T2IN

R1OUT

R2OUT

T1OUT

T2OUT

1.0F

1.0F

1

3

4

5

1.0F

+5 V

16

V+

V-1.0F

2

6

VCC

GND

+-

C1+

C1-

C2+

C2-

6.3V

DC-to-DC Converter

C1

C2

R1

R2

D1

D2

C4

C3

Typical RS-232 Transceiver IC

Parts Kit RS-232 Transceiver ICMAX232IN• Meets or Exceeds TIA/EIA-232-F

and ITU• Recommendation V.28• Operates From a Single 5-V Power

Supply With 1.0-uF Charge-Pump Capacitors

• Operates Up To 120 kbit/s• Two Drivers and Two Receivers• ±30-V Input Levels• Low Supply Current . . . 8 mA

Typical• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

• Upgrade With Improved ESD (15-kV HBM) and 0.1-uF Charge-Pump Capacitors is

• Available With the MAX202• Applications

– TIA/EIA-232-F, Battery-Powered Systems,– Terminals, Modems, and Computers

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PS1/TxD

PS0/RxD

Note: Both CTS and RTS arejumpered to an I/O pin in casehardware handshake is needed

CTS*

RTS*

T1IN

T2IN

R1OUT

R2OUT

T1OUT

T2OUT

R1IN

R2IN

11

10

12

9

8

13

7

14

1

6

2

7

3

8

4

9

5

DCD

DSR

RxD

RTS

TxD

CTS

DTR

RI

GND

DB9 connector

DS14C232

Figure 9.19 Diagram of SCI and EIA232 DB9 connector wiring in SSE256 demo board

Interfacing with the Transceiver

• Interfacing the HCS12 SCI0 to the EIA-232 using the DS14C232 chip and implements the NULL modem connection so that this connection can talk to a PC directly.

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ASCII (American Standard Code for Information Interchange ) Table

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#include "c:\miniide\hcs12.inc"sendbrk: bset SCI0CR2, $01 ; turn on send break

ldy #1jsr delayby1msbclr SCI0CR2, $01 ; turn off send breakrts

#include “c:\miniide\delay.asm”

Example 9.3 Write a subroutine to send a break

• Write a subroutine to send a break to the communication port controlled by the SCI0 interface. The duration of the break is approximately 24,000 E clock cycles, or 1 ms at 24 MHz.

• Solution: A break character is represented by ten or eleven consecutive zeros and can be sent out by setting the bit 0 of the SCI0CR2 register.

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#include “c:\egnu091\include\hcs12.h”#include “c:\egnu091\include\delay.c”void send_break (void){

SCI0CR2 |= SBK; /* start to send break /delayby1ms(1);SCI0CR2 &= ~SBK; /* stop sending break */

}

Example 9.3: C-Code

• The C language version of the function:

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#include "c:\miniide\hcs12.inc"putcSCI0: brclr SCI0SR1,TDRE, putcSCI0 ; wait for TDRE to be set

staa SCI0DRL ; output the characterrts

void putcSCI0 (char cx){

while (!(SCI0SR1 & TDRE));SCI0DRL = cx;

}

Example 9.4: Subroutine to output a character

• Write a subroutine to output the character in accumulator A to the SCI0 channel using the polling method.

• Solution: The subroutine will wait until the bit 7 of SCI0SR1 register is set before sending out the character in accumulator A.

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putcSCI0 : brclr SCI0SR1,RDRF, putcSCI0 ; wait until RDRF bit is setldaa SCI0DRL ; read the characterrts

char getcSCI0 (void){

while ((SC0SR1 & RDRF) == 0);return (SCI0DRL);

}

Example 9.5 Write a subroutine to read a character

• Example 9.5 Write a subroutine to read a character from SCI0 using the polling method. Return the character in accumulator A.

• Solution: The subroutine will wait until the bit 5 of SCI0SR1 register (RDRF) is set before reading in the character in accumulator A.

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putsSCI0: ldaa 1,x+ ; get a character and move the pointerbeq done ; is this the end of the stringjsr putcSCI0bra putsSCI0

Done: rts

void putsSCI0 (char *cx){

while (!(*cx)) {putcSCI0(*cx);cx++;

}}

Example 9.6 Write a subroutine to output a string

• Example 9.6 Write a subroutine to output a string pointed to by index register X to the SCI0 using the polling method.

• Solution: This subroutine will call putcSCI0( ) repeatedly until all characters have been sent.

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CR = $0DgetsSCI0: jsr getcSCI0

cmpa #CR ; is the character a carriage return?beq exitstaa 1,x+ ; save the character in the buffer pointed to by Xbra getsSCI0 ; continue

exit: clr 0,x ; terminate the string with a NULL characterrts

void getsSCI0 (char *buf){

while ((*buf++ = getcSCI0()) != CR);*buf = 0; /* terminate the string with a NULL character */

}

Example 9.7 Write a subroutine to input a string from SCI0.

• Write a subroutine to input a string from SCI0. The string is terminated by the carriage return character and must be stored in a buffer pointed to by index register X.

• Solution: This subroutine will call getcSCI0( ) repeatedly until the carriage return character is

Using the stdio libraryInput-output manipulation functionsName Notesfgetc returns one character from a filefgets gets a string from the file (ending at newline or end-of-file)fputc writes one character to a filefputs writes a string to a filegetc reads and returns a character from a given stream and advances the file position indicator; it is allowed to

be a macro with the same effects as fgetc, except that it may evaluate the stream more than oncegetchar has the same effects as getc(stdin)gets reads characters from stdin until a newline is encountered and stores them in its only argumentprintf used to print to the standard output streamfprintf used to print to a filesprintf used to print to a char array (C string)putc writes and returns a character to a stream and advances the file position indicator for it; equivalent to

fputc, except that a macro version may evaluate the stream more than onceputchar has the same effects as putc(stdout)scanf, used to input from the standard input streamfscanf, used to input from a filesscanf, used to input from a char array (e.g., a C string)ungetc pushes a character back onto a streamputs outputs a character string to stdout

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