ECE 4510/5530Microcontroller Applications

Week 9

Dr. Bradley J. BazuinAssociate Professor

Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences

ECE 2510 2

Lab 7 & 8 Elements & Project 2

• Midterm Exam

• LCD Display for Calculator

• SPI, ADC/DAC and Temperature Measurement– SPI and ADC

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Problem 1

• See Lab 5, Task 2 • midterm example problem

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This waveform is designed to support a stepper motor “full stepping” driving operation, so the phases must be sequential and exactly equal to 1/2 of the total period. Assume that you are using a 24 MHz E-clock and that the PWM signal frequencies should all be 15 kHz. Hints 1: If the period count were a perfect multiple of 2 or 4, such as 400, each “channel” would be turned on for a count of 200 to create a perfect 200/400 duty cycle.Hint 2: While PWM.1 and PWM.5 are left aligned, does PWM.3 and PWM.7 look like they might be center aligned on a count of 200? If so, how do the period and duty cycle values differ?

Midterm Example Problem

PWMPRCLK = 0x44; // Prescale A and B by 16 (1.5 MHz)PWMCLK = 0x00; // Select A and B clocksPWMCTL |= PSWAI | PFRZ; // All 8 bit registers, stop clocks for W or FPWMCAE |= CAE2; // PWM.2 is center alignedPWMCAE &= ~(CAE4 | CAE0); // PWM.0 and PWM.4 are left alignedPWMPOL |= PPOL0; // PWM.0 is positive polarityPWMPOL &= ~(PPOL2 | PPOL4); // PWM.2 and PWM.4 are negative polarityPWMPER0 = 150; // Left aligned 150 count period (10 kHz)PWMPER2 = 75; // Center aligned 2 x 75 count period (10 kHz)PWMPER4 = 150; // Left aligned 150 count period (10 kHz)PWMDTY0 = 50; // Positive 50/150 duty cyclePWMDTY2 = 50; // Centered Negative (75-50)/75 duty cyclePWMDTY4 = 100; // Negative (150-100)/150 duty cyclePWME |= (PWME0 | PWME2 | PWME4); //Enable channel 0, 2 and 4

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Problem 2

The repeat period is to be 2 msec or 500 Hz with the sequential on times of 500 usec each. Compose the “main()” C program to initialize the ECT so that the sequence can be achieved and then wait in an infinite while loop. Four similar interrupt service routines are to be used to generate each of the on times for the four output compare timer channels.

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• See Lab 4, Task 4 for a single output compare operations.• See Example 8.4 in the textbook and notes (Week5_1) for a single output.

Example 8.4 Modified

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# include "mc9s12dp512.h"#define HiCnt 1200#define LoCnt 1800char HiorLo;void main (void){

asm(“sei"); // disable interrupt globallytimer_init();asm("cli"); // enable interrupt globallytimer5_start();

while(1);{ asm(“nop”); asm(“nop”); }

}interrupt void timer5_ISR (void){

if(HiorLo){TC5 += HiCnt;HiorLo = 0; }

else{TC5 += LoCnt;HiorLo = 1; }

}

void timer_init(void){

TSCR1 = 0x90; // enable TCNT and fast timer flag clearTSCR2 = 0x03; // disable TCNT interrupt, set prescaler to 8

TIOS |= OC5; // enable OC5 functionTFLG1 = 0xFF; // clear all CxF flags

}

void timer5_start(void){

extern char HiorLo;TCTL1 = 0x0C; // set OC5 action to be pull highCFORC = 0x20; // Force pin action to highTFLG1 = 0x0x20; // clear all C5F flagsTCTL1 = 0x04; // set OC5 pin action to toggleTC5 = TCNT + HiCnt; // start an new OC5 operationHiorLo = 0; // add LoCnt for the next OC5 operationTIE = 0x20; // enable OC5 interrupt locally

}

Problem 3

(a) Initialization function: Use port H (PTH) for the control signals and port P (PTP) for the data signals. Provide a function call that sets data direction for all control signals and assumes that the data bus will be an input. Note: for bi-directional data buses, signals are not driven by any connected device until required. Therefore, at initialization the data bus should be an input. (b) Write LCD function: Based on the data write timing diagram, compose a C-code function that pass an 8-bit value to the function and execute a write. (c) Read LCD function: Based on the data read timing diagram, compose a C-code function that reads an 8-bit value and provide it as the return value for the function.

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LCD Read and Write

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Data Read Timing

Data Write TimingTable of Min/Max Required Times

Time Item Symbol Min Max Unit Enable Cycle tCYCLE 1000 nsec Enable Pulse Width High Level tPWEH 450 nsec Enable Pulse Width Low Level tPWEL 350 nsec Address Set-up Time (RS,R/Wn) tAS 100 nsec Address Hold Time (RS,R/Wn) tAH 10 nsec Data Set-up Time tDSW 100 nsec Data Hold Time tDHR 20 nsec Data Read Delay Time tDDR 190 nsec

LCD Operation

The interface consists of three control signals and 8 parallel data bits. The control signals are register_select (RS), selecting control (low) or memory (high) registers, read/write_not (R/Wn), read or write operation select, and enable (E), the controller positive enable. The timing diagrams to perform a write and a read follow with times shown in the diagrams and table.

Control: Port H (PTH), 3 pinsRS Register Select 0 = control1=memoryR/Wn Read/Write not 0 = write 1=readE Enable 0 = not enabled 1= enabled

Data: Port P (PTP), 8 pins for 8 parallel bits

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LCD Initialization

• Port H has 3 outputs– DDRH for 3 outputs. DDRP = ?– Initial condition of outputs. PTH = ?

• RS don’t care• Read/Write not always in read when inactive• Enable always 0 when inactive

• DDRP for 8 bidirectional data lines– Should be inputs whenever not actively requiring an output signal– DDRP = ?

• Is there anything else?

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Prototype Time Delays: Write

• tAS 100 nsec min. 3 E-clock cycles• tPWEH 450 nsec min 11 E-clock cycles• tAH 10 nsec min. 1 E-clock cycles• tDSW 100 nsec nom. 3 E-clock cycles• tDHR 20 nsec min. 1 E-clock cycles• tDDR 190 nsec nom. 5 E-clock cycles• tPWEL 350 nsec min 9E-clock cycles• tCYCLE 1000 nsec min. 24 E-clock cyclesECE

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1) RS & Wn2) 3 nop3) E Enable4) 7 nop5) DDRP, Data6) 3 nop7) E Disable8) nop9) all to steady state(DDRP and R/Wn)

Prototype Time Delays: Read

• tAS 100 nsec min. 3 E-clock cycles• tPWEH 450 nsec min 11 E-clock cycles• tAH 10 nsec min. 1 E-clock cycles• tDSW 100 nsec nom. 3 E-clock cycles• tDHR 20 nsec min. 1 E-clock cycles• tDDR 190 nsec nom. 5 E-clock cycles• tPWEL 350 nsec min 9E-clock cycles• tCYCLE 1000 nsec min. 24 E-clock cyclesECE

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1) RS & read2) 3 nop3) E Enable4) 11 nop5) PTP input6) E Disable7) nop8) all to steady state

LCD INTERFACE

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LCD Display

• SSC2F16DLNW• See Data Sheet

– Mechanical– Electrical– Timing– Initialization sequence– Controller IC Hitachi HD44780U

• Note: code in textbook is setup for a 4-bit data, write only interface. Used on the Dragon demo board. p. 322-338.– Textbook notes follow.

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DB7

DB0

ER/W

RSVEE

VCCVSS

COM 16

LCDP (FRD7069)

SEG 160SEG 40

4 SEGMENT DRIVER x 4

CONTROLLERLSI

HD44780

Figure 7.35 Block diagram of a HD44780-based LCD kit

A HD44780-Based LCD Kit (1 of 3)• Display capability: 4 x 20• Uses the HD44780 as the controller as shown in Figure 7.35.• Pins DB7~DB0 are used to exchange data with the CPU.• E input should be connected to one of the address decoder output or I/O pin.• The RS signal selects instruction register (0) or data register (1).• The VEE signal allows the user to adjust the LCD contrast.• The HD44780 can be configured to display 1-line, 2-line, and 4-line information.• The pin assignment for character-based LCD module with less than and more than 80 characters are

shown in Table 7.7 and 7.8.

Table 7.7 Pin assignment for displays with less than 80 characters

Pin No. symbol I/O Function

123456789

1011121314

VSSVCCVEERS

R/WE

DB0DB1DB2DB3DB4DB5DB6DB7

---III

I/OI/OI/OI/OI/OI/OI/OI/O

Power supply (GND)Power supply (+5V)Contrast adjust0 = instruction input, 1 = data input0 = write to LCD, 1 = read from LCDenable signaldata bus line 0data bus line 1data bus line 2data bus line 3data bus line 4data bus line 5data bus line 6data bus line 7

A HD44780-Based LCD Kit (2 of 3)

PK4

PK6

PK5

PH7...PH0 DB7..DB0

E

RS

R/W

HD44780U-basedLCD ModuleHCS12 MCU

Figure 7.36a LCD interface example (8-bit bus, used in SSE256)

5V

VCC

VEE

GND

5V

PK0

PK1

PK5...PK2 DB7..DB4

RS

E

R/W

HD44780U-basedLCD ModuleHCS12 MCU

Figure 7.36b LCD interface example (4-bit bus, used in Dragon12)

5V

VCC

VEE

GND

5V

Interfacing the HD44780 with the HCS12

• One can treat the LCD kit as an I/O device and use an I/O port and several other I/O pins as control signals.

• The interface can be 4 bits or 8 bits. • To read or write the LCD successfully, one must satisfy the timing

requirements of the LCD. The timing diagrams for read and write are shown in Figure 7.37 and 7.38.

tA S

R/W

RS

E

DB0-DB7 Valid data

t E r

PW E H

tA H

t D D R

t CYCLE

t D H R

tEf

Figure 7.37 HD44780U LCD controller read timing diagram

tA S

R/W

RS

E

DB0-DB7 Valid data

t E r

PW E H

tA H

t D SW

t CYCLE

tH

tEf

Figure 7.38 HD44780U LCD controller write tim ing diagram

HD44780 Timing (1 of 2)

Table 7.15 HD44780U bus timing parameters (2 MHz operation)

MeaningSymbol

Enable cycle timeEnable pulse width (high level)Enable rise and decay timeAddress setup time, RS, R/W, EData delay timeData setup timeData hold time (write)Data hold time (read)Address hold time

tCYCLEPWEHtEr, tEftAStDDRtDSWtHtDHRtAH

Min Typ Max. Unit

500230

-40-

80105

10

---------

--

20-

160----

nsnsnsnsnsnsnsnsns

HD44780 Timing (1 of 2)

• Procedure to send a command to the IR register– Step 1

• Pull the RS and the E signals to low.– Step 2

• Pull the R/W signal to low.– Step 3

• Pull the E signal to high.– Step 4

• Output data to the output port attached to the LCD data bus. One needs to configure the I/O Port for output before writing data to the LCD kit.

– Step 5• Pull the E signal to low and make sure that the internal operation is complete.

Table 7.12 Register selection

RS R/W Operation

0011

0101

IR write as an internal operation (display clear, etc)Read busy flag (DB7) and address counter (DB0 to DB6)DR write as an internal operation (DR to DDRAM or CGRAM)DR read as an internal operation (DDRAM or CGRAM to DR)

Registers of HD44780

• The HD44780 has two 8-bit user accessible registers: instruction register (IR) and data register (DR).

• To write data into display data RAM or character generator RAM, the MCU writes into the DR register.

– The address of the data RAM should be set up with a previous instruction.

• The DR register is also used for data storage when reading data from DDRAM or CGRAM.

• The HD44780 has a busy flag that is output from the DB7 pin.• The HD44780 uses a 7-bit address counter to keep track of the address of the

next DDRAM or CGRAM location to be accessed.

Table 7.9 HD44780U instruction set

InstructionCode

RS R/W B7 B6 B5 B4 B3 B2 B1 B0Description Execution

time

Clear display

Cursor home

Entry mode set

Display on/offcontrol

Cursor /displayshift

Function set

Set CGRAMaddressSet DDRAMaddressRead busy flagand addresscounter

Write CGRAMor DDRAMRead fromCGRAM orDDRAM

Clears display and returns cursor to thehome position (address 0).Returns cursor to home position (address0). Also returns display being shifted to theoriginal position. DDRAM contents remainunchanged.Set cursor move direction (I/D), specifiesto shift the display (S). These operationsare performed during data read/write.Sets on/off of all display (D), cursor on/off (C) and blink of cursor positioncharacter (B).Sets cursor-move or display-(S/C), shiftdirection (R/L). DDRAM contents remainsunchanged.Sets interface data length (DL), number ofdisplay line (N) and character font (F).Sets the CGRAM address. CGRAM data issent and received after this setting.Sets the DDRAM address. DDRAM data issent and received after this setting.Reads busy flag (BF) indicating internaloperation is being performed and readsCGRAM or DDRAM address countercontents (depending on previousinstruction).Writes data to CGRAM or DDRAM.

Reads data from CGRAM or DDRAM.

1.64 ms

1.64 ms

40 s

40 s

40 s

40 s

40 s

40 s

0 s

40 s

40 s

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

1

BF

0

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

DL

0

0

0

1

S/C

N

0

0

1

D

R/L

F

0

1

I/D

C

*

*

1

*

S

B

*

*

CGRAM address

DDRAM address

CGRAM/DDRAMaddress

write data

read data

HD44780 Commands (1 of 4)

Bit name Settings

I/DSDCB

S/CR/LDLNF

BF

0 = decrement cursor position.0 = no display shift.0 = display off0 = cursor off0 = cursor blink off0 = move cursor0 = shift left0 = 4-bit interface0 = 1/8 or 1/11 duty (1 line)0 = 5x8 dots0 = can accept instruction

1 = increment cursor position1 = display shift1 = display on1 = cursor on1 = cursor blink on1 = shift display1 = shift right1 = 8-bit interface1 = 1/16 duty (2 lines)1 = 5 x 10 dots1 = internal operation in progress

Table 7.10 LCD instruction bit names

HD44780 Commands (2 of 4)

Table 7.11a DDRAM address usage for a 1-line LCD

Display sizeVisible

character positions DDRAM addresses1 * 8

1 * 161 * 201 * 241 * 321 * 40

00..0700..1500..1900..2300..3100..39

0x00..0x070x00..0x0F0x00..0x130x00..0x170x00..0x1F0x00..0x27

HD44780 Commands (3 of 4)

• The HD44780 has a display data RAM (DDRAM) to store data to be displayed on the LCD.

• The address range of DDRAM for 1-line, 2-line, and 4-line LCDs are shown in Table 7.11a, 7.11b, and 7.11c.

• The HD44780 has a character generator ROM that can generates 5 8 or 5 10 character patterns from a 8-bit code.

• The user can rewrite character patterns into the character generator RAM (CGRAM).

• Up to eight 5 8 patterns or four 5 10 patterns can be programmed.

Table 7.11b DDRAM address usage for a 2-line LCD

Display sizeVisible

character positions DDRAM addresses

2 * 162 * 202 * 242 * 322 * 40

00..1500..1900..2300..3100..39

0x00..0x0F + 0x40..0x4F0x00..0x13 + 0x40..0x530x00..0x17 + 0x40..0x570x00..0x1F + 0x40..0x5F0x00..0x27 + 0x40..0x67

Table 7.11c DDRAM address usage for a 4-line LCD

Display sizeVisible

character positions DDRAM addresses4 * 164 * 204 * 40

00..1500..19

00..39 on 1st controllerand 00..39 on 2nd

controller

0x00..0x0F + 0x40..0x4F + 0x14..0x23 + 0x54..0x630x00..0x13 + 0x40..0x53 + 0x14..0x27 + 0x54..0x670x00..0x27 + 0x40..0x67 on 1st controller and0x00..0x27 + 0x40..0x67 on 2nd controller

HD44780 Commands (4 of 4)

HD44780 Data Sheet

• This data sheet reads rather well to describe registers and the initialization procedure.

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