ECE 4510/5530Microcontroller Applications

Week 4 Lab 4 & Project #1

Dr. Bradley J. BazuinAssociate Professor

Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences

ECE 2510 2

Lab 4 Elements

• Hardware Development– Three terminal linear regulator– Enhanced Capture Timer (ECT) (Chap. 8)

• Modulus Down Counter– Serial Communication Interface (SCI) (Chap. 9)– Relay Driver– IRQn Interrupt (Chap. 6)

• Software Development– Polling vs. Interrupts

Timing and Timing Diagrams

• Lab 3 assignment timing elements

• You should know the timing before the code executes … and probably even before you start writing the code!

• When “inside” a microcontroller, things are driven by clocks. On the outside, if the clock is not visible it is all asynchronous.– Software affects things inside that are driven outside.

ECE 4510/5530

3

DRIVING A RELAY

ECE 4510/5530

4

ECE 4510/5530

5

Chapter 8

• Enhanced Capture Timer– 16-bit main counter with 7-bit prescaler– 8 programmable input capture or output compare channels– Two 8-bit or one 16-bit pulse accumulators

• Software– Textbook delay code

• Modulus counter– Interrupt driven periodicity

• Counter comparison

Electro-Mechanical Relay

ECE 4510/5530

6

16-pin Dip Compatible Relay

• no – normally open when the relay is not energized• nc – normally closed when the relay is no energized• com – the common node for connecting to no or nc

ECE 4510/5530

7

DPDT Configuration

Switching Terminology

• SPST – single pole single throw– One moving contact, one pole connected or not (on-off)

• SPDT – single pole double throw– One moving contact, two pole contacts when the switch is thrown

(used for a three-way switch)

• DPDT – double pole double throw– Two SPDT switches controlled by the same “switching” structure

ECE 4510/5530

8

Wikipedia Switch pagehttp://en.wikipedia.org/wiki/Switch

Driving the Relay

• Conceptually, the relay uses an electro-magnet to move a mechanical switch.– Spring loaded to stay in the NC

position– Current energizes the electro-

magnet to change the mechanical switch.

– Needs enough energy/attraction to overcome the spring.

– Not a great approach when strong physical vibration or impulses are expected.

ECE 4510/5530

9Our relays rated for 5V coil

Driving the Relay

• Electro-magnets have resistance and inductance.– Magnetic field results from winding wire around a metal rod.– Higher fields result from more windings using a longer wire which

also results in a higher “on” resistance.– Expect R-L switching delay.

– Expect voltage spike when “turned off”• Kick-back voltage diode protection

ECE 4510/5530

10

dtdILV

Lab 4 Relay Design

ECE 4510/5530

11

Alternate FET Design

• If the relay/diode combination were connected to the power supply an FET could be used as a pull-down.

ECE 4510/5530

12

IRQ INTERRUPT REVIEW

ECE 4510/5530

13

ECE 4510/5530

14

External (IRQ) interrupt

• IRQ pin the only external maskable interrupt signal available in the HCS12

• IRQ interrupt pin can be edge- triggered (falling edge) or level-triggered (low) signal

• The triggering method is selected by programming the IRQE bit of the “Interrupt Control register” (IRQCR)

• The IRQ pin interrupt has a local enable bit IRQEN bit, which is bit6 of the IRQCR (location $001E)

ECE 4510/5530

15

External (IRQ) Interrupt

• IRQCR Register

ECE 4510/5530

16

Making IRQ Level-sensitive

• Pros– Multiple interrupt sources can be tied to this pin. Whenever one of

the interrupt sources that are tied to the IRQ pin is low, an interrupt request will be detected by the HCS12

• Cons– Need to make sure that the IRQ signal has become inactive before

the IRQ service routine is complete if there is only one interrupt request pending.

ECE 4510/5530

17

Making IRQ Edge-sensitive

• Pros– Advantage of making the IRQ interrupt edge-sensitive (falling

edge) is that the user does not need to concern about the assertion time of the IRQ signal

• Cons– This approach is not appropriate in a noisy environment– Any noise spikes could generate an undesirable interrupt request

on the IRQ pin

Approach to be used in Lab #4

ECE 2510 18

External IRQ Example

Ex: • Assume that the IRQ pin of HCS12 is connected to a 1-Hz

digital waveform and PortB is connected to eight LED’s. • Write a program to configure PortB for output and enable

the IRQ interrupt• Write the service routine for the IRQ interrupt• Service routine for the IRQ interrupt should simply

increment a counter and output it to PortB (a parallel port on the microprocessor)

ECE 2510 19

External IRQ Example Steps

• Step1: Write ISR start address into the IRQ vector address• Step2: Configure PortB as output port• Step3: Disable global maskable interrupt pin• Step4: Enable IRQ interrupt, by enabling the local interrupt

in the interrupt register• Step5: Enable global maskable interrupts• Step6: Develop the interrupt service routine

ECE 2510 20

Using IRQ: Code (1 of 2)

.area prog(abs)PortB = $01DDRB = $03 ; DDRB is the data direction registers for PORTB to

; configure a I/O pin for output (1) or input (0), write a 1 or 0 to; the corresponding bit in the data direction register

IRQCR = $1E ;Defined as INTCR in Register definition file.text_main::

sei ; set interrupt mask (insure ints off)lds #$3C00 ; load the stack pointerldx #IRQ_isr ;Load start addr of ISRstx $3E72 ;Store in the vector locationldaa #$FF ;set PortB as output portstaa DDRBldaa #$00staa PortB ;Initial output to the port

ECE 2510 21

Using IRQ: Code (2 of 2)

ldaa #$C0staa IRQCR ; falling edge external interrupt enablecli ; clear interrupt mask to enable I interrupts

End: nop ; do nothingnopbra End

.org $1400IRQ_isr:

inc 1,SP ; increment A reg in interrupt stackstaa PortB ; let the PortB outputs be the A reg valuerti

ECE 2510 22

External IRQ Example C Code (1 of 2)

#include <hc12def.h>#include <mc9s12dp512.h> //header file to be includedchar i = 0;

main() {

asm(“sei”); // insure that INTs are offDDRB = 0xFF; // initialize port DDRPORTB = i; // provide an initial output valueINTCR = 0xC0; // setup and enable IRQasm(“cli”); // enable INTswhile() {asm(“nop”); // do nothingasm(“nop”); // do nothing}

}

ECE 2510 23

External IRQ Example C Code (2 of 2)

// The ISR code with pragma so an RTI is used for returning#pragma interrupt_handler IRQ_isrvoid IRQ_isr (void) {

i = i+1;PORTB = i;

}

#pragma abs_address:virq // Initialize the Interrupt Vector addressvoid (*interrupt_vectors[]) (void) = {IRQ_isr }; // Assign the function pointer #pragma end_abs_address // to the ISR

ENHANCED TIMER COUNTERINPUT CAPTURE

ECE 4510/5530

24

ECE 4510/5530

• Pulse width measurement: need to capture the rising and falling edges

one period

(a) Capture two rising edges

one period

(b) Capture two falling edges

Figure 8.9 Period measurement by capturing two consecutive edges

Pulse width

Rising edge Falling edge

Figure 8.10 Pulse-width measurement using input capture

Applications of Input Capture Function

• Event arrival time recording

• Period measurement: need to capture the main timer values corresponding to two consecutive rising or falling edges

ECE 4510/5530

• Time reference: input-capture used in conjunction with an output compare function

Start ofinterval

End ofinterval

e1 e2 e3 e4 ei ej

Figure 8.11 Using an input-capture function for event counting

... ...

Time t0

Time of reference(set up by signal edge)

Time t0 + delay

Time to activateoutput signal

(set up by output compare)Figure 8.12 A time reference application

Input Capture

• Interrupt generation: Each input capture function can be used as an edge-sensitive interrupt source.

• Event counting: count the number of signal edges arrived during a period

ECE 4510/5530

27

T

T

duty cycle =T

T* 100%

Figure 8.13 Definition of duty cycle

Duty Cycle Measurement

ECE 4510/5530

28

T

T

signal S1

signal S2

phase difference =T

T* 360o

Figure 8.14 Phase difference definition for two signals

Phase Difference Measurement

Timer Block Diagram (Queue Mode)

ECE 4510/5530

29

Prescaler 16-bit free-runningmain timer

pin logic Delaycounter

comparator

TCx capture/compareregister

TCxH hold register

EDG x

Prescalerbus clock÷1, 4, 8, 16

÷1,2,...,128 16-bit load register

16-bit modulusdown counter

Figure 8.36 Enhanced Input capture function block diagram in Queue mode (channels IC0..IC3 block diagram)

to other IC channels

bus clock

PTxone IC channel

(IC0..IC3)

pin logicPTicomparator

TCx capture/compareregisterMUX

EDG i

EDG jj = 8 - i

one IC channel(IC4..IC7)

ECE 4510/5530

30

Timer Counter Register (TCNT)

• Required for input capture and output compare functions. An up counter.

• Must be accessed in one 16-bit operation in order to obtain the correct value

• Three other registers related to the operation of the TCNT: TSCR1, TSCR2, TFLG2.

The 16-bit main timer is an up counter.

A full access for the counter register should take place in one clock cycle. A separate read (any mode)/write (test mode) for high byte and low byte will give a different result than accessing them as a word.

Read anytime.

Write has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).

The period of the first “count” after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.

ECE 4510/5530

31

7 6 5 4 3 2 1 0

TEN TSWAI TSFRZ TFFCA 0 0 0 0valueafter reset 0 0 0 0 0 0 0 0

TEN -- timer enable bit

0 = disable timer; this can be used to save power consumption1 = allows timer to function normally

TSWAI -- timer stops while in wait mode bit0 = allows timer to continue running during wait mode1 = disables timer when MCU is in wait mode

TSFRZ -- timer and modulus counter stop while in freeze mode0 = allows timer and modulus counter to continue running while in freeze mode1 = disables timer and modulus counter when MCU is in freeze mode

TFFCA -- timer fast flag clear all bit0 = allows timer flag clearing to function normally1 = For TFLG1, a read from an input capture or a write to the output compare channel causes the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.

Figure 8.2 Timer system control register 1 (TSCR1)

Timer System Control Register 1 (TSCR1)

• Setting and clearing the bit 7 of TSCR1 will start and stop the counting of the TCNT.

• Setting the bit 4 will enable fast timer flag clear function. If this bit is clear, then the user must write a one to a timer flag in order to clear it.

ECE 4510/5530

32

Timer System Control Register 2 (TSCR2)

• Bit 7 is the TCNT overflow interrupt enable bit.

• The clock input (E-CLK) to TCNT (E-Clock) can be prescaled by a factor selecting by bits 2 to 0 of TSCR2.

• TCNT can be reset to 0 when TCNT equals TC7 by setting bit 3 of TSCR2.

7 6 5 4 3 2 1 0

TOI 0 0 0 TCRE PR2 PR1 PR0valueafter reset 0 0 0 0 0 0 0 0

TOI -- timer overflow interrupt enable bit 0 = interrupt inhibited 1 = interrupt requested when TOF flag is setTCRE -- timer counter reset enable bit 0 = counter reset inhibited and counter free runs 1 = counter reset by a successful output compare 7 If TC7 = $0000 and TCRE = 1, TCNT stays at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT rolls over from $FFFF to $0000.

Figure 8.3 Timer system control register 2 (TSCR2)

PR2 PR1 PR0 Prescale Factor

00001111

00110011

01010101

1248163264

128

Table 8.1 Timer counter prescale factor

ECE 4510/5530

33

Timer Interrupt Flag 2 Register (TFLG2)

• Only bit 7 (TOF) is implemented. – Bit 7 will be set

whenever TCNT overflows.

TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one.

Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared).

Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.

TOF — Timer Overflow Flag

Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)

ECE 4510/5530

34

Using TCNT Values

• Once the counter is set up, the timer functions can be used to:

• In - Input-Capture:– The TCNT value is

captured when the desired external event occurs

• Out - Output-Compare:– The output occurs when

TCNT equals the preset register value

ECE 4510/5530

Rising edge Falling edge

or

Figure 8.4 Events represented by signal edges

Input Capture Functions (1 of 2)

• Physical time is often represented by the contents of the main timer.• The time when an event occurs can be recorded by latching the count

of the main timer when a signal edge arrives as illustrated in Figure 8.4.– The occurrence of an event is represented by a signal edge (rising or

falling edge).– The HCS12 has eight input capture channels. Each channel has a 16-bit

capture register, an input pin, edge-detection logic, and interrupt generation logic.

• Input capture channels share most of the circuit with output compare functions. For this reason, they cannot be enabled simultaneously.

ECE 4510/5530

36

• The selection of input capture and output compare is done by programming the TIOS register.

• The contents of the TIOS register are shown in Figure 8.5. Setting a bit select the output compare function. Otherwise, the input capture function is selected.

• The following instruction will enable the output compare channels 7...4 and input capture channel 3…0:

• movb #$F0,TIOS

7 6 5 4 3 2 1 0

IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0valueafter reset 0 0 0 0 0 0 0 0

Figure 8.5 Timer input capture/output compare select register (TIOS)

IOS[7:0] -- Input capture or output compare channel configuration bits 0 = The corresponding channel acts as an input capture 1 = The corresponding channel acts as an output compare

Input Capture Functions (2 of 2)

ECE 4510/5530

37

7 6 5 4 3 2 1 0

EDG7 B EDG7 A EDG6 B EDG6 A EDG5 B EDG5 A EDG4 B EDG4 Avalueafte r re se t 0 0 0 0 0 0 0 0

Figure 8 .5 Tim er co ntro l regis te r 3 and 4

7 6 5 4 3 2 1 0

EDG3 B EDG3 A EDG2 B EDG2 A EDG1 B EDG1 A EDG0 B EDG0 A

0 0 0 0 0 0 0 0

(a) Tim er co ntro l regis te r 3 (TCTL3 )

(b) Tim er co ntro l regis te r 4 (TCTL4 )

EDGnB EDGnA -- Edge co nfiguratio n

0 0 : Capture disabled0 1 : Capture o n ris ing edges o nly1 0 : Capture o n falling edges o nly1 1 : Capture o n bo th edges

Timer Control Register 3 and 4

• The signal edge to be captured is selected by TCTL3 and TCTL4.

• The edge to be captured is selected by two bits. The user can choose to capture the rising edge, falling edge, or both edges.

ECE 4510/5530

38

7 6 5 4 3 2 1 0

C7I C6I C5I C4I C3I C2I C1I C0I

reset: 0 0 0 0 0 0 0 0

Figure 8.7 Timer interrupt enable register (TIE)

C7I-C0I: input capture/output compare interrupt enable bits 0 = interrupt disabled 1 = interrupt enabled

Timer Interrupt Enable Register (TIE)

• The arrival of a signal edge may optionally generate an interrupt to the CPU.

• The enabling of the interrupt is controlled by the Timer Interrupt Enable Register.

ECE 4510/5530

39

7 6 5 4 3 2 1 0

C7F C6F C5F C4F C3F C2F C1F C0Freset: 0 0 0 0 0 0 0 0

Figure 8.8 Timer interrupt flag register 1 (TFLG1)

CnF: input capture/output compare interrupt flag bits 0 = interrupt condition has not occurred 1 = interrupt condition has occurred

Timer Interrupt Flag 1 Register (TFLG1)

• Whenever a signal edge arrives, the associated timer interrupt flag will be set to 1.

• Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit.

ECE 4510/5530

How to Clear a Timer Flag Bit

• In normal mode, write a 1 to the flag bit to be cleared (and only the flag bit to cleared).– movb #$01,TFLG1 ;will clear the C0F flag.

• C-code– TFLG1 = C0F; //clear the C0F Flag

• When the fast timer flag clear function is enabled (TFFCA bit in the TSCR register is set), a read from an input capture or a write into an output compare channel ($10–$1F) will cause the corresponding channel flag CnF to be cleared. See Figure 8.1.

ECE 4510/5530

Example 8.2: Period Measurement (1 of 2)

• Use the IC0 to measure the period of an unknown signal. The period is known to be shorter than 128 ms. Assume that the E clock frequency is 24 MHz. Use the number of clock cycles as the unit of the period.

Solution: • Since the input-capture register is 16-bit, the longest period of the

signal that can be measured with the prescaler to TCNT set to 1 is: – 2^16 ÷ 24 MHz = 2.73 ms.

• To measure a period that is equal to 128 ms, we have two options: – Set the prescale factor to 1 and keep track of the number of times the timer

counter overflows.– Set the prescale factor to 64 and do not keep track of the number of times

the timer counter overflows. • We will set the prescale factor to TCNT to 64

(2^16 ÷ 24 MHz /64 = 174.76 ms or 2 2/3 usec time steps). The logic flow for measuring the signal period is shown in Figure 8.16.

ECE 4510/5530

42

Start

Choose to capture the rising edgeSet the timer counter prescale factor to 16Enable the timer counter

Clear the C0F flag

C0F = 1?

yes

no

Saved the captured first edgeClear the C0F flag

C0F = 1?no

yes

Take the difference of the second and thefirst captured edges

Stop

Figure 8.16 Logic flow of period measurement program

Example 8.2: Period Measurement (2 of 2)

one period

(a) Capture two rising edges

one period

(b) Capture two falling edges

Figure 8.9 Period measurement by capturing two consecutive edges

ECE 4510/5530

43

#include "c:\miniide\hcs12.inc".org $1000edge1: .byte 2 ; memory to hold the first edgeperiod: .byte 2 ; memory to store the period.text_main::

movb #$90,TSCR1 ; enable timer counter and enable fast timer flags clearbclr TIOS,IOS0 ; enable input-capture 0movb #$06,TSCR2 ; disable TCNT overflow interrupt, set prescaler to 64movb #$01,TCTL4 ; capture the rising edge of PT0 signalmovb #C0F,TFLG1 ; clear the C0F flag

L1: brclr TFLG1,C0F,L1 ; wait for the arrival of the first rising edgeldd TC0 ; save the first edge and clear the C0F flagstd edge1

L2: brclr TFLG1,C0F,L2 ; wait for the arrival of the second edgeldd TC0subd edge1 ; compute the periodstd periodswi

Example 8.2: Assembly Program for Period Measurement

ECE 4510/5530

44

#include "c:\egnu091\include\hcs12.h"void main(void){

unsigned int edge1, period;TSCR1 = 0x90; /* enable timer counter, enable fast flag clear*/TIOS &= ~IOS0; /* enable input-capture 0 /TSCR2 = 0x06; /* disable TCNT overflow interrupt, set prescaler to 64 */TCTL4 = 0x01; /* capture the rising edge of the PT0 pin */TFLG1 = C0F; /* clear the C0F flag */while (!(TFLG1 & C0F)); /* wait for the arrival of the first rising edge */edge1 = TC0; /* save the first captured edge and clear C0F flag */while (!(TFLG1 & C0F)); /* wait for the arrival of the second rising edge */period = TC0 - edge1;asm ("swi");

}

Example 8.2: C Program for Period Measurement

ECE 4510/5530

Case 1: edge2 edge1pulse width = ovcnt × 216 + diff

Case 2: edge2 < edge 1pulse width = (ovcnt – 1) × 216 + diff

Example 8.3: Measure the Pulse Width

• Write a program to measure the pulse width of a signal connected to the PT0 pin. The E clock frequency is 24 MHz.

• Solution:– Set the prescale factor to TCNT to 32. Use clock cycle as the unit of

measurement. (1 1/3 usec time steps)– The pulse width may be longer than 2^16 clock cycles (87.4 msec). We need

to keep track of the number of times that the TCNT timer overflows. Let• ovcnt = TCNT counter overflow count• diff = the difference of two consecutive edges• edge1 = the captured time of the first edge• edge2 = the captured time of the second edge

– The pulse width can be calculated by the following equations:

Pulse width

Rising edge Falling edge

Figure 8.10 Pulse-width measurement using input capture

ECE 4510/5530

46

Star

t

over

flow

0Se

t up

to c

aptu

re th

e ris

ing

edge

.D

isab

le a

ll in

terr

upts

.

C0F

= 1

?

Cle

ar ti

mer

ove

rflo

w fl

ag.

Enab

le m

ain

timer

ove

rflo

w in

terr

upt.

C0F

= 1

?

Com

pute

the

diff

eren

ce o

f tw

o ed

ges.

Cle

ar C

0F fl

ag.

Save

the

first

cap

ture

d ed

ge.

yes

yes

no no

Is se

cond

edg

e sm

alle

r?

over

flow

ov

erflo

w -

1

Com

bine

the

resu

lts.

Stop

no

yes

Cle

ar T

OF

flag.

over

flow

o

verf

low

+ 1

.

Exec

ute

the

RTI

inst

ruct

ion.

TOV inter

rupt

Retu

rn fr

om in

terru

pt

Tim

er o

verf

low

inte

rrup

tse

rvic

e ro

utin

e

Figu

re 8

.17

Logi

c flo

w fo

r mea

surin

g pu

lse

wid

th o

f slo

w si

gnal

s

Example 8.3 Flow Diagram

Note: an interrupt is used

ECE 4510/5530

47

#include "c:\miniide\hcs12.inc".org $1000edge1: .byte 2overflow: .byte 2 ; overflow and pulse-width form a 32-bitpulse_width: .byte 2 ; long word for the solution.text_main::

movw #tov_isr,UserTimerOvf ; set up TCNT overflow interrupt vectorlds #$3C00 ; set up stack pointermovw #0, overflowmovb #$90, TSCR1 ; enable TCNT and fast timer flag clearmovb #$05, TSCR2 ; disable TCNT interrupt, set prescaler to 32bclr TIOS, IOS0 ; select IC0movb #$01, TCTL4 ; capture rising edgemovb #C0F, TFLG1 ; clear C0F flag

wait1: brclr TFLG1,C0F,wait1 ; wait for the first rising edgemovw TC0,edge1 ; save the first edge & clear the C0F flagmovb #TOF,TFLG2 ; clear TOF flagbset TSCR2,$80 ; enable TCNT overflow interruptcli ; "movb #$02,TCTL4 ; capture the falling edge on PT0 pin

wait2: brclr TFLG1,C0F,wait2 ; wait for the arrival of the falling edge

Example 8.3: Code (1)

ECE 4510/5530

ldd TC0subd edge1std pulse_widthbcc next ; is the second edge smaller?ldx overflow ; second edge is smaller, so decrementdex ; overflow count by 1stx overflow ; "

next swi

tov_isr movb #TOF, TFLG2 ; clear TOF flagldx overflowinxstx overflowrti

Example 8.3: Code (2)

ECE 4510/5530

#include <hcs12.h>#include <vectors12.h>#define INTERRUPT __attribute__((interrupt)) unsigned diff, edge1, overflow;unsigned long pulse_width;void INTERRUPT tovisr(void);void main(void){

UserTimerOvf = (unsigned short)&tovisr;overflow = 0;TSCR1 = 0x90; /* enable timer and fast flag clear */TSCR2 = 0x05; /* set prescaler to 32, no timer overflow interrupt */TIOS &= ~IOS0; /* select input-capture 0 */TCTL4 = 0x01; /* prepare to capture the rising edge */TFLG1 = C0F; /* clear C0F flag */while(!(TFLG1 & C0F)); /* wait for the arrival of the rising edge */TFLG2 = TOF; /* clear TOF flag */

Example 8.3: C Program for Pulse Width Measurement (1 of 2)

ECE 4510/5530

50

TSCR2 |= 0x80; /* enable TCNT overflow interrupt */asm("cli");edge1 = TC0; /* save the first edge */TCTL4 = 0x02; /* prepare to capture the falling edge */while (!(TFLG1 & C0F)); /* wait for the arrival of the falling edge */diff = TC0 - edge1;if (TC0 < edge1)

overflow -= 1;pulse_width = overflow * 65536u + diff;asm ("swi");

}

void INTERRUPT tovisr(void){

TFLG2 = TOF; /* clear TOF flag */overflow = overflow + 1;

}

Example 8.3: C Code (2 of 2)