ECE 477 Digital Systems Senior Design Project Rev 8/09

Homework 9: Software Design Considerations

Team Code Name: _Quazyx: Laser Warfare System__________________ Group No. __4___

Team Member Completing This Homework: _Michael Niksa_________________________

E-mail Address of Team Member: ____mniksa____ @ purdue.edu

Evaluation:

SCORE DESCRIPTION

10 Excellent – among the best papers submitted for this assignment. Very few corrections needed for version submitted in Final Report.

9 Very good – all requirements aptly met. Minor additions/corrections needed for version submitted in Final Report.

8 Good – all requirements considered and addressed. Several noteworthy additions/corrections needed for version submitted in Final Report.

7 Average – all requirements basically met, but some revisions in content should be made for the version submitted in the Final Report.

6 Marginal – all requirements met at a nominal level. Significant revisions in content should be made for the version submitted in the Final Report.

* Below the passing threshold – major revisions required to meet report requirements at a nominal level. Revise and resubmit.

* Resubmissions are due within one week of the date of return, and will be awarded a score of “6” provided all report requirements have been met at a nominal level.

Comments:

ECE 477 Digital Systems Senior Design Project Rev 8/09

1.0 Introduction

The Quazyx Laser Warfare System is designed to be a laser tag game system with features

from professional-grade laser tag systems combined with unique video-game inspired bonuses at

a cost significantly lower than those comparable professional systems. As such, the software for

the Quazyx system is similar to any other laser tag system including infrared transmission and

sensing, LCD displays, keypad configuration, and button-triggered firing mostly based on

interrupts for near real-time operation. However, Quazyx includes radio frequency

communication between the portable gun packs and the base station for live game statistics and

game enhancements like an invincibility mode that require the use of messaging queues,

collision-detection protocols, and coordinated timing within the software. This document will

detail the software design considerations and the architecture of the code modules that make

Quazyx operate.

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2.0 Software Design Considerations

Within the Quazyx software project, all of the detailed memory mappings and addresses

for data registers and configuration are handled by the Microchip C30 compiler and the

dsPIC30F4011 header that is imported upon compilation. This header file allows the use of the

pin names with an underscore prefix for reading and writing within the C code and abstracts the

exact address and structures of the microcontroller memory. The mappings of the utilized

peripherals to their respective port pins and underscore-prefixed variable names can be seen in

Table 2.1 below. During the build process, the C30 compiler reports program memory in Flash

starting at 0x100 with strings followed by application code and ending with initialization

routines. Data memory utilizes 0x000 through 0x800 for the heap and 0x804 through the end of

SRAM for the stack. The addresses overlap because the PIC uses separate instruction and data

memories. See the dsPIC30F reference manual for register name and memory address details [1].

Base Portable

External Device Variable Name - Function Pin External Device Variable Name - Function Pin

Shift Register _SDO1 - SPI Data out 44 Shift Register _SDO1 - SPI Data out 44

_SCK1 43 _SCK1 43

LCD Screen _RF1 - LCD Enable 4 LCD Screen _RF1 - LCD Enable 4

_RF0 - Register Select 5 _RF0 - Register Select 5

Key Encoder _RE4 - output enable 9 RF Transceiver _AN3 - RSSI 22

_RE3 - Data out D 10 _RB0 - Data 19

_RE2 - Data out C 11 _RB1 - T/R Select 20

_RE1 - Data out B 14 _RB2 -Power down 21

_RE0 - Data out A 15 Trigger _RE5 - trigger input 8

_IC7 - Data Available 23 IR LED _PWM1H 14

RF Transceiver _AN3 - RSSI 22 IR LED 2 _PWM2H 10

_RB0 - Data 19 Laser LED _RE4 - Gen I/O 9

_RB1 - T/R Select 20 Color LED Set 1 _RB6 - Gen I/O 25

_RB2 -Power down 21 Color LED Set 2 _RB7 - Gen I/O 26

Photo Transistor 1 _IC1 - input capture 42

Photo Transistor 2 _IC2 - input capture 37

Photo Transistor 3 _IC8 - input capture 24

Photo Transistor 4 _IC7 - input capture 23

Table 2.1: Variable Name to Pin and Peripheral Mapping

The peripherals utilized include SPI, timer, input capture, PWM, and general purpose I/O.

Initializing the SPI for connection to the shift register requires modifying the SPI1CONbits

structure to set the data rate, trigger clock edge, word size, and framing/checksum options. Then

the SPI is operated simply by filling the SPI1BUF variable and checking the status within the

SPI1STATbits structure. The interrupt must also be set by filling the _SPI1IE register with 1.

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The timer module operates similarly using the T1CONbits structure (for timer 1 with other

timers replacing 1 for their respective value) to set up the tick rate and configuration settings,

clearing the TMR1 register containing the current timer count, setting the PR1 register for the

value to trigger an interrupt on, and setting that interrupt by filling the _T1IE register. For the

input capture module, the IC1CONbits structure is used to set up interrupts as well as trigger

edge for the input pin. The PWM, used to control the infrared shot pulse, is configured first by

setting a time base in the PTCON register that all PWM channels share, then adjusting the

individual PWMCON control and PDC duty cycle structures for each channel. Lastly, all general

purpose I/O pins are easy to set up using their respective _TRIS and the values for input or

output can be manipulated with the _R variables. The only notable issue with general purpose

I/O is that for any pin that shares input with the ATD module (most of the B section pins), an

additional set of flags within the PCFG register controls whether those pins connect to the ATD

or digital input and must be set accordingly.

The overall organization of the application code centers around interrupts with a small

polling loop responsible for the processing of the message queues after the initialization

sequence. A diagram of this design can be seen in Appendix A, Figures A.1 through A.3. This

organization was chosen as it allows the microcontroller to react in near real-time to human

input. The messaging queues are established and placed within a polling loop containing a delay.

In the case of the LCD panel, this messaging queue and delay prevents multiple interrupts from

sending messages to the panel too quickly for the user to see and potentially covering up one

message with another. In the case of the RF communication, the messaging queue allows our RF

protocol to process actions in a well-ordered manner and leave a message in the queue for later

retry if a collision or corruption error occurs in transmission.

For debugging the application, standard 6-pin Microchip programmer/debugger headers

have been attached to both the gun and base station PCBs [2]. The chosen microcontroller has a

memory resident debugging area supporting two hardware breakpoints and interaction with the

MPLAB development environment for execution trace and memory inspection. Additionally, for

debugging RF communication, the raw analog signal from the RF chip has been mapped to an

ATD port on the microcontroller which can be initialized and read through the Microchip

debugger if necessary.

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3.0 Software Design Narrative

The overall architecture of the Quazyx software can be seen in the hierarchical figure in

Appendix B. Generally, the main loop on top initializes the various wrapper modules and

interrupts, the wrappers initialize their respective device drivers and processor peripherals, then

the machine moves into the main polling loop state where interrupts drive most of the reactions

back up through the main class and down into whichever module needs to respond to the request.

The RF and LCD messaging queue modules simply provide a circular buffer with SRAM

memory space allocated to hold a group of messages to be delivered to their respective wrappers

allowing messages to be retried or delayed until they can be properly operated upon. They are a

form of passing information from an interrupt to the user or to a remote microcontroller. These

modules are designed out on paper, but not yet implemented.

The Timer software module provides support for other functions such as the LCD driver.

It is set up to allow other routines to request a specific synchronous “wait” period of time when

set-up and hold times in communication with peripherals need to be met. This module has been

implemented with the help of online source code [3] and tested in hardware. An additional

asynchronous timer is sketched out in designs for allowing wake up from a low power

operational state when a laser tag game is not active.

The LCD, Keypad, IR, RF, and PWM wrapper classes provide higher level commands such

as writing or reading of entire lines of data and overall initialization routines. Individual

character, byte, or bit level transfers are abstracted away within the wrappers or down one level

in the device drivers. The LCD and Keypad modules are coded and verified in hardware as

operational, but the IR and PWM are waiting on prototypes to be soldered before coding and

testing. The RF module is waiting for the PCB to come in as the only available package from the

supplier was a QFN which must be attached before the code and testing process can begin.

Lastly, the specific SPI, input capture, PWM, and general purpose I/O device drivers

contain all the control bits, registers, and operational flags that are necessary to activate those

microcontroller peripherals and establish a properly timed connection over the link. These

modules accept only the most basic bit or byte input and output commands and map them to the

registers and timings required by the interface. The SPI driver and GPIO drivers for the LEDs

have been written and tested in hardware while the input capture and PWM modules have not yet

been coded but are outlined in design sketches.

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4.0 Summary

This software design report for the Quazyx Laser Warfare System contains an overview of

the design considerations in terms of Flash and SRAM utilization, pin to register mapping within

the code, the utilized microcontroller peripherals and their respective setup and operational

registers, and the overall architecture of the Quazyx code. A main polling loop is responsible for

a small portion of message passing functionality for the RF communication and LCD panel

display while interrupts from the SPI, input capture, and timer drive a majority of the actions and

responses to user input. Device drivers are already written and tested for most off-chip

peripherals and wrappers are in the design and partial implementation phase to create

convenience functions for the main program logic in manipulating strings, initializations, and

multi-byte messages. Debugging and support is provided by the MPLAB development

environment packaged with the microcontroller and available in-circuit through a standard set of

header pins. Lastly, protocols for IR and RF communication have been drafted but are not yet

implemented in code or tested and are waiting on supporting functionality.

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List of References

[1] Microchip Technology, Inc, “dsPIC30F Family Reference Manual,” Microchip Technology, Inc., 2005. Available: http://ww1.microchip.com/downloads/en/DeviceDoc/ 70046D . pdf . [Accessed: Feb. 27, 2010].

[2] Microchip Technology, Inc, “PICkit 2 Programmer/Debugger Users Guide,” Microchip Technology, Inc., 2008. Available: http:// ww1.microchip.com/downloads/en/DeviceDoc/51553E.pdf . [Accessed: Mar. 25, 2010].

[3] Btbass, “Delay and Timeout Routine for dsPIC in Hi-Tech dsPICC,” EDAboard.com Forum, 2009. Available: http://www.edaboard.com/ftopic371067.html. [Accessed: Mar. 23, 2010].

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Appendix A: Flowchart/Pseudo-code for Main Program

Figure A.1: Main Initialization and Polling Loop

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Figure A.2: Main Interrupt Processes

Figure A.3: Appendix A Color Key

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Appendix B: Hierarchical Block Diagram of Code Organization

Figure B.1: Overall Code Hierarchy

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