SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 IDT88P8341

12006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-6372/9

APRIL 2006IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

INDUSTRIAL TEMPERATURE RANGE

IDT88P8341SPI EXCHANGE SPI-3 TO SPI-4

Issue 1.0

FUNCTIONAL BLOCK DIAGRAM

FEATURES• Functionality

- Low speed to high speed SPI exchange device- Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction- Per LP configurable memory allocation- Maskable interrupts for fatal errors- Fragment and burst length configurable per interface: min 16 bytes,

max 256 bytes• Standard Interfaces

- OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface

- One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 64 concurrently active LPs

- SPI-4 FIFO status channel options:• LVDS full-rate• LVTTL eighth-rate

- Compatible with Network Processor Streaming Interface (NPSI)NPE-Framer mode of operation- SPI-4 ingress LVDS automatic bit alignment and lane de-skew overthe entire frequency range- SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle- IEEE 1149.1 JTAG- Serial or parallel microprocessor interface for control and monitoring

• Full Suite of Performance Monitoring Counters- Number of packets- Number of fragments

- Number of errors- Number of bytes

• Green parts available, see ordering information

APPLICATIONS• Ethernet transport• SONET / SDH packet transport line cards• Broadband aggregation• Multi-service switches• IP services equipment

DESCRIPTIONThe IDT88P8341 is a SPI (System Packet Interface) Exchange with a SPI-

3 interface and a SPI-4 interface. The data that enter on the low speed interface(SPI-3) are mapped to logical identifiers (LIDs) and enqueued for transmissionover the high speed interface (SPI-4). The data that enter on the high speedinterface (SPI-4) are mapped to logical identifiers (LIDs) and enqueued fortransmission over the low speed interface (SPI-3). A data flow between SPI-3 and SPI-4 interfaces is accomplished with LID maps. The logical portaddresses and number of entries in the LID maps may be dynamicallyconfigured. Various parameters of a data flow may be configured by the usersuch as buffer memory size and watermarks. In a typical application, theIDT88P8341 enables connection of a SPI-3 device to a SPI-4 networkprocessor. In other applications a SPI-4 device may be connected to a SPI-3network processor or traffic manager.

6372 drw01

JTAG IF

Control Path Data Path

Uproc IF Clock Generator

PFP = Packet Fragment Processor

SPI-364 Logical Ports

SPI-464 Logical

Ports

SPI-3 to SPI-4 PFP

SPI-4 to SPI-3 PFP

https://www.application-datasheet.com/



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IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE

APRIL 10, 2006

Table of ContentsFeatures ........................................................................................................................................................................................................................ 1Applications .................................................................................................................................................................................................................. 11. Introduction ............................................................................................................................................................................................................. 82. Pin description ......................................................................................................................................................................................................... 93. External interfaces ................................................................................................................................................................................................. 13

3.1 SPI-3 ............................................................................................................................................................................................................... 133.1.1 SPI-3 ingress ........................................................................................................................................................................................ 133.1.2 SPI-3 egress ........................................................................................................................................................................................ 15

3.2 SPI-4 ............................................................................................................................................................................................................... 173.2.1 SPI-4 ingress ........................................................................................................................................................................................ 173.2.2 SPI-4 egress ........................................................................................................................................................................................ 203.2.3 SPI-4 startup handshake ....................................................................................................................................................................... 20

3.3 Microprocessor interface .................................................................................................................................................................................. 224. Datapath and flow control .................................................................................................................................................................................... 23

4.1 SPI-3 to SPI-4 datapath and flow control .......................................................................................................................................................... 254.2 SPI-4 to SPI-3 datapath and flow control .......................................................................................................................................................... 304.3 Microprocessor interface to SPI-3 datapath ...................................................................................................................................................... 33

4.3.1 SPI-3 to ingress microprocessor interface datapath ................................................................................................................................ 334.3.2 Microprocessor insert to SPI-3 egress datapath ..................................................................................................................................... 344.3.3 Microprocessor interface to SPI-4 egress datapath ................................................................................................................................ 354.3.4 SPI-4 ingress to microprocessor interface datapath ................................................................................................................................ 36

5. Performance monitor and diagnostics ................................................................................................................................................................. 375.1 Mode of operation ............................................................................................................................................................................................ 375.2 Counters ......................................................................................................................................................................................................... 37

5.2.1 LID associated event counters ............................................................................................................................................................... 375.2.2 Non - LID associated event counters ..................................................................................................................................................... 37

5.3 Captured events .............................................................................................................................................................................................. 375.3.1 Non LID associated events .................................................................................................................................................................... 375.3.2 LID associated events ........................................................................................................................................................................... 37

5.3.2.1 Non critical events ...................................................................................................................................................................... 375.3.2.2 Critical events ............................................................................................................................................................................. 37

5.3.3 Timebase .............................................................................................................................................................................................. 375.3.3.1 Internally generated timebase ..................................................................................................................................................... 375.3.3.2 Externally generated timebase .................................................................................................................................................... 37

6. Clock generator ...................................................................................................................................................................................................... 387. Loopbacks .............................................................................................................................................................................................................. 39

7.1 SPI-3 Loopback ............................................................................................................................................................................................... 398. Operation guide ..................................................................................................................................................................................................... 40

8.1 Hardware operation ........................................................................................................................................................................................ 408.1.1 System reset ......................................................................................................................................................................................... 408.1.2 Power on sequence .............................................................................................................................................................................. 408.1.3 Clock domains ...................................................................................................................................................................................... 40

8.2 Software operation ........................................................................................................................................................................................... 408.2.1 Chip configuration sequence ................................................................................................................................................................. 408.2.2 Logical Port activation and deactivation .................................................................................................................................................. 418.2.3 Buffer segment modification .................................................................................................................................................................... 418.2.4 Manual SPI-4 ingress LVDS bit alignment .............................................................................................................................................. 418.2.5 SPI-4 status channel software ............................................................................................................................................................... 428.2.6 IDT88P8341 layout guidelines .............................................................................................................................................................. 428.2.7 Software Eye-Opening Check on SPI-4 Interface .................................................................................................................................. 43

9. Register description .............................................................................................................................................................................................. 459.1 Register access summary ................................................................................................................................................................................ 45

9.1.1 Direct register format ............................................................................................................................................................................. 459.1.2 Indirect register format ........................................................................................................................................................................... 45

9.2 Direct access registers ..................................................................................................................................................................................... 49



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Table of Contents (Continued)9.3 Indirect registers for SPI-3A module .................................................................................................................................................................. 54

9.3.1 Block base 0x0000 registers ................................................................................................................................................................. 559.3.2 Block base 0x0200 registers ................................................................................................................................................................. 559.3.3 Block base 0x0500 registers ................................................................................................................................................................. 569.3.4 Block base 0x0700 registers ................................................................................................................................................................. 579.3.5 Block base 0x0A00 registers ................................................................................................................................................................. 599.3.6 Block base 0x0C00 registers ................................................................................................................................................................. 599.3.7 Block base 0x0100 registers ................................................................................................................................................................. 629.3.8 Block base 0x1100 registers .................................................................................................................................................................. 629.3.9 Block base 0x1200 registers ................................................................................................................................................................. 629.3.10 Block base 0x1300 registers ............................................................................................................................................................... 639.3.11 Block base 0x1600 registers ................................................................................................................................................................ 649.3.12 Block base 0x1700 registers ............................................................................................................................................................... 649.3.13 Block base 0x1800 registers ............................................................................................................................................................... 649.3.14 Block base 0x1900 registers ............................................................................................................................................................... 65

9.4 Common module indirect registers (Module_base 0x8000) ............................................................................................................................... 669.4.1 Common module block base 0x0000 registers ....................................................................................................................................... 679.4.2 Common module block base 0x0100 registers ....................................................................................................................................... 679.4.3 Common module block base 0x0200 registers ....................................................................................................................................... 679.4.4 Common module block base 0x0300 registers ....................................................................................................................................... 679.4.5 Common module block base 0x0400 registers ....................................................................................................................................... 709.4.6 Common module block base 0x0500 registers ....................................................................................................................................... 709.4.7 Common module block base 0x0600 registers ....................................................................................................................................... 719.4.8 Common module block base 0x0700 registers ....................................................................................................................................... 719.4.9 Common module block base 0x0800 registers ....................................................................................................................................... 73

10. JTAG interface ....................................................................................................................................................................................................... 7711. Electrical and Thermal Specifications ................................................................................................................................................................ 77

11.1 Absolute maximum ratings ............................................................................................................................................................................... 7711.2 Recommended Operating Conditions .............................................................................................................................................................. 7711.3 Terminal Capacitance ..................................................................................................................................................................................... 7811.4 Thermal Characteristics .................................................................................................................................................................................. 7811.5 DC Electrical characteristics ............................................................................................................................................................................ 7911.6 AC characteristics ........................................................................................................................................................................................... 80

11.6.1 SPI-3 I/O timing ................................................................................................................................................................................... 8011.6.2 SPI-4 LVDS Input / Output ................................................................................................................................................................... 8111.6.3 SPI-4 LVTTL Status AC characteristics ................................................................................................................................................. 8211.6.4 REF_CLK clock input .......................................................................................................................................................................... 8211.6.5 MCLK internal clock and OCLK[3:0] clock outputs ................................................................................................................................ 8211.6.6 Microprocessor interface ..................................................................................................................................................................... 82

11.6.6.1 Microprocessor parallel port AC timing specifications .................................................................................................................. 8311.6.6.2 Serial microprocessor interface (serial peripheral interface mode) .............................................................................................. 87

12. Mechanical characteristics .................................................................................................................................................................................. 8812.1 Device overview ........................................................................................................................................................................................... 8812.2 Pin name/ball location table ............................................................................................................................................................................ 8912.3 Device package ............................................................................................................................................................................................. 92

13. Glossary ................................................................................................................................................................................................................ 9414. Datasheet Document Revision History .............................................................................................................................................................. 9515. Ordering information ........................................................................................................................................................................................... 96


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List of FiguresFigure 1. Typical application: optical port and NPU/Traffic Manager .................................................................................................................................. 8Figure 2. Data Path Diagram ........................................................................................................................................................................................... 8Figure 3. Link mode SPI-3 ingress interface ................................................................................................................................................................... 14Figure 4. PHY mode SPI-3 ingress interface .................................................................................................................................................................. 14Figure 5. Link mode SPI-3 egress interface .................................................................................................................................................................... 16Figure 6. PHY mode SPI-3 egress interface ................................................................................................................................................................... 16Figure 7. Data sampling diagram ................................................................................................................................................................................... 18Figure 8. SPI-4 ingress state diagram ............................................................................................................................................................................ 19Figure 9. SPI-4 egress status state diagram ................................................................................................................................................................... 21Figure 10. Interrupt scheme ........................................................................................................................................................................................... 22Figure 11. Definition of data flows ................................................................................................................................................................................... 23Figure 12. Logical view of datapath configuration using PFPs ......................................................................................................................................... 24Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor ............................................................................................................................. 25Figure 14. SPI-3 ingress LP to LID map ........................................................................................................................................................................ 27Figure 15. SPI-4 egress LID to LP map ......................................................................................................................................................................... 28Figure 16. SPI-3 ingress to SPI-4 egress datapath ........................................................................................................................................................ 28Figure 17. SPI-3 ingress to SPI-4 egress flow control path ............................................................................................................................................. 29Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor ............................................................................................................................. 30Figure 19. SPI-4 ingress to SPI-3 egress datapath ........................................................................................................................................................ 31Figure 20. SPI-4 ingress to SPI-3 egress flow control ..................................................................................................................................................... 32Figure 21 . Microprocessor data capture buffer .............................................................................................................................................................. 33Figure 22. SPI-3 ingress to microprocessor capture interface datapath ........................................................................................................................... 33Figure 24. Microprocessor interface to SPI-3 egress detailed datapath diagram .............................................................................................................. 34Figure 23. Microprocessor data insert buffer .................................................................................................................................................................. 34Figure 25. Microprocessor data insert buffer .................................................................................................................................................................. 35Figure 26. Microprocessor data insert interface to SPI-4 egress datapath ....................................................................................................................... 35Figure 27. Microprocessor data capture buffer ............................................................................................................................................................... 36Figure 28. SPI-4 ingress to microprocessor data capture interface path .......................................................................................................................... 36Figure 29. Clock generator ............................................................................................................................................................................................ 38Figure 30. SPI-3 Loopback diagram .............................................................................................................................................................................. 39Figure 31. Power-on-Reset Sequence .......................................................................................................................................................................... 40Figure 32. DDR interface and eye opening check through over sampling ....................................................................................................................... 43Figure 33. Direct & indirect access ................................................................................................................................................................................. 45Figure 34. SPI-3 I/O timing diagram ............................................................................................................................................................................... 80Figure 35. SPI-4 I/O timing diagram ............................................................................................................................................................................... 81Figure 36. Microprocessor parallel port Motorola read timing diagram ............................................................................................................................ 83Figure 37. Microprocessor parallel port Motorola write timing diagram ............................................................................................................................ 84Figure 38. Microprocessor parallel port Intel mode read timing diagram .......................................................................................................................... 85Figure 39. Microprocessor parallel port Intel mode write timing diagram .......................................................................................................................... 86Figure 40. Microprocessor serial peripheral interface timing diagram .............................................................................................................................. 87Figure 41. IDT88P8341 820PBGA package, bottom view .............................................................................................................................................. 92Figure 42. IDT88P8341 820PBGA package, top and side views .................................................................................................................................... 93




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List of TablesTable 1 – I/O types .......................................................................................................................................................................................................... 9Table 2 – SPI-3 ingress interface pin definition .................................................................................................................................................................. 9Table 3 – SPI-3 egress interface pin definition ................................................................................................................................................................ 10Table 4 – SPI-3 status interface pin definition .................................................................................................................................................................. 10Table 5 – SPI-4 ingress interface definition ..................................................................................................................................................................... 11Table 6 – SPI-4 egress interface definition ...................................................................................................................................................................... 11Table 7 – Parallel microprocessor interface .................................................................................................................................................................... 12Table 8 – Serial microprocessor interface (serial peripheral interface mode) ................................................................................................................... 12Table 9 – Miscellaneous ................................................................................................................................................................................................ 12Table 10 – Both attached devices start from reset status .................................................................................................................................................. 20Table 11 – Ingress out of synch, egress in synch ........................................................................................................................................................... 20Table 12 – Ingress in synch, egress out of synch ........................................................................................................................................................... 20Table 13 - DIRECTION code assignment ...................................................................................................................................................................... 26Table 14 – CK_SEL[3:0] input pin encoding ................................................................................................................................................................... 38Table 15 - Zero margin SPI-3 timing budget ................................................................................................................................................................... 42Table 16 - Margin check for SPI-3 timing ........................................................................................................................................................................ 42Table 17 - Bit order within an 8-Bit data register ............................................................................................................................................................. 45Table 18 - Bit order within a 32-Bit data register ............................................................................................................................................................. 45Table 19 - Bit order within an 8-Bit data register ............................................................................................................................................................. 45Table 20 - Bit order within a 16-Bit address register ....................................................................................................................................................... 46Table 21 - Bit order within an 8-Bit control register .......................................................................................................................................................... 46Table 22 - Module base address (Module_base) ........................................................................................................................................................... 46Table 23 - Indirect access block bases for Module A ....................................................................................................................................................... 46Table 24 - Indirect access block bases for common module ............................................................................................................................................ 47Table 25 - Indirect access data registers (direct accessed space) at 0x30 to 0x33 .......................................................................................................... 47Table 26 - Indirect access address register (direct accessed space) at 0x34 to 0x35 ...................................................................................................... 47Table 27 - Indirect access control register (direct accessed space) at 0x3F ..................................................................................................................... 47Table 28 - Error coding table ......................................................................................................................................................................................... 48Table 29 - Direct mapped Module A registers ................................................................................................................................................................ 49Table 30 - Direct mapped other registers ....................................................................................................................................................................... 49Table 31 - SPI-3 data capture control register (register 0x00 ) ....................................................................................................................................... 49Table 32 - SPI-3 data Capture register (register 0x01) ................................................................................................................................................... 49Table 33 - SPI-4 data insert control register (register 0x02) ............................................................................................................................................ 50Table 34 - SPI-4 data insert register (register 0x03) ....................................................................................................................................................... 50Table 35 - SPI-4 data capture control registers (register 0x04) ....................................................................................................................................... 50Table 36 - SPI-3 data insert control register (register 0x05) ............................................................................................................................................ 50Table 37 - SPI-4 data capture register (register 0x06) .................................................................................................................................................... 50Table 38 - SPI-3 data insert register (register 0x07) ....................................................................................................................................................... 50Table 39 - Software reset register (0x20 in the direct accessed space) ........................................................................................................................... 51Table 40 - SPI-4 status register (0x22 in the direct accessed space) ............................................................................................................................... 51Table 41 - SPI-4 enable register (0x23 in the direct accessed space) ............................................................................................................................. 51Table 42 - Module status register (0x24 in the direct accessed space) ............................................................................................................................ 52Table 43 - Module enable register (0x28 in the direct accessed space) .......................................................................................................................... 52Table 44 - Primary interrupt status register (0x2C in the direct accessed space) ............................................................................................................. 53Table 45 - Secondary interrupt status register (0x2D in the direct accessed space) ........................................................................................................ 53Table 46 - Primary interrupt enable register (0x2E in the direct accessed space) ............................................................................................................ 53Table 47 - Secondary interrupt enable register (0x2F in the direct accessed space) ....................................................................................................... 53Table 48 - Module A indirect register .............................................................................................................................................................................. 54Table 49 - SPI-3 ingress LP to LID map ......................................................................................................................................................................... 55Table 50 - SPI-3 general configuration register (register_offset=0x00) ............................................................................................................................ 55Table 51 - SPI-3 ingress configuration register (register_offset=0x01) ............................................................................................................................. 56Table 52 - SPI-3 ingress fill level register (register_offset=0x02) ..................................................................................................................................... 56Table 53 - SPI-3 ingress max fill level register (register_offset=0x03) .............................................................................................................................. 56Table 54 - SPI-3 egress LID to LP map ......................................................................................................................................................................... 56Table 55 - SPI-3 egress configuration register (register_offset=0x00) ............................................................................................................................. 57Table 56 - SPI-4 ingress to SPI-3 egress flow control register (register_offset=0x01) ...................................................................................................... 57


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List of Tables (Continued)Table 57 - SPI-3 egress test register (register_offset=0x02) ............................................................................................................................................ 57Table 58 - SPI-3 egress fill level register (register_offset=0x03) ...................................................................................................................................... 58Table 59 - SPI-3 egress max fill level register (register_offset=0x04) .............................................................................................................................. 58Table 60 - LID associated event counters (0x000-0x17F) .............................................................................................................................................. 59Table 61 - Non LID associated event counters (0x00 - 0x0B) ........................................................................................................................................ 59Table 62 - Non LID associated interrupt indication register (register_offset 0x0c) ............................................................................................................. 60Table 63 - Non LID associated interrupt enable register(register_offset 0x0D) ................................................................................................................ 60Table 64 - LID associated interrupt indication register (register_offset 0x0E) .................................................................................................................... 60Table 65 - LID associated interrupt enable register (register_offset 0x0F) ....................................................................................................................... 60Table 66 - Non critical LID associated capture table (register_offset 0x10-0x15) ............................................................................................................. 61Table 67 - SPI-3 to SPI-4 critical LID interrupt indication registers (register_offset 0x16-0x17) ......................................................................................... 61Table 68 - SPI-3 to SPI-4 critical LID interrupt enable registers (register_offset 0x18-0x19) ............................................................................................ 61Table 69 - SPI-4 to SPI-3 critical LID interrupt indication registers (register_offset 0x1A-0x1B) ........................................................................................ 61Table 70 - SPI-4 to SPI-3 critical LID interrupt enable registers (register_offset 0x1C-0x1D) ........................................................................................... 61Table 71 - Critical events source indication register (register_offset 0x1E) ....................................................................................................................... 61Table 72 - SPI-3 ingress packet length configuration register .......................................................................................................................................... 62Table 73 - SPI-4 egress port descriptor table (64 entries) ............................................................................................................................................... 62Table 74 - SPI-4 egress DIRECTION code assignment ................................................................................................................................................. 62Table 75 - SPI-3 ingress port descriptor table (Block_base 0x1200) ............................................................................................................................... 62Table 76 - SPI-3 to SPI-4 PFP register (register_offset 0x00) ......................................................................................................................................... 63Table 77 - NR_LID field encoding .................................................................................................................................................................................. 63Table 78 - SPI-3 to SPI-4 flow control register (register_offset 0x01) ............................................................................................................................... 63Table 79 - SPI-4 ingress packet length configuration (64 entries configurable) ................................................................................................................ 64Table 80 - SPI-3 egress port descriptor table (64 entries) .............................................................................................................................................. 64Table 81 - SPI-3 egress DIRECTION code assignment ................................................................................................................................................. 64Table 82 - SPI-4 ingress port descriptor tables (64 entries) ............................................................................................................................................ 64Table 83 - SPI-4 to SPI-3 PFP register (0x00) ............................................................................................................................................................... 65Table 84 - NR_LID field encoding .................................................................................................................................................................................. 65Table 85 -Common Module (Module_base 0x8000) indirect register table ...................................................................................................................... 66Table 86 - SPI-4 ingress LP to LID map (256 entries, one per LP) ................................................................................................................................. 67Table 87 - SPI-4 ingress calendar_0 (256 entries) ......................................................................................................................................................... 67Table 88 - SPI-4 ingress calendar_1 (256 entries) ......................................................................................................................................................... 67Table 89 - SPI-4 ingress configuration register (0x00) .................................................................................................................................................... 67Table 90 - SPI-4 ingress status configuration register (register_offset 0x01) .................................................................................................................... 68Table 91 - SPI-4 ingress status register (register_offset 0x02) ........................................................................................................................................ 68Table 92 - SPI-4 ingress inactive transfer port (register_offset 0x03) ............................................................................................................................... 68Table 93 - SPI-4 ingress calendar configuration register (0x04 to 0x05) ......................................................................................................................... 69Table 94 – SPI-4 ingress watermark register (register_offset 0x06) ............................................................................................................................... 69Table 95 - SPI-4 ingress fill level register (register_offset 0x07) ..................................................................................................................................... 69Table 96 - SPI-4 ingress max fill level register (register_offset 0x0B) ............................................................................................................................. 69Table 97 - SPI-4 ingress diagnostics register (register_offset 0x0F) ................................................................................................................................ 69Table 98 - SPI-4 ingress DIP-4 error counter (register_offset 0x10) .............................................................................................................................. 70Table 99 - SPI-4 ingress bit alignment control register (register_offset 0x11) ................................................................................................................... 70Table 100 - SPI-4 ingress start up training threshold register (register_offset 0x12) ........................................................................................................ 70Table 101 - SPI-4 egress LID to LP map (256 entries) ................................................................................................................................................... 70Table 102 - SPI-4 egress calendar_0 (256 locations) .................................................................................................................................................... 70Table 103 - SPI-4 egress calendar_1 (256 locations) .................................................................................................................................................... 71Table 104 – SPI-4 egress configuration register_0 (register_offset 0x00) ........................................................................................................................ 71Table 105 - SPI-4 egress configuration register_1 (register_offset 0x01) ........................................................................................................................ 71Table 106 - SPI-4 egress status register (register_offset 0x02) ....................................................................................................................................... 72Table 107 - SPI-4 egress calendar configuration register (Register_offset 0x03 - 0x04) .................................................................................................. 72Table 108 - SPI-4 egress diagnostics register (register_offset 0x05) .............................................................................................................................. 72Table 109 - SPI-4 egress DIP-2 error counter (register_offset 0x06) ............................................................................................................................. 72Table 110 - SPI-4 ingress bit alignment window register (register_offset 0x00) ................................................................................................................ 73Table 111 - SPI-4 ingress lane measure register (register_offset 0x01) .......................................................................................................................... 73


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List of Tables (Continued)Table 112 - SPI-4 ingress bit alignment counter register (0x02 to 0x0B) ......................................................................................................................... 73Table 113 - SPI-4 ingress manual alignment phase/result register (0x0C to 0x1F) .......................................................................................................... 73Table 114 - SPI -4 egress data lane timing register (register_offset 0x2A) ....................................................................................................................... 73Table 115 - SPI-4 egress Control Lane Timing register (Register_offset 0x2B) ............................................................................................................... 74Table 116 - SPI-4 egress data clock timing register (register_offset 0x2C) ....................................................................................................................... 74Table 117 - SPI-4 egress status timing register (register_offset 0x2D) ............................................................................................................................ 74Table 118 - SPI-4 egress status clock timing register (register_offset 0x2E) .................................................................................................................... 74Table 119 - PMON timebase control register (register_offset 0x00) ................................................................................................................................. 75Table 120 - Timebase register (register_offset 0x01) ...................................................................................................................................................... 75Table 121 - Clock generator control register (register_offset 0x10) ................................................................................................................................. 75Table 122 - OCLK and MCLK frequency select encoding ............................................................................................................................................... 75Table 123 - GPIO register (register_offset 0x20) ............................................................................................................................................................ 76Table 124 - GPIO monitor table (5 entries 0x21-0x25 for GPIO[0] through GPIO[4]) ....................................................................................................... 76Table 125 - Version number register (register_offset 0x30) ............................................................................................................................................. 76Table 126 – JTAG instructions ........................................................................................................................................................................................ 77Table 127 – Absolute maximum ratings ........................................................................................................................................................................... 77Table 128 – Recommended Operating Conditions .......................................................................................................................................................... 77Table 129 – Terminal Capacitance ................................................................................................................................................................................. 78Table 130 – Thermal Characteristics .............................................................................................................................................................................. 78Table 131 – DC Electrical characteristics ........................................................................................................................................................................ 79Table 132 – SPI-3 AC Input / Output timing specifications ................................................................................................................................................ 80Table 133 – SPI-4.2 LVDS AC Input / Output timing specifications .................................................................................................................................... 82Table 134 – SPI-4 LVTTL status AC Characteristics ....................................................................................................................................................... 82Table 135 – REF_CLK clock input ................................................................................................................................................................................. 82Table 136 – OCLK[3:0] clock inputs and MCLK internal clock ......................................................................................................................................... 82Table 137 – Microprocessor interface ............................................................................................................................................................................ 82Table 138 – Microprocessor parallel port Motorola read timing ....................................................................................................................................... 83Table 139 – Microprocessor parallel port Motorola write timing ....................................................................................................................................... 84Table 140 – Microprocessor parallel port Intel mode read timing ..................................................................................................................................... 85Table 141 – Microprocessor parallel port Intel mode write timing ..................................................................................................................................... 86Table 142 – Microprocessor serial peripheral interface timing ......................................................................................................................................... 87


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TYPICAL APPLICATIONExchange between optical ports and NPU/Traffic Manager

Figure 2. Data Path Diagram

Figure 1. Typical application: optical port and NPU/Traffic Manager

SPI-3

SPI-3 ingress to SPI-4 egress

I/F Memory I/FSPI-4

SPI-4 ingress to SPI-3 egress 6372 drw03

1. INTRODUCTIONThe IDT88P8341 device is a SPI-3 to SPI-4 exchange intended for use

in optical line cards, Ethernet transport, and multi-service switches. The SPI-3 and SPI-4 interfaces are defined by the Optical Interworking Forum.

The device can be used as a rate adapter, a switch, or an aggregationdevice between network processor units, multi-gigabit framers and PHYs, andswitch fabric interface devices.

DATA PATH OVERVIEWFigure 1. Data Path Diagram shows an overview of the data path through

the device.In normal operation, there are two paths through the IDT88P8341 device:

the SPI-3 ingress to SPI-4 egress path, and the SPI-4 ingress to SPI-3 egresspath. SPI-3 and SPI-4 burst sizes are separately configurable.

In the SPI-3 ingress to SPI-4 egress path, data enter in fragments on the SPI-3 interface and are received by the SPI-3 interface block. The fragments aremapped to a SPI-4 address and stored in memory allocated at the SPI-3 leveluntil such a time that the Packet Fragment Processor determines that they are tobe transmitted on the SPI-4 interface. The data is transferred in bursts, in line withthe OIF SPI-4 implementation agreement, to the SPI-4 interface block, and aretransmitted on the SPI-4 interface.

In the SPI-4 ingress to SPI-3 egress path, data enter in bursts on the SPI-4interface and are received by the SPI-4 interface block. The SPI-4 address istranslated to a SPI-3 address, and the data contained in the bursts are storedin memory allocated at the SPI-3 level until such a time that the Packet FragmentProcessor determines that they are to be transmitted on the SPI-3 interface. Thedata is transferred in packet fragments, in line with the OIF SPI-3 implementationagreement, to the SPI-3 interface block, and are transmitted on the SPI-3interface.

Multi-RateSONETFramer

SPI-3 IDT88P8341 NPUSPI-4 Control

Processor

OC-48/4xOC-12/16xOC-3

PCI 6372 drw02





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2. PIN DESCRIPTIONSPI-3

For the SPI-3 interface, each pin is used differently depending whether theSPI-3 is in Link mode or in PHY mode. The SPI-3 interface is configurable foreither Link or PHY mode. This configuration pertains to both the ingress andegress paths. The device pin is given a generic name, and mapped to thestandard pin name according to the mode of the interface (Link or PHY).

TABLE 2 � SPI-3 INGRESS INTERFACE PIN DEFINITIONGeneric Name Specific Name I/O type Description Mode

Link PHYI_FCLK SPI3A_I_FCLK I-ST Ingress SPI-3 write clock RFCLK TFCLK

LVTTLRVAL SPI3A_I_RVAL B-PU Receive data valid RVAL (I) RVAL (O)

LVTTLI_ENB SPI3A_I_ENB B-PU Ingress read enable RENB (O) TENB (I)

LVTTLI_DAT[31:0] SPI3A_I_DAT[31:0] I-PU Ingress data bus RDAT [31:0] TDAT [31:0]

LVTTLI_MOD[1:0] SPI3A_I_MOD[1:0] I-PU Ingress word modulus RMOD [1:0] TMOD [1:0]

LVTTLI_PRTY SPI3A_I_PRTY I-PU Ingress parity RPRTY TPRTY

LVTTLI_SOP SPI3A_I_SOP I-PU Ingress start of packet RSOP TSOP

LVTTLI_EOP SPI3A_I_EOP I-PU Ingress end of packet REOP TEOP

LVTTLI_ERR SPI3A_I_ERR I-PU Ingress EOP error RERR TERR

LVTTLI_SX SPI3A_I_SX I-PU Ingress start of transfer RSX TSX

LVTTL

I/O type FunctionI_ST Input with Schmitt trigger with weak pull upI-PU Input with weak pull upB-PU Bidirectional I/O with weak pull upI_PD Input with pull downI InputO OutputO-Z Output with tri-stateOD Output with open drain

TABLE 1 � I/O TYPES


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APRIL 10, 2006

Generic Name Specific Name I/O type Description ModeLink PHY

E_FCLK SPI3A_E_FCLK I-ST Egress SPI-3 write clock TFCLK RFCLKLVTTL

E_ENB SPI3A_E_ENB B-PU Egress read enable TENB (O) RENB (I)LVTTL

E_DAT[31:0] SPI3A_E_DAT[31:0] O-Z Egress data bus TDAT [31:0] RDAT [31:0]LVTTL

E_MOD[1:0] SPI3A_E_MOD[1:0] O-Z Egress word modulus TMOD [1:0] RMOD [1:0]LVTTL

E_PRTY SPI3A_E_PRTY O-Z Egress parity TPRTY RPRTYLVTTL

E_SOP SPI3A_E_SOP O-Z Egress start of packet TSOP RSOPLVTTL

E_EOP SPI3A_E_EOP O-Z Egress end of packet TEOP REOPLVTTL

E_ERR SPI3A_E_ERR O-Z Egress EOP error TERR RERRLVTTL

E_SX SPI3A_E_SX O-Z Egress start of transfer TSX RSXLVTTL

TABLE 3 � SPI-3 EGRESS INTERFACE PIN DEFINITION


DTPA[3:0] SPI3A_DTPA[3:0] B-PU Direct transmit packet available DTPA (I) DTPA (O)LVTTL

STPA SPI3A_STPA B-PU Selected-PHY transmit packet available STPA (I) STPA (O)LVTTL

PTPA SPI3A_PTPA B-PU Polled-PHY transmit packet available PTPA (I) PTPA (O)LVTTL

ADR[7:0] SPI3A_ADR[7:0] B-PU Polled transmit PHY address ADR (O) ADR (I)LVTTL

TABLE 4 � SPI-3 STATUS INTERFACE PIN DEFINITION


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APRIL 10, 2006


I_DCLK (P & N) SPI4_I_DCLK_P I LVDS Ingress data clock RDCLK TDCLKSPI4_I_DCLK_N

I_DAT[15:0] SPI4_I_DAT_P[15:0] I LVDS Ingress data bus RDAT TDAT(P & N) SPI4_I_DAT_N[15:0]I_CRTL (P & N) SPI4_I_CTRL_P I LVDS Ingress control word RCTL TCTL

SPI4_I_CTRL_NI_SCLK_L SPI4_I_SCLK_P O LVDS Ingress status clock RSCLK TSCLK

(P & N) SPI4_I_SCLK_NI_STAT_L[1:0] SPI4_I_STAT_P[1:0] O LVDS Ingress status info RSTAT TSTAT

(P & N) SPI4_I_STAT_N[1:0]I_SCLK_T SPI4_I_SCLK_T O LVTTL Ingress status clock RSCLK TSCLKI_STAT_T[1:0] SPI4_I_STAT_T[1:0] O LVTTL Ingress status info RSTAT TSTATBIAS BIAS Analog Use an external 3K Ohm ---------- ----------

1% resistor to VSSLVDS_STA LVDS_STA I-PU LVDS(high)/LVTTL (low) status ---------- ----------

selection (See note below)

TABLE 5 � SPI-4 INGRESS INTERFACE DEFINITION


E_DCLK (P & N) SPI4_E_DCLK_P O LVDS Egress data clock TDCLK RDCLKSPI4_E_DCLK_N

E_DAT[15:0] SPI4_E_DAT_P[15:0] O LVDS Egress data bus TDAT[15:0] RDAT[15:0](P & N) SPI4_E_DAT_N[15:0]E_CRTL (P & N) SPI4_E_CTRL_P O LVDS Egress control word TCTL RCTL

SPI4_E_CTRL_NE_SCLK_L SPI4_E_SCLK_P I LVDS Egress status clock TSCLK RSCLK

(P & N) SPI4_E_SCLK_NE_STAT_L[1:0] SPI4_E_STAT_P[1:0] I LVDS Egress status info TSTAT[1:0] RSTAT[1:0]

(P & N) SPI4_E_STAT_N[1:0]E_SCLK_T SPI4_E_SCLK_T I-ST LVTTL Egress status clock TSCLK RSCLKE_STAT_T[1:0] SPI4_E_STAT_T[1:0] I-PU LVTTL Egress status info TSTAT RSTAT[1:0]

TABLE 6 � SPI-4 EGRESS INTERFACE DEFINITION

SPI-4For the SPI-4 interface, each pin is used differently depending whether the

SPI-4 is in Link mode or in PHY mode. The pin is given a generic name, shown

in the Name column, and mapped to the OIF standard pin name according tothe mode of operation of the interface (Link to PHY).

NOTE:1. A hardware reset or software reset must be performed after changing the level of this pin.


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APRIL 10, 2006

Name I/O type Parallel microprocessor Serial Peripheral Interface Pin Use Description pin used

SDI I-ST CMOS WRB Serial data in, rise edge samplingSDO B-PU CMOS DBUS[0] Serial data out, falling edge drivingCSB I-ST CMOS CSB Chip select, active low. SDO is tri-stated when CSB is highSCLK I-ST CMOS RDB Input clockINTB OD CMOS ---------- Interrupt, active low, open drainSPI_EN I-PU CMOS ---------- Dedicated input. High selects SPI microprocessor interface (internally pulled up)

TABLE 9 � MISCELLANEOUS

Name I/O type DescriptionREF_CLK I-ST CMOS Master clock inputOCLK[3:0] O LVTTL Clock outputs that can be used for SPI-3, phase-shifted to avoid simultaneously switching outputsCLK_SEL[3:0] I-PU CMOS Clock select inputs for internal PLL, internal MCLK, and OCLK[3:0] outputsTIMEBASE B-PU CMOS Timeout signal for countersGPIO[4:0] B-PU CMOS General purpose I/O or internal state monitor pinsTDI I-PU CMOS JTAG data in (internally pulled up)TDO O-Z CMOS JTAG data outTCK I-ST CMOS JTAG clockTMS I-PU CMOS JTAG mode (internally pulled up)TRSTB I-PU CMOS JTAG reset, active low (internally pulled up). Pull down for normal operation.RESETB I-PD CMOS Master hardware reset, active low

NOTE:1. Inputs with internal pull-ups do not need external pull-ups unless connected to PCB trace (except TRSTB).

Parallel microprocessor InterfaceThe Parallel microprocessor interface is configurable to work in Intel or Motorola modes. Be sure to connect SPI_EN to a logic low when

using the parallel microprocessor interface mode.

Name I/O type DescriptionMPM I-PU CMOS Microprocessor mode: 0=Motorola Mode, 1=Intel mode (sampled after reset)CSB I-ST CMOS Chip select; active lowRDB I-ST CMOS RDB: Read control, active low (in Intel mode), or

DSB: Data strobe, active low (in Motorola mode)WRB I-ST CMOS WRB: Write control; active low; (in Intel mode), or

R/WB: Read/write control; when high, read is active; when low, write is active; (in Motorola mode)ADD[5:0] I-PU CMOS Address busDBUS[7:0] B-PU CMOS Data busINTB OD CMOS Interrupt, active low, open drainSPI_EN I-PU CMOS Logic low selects parallel microprocessor interface (internally pulled up, sampled after reset)

TABLE 7 � PARALLEL MICROPROCESSOR INTERFACE

TABLE 8 � SERIAL MICROPROCESSOR INTERFACE (SERIAL PERIPHERAL INTERFACE MODE)Four Pins Multiplexed with Parallel microprocessor Pins. Be sure to connect SPI_EN to a logic high when using the serial microprocessor

interface mode.


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APRIL 10, 2006

3. EXTERNAL INTERFACESThe external interfaces provided on the IDT88P8341 device are two SPI-

3 interfaces, one SPI-4 interface, a serial or parallel microprocessor interface,a JTAG interface, and a set of GPIO pins. Each of the interfaces is defined in therelevant standard.

The following information contains a set of the highlights of the featuressupported from the relevant standards, and a description of additional featuresimplemented to enhance the usability of these interfaces for the system architect.

3.1 SPI-3Refer to OIF SPI-3 document (see 13.Glossary for a reference) for full details

of the implementation agreement.- Two instantiations of SPI-3 interface; each interface independently

configurable- Device supports a 8-bit and 32-bit data bus structure.- Clock rate is minimum 19.44 to maximum 133 MHz- Link, single port PHY, and single device multi port PHY modes supported- Byte level and packet level transfer control mechanisms supported

• Four DTPA signals supported, mapped to LP addresses 0 – 3, for STPAin byte-level mode

• Eight ADR signals supported for PTPA in packet-level mode- Address range 0 to 255 with support for 64 simultaneously active logical ports- Fragment length (section) configurable from 16 to 256 bytes in 16 byte

multiples- Configurable standard and non-standard bit ordering

SPI-3 implementation featuresThe following are implemented per SPI-3 interface, and there are two

instantiations per device.- Link / PHY layer device- Packet / byte level FIFO status information- Physical port enable- Width of data bus (32 bit or 8 bit)- Parity selection (odd or even)- Enable parity check

3.1.1 SPI-3 ingressThe following are implemented per SPI-3 interface, and there are 4

instantiations per device.- SPI-3 LP to Link Identifier (LID) map- 256 entries, one per SPI-3 LP address- LP enable control- Only 64 of these entries are to be in the active state simultaneously

Backpressure enable- Link mode only- Enables the assertion of the I_ENB when at least one active LID can not

accept data- If not enabled, the I_ENB signal will never be asserted in Link mode, possibly

leading to fragments being discarded.

Minimum packet length- Packets shorter than the minimum length will be optionally counted in the

short packet counter.- Range 0 – 255 in 1 byte increments

Maximum packet length- Packets longer than the maximum length will be optionally counted in the

long packet counter.- Range 0 – 16,383 in 1 byte increments

Backpressure threshold- Number of free segments allocated below which backpressure will be

triggered for the LP

SPI-3 ingress interfaceMultiple independent data streams can be transmitted over the physical SPI-

3 port. Each of those data streams is identified by a SPI-3 logical port ( LP ). Datafrom a transfer on a SPI-3 logical port and the associated descriptor fields aresynchronized to the configurable internal buffer segment pool.

Normal operationRefer to [13. Glossary] for details about the SPI-3 interface.

• A SPI-3 interface ( a physical port ) is enabled by the SPI-3_ENABLE flagin the SPI-3 configuration register. A disabled interface tri-states all outputpins and does not respond to any input signals.

• The interface is configured in PHY or Link layer mode by the LINK flagin the SPI-3 general configuration register.

• The interface supports a SPI-3 logical port number range [0..255], note thatat most 64 logical ports can be configured.

• The SPI-3 interface supports data transport over either a 32 bit datainterface or over one single 8 bit interface (data[7:0] ) only. The selectionis defined by the BUSWIDTH flag in the SPI-3 general configuration register.

• The SPI-3 interface is configured in byte mode or packet mode by thePACKET flag in the SPI-3 general configuration register.

• The SPI-3 interface supports over-clocking.• Parity checking over data[31:0] is enabled by the PARITY_EN flag in the

Table 50, SPI-3 general configuration register (register_offset=0x00). Theparity type is defined by the EVEN_PARITY flag. Parity check results overthe in-band port address and the data of a transfer are forwarded towardsthe packet fragment processor.

• SPI Exchange supports zero clock interval spacing between transfers.

SPI-3 ingress interface errorsGiven an I_FCLK within specification, the SPI-3 will not dead lock due to any

combination or sequence on the SPI-3 interface. The SPI Exchange detects forincorrect SOP / EOP sequences on a logical port. The following sequences aredetected:

Successive SOP ( SOP- SOP sequence rather than SOP –EOP –SOP-EOP )Successive EOP ( EOP- EOP sequence rather than SOP –EOP –SOP-EOP )Detection of an illegal sequence results in the generation of an SPI-3 illegal

SOP sequence event or SPI-3 illegal EOP sequence even generated. Theevent is associated to the physical port. The event is directed towards the PMON& DIAG module.

A clock available process detects a positive I_FCLK within a 64 MCLK clockcycle period. The result of this process is reported in the I_FCLK_AV flag in theTable 52 SPI-3 ingress fill level register (Block_base 0x0200 + Register_offset0x02).

A status change from the clock available status to the clock not available statusgenerates a maskable SPI-3 ingress clock unavailable interrupt indication,SPI3_ICLK_UN, in Table 62-Non LID associated interrupt indication register(Block_Base 0x0C00 + Register_offset 0x0C).



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Figure 3. Link mode SPI-3 ingress interface

Figure 4. PHY mode SPI-3 ingress interface

SPI-3 ingress Link modeRefer to [Glossary] for details about the SPI-3 interface.

• The PHY pushes data into the device in blocks from 1 up to 256 bytes.• The SPI Exchange provides backpressure for the SPI-3 ingress physical

interface by the I_ENB signal. The I_ENB is asserted when at least one

active LID can not accept data. This feature is enabled by theBACKPRESSURE_EN flag in the SPI-3 ingress configuration register

(register_offset = 0x01). When the flag is cleared the I_ENB signal will not beasserted, hence no backpressure can be generated.

SPI-3 ingress PHY modeThe SPI Exchange indicates to the Link layer it has buffer space available

by proper response to either Link layer polling (packet mode ) or direct indicationon DTPA signals (byte mode). The selection is made by the PACKET flag inthe SPI-3 configuration register.

• In packet mode the device responds to polling (by Link layer device)• In byte mode the direct status indication is limited to 4 addresses (fixed ports

[3:0])

IDT88P8341(LINK MODE)

PHY

I_FCLK

I_MOD[1:0]

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I_RSX

I_ENB

I_EOP

I_SOP

RVAL

I_PRTY

I_Data[31:0]

I_ERR

byte mode

packet mode

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IDT88P8341(PHY MODE)LINK

I_FCLK

I_MOD[1:0]

I_SOP

I_ENB

I_PRTY

I_Data[31:0]

I_ERR

ADDR[7:0]

PTPA

DTPA[3:0]

STPA

I_EOP

I_RSX




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3.1.2 SPI-3 egress - All fragments will be of a programmable equal length with the exception

of EOP fragment which may be shorter

LID to LP map- 64 entries, one per LID, for each SPI-3 egress port- LP enable control

Multiple burst enable- Allows more than one burst to be sent to an LP.

Poll length- For use when in Link mode and when using the packet level mode- Causes polling of the PHY for the logical ports associated to LIDs ranging

from [0 up to POLL_LENGTH] to find logical ports that can accept data- Range is 0-63

Loopback enable- Enables loopback from SPI-3 physical interface to same SPI-3 physical

interface for test purposes

Data memory egress controlThe SPI-3 egress port descriptor table (block_base 0x1700) for both paths

out of the data memory. The function of the SPI-3 egress port descriptor table(block_base 0x1700) is to define where data goes after exiting the main datamemory. There are four options configurable:

- SPI-3- SPI-4- Capture- Discard

Maximum number of memory segments- Defines the largest BUFFER available to a LP / LID- Each segment is 256 bytes- Range 1 – 508 in increments of one segment

SPI-3 egress interface configuration• SPI Exchange allows for a pause at least two cycles of E_FCLK between

successive transfers.• SPI Exchange allows for over clocking for a higher clock frequency

supported as opposed to the one defined by the SPI-3 implementationagreement.

• The Link mode is selected by the Link flag in the SPI-3 general configurationregister.

• The interface operates in PACKET mode or BYTE mode as defined bythe PACKET flag in the SPI-3 general configuration register.

• SPI Exchange generates even or odd parity over E_DATA[7/31:0] onthe E_PRTY signal as defined by the EVEN flag in the Table 50, SPI-3 generalconfiguration register (register_offset=0x00).

• SPI Exchange optionally generates two dummy cycles after assertion ofthe STX signal. The option is enabled by the STX_SPACING flag in the Table50, SPI-3 general configuration register (register_offset=0x00).

• SPI Exchange optionally generates two dummy cycles after assertion ofan EOP signal. The option is enabled by the EOP_SPACING flag in the Table50, SPI-3 general configuration register (register_offset=0x00).

SPI-3 egress interface errorsA clock available process detects an E_FCLK cycle within a 64 MCLK clock

cycle period. The result of this process is reported in the E_FCLK_AV flag inTable 58, SPI-3 egress fill level register (Block_base 0x0700 +Register_offset=0x03).

A status change from the clock available status to the clock not available statusgenerates a maskable SPI-3 egress clock unavailable interrupt indication,SPI3_ECLK_UN, in Table 62-Non LID associated interrupt indication register(Block_Base 0x0C00 + Register_offset 0x0C).


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Figure 6. PHY mode SPI-3 egress interface

Figure 5. Link mode SPI-3 egress interface

SPI-3 egress Link modeThe SPI Exchange receives status information from the PHY. The PHY

indicates its ability to receive data. Status information for all logical ports is directedtowards the packet fragment processor.

Status information is received from the PHY.• In packet mode, the SPI Exchange polls the PHY for the logical ports

associated to LIDs ranging from 0 up to POLL_LENGTH to find logical ports that

can accept data. The POLL_LENGTH field is defined in the SPI-3 egressconfiguration register.

• In byte mode the SPI Exchange allows for direct status detection.This status information is directly forwarded to the packet fragment proces-

sor if enabled by the BURST_EN flag. When the BURST_EN flag is clearedthe only one packet fragment per LP is allowed into the SPI-3 egress buffers.

SPI-3 egress PHY modeIn PHY mode, the SPI Exchange sends data to the attached Link-mode device

as long as the E_ENB signal is asserted. The SPI-3 packet fragment processortransfers data to the SPI-3 egress buffers.

byte mode

packet mode

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IDT88P8341(LINK MODE)PHY

E_FCLK

E_MOD[1:0]

E_SOP

E_ENB

E_PRTY

E_Data[31:0]

E_ERR

ADDR[7:0]

PTPA

DTPA[3:0]

STPA

E_EOP

E_RSX

6372 drw07

IDT88P8341(PHY MODE)

LINK

E_FCLK

E_MOD[1:0]

E_SOP

E_ENB

E_EOP

E_RSX

E_PRTY

E_Data[31:0]

E_ERR

RVAL




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APRIL 10, 2006

3.2 SPI-4Refer to OIF SPI-4 document (see Glossary) for full details of the implemen-

tation agreement.- Clock rate is 80 - 400 MHz (160 - 800MHz DDR)- Link and PHY modes supported- Address range 0 to 255 with support for 64 simultaneously active logical

ports- MAXBURST parameters configurable 16-256 bytes in 16 byte multiples- 256 entry calendar- LVTTL and LVDS status signals supportedThe following are implemented for the SPI-4 interface:- Link / PHY layer device- Physical port active

3.2.1 SPI-4 ingressThe SPI-4 ingress includes• Bit alignment• Word alignment/ de-skew• Transfer decode and dispatch• PFP interface• Status frame generation

SPI-4 ingress configurable parametersSPI-4 LID map

- 256 entries, one per SPI-4 LP- SPI-3 physical interface identifier- Physical port enable

Word / bit synchronization- LVDS clock data alignment and LVDS data de-skew

Minimum packet length- Packets shorter than the minimum length will be optionally counted in the

short packet counter.- Range 0 – 255 in 1 byte increments

Maximum packet length- Packets longer than the maximum length will be optionally counted in the

long packet counter.- Range 0 – 16,383 in 1 byte increments

Free segment backpressure threshold- Number of free buffer segments allocated to trigger backpressure for the LP


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Eye measurementC[0]= Rt.D2^Rt.D3C[1]= Rt.D3^Rt.D4…..C[7]= Rt.D9^Rt+1.D0C[8]= Rt+1.D0^Rt+1.D1C[9]= Rt+1.D1^Rt+1.D2Accumulation results during a window defined by W are stored in the

diagnostics table.The latest result can be read out for diagnostic purposes.

Output tap selectionThe sampling tap is automatically selected based on the eye measurement.

Data samplingThe I_LOW field in the Table 89 SPI-4 ingress configuration register

(Block_base 0x0300 + Register_offset 0x00) selects an operating modebetween 80 MHz and 200 MHz or between 200 MHz and 400 MHz.

Each lane is over-sampled by a factor of five. The over-sampled data isgenerated by a locked tapped delay line and clocked in to a register at the clock

rate. The current samples c(n) and the previously generated samples providesamples for the eye computation. The optimized sampling point will be selectedbased on the eye computation. The tap selector is updated if necessary at theend of the eye pattern measurement interval. The tap selector moves no morethan one tap at a time as a result of the eye pattern measurement.

CLK

d0 d1 d2 d3 d4 d5 d6 d7 d8 d9

FF FF FF FF FF FF FF FF FF FF

Data

CLK D0 D1 D9

D0

D2 D3 D4 D5 D8D7D6

D9D8D7D6D5D4D3D2D1

R(t+1)

R(t)

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Figure 7. Data sampling diagram


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APRIL 10, 2006

Manual phase selectionThe automatic phase adjustment can be overruled by the processor when

the FORCE flag is set see Table 99, SPI-4 ingress bit alignment control register(register_offset 0x11). The PHASE_ASSIGN field see Table 113, SPI-4ingress manual alignment phase/result register (0x0C to 0x1F) now defines theselected phase.

Word alignmentThe de-skew block searches for the Training Control Word 0x0FFF. If the

Training Control Word is found, then training data is expected to follow theTraining Control Word. The orthogonal training data will be used to align theword.

A de-skew control bit (I_DSC in Table 89-SPI-4 ingress configuration registerat Block_base 0x0300 + Register_offset 0x00) is used to protect against arandom data error during de-skew. If I_DSC=1, then two consecutive de-skewresults are required. It is recommended to set I_DSC to a logic one.

For diagnostics, an out of range offset between lines is provided. If the offsetis more than two bits between the earliest and latest samples, I_DSK_OOR isset to a logic one. I_DSK_OOR is cleared to a logic zero when the offset is inrange.

Transfer decode and dispatchIn the OUT_OF_SYNCH state, the de-skew block will decode the transfer,

and check the DIP-4 for validation.

A number of consecutive error free DIP-4 ingress bursts will lead to a transitionto the IN_SYNCH. The number is defined by the I_INSYNC_THR field in Table89-SPI-4 ingress configuration register (Block_base 0x0300 + Register_offset0x00).

In the IN_SYNCH state, the PFP decodes the status transfer, check the DIP-4, and dispatches the data.

A number of consecutive DIP-4 errors will lead to the OUT_OF_SYNCHstate. The number is defined by the I_OUTSYNC_THR field in Table 89-SPI-4 ingress configuration register (Block_base 0x0300 + Register_offset 0x00).

A number of consecutive training patterns will lead to OUT_OF_SYNCH.The number is defined by the STRT_TRAIN field in the Table 100 SPI-4 ingressstart up training threshold register (Block_base 0x0300 + Register_offset 0x12).This feature is disabled if STRT_TRAIN=0.

Control word and dataA control word is distinguished by the SPI-4 RTCL signal. (logic one = control

word).

DIP-4 checkFor the DIP-4 check algorithm refer to the OIF SPI-4 document [Glossary].

In both IN_SYNCH and OUT_OF_SYNCH states, only control word previousand following data is checked. Any transition on synch status will be captured.In IN_SYNCH state, each DIP-4 error is captured and counted.

IN_SYNCH

OUT_OF_SYNCH

A= A number of consecutive DIP-4 error or reset or interface disabled or a number of consecutive training pattern receivedB= A number of consecutive DIP-4 error free

A B

6372 drw09

Figure 8. SPI-4 ingress state diagram

Transfer decodeThe SPI-4 ingress control word contains various fields. Refer to the OIF SPI-

4 document [Glossary] for details. If reserved control word, BIT[15:12]=0011,0001, 0101, or 0111 is detected, a BUS_ERROR event is generated. If apayload control word is not followed by a data word, or a data word does notfollow a payload control word, a BUS_ERROR event is generated. If abort isdetected, the next packet will be tagged with an error.

Data dispatchThe port address field of a payload control word is extracted as a search key.

The search key is used to search the dispatch info in Table 86, SPI-4 ingressLP to LID map (256 entries, one per LP). If the searched port is active, transferdata is sent to the associated PFP with SOP, EOP, LENGTH, PACKET_ERROR.If the searched port is inactive, a SPI4_INACTIVE_TRANSFER event is

generated. A SPI-4 inactive transfer event with it's associated LP will be capturedin the Table 40, SPI-4 status register (0x22 in the direct accessed space).

SPI-4 ingress status channelCalendar structure and swapping

The SPI Exchange supports one or two sets of calendars. If I_CSW_EN fieldin the Table 89, SPI-4 ingress configuration register (0x00)=1, two sets ofcalendars are supported. A calendar selection word must be placed followingthe framing bit. Refer to the OIF SPI-4 document [see Glossary] for more details.

SPI-4 ingress status channel frame generationThe status frame can be one of the following cases:• All ‘11’ when LVTTL is in the out of synch state• Training pattern when LVDS is in the out of synch state or in periodic training


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APRIL 10, 2006

• Normal status information when in the IN_SYNCH stateThe normal status information is generated based on ingress buffer full

information and PFP buffer segment fill level.For information on DIP-2 generation and training pattern refer to the OIF SPI-

4 document [Glossary].

DIP-2 error insertionA number of consecutive DIP-2 errors can be generated. The I_ DIP_E_NUM

field in Table 97, SPI-4 ingress diagnostics register (register_offset 0x0F)specifies the number of errors to be generated. A logic one written toI_ERROR_INS will activate the I_DIP_E_NUM field and trigger error insertion.The I_ERROR_INS field self clears when the number of errors have beengenerated.

LVTTL and LVDS status interface selectionThe LVDS_STA pin selects which FIFO status interface is being used for SPI-

4. HIGH = LVDS status interface, LOW = LVTTL status interface.

3.2.2 SPI-4 egressThe SPI-4 egress includes• Status channel synchronization• Status updating• Data transfer• Periodic training• PFP interface

SPI-4 egress configurable parametersAll parameters as listed in the 0IF SPI-4 document [see Glossary]CALENDAR_LEN: 4 to 1,024 in increments of 4CALENDAR_M: 1 to 256 in increments of 1MaxBurst1 (MaxBurst_S): 16 to 256 in increments of 16MaxBurst2 (MaxBurst_H): 16 to 256 in increments of 16Alpha: 1 to 256 in increments of 1DATA_MAX_T: 1 to 4,294,967,040 in increments of 1FIFO_MAX_T: 1 to 16,777,215 in increments of 1

Calendar and shadow calendar- 256 entries- E_CSW_EN field in Table 104, SPI-4 egress configuration register_0

(register_offset 0x00) bit for manual reconfiguration swap

Multiple burst enable- Allows more than one burst to be sent to an LP. Feature included to relieve

systems with long latency between updates.

SPI-4 egress LID to LP map- 256 entries, one per SPI-4 LP- Enable bit

Ingress egressOut of synch, send status training Out of synch, send data trainingIn synch, send status frame Out of synch, send data trainingIn synch, send status frame In synch, send data/idle

3.2.3 SPI-4 startup handshake

Ingress EgressOut of synch, send status training In synch, send data/idleOut of synch, send status training Out of synch, send data trainingIn synch, send status frame Out of synch, send data trainingIn synch, send status frame In synch, send data/idle

Ingress EgressIn synch, send status frame Out of synch, send data trainingOut of synch, send status training Out of synch, send data trainingIn synch, send status frame Out of synch, send data trainingIn synch, send status frame In synch, send data/idle

TABLE 11 � INGRESS OUT OF SYNCH, EGRESS IN SYNCH

TABLE 10 � BOTH ATTACHED DEVICES START FROM RESET STATUS

TABLE 12 � INGRESS IN SYNCH, EGRESS OUT OF SYNCH


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SPI-4 egress status channelStatus channel bit alignment

The bit alignment algorithm for the status channel is the same as was describedfor the data channel.

Validate

IN_SYNCH

A

B

A= a number of consecutive error free DIP-2s receivedB= a number of consecutive DIP-2 errors, in training, port disabled, or reset

HUNT

C

D

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Figure 9. SPI-4 egress status state diagram

The status channel frame module has 3 states: HUNT, VALIDATE andIN_SYNCH.

In the HUNT state, the status channel frame module searches for statusframe, status clear and status freeze.

In the VALIDATE state, the status channel frame module checks DIP-2.In the IN_SYNCH state, the status channel frame module checks DIP-2, and

updates status.

HUNT state• In the HUNT state, per Link status is fixed to ‘satisfied’.• In HUNT state, the PFP searches frame continuously. It transitions to the

VALIDATE state if a single frame is found accompanied by a single valid trainingpattern. A frame is considered to be found if : 1) only one frame word is at thebeginning of a frame, 2) the calendar selection word, if enabled, is matched, and3) the DIP-2 calculation matched the received DIP-2.

VALIDATE stateIn the validate state, based on the frame found while in the HUNT state,

the DIP-2 is checked.If a single DIP-2 error is found, transition to the HUNT state.After a number of consecutive DIP-2 calculations proves to be error free,

transition to the IN_SYNCH state. The number is defined by the E_INSYNC_THRfield in Table 104-SPI-4 egress configuration register_0 (Block_base 0x0700+ Register_offset 0x00).

In the validate state, the training pattern is not checked.

IN_SYNCH stateIn the IN_SYNCH state, training frame and status frame are checked.DIP-2 is checked for status frame. Each mismatched DIP-2 will generate a

DIP-2 error event, each event will be captured and counted.After a number of consecutive DIP-2 errors, transition to the HUNT state.

(Clear status in HUNT mode). The number is defined by the E_OUTSYNC_THRfield in Table 104-SPI-4 egress configuration register_0 (Block_base 0x0700+ Register_offset 0x00).

The reception of twelve consecutive training patterns forces a transition toHUNT mode. If less than twelve consecutive training patterns are received,synch will not be lost, and status frame starts at the end of training.

Twelve consecutive ‘11’ patterns force a transition to the HUNT state.Status updating occurs without waiting for the end of a status frame.

LVTTL or LVDS status channel optionThe LVDS_STA pin selects the interface type. A logic high enables the LVDS

status interface. A logic low enables the LVTTL status interface.

Data channelData transfer and training

At any cycle, the contents on the interface can be one of the following:• Control word: Payload control word, or idle control word or training control

word.• Data word: Payload data word or training data word.

In the HUNT or the VALIDATE state, the training pattern is sent.In the IN_SYNCH state, data from is taken from the buffer segments and

egressed to the SPI-4 interface. The switch between data burst, IDLE, andtraining must obey the following rules:

• Send IDLE if no data to transmit• SOP must not occur less than 8 cycles apart.• periodic training after current transfer finished

Payload control word generation:• Bit 15, Control word type=1• Bit [14:13] EOPS per [see Glossary: SPI-4]. If an error tag is in the

descriptor, abort.• Bit [12] SOP refer to [see Glossary: SPI-4]• Eight Bit Address. Mapping table defined in Table 101, SPI-4 egress LID

to LP map (256 entries)• DIP-4 bit refer to [see Glossary]

Payload data word• Bit order refer to [see Glossary: SPI-4]• If only one byte is valid, 8 LSB (B7 to B0) is set to 0x00.

No status channel optionOnce the NOSTAT bit is set, the status channel is ignored. Refer to Table 104,

SPI-4 egress configuration register_0 (register_offset 0x00).Status in default value.No DIP error check.No status updating, the received status fixed to STARVING.Data channel works same as in IN_SYNCH state.

Status Channel Frame synchronization

Status channel de-skewThe LVDS status channel deskew uses the same algorithm as the as the data

channel.


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APRIL 10, 2006

3.3 Microprocessor interface- Parallel microprocessor interface

• 8 bit data bus for parallel operation• Byte access• Direct accessed space• Indirect access space is used for most registers• Read operations to a reserved address or reserved bit fields return 0• Write operations to reserved addresses or bit fields are ignored

- Serial microprocessor interface• Compliance to Motorola serial processor interface (SPI) specification• Byte access• Direct accessed space• Indirect access space is used for most registers• Read operations to a reserved address or reserved bit fields return 0• Write operations to reserved addresses or bit fields are ignored

General purpose I/OFive general purpose I/O pins are provided. The direction is independently

controlled by the DIR_OUT field in the GPIO register (Table 123 GPIO Register

(0x20)). The logical level on a pin is controlled by the LEVEL field in the GPIOregister if DIR_OUT=1, or sensed if DIR_OUT=0. The LEVEL bit monitors thelogic level of any bit selected from the indirect access space if MONITOR_ENis set high. A bit in the indirect access space can be selected for monitoring bythe by the ADDRESS and BIT fields in the GPIO Link table (Table 124, GPIOMonitor Table (5 entries 0x21-0x25 for GPIO[0] through GPIO[4])).

All GPIO pins must be programmed into or out of monitor mode at the sametime.

Interrupt schemeEvents are captured in interrupt status registers. Interrupt status flags are

cleared by an microprocessor write cycle. A logical one must be written to clearthe flag(s) targeted. A two level interrupt scheme is provided comprising aprimary level and a secondary level.

The primary level identifies the secondary interrupts sources with a pendinginterrupt. This information is reflected in the primary interrupt register. Interruptstatus can be enabled by associated flags both in the primary and secondarylevel of the interrupt scheme.

Figure 10. Interrupt scheme

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event

enable

&

|

|INTB

interrupted status

primary interrupt level

&captured event

interrupted status

enable

model status

secondary interrupt level


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APRIL 10, 2006

4. DATAPATH AND FLOW CONTROLThe following sections describe the datapaths through the device. The

datapaths shown are as follows:- SPI-3A <-> SPI-4- SPI-3A <-> microprocessor interface- SPI-4 <-> microprocessor interfaceWhere <-> indicates a bidirectional data path.

The IDT88P8341 supports one SPI-3 interface and one SPI-4 interface. TheSPI-3 interface can operate in a PHY or Link mode. Refer to Figure 11, Definitionof Data Flows for the main data flows in the device. Logical data flows aretransported over the physical ports. The logical flows are identified by logicalport addresses on the physical port and by a Link identification (LID) map in thecore of the IDT88P8341.

DATA BUFFER ALLOCATIONFlexibility has been provided to the user for data buffer allocation. The device

has 128 KByte of on chip memory per direction – a total of 256 KByte of on-chipdata memory.

The 128 KByte SPI-3 buffers are divided into 256 byte segments. Thesegments are controlled by a packet fragment processor. The user configuresthe maximum number of segments per LP to allocate to a port and the numberof segments allocated from the buffer segment pool that will trigger the flow controlmechanism. There is no limitation on the reallocation of freed segments amonglogical ports, as would be present if the memory had been allocated by a simpleaddress mechanism.

Figure 11. Definition of data flows

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SPI-3 physical port SPI-4

to SPI-3

from SPI-3 to SPI-4

from SPI-4

SPI-3 egress

SPI-3 ingress

SPI-4 ingress

SPI-4 egress

SPI-3-4 path

SPI-4-3 pathphysical

port

SPI-3 extract

SPI-3 insert

SPI-4 insert

SPI-4 extract




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APRIL 10, 2006

DATAPATH CONFIGURATIONA logical view of datapath configuration using Packet Fragment Processors

is shown in Figure 12, Logical View of Datapath Configuration Using PFPs.Two PFPs are associated with each SPI-3 port, one for ingress and one for

egress. Logical ports are mapped internally into Logical Identifiers (“LIDs”, “LIDMap”) for the control of each per-LID data flow to each physical port, logical port,memory queue size, and backpressure threshold (watermark), by program-ming the LID register files.

Figure 12. Logical view of datapath configuration using PFPs

LID - Logical IdentifierEN - LID enable flagBRV - Bit reversalLP - Logical portPFP - Packet fragment processor

[LID] = LP | EN | BRV

SPI-3 Egress LID to LP Map

[LP] = LID | EN | BRV

SPI-3 Ingress LP to LID Map

[LID] = LP | EN

SPI-4 INGRESS DATA

SPI-4 EGRESS DATA

[LP] = LID | PPE | EN

LID BRVEN

LP BRVEN

LP EN

256 LIDs

SPI-4 Egress LID to LP Map

PFP AND MEMORY(ONE OF FOUR: ABCD)



PFP AND MEMORY




SPI-3 INGRESS DATA

SPI-3 EGRESS DATA

PFP AND MEMORY

LID ENA/B

256 LPs

SPI-4 Ingress LP to LID Map

256 LPs

64 LIDs

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APRIL 10, 2006

4.1 SPI-3 to SPI-4 datapath and flow controlTwo packet fragment processor modules from SPI-3 to SPI-4 are provided.

One packet fragment processor module is associated with one SPI-3 ingressinterface. The packet fragment processor module connects to the SPI-4interface.

Packet fragments from the SPI-3 ingress are received into the SPI-3 ingressport buffers. A packet fragment processor transfers complete packet fragmentsfrom the SPI-3 ingress port buffers to memory segments previously reservedon a per-LP basis in the buffer segment pool. The SPI-3 ingress port buffer

watermark and the per-LP free buffer segment threshold information is combinedto produce SPI-3 ingress FIFO status towards the attached device. Packets orpacket fragments received on one SPI-3 ingress logical port can be forwardedto any one of:

A logical port on the egress SPI-4 interface.The microprocessor interface, using the capture buffer.The connection on the logical port level is performed through an intermediate

mapping to a Link Identification number (LID).

Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor

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buffer segment pool

PMON & DIAG

SPI3 egress portbuffers

uPAssociatedegress PFP

capturebuffer

SPI-3redirectbuffers

uP

insert buffer

SPI3 Ingress

SPI4 Egress

FIFO status

FIFO status

SPI3 ingress portbuffers

SPI-3 ingress PFP functionsThe packet fragment processor(PFP) receives status information about the

SPI-3 ingress buffers and the microprocessor insert buffer. The PFP processesSPI-3 ingress buffers in high priority and the insert buffer with low priority. ThePFP copies data into the buffer segment , requests new buffer segments, andgenerates entries in the SPI4-egress queue.

SPI-3 ingress buffer processingThe PFP verifies whether a SPI-3 ingress buffer is occupied. If the SPI-3

ingress buffer is not occupied the PFP processes the insert buffer.

Normal operationIn loopback mode, all of the SPI-3 ingress buffers of a physical SPI-3 port are

copied into the SP-3 egress buffers of that same port. This is a test mode only,as no non-loopback traffic can be transferred at this time.

In non – loop back mode (normal operation) the SPI-3 ingress buffers areforwarded to the LID process by the PFP.

The LID process generates a set of events for an associated LID. The eventsthat are directed towards the PMON&DIAG module are:

• SPI-3 error tagged packet event (errored packets)• SPI-3 EOP event (all packets)• SPI-3 fragment event (all fragments) with an associated length field


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APRIL 10, 2006

Erroneous operationSPI-3 ingress buffers marked with an address parity error are always

immediately flushed. A SPI-3 flush event is generated.

Store processThe process parameters are stored in a descriptor table. One entry in the

table is required for each of the SPI-3 logical ports. Refer to Table 49, SPI-3ingress LP to LID Map.

• Fragments tagged with an SOP indication trigger the buffer segment requestprocess. The internal Packet_length variable is initialized. The copy processis triggered.

• Fragments tagged with an EOP indication will trigger the packet length checkprocess and the queue process.

• Non marked (EOP or SOP) buffers are subject to the copy process.

Buffer segment request processA new buffer segment is requested for the logical port from the buffer segment

pool.The request can be accepted or rejected by the buffer pool.When accepted, the Current_Seg and current Seg_Length variables are

updated.When rejected, the SPI-3 ingress buffer is flushed. An SPI-3 flush event is

generated and directed towards the Table 61, Non LID associated eventcounters (0x00 - 0x0B). The buffer data is not copied into the SPI3-4 buffer.

Copy processData is retrieved from the buffer and stored in the current segment. The data

parity error status is stored in the Pack_Err variable. The Packet_Lengthvariables and Seg_Length variables are updated. The queue and requestprocesses are triggered when the number of bytes in the buffer segment equalsthe SPI-3 packet fragment size programmed for that physical interface, or anEOP is reached.

Queue processThe current segment is entered into the SPI-4 egress queue.

Packet length checkThe length of the packet is compared to the MIN_LENGTH and MAX_LENGTH

parameters in the ingress SPI-3 Port descriptor table. If the packet length is lessthan the programmed field MIN_LENGTH a “SPI-3 too short packet event” isgenerated. If the packet length is greater than the programmed field MAX_LENGTHa “SPI-3 too long packet event” is generated. The events are directed towardsthe Table 61, Non LID associated event counters (0x00 - 0x0B).

SPI-3 to SPI-4 buffer managementA 128 KB SPI-3 to SPI-4 buffer segment pool is assigned to each physical

SPI-3 ingress port. A configurable part of this buffer segment pool is assignedto buffers associated to each of the up to 64 LIDs. The buffer size for a LID canbe configured in multiples (M) of 256 bytes. Fewer LIDs allow larger buffers perLID, conversely a large number of LIDs will require smaller buffers per LID.Within this restriction, the buffer size of each LID can be further restricted as

needed to control latency. Modifications of the buffer size allocated to a LID aresupported only when the logical port associated to the LID is disabled. Attemptsto allocate more memory than available will generate an allocation error event.The indirect access module will discard the attempt.

Free buffer segment poolStorage

The buffer segment pool is divided into 508 segments. The device holds apool of free buffer segments. The buffer segment pool keeps track of the numberof segments assigned to each LID and holds a list of free segments.

Buffer segment requestsA new segment for a logical Link (LID) can be requested from the buffer

segment pool for that SPI-3 ingress physical port by the SPI-3 ingress packetfragment processor associated to that SPI-3 physical port. A request may beaccepted immediately or rejected. When the request is accepted a buffersegment ID is returned immediately.

Buffer segment pool returned segmentsA buffer segment can be returned to the buffer segment pool when the egress

module releases it. This allows the segment to be used once more by the SPI-3 ingress.

SPI-4 egress queuesNormal operation

508 SPI-4 egress queue entries are provided. They are evenly allocatedto the number of logical ports as defined by the static NR_LID configuration. Oneentry in the queue corresponds to a packet or a packet fragment to be forwardedto the SPI-4 egress interface.

SPI-3 ingress BackpressureThe module directs status signals for each of the 64 LIDs associated with a

SPI-3 physical interface towards the SPI-3 ingress interface. The status signalsrequest to transfer more data on the logical port associated to the LID. Theavailable status is defined by the function (if free segments [LID] > Threshold,status =available).

SPI-4 egress direction controlThe SPI-4 egress traffic can be captured by the microprocessor, directed to

an associated SPI-3 egress port (SPI-3 port A to B, or port C to D, only), to theSPI-4 egress port, or discarded. The selection is defined for each of the 64 LIDsby the associated DIRECTION field in the Table 13, Direction code assignment.

DIRECTION Path00 SPI-401 Associated SPI-310 Capture to microprocessor11 Discard

TABLE 13 - DIRECTION CODE ASSIGNMENT


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APRIL 10, 2006

SPI-4 egress data burstsThe PFP produces fragments of up to N*16 bytes. N is defined by the

MAX_BURST_H or MAX_BURST_S parameter associated with each LID. Fora high priority (starving) LID the MAX_BURST_S parameter is used. For a lowpriority (hungry) LID the MAX_BURST_H parameter is used. The PFP maynot fill the buffers to the level granted when a new segment needs to be usedin the SPI3-4 buffer memory or when the last fragment of a packet is copied intothe buffer. The information received over the FIFO status channel is interpretedas status or credit information as selected by the CREDIT_EN flag in Table 78,SPI-3 to SPI-4 flow control register (0x01). If the status mode is used, data willbe egressed until the status is changed. If the credit mode is used, the SPI-4egress will issue only one credit’s worth data burst and then wait for another creditfrom the status channel before issuing another LID burst.

SPI-4 egress FIFO status channel updatesThe SPI-4 egress FIFO Status Channel Module continuously verifies the

status information for the LIDs associated to SPI-4 logical ports. The PFPsearches and selects a LID, fetches the associated information and queues datato the SPI-4 egress. The obsolete buffer segment is returned to the free buffersegment pool (unless the repeat test feature is enabled). Searching the LID tobe served is performed for both a high priority and a low priority LID. The priorityis defined by the status received from the SPI-4 egress module.

SPI-3 ingress logical port mappingThe SPI-3 interface has an associated SPI-3 ingress LP to LID map, (See

Table 49) for the purpose of directing the packet fragments from the SPI-3 ingressto its associated SPI-3 ingress main memory buffer segment pool. The SPI-3LID map has 256 entries, one per SPI-3 LP, but only 64 LPs are supported onthe SPI-3 interface at any one time. The SPI-3 interface has an enable bit, aswell as the ability to reverse the bit ordering within bytes of the interface. Thepacket fragment length is associated with the SPI-3 interface. The allowed rangeis 0 to 255 bytes per packet fragment. The last fragment of a packet can be shorterthan the programmed fragment size. The SPI-3 port can be independently setfor either Link or PHY mode of operation.

SPI-3 ingress LID associated controlEach LID on the SPI-3 interface has the ability to be programmed for minimum

and maximum packet length. The minimum packet length can be set from 0 to255 bytes in one byte increments. The maximum packet length can be set from0 to 16,383 bytes in one byte increments. Each LID can be enabled and disabledindependently.

Figure 14. SPI-3 ingress LP to LID map

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LID BRVEN

256 LPs

[LP] = LID | EN | BRV

LID: Logical IdentifierEN: LID EnableBRV: Bit Reversal


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APRIL 10, 2006

SPI-4 egress interface port associated controlThe SPI-4 interface has an associated LID to LP map (See Table 101 - SPI-

4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF)for the purpose of directing the packet fragments from the selected SPI-3 ingressmain memory buffer segment pool to the SPI-4 egress interface. The SPI-4 LIDmap has 256 entries, one per LID. The SPI-4 interface has an enable bit. Theburst length is associated with the SPI-4 interface. The allowed burst range is16 to 256 bytes per burst. The last burst of a packet can be shorter than theprogrammed burst size.

SPI-4 egress LID associated controlEach of the 256 entries in the SPI-4 egress LID to LP map (See Table 101

- SPI-4 egress LID to LP Map (256 entries)) is used to control the pulling of burstsout of the buffer segment pool and into the SPI-4 egress interface. Each LID canbe enabled and disabled independently.

Figure 15. SPI-4 egress LID to LP map

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LP EN

256 LIDs

[LID] = LP | EN

Figure 16. SPI-3 ingress to SPI-4 egress datapath

LP: Logical PortEN: LP Enable

…

…

JTAG uproc

LID Counters Memory

SPI-38 bit / 32 bit

Min: 19.44MHzMax: 133MHz

Interface Block

Chip Counters Memory

Interface Block

SPI-3 /LID map

MainMemory

A

SPI-4.2Min: 80 MHzMax:400 MHz

SPI-4 /LID map

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The diagram below shows the datapath through the device from the SPI-3 ingress interface to the SPI-4 egress interface.


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APRIL 10, 2006

SPI-3 ingress to SPI-4 egress flow controlFor control information there are two separate cases to consider: The case

that the SPI-3 physical interface port is configured in Link mode, and the casethat the SPI-3 is configured in PHY mode. Note that since the SPI-3 physicalinterfaces are configured separately, the device is able to deal with the case thatsome of the LP fragments have been received on a Link layer device SPI-3interface and some have been received on a PHY layer device SPI-3 interface.

For a device in Link mode the Link device can only control the flow of datathrough the RENB signal. Two modes of operation are implemented andconfigurable for flow control on this interface – either the data can be allowedto flow freely into the device or the RENB signal will be asserted if a conditionarises that one of the LPs is unable to receive another fragment. The first of thesemodes is considered to have no Link layer device flow control, and the secondhas Link layer device flow control.

For the no Link flow control mode, any data sent to an LP unable to receiveanother fragment will cause an LP overflow.

For a device in Link mode the Link has complete knowledge of the fill levelof the data buffers in each of the LPs in the PHY. This knowledge is attained eitherthrough byte level polling or packet level polling.

Both in Link and PHY modes, the data is collected to buffer segmentsassociated with an LP. The SPI-4 PFP is updated with the number of freesegments available to the LP. The SPI-4 PFP determines which LP to servicebased on two factors: whether the LP contains enough data for a burst, and thestarving / hungry / satisfied state of the LP. For details on the mapping of LPsto LIDs, refer to Table 101 - SPI-4 egress LID to LP Map Block_base 0x0400= Register_offset 0x00 - 0xFF.

SPI-3 ingress flow control registersThe following are implemented per SPI-3 interface, and there are two

instantiations per device.

Backpressure enableLink mode onlyEnables the assertion of the I_ENB pin when at least one active LID can not

accept dataIf not enabled, the I_ENB signal will never be asserted in Link mode, possibly

leading to fragments being discarded.

SPI-4 egress flow control configurable parametersAll parameters as listed in SPI-4 implementation agreement:CALENDAR_LEN: 4 to 1,024 in increments of 4CALENDAR_M: 1 to 256 in increments of 1MaxBurst1 (MaxBurst_S): 16 to 256 in increments of 16MaxBurst2 (MaxBurst_H): 16 to 256 in increments of 16Alpha: 1 to 256 in increments of 1DATA_MAX_T: 1 to 4,294,967,040 in increments of 1FIFO_MAX_T: 1 to 16,777,215 in increments of 1

SPI-4 egress flow control calendar and shadow calendar256 entries

SPI-4 egress flow control multiple burst enableAllows more than one burst to be sent to an LP. This feature was included

to increase throughput in systems with long latency between updates.

Figure 17. SPI-3 ingress to SPI-4 egress flow control path

The diagram below shows the SPI-3 ingress to SPI-4 egress flow control Paththrough the IDT88P8341 device.

4

…

…

JTAG uproc

LID Counters Memory

SPI-38 bit / 32 bit


Interface Block


Interface Block

SPI-3 /LID map

MainMemory

A


SPI-4 /LID map

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STATUS

DATA PATH

STATUS

STATUS



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APRIL 10, 2006

4.2 SPI-4 to SPI-3 datapath and flow controlTwo Packet Fragment Processor modules from SPI4 ingress to SPI-3 egress

are provided, all connected to one SPI-4 ingress interface.Packet bursts from the SPI-4 ingress are received into the SPI-4 ingress port

buffers. A packet fragment processor transfers complete packet bursts from theSPI-4 ingress port buffers to memory segments previously reserved on a per-LP basis in the buffer segment pool. The SPI-4 ingress port buffer watermarksand the per-LP free buffer segment threshold information is combined to produceSPI-4 ingress FIFO status (per-LP starving, hungry, or satisfied) towards theattached SPI-4 device. Per-LP buffer segment threshold information is used toproduce FIFO status information for the attached SPI-3 device. Packets orpacket fragments are forwarded to the SPI-3 interface when a packet is completeor a predefined number of bytes have been received. Packets or packetfragments received on one SPI4 logical port are cross connected to an SPI3logical port through an intermediate mapping to a Link identification, or LID. Itsmode of operation is similar to the SPI-3 ingress to SPI-4 egress packet fragmentprocessor, with the following differences:

1) The PFP4-3 data input has three sources, listed in descending priority:SPI-4 buffers, redirect buffers, and insert buffers.

2) The PFP3-4 data output has only three destinations. There is no SPI-3to SPI-4 redirect path.

Each SPI-3 interface feeds ingress buffer available or ingress bufferunavailable status information to its packet fragment processor.

If the number of free segments available to a LP exceeds the starvingthreshold, the SPI-4 status is moved to starving for that LP. If the number of freesegments available to a LP exceeds the hungry but not the starving threshold,the SPI-4 status is moved to hungry for that LP. If the hungry threshold is notexceeded, the SPI-4 FIFO status channel will indicate satisfied for that LP.

SPI-4 ingress to SPI-3 egress datapathThe following is a description of the path taken by a burst of data through the

device from the SPI-4 ingress to a SPI-3 egress.Data enters on the SPI-4 ingress interface in bursts. Bursts are normally of

equal length except the last burst of a packet which may be shorter. The controlword is in-band with the data. Burst data enters a SPI-4 ingress buffer. SPI-4LP address, error information, SOP, EOP are stored with the burst data. A SPI-4 LP address is mapped to a Logical IDentifier (LID). The burst is stored in perLID allocated buffer segments reserved from the buffer segment pool.

The appropriate SPI-3 egress control register (Table 80 - SPI-3 egress portdescriptor table (64 entries)) is consulted, and it determines to send this LID toa prescribed SPI-3 egress port.

The selection of which LP is to be transmitted next is dependent on the statusof the LP and the availability of a complete fragment. Data is moved to theappropriate SPI-3 egress buffer along with the LP address. SPI-3 LP address,error information, SOP, and EOP information is stored with the packet fragment.Next, data is transmitted in packet fragments over the selected SPI-3 interface.

Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor

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FIFO Status

SPI4 Ingress

uP

capturebuffer

uP

insertbuffer

Associatedingress PFP

SPI-3redirectbuffers

buffer segment pool

SPI-3 egress portbuffers

SPI-4 ingress portbuffers

FIFO Status

EgressSPI-3


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APRIL 10, 2006

SPI-4 ingress interface configurable parameters:The IDT88P8341 can interface to either a Link or a PHY layer device. The

SPI-4 port can be enabled or disabled.The SPI-4 ingress bits are aligned with the ingress clock. In addition, the SPI-

4 words are then aligned among each other to produce valid words. This isperformed both on the data channel and the status channel. The bit alignmentalgorithm runs as long as the interface is active. The word alignment algorithmis run during training intervals.

SPI-4 ingress per-LID configurable parametersSPI-4 to SPI-3 LID map

256 entries, one per SPI-4 LPSPI-3 physical interface identifierSPI-3 LIDEnable bit per LID

SPI-4 ingress packet length checkEach LID on the SPI-4 ingress interface has the ability to be programmed for

minimum and maximum packet length. The minimum packet length can be setfrom 0 to 255 bytes in one byte increments. The maximum packet length canbe set from 0 to 16,383 bytes in one byte increments. Packets shorter or longerthan set by these parameters will be optionally counted in the short or long packetcounter for that LID.

SPI-3 egress configurable parametersLength of SPI-3 packet fragment

All packet fragments from a particular SPI-3 physical interface are program-mable to an equal length with the possible exception of an EOP fragment whichmay be shorter.

SPI-3 egress poll lengthApplies when the SPI-3 interface is acting as a Link layer device when using

the packet level polling modeCauses polling of the PHY for the logical ports associated with LIDs ranging

from [0 up to POLL_LENGTH] to find logical ports that can accept dataPoll range is 0-63 LPs.

SPI-3 egress per-LID configurable parametersMany parameters to control the flow of data are programmable per LID. The

following paragraphs describe these parameters.

SPI-3 egress LID to LP mapone map per SPI-3 physical port64 entries per map, one per LIDLP enable bit per LPBit reversal enable per LP

SPI-3 egress multiple burst enableMultiple Burst Enable allows more than one burst to be sent to an LP. This

feature is included to relieve systems with long latency between updates. Whenthis feature is not enabled, only one burst per LP is allowed into the round robinSPI-3 egress buffers at a time.

SPI-4 ingress to SPI-3 egress data memorySPI-3 egress control

There is a SPI-3 egress port descriptor table for the paths out of the datamemory. The function a SPI-3 egress port descriptor table is to define wheredata goes after leaving the main data memory. There are three configurableoptions:

SPI-3 egressMicroprocessor Interface CaptureDiscard

Maximum number of memory segmentsDefines the largest Buffer available to an LP / LIDEach segment is 256 bytesRange 1 – 508 in increments of one segmentThe figure below shows the datapath through the device from the SPI-4

interface to the SPI-3 interface.

Figure 19. SPI-4 ingress to SPI-3 egress datapath

…

…

JTAG uproc

LID Counters Memory

SPI-38 bit / 32 bit


Interface Block


Interface Block

SPI-3 /LID map

MainMemory

A


SPI-4 /LID map

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APRIL 10, 2006

SPI-4 ingress to SPI-3 egress flow controlThe SPI-4 control information is transmitted to the adjacent device. The

adjacent device determines which LP to service next according to the statusinformation it receives from the IDT88P8341. The SPI-4 ingress data arrive inbursts that are of equal length except for the last burst of a packet which maybe shorter.

The SPI-4 burst data is transferred to the per LID allocated buffer segments.The addition of the data may cause an update of the SPI-4 status information(starving, hungry, satisfied), and may change the SPI-3 STPA, DTPA, or PTPAsignals when in PHY mode.

For the control information there are two separate cases to consider: the casethat the SPI-3 is configured to Link mode, and the case that the SPI-3 is configuredto PHY mode.

When in PHY mode, the data is sent according the availability of the data inthe buffer segment pool. In the Link mode an extra consideration is taken toaccount – that of the fill level of the ingress FIFOs in the adjacent device.

Backpressure threshold- Number of free segments allocated to trigger backpressure for the LPThe diagram below shows the SPI-4 to SPI-3 flow control path through the

IDT88P8341 device.

Figure 20. SPI-4 ingress to SPI-3 egress flow control

…

…

JTAG uproc

LID Counters Memory

SPI-38 bit / 32 bit


Interface Block


Interface Block

SPI-3 /LID map

MainMemory

A


SPI-4 /LID map

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STATUS

STATUS

STATUS




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APRIL 10, 2006

4.3 Microprocessor interface to SPI-3 datapathcapture/insert configurable parameters

Enable insertion / capture of data to the SPI-3 or SPI-4 data stream (whichis dependent on the egress control register). For each direction, the followingare to be used:

- Data for insertion or data captured- Data available: set when data is available. Asserted by device for capture,

asserted by microprocessor for insertion.- LID: Logical Identifier of capture / insertion channel- Length: length of data for insertion or capture- Flags: SOP, EOP, address parity error, data parity error, packet error

There are separate instantiations of microprocessor insert capture buffers forSPI-3 and SPI-4.

Capture data fragmentPackets can be captured from the SPI-3-4 stream and directed towards the

microprocessor. The capture buffer can store only one 256 byte packetfragment. When the buffer is full the DATA_AVAILABLE flag is set and a SPI-3 capture event is generated. The event is directed towards the interrupt module.

Read packet data fragmentThe microprocessor needs to read a buffer to capture a packet fragment. It

verifies the DATA_AVAILABLE flag in the SPI-3 capture control register.

Microprocessor reads the packet fragment and EOP, SOP, ERROR, LID andLENGTH fields from the SPI-3 data capture buffer. Microprocessor hands overcontrol of the capture buffer when it clears the DATA_AVAILABLE flag in the SPI-3 data capture control register (Table 31 - SPI-3 data capture control register).

4.3.1 SPI-3 to ingress microprocessor interfacedatapath

The diagram below shows the datapath through the device from the SPI-3interface to the microprocessor capture interface.

The following is a description of the path taken by a fragment of data throughthe device.

Data enters on a SPI-3 interface in fragments. Fragments are of equal lengthexcept the last fragment of a packet which may be shorter. The LP address isin-band with the data. The fragment enters a SPI-3 ingress buffer. SPI-3 LPaddress, error information, SOP, and EOP are stored with the fragment. TheLP address is mapped to a LID. The fragment is stored in LID allocated buffersegments.

The Table 80, SPI-3 egress port descriptor table (64 entries) is consulted,and the PFP decides to send this LID to the microprocessor capture port. Datais moved to the capture buffer along with the LP address. LID, error information,SOP, and EOP. The data available bit is set. Data and control information areread from the relevant register space through the microprocessor interface.

Figure 22. SPI-3 ingress to microprocessor capture interface datapath

Figure 21 . Microprocessor data capture buffer6372 drw22

flags

length

data[1]

data[2]

data[255]

lid

data[0]

SOP EA ED PAR EOP not used

EA

ED

PAR data parity error

address parity error

packet error

7 0

inse

rt s

eque

nce

t

t+1

t+258

extr

act s

eque

nce

t

t+1

t+258

…

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SPI-38 bit / 32 bit


SPI-4.2Min: 80 MHz

Max: 400 MHz

Interface Block

Interface Block SPI-3 /

LID mapSPI-4 /LID map

MainMemory

A

LID Counters Memory

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4.3.2 Microprocessor insert to SPI-3 egressdatapath

The diagram below shows the datapath through the device from themicroprocessor data insert interface to a SPI-3 egress port.

The following is a description of the path taken by a fragment of data throughthe device.

Data and control information are written to the insert buffer through themicroprocessor interface. The data available bit is set. Data is stored along withits LP address, LID (including SPI-3 choice), error information, SOP, and EOP.

Data is stored in LID-allocated buffer segments. The Table 80, SPI-3 egressport descriptor table (64 entries) is consulted and the PFP decides to move thedata to the SPI-3 egress port. The SPI-3 packet fragment processor choosesthe next LP. The choice of LP is dependent on the status of the LP and theavailability of a complete fragment. Data is moved to a SPI-3 egress buffer alongwith its LP address. SPI-3 LP address, error information, SOP, and EOP.

Data is transmitted in packet fragments over the selected SPI-3 egressinterface.

Figure 24. Microprocessor interface to SPI-3 egress detailed datapath diagram

Figure 23. Microprocessor data insert buffer

6372 drw22

flags

length

data[1]

data[2]

data[255]

lid

data[0]


EA

ED



packet error

7 0

inse

rt s

eque

nce

t

t+1

t+258

extr

act s

eque

nce

t

t+1

t+258

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Interface Block


Interface Block

SPI-3 /LID map

MainMemory

A


SPI-4 /LID map

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4.3.3 Microprocessor interface to SPI-4 egressdatapath

Packets can be inserted into the SPI-3-4 datapath by the microprocessor. Thefollowing is a description of the path taken by a burst of data through the device.

Data and control information are written to the insert buffer through themicroprocessor interface. The data available bit is set. Data is stored in the insertbuffer along with the LP address, LID, error information, SOP, and EOP. Datais stored in per-LID allocated buffer segments. The Table 36-SPI-3 data insertcontrol register is consulted, and determines to send this LID to the SPI-4 egressport. The SPI-4 Packet Fragment Processor chooses the next LP. Data is sentto the SPI-4 egress buffer along with the SPI-4 LP address, error information,SOP, and EOP. Data is transmitted in bursts over the SPI-4 egress interface.

The microprocessor needs to write data into a dedicated buffer to insert apacket burst. Refer to Figure 25, Microprocessor data insert buffer for the dataformat in the buffer. The microprocessor must verify the DATA_AVAILABLE flagin the SPI-4 insert control register and waits until the flag is cleared. Themicroprocessor specifies the EOP, SOP, ERROR, LID and LENGTH fields andwrites up to 256 bytes of packet fragment burst into the insert buffer. The packetburst insert buffer is accessed through the Table 34, SPI-4 data insert register(register_offset 0x03) SPI-4 data insert register. The microprocessor handsover control of the buffer setting the DATA_AVAILABLE flag in the SPI-4 insertcontrol register. A SPI4_insert_empty event is generated when theDATA_AVAILABLE flag is cleared. The event is directed towards the interruptmodule.

Figure 25. Microprocessor data insert buffer

6372 drw22

flags

length

data[1]

data[2]

data[255]

lid

data[0]


EA

ED



packet error

7 0

inse

rt s

eque

nce

t

t+1

t+258

extr

act s

eque

nce

t

t+1

t+258

Figure 26. Microprocessor data insert interface to SPI-4 egress datapath

The diagram below shows the datapath through the device from themicroprocessor data insert interface to the SPI-4 egress interface.

…

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Interface Block


Interface Block

SPI-3 /LID map

MainMemory

A


SPI-4 /LID map

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4.3.4 SPI-4 ingress to microprocessor interfacedatapath

The diagram below shows the datapath through the device from the SPI-4interface to the microprocessor data capture interface.

The following is a description of the path taken by a burst of data through thedevice.

Data enters on the SPI-4 interface in bursts. Bursts are normally of equallength except the last burst of a packet which may be shorter. The control wordis in-band with the data. The burst data enters a SPI-4 ingress buffer. SPI-4 LP

address, error information, SOP, and EOP are stored along with the burst data.The SPI-4 LP address is mapped to a LID. Data is stored in per-LID allocatedbuffer segments. The DIRECTION field of the SPI-3 egress port descriptor(Block_base 0x1700 + Register_offset 0x00 - 0xFF) is used to send this LIDdata to the microprocessor port. Data is moved to the capture buffer along withthe LP address, LID, error information, SOP, and EOP.

The data available bit is set by the PFP. Data and control information are readfrom the capture buffer through the microprocessor interface.

Figure 28. SPI-4 ingress to microprocessor data capture interface path

Figure 27. Microprocessor data capture buffer

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flags

length

data[1]

data[2]

data[255]

lid

data[0]


EA

ED



packet error

7 0

inse

rt s

eque

nce

t

t+1

t+258

extr

act s

eque

nce

t

t+1

t+258

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Interface Block


Interface Block

SPI-3 /LID map

MainMemory

A


SPI-4 /LID map

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5. PERFORMANCE MONITOR ANDDIAGNOSTICS

5.1 Mode of operationA performance monitor & diagnostics module is available. The performance

monitor captures events and accumulates error events and diagnostics data.Some performance monitor accumulators are associated to a physical port,some to a LID.

5.2 CountersAll events and diagnostics data are accumulated during an interval defined

by the timebase event. The data accumulated during the previous time periodcan be accessed by the indirect access scheme. The counters are cleared whenthe timebase expires. All counters are saturating, and will not overflow.

5.2.1 LID associated event countersA set of event counters is provided for each of the 64 LPs on the SPI-3 interface

and for each LID to/from the SPI-4 module.A packet is delineated by an SOP and EOP on the SPI-3 / SPI-4 logical port.

It is defined as “bad” when the packet is tagged with an error.All packets that are not “bad” are considered “good”.For more information refer to Table 60 - LID associated event counters

(0x000-0x17F).

5.2.2 Non - LID associated event countersA set of event counters is provided for the SPI-3 and the SPI-4 physical

interfaces.Refer to Table 61, Non LID associated event counters (0x00-0x0B) for the

offset in the indirect access space, and for the events recorded.

5.3 Captured eventsTwo categories of events are captured: LID and non LID associated events.

If at least one event is captured in one of the interrupt indication registers, an activePMON service request is directed towards the interrupt module.

5.3.1 Non LID associated eventsNon LID associated events are captured into the Table 62 - Non LID

associated interrupt indication register (Block_base 0x0C00 + Register_offset0x00 to 0x0B). An interrupt is generated if the event is enabled by its enableflag in the Table 63 - Non LID associated interrupt enable register(Block_base0x0C00 + Register_offset 0x0D). The interrupt is cleared by writing a logicalone to the Table 62 - Non LID associated interrupt indication register (Block_base0x0C00 + Register_offset 0x00 to 0x0B).

5.3.2 LID associated eventsTwo types of LID associated events are captured. Non critical events are

defined in Table 64 - LID-associated interrupt indication register(0x0E) and areassociated with the physical interface. Critical events are defined as bufferoverflows within the IDT88P8341 device in Table 67, SPI-3 to SPI-4 critical LIDinterrupt indication registers (register_offset 0x16-0x17).

5.3.2.1 Non critical eventsLID associated non critical events are captured in the Table 64, LID-

associated interrupt indication register(0x0E). An interrupt is generated if theinterrupt is enabled by its enable flag in the Table 65, LID-associated interruptenable register(0x0F). The interrupt indication is cleared by writing a logical oneto the Table 64, LID associated interrupt indication register(0x0E).

When the event is captured, the LID or LP associated with the event iscaptured in Table 66, Non-critical LID associated capture table (0x10-0x15).The table records the latest captured LID or LP.

5.3.2.2 Critical eventsCritical events are captured per LID in Table 67, SPI-3 to SPI-4 critical LID

interrupt indication registers (Block_base 0x0C00 + Register_offset 0x16-0x17) and Table 69, SPI-4 to SPI-3 critical LID interrupt indication registers(0x1A-0x1B). An interrupt is generated if enabled by the corresponding enableflag in the Table 68, SPI-3 to SPI-4 critical LID interrupt enable registers (0x18-0x19) and Table 70, SPI-4 to SPI-3 critical LID interrupt enable registers (0x1C-0x1D). The indication is cleared by writing a logical one to the Table 67, SPI-3 to SPI-4 critical LID interrupt indication registers (0x16-0x17) or Table 69, SPI-4 to SPI-3 critical LID interrupt indication registers (0x1A-0x1B). Only one kindof critical event is defined, buffer overflow. Since there are 64 x 2=128 criticalLID associated event sources, two source indication bits are contained in Table71, Critical events source indication register (0x1E). The bits are read only. BitSPI34_OVR reflects the OR result of all bits in Table 67, SPI-3 to SPI-4 criticalLID interrupt indication registers (0x16-0x17). Bit SPI43_OVR reflects the ORresult of all bits in Table 69, SPI-4 to SPI-3 critical LID interrupt indication registers(0x1A-0x1B).

5.3.3 TimebaseA single timebase module is provided in the device. The timebase period can

be configured to be internally or externally generated. A snapshot of thecounters is taken when the timebase expires and the counters are cleared. Thesnapshot registers are accessed by an indirect access scheme.

5.3.3.1 Internally generated timebaseThe period of the timebase is configured for the device using the register

defined in Table 120, Timebase register (Register_offset 0x01). The configu-ration specifies the number of master clock (MCLK) cycles required for eachperiod. For a description of MCLK refer to Chapter 6 Clock generator. Thetimebase event is captured by the timebase status in Table 45, Secondaryinterrupt status register (0x2D in the direct accessed space).

The internal timebase is generated either by the microprocessor or by a freerunning timer input. The selection is made by the TIMER flag in the Table 119,PMON update control register (Register_offset 0x00). When the time intervalexpires, the TIMEBASE pin is asserted for sixteen MCLK cycles.

5.3.3.2 Externally generated timebaseThe externally generated timebase signal is applied on the TIMEBASE pin.

A positive edge detector generates the timebase event. The timebase event iscaptured by the timebase status in the Table 45 - Secondary interrupt statusregister (0x2D in the direct accessed space).



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APRIL 10, 2006

6. CLOCK GENERATORThe device generates clocks from the SPI-4 ingress clock (I_DCLK) or from

the REF_CLK input pin. The clock so selected is used for core functions of thedevice, and must be present during reset and thereafter. The selection andfrequency divisors are defined by CK_SEL[3:0] pins as defined in the followingTable 14, CK_SEL[3:0] input pin encoding.

The clock generator provides four clock outputs on the OCLK[3:0] pins,MCLK for internal use, and SPI-4 data and FIFO status channel egress clocks.The OCLK[3:0] clock frequencies can be selected independently of each other.OCLK[3:0] outputs always have a relative output skew of one pll_oclk (refer toFigure 29 Clock generator) to prevent simultaneous switching when used asSPI-3 clock sources. Use of the OCLK[3:0] outputs is encouraged for the SPI-3 clock inputs to reduce system jitter. The frequency is divided according to thevalue selected in the clock generator control register shown below. The

OCLK[3:0] pins are separately enabled by setting each associated enable flagin Table 121, Clock generator control register (Register_offset 0x10). When anOCLK[3:0] output is not enabled, it is in a logic low state. MCLK is the internalprocessing clock, and is always enabled. Divide options should be selected tokeep the internal PLL output pll_oclk within its operating frequency range of 400to 800 MHZ. Refer to Table 122, OCLK and MCLK frequency select encodingfor selecting the frequencies of MCLK and OCLKs. Note that divider valuesshould be chosen so that OCLK[3:0] and MCLK are within their specifiedoperating range provided in Table 136, OCLK[3:0] clock outputs and MCLKinternal clock .

During either a hardware or a software reset, the OCLK[3:0] pins are all logiclow. Immediately following reset, all OCLK[3:0] outputs are active with the outputfrequency defined by pll_oclk divided by the initial value in the Table 121, Clockgenerator control register (Register_offset 0x10).

X 32 PLL

(400-800 MHz)MUX

I_DCLK4/8/16

E_DCLK

REF_CLK2/4/6/8

4

OC

LK0

OC

LK1

OC

LK2

OC

LK3

MC

LK

pll_oclk

CK_SEL[1:0]

CK_SEL[3:2]

pll_rclk

I_SCLK_T

I_SCLK_L

(80-400 MHz)

(80-400 MHz)

(12.5-25 MHz)

(40-133 MHz)

N_O

CLK

0

4/6/

8/10

N_O

CLK

1

4/6/

8/10

N_O

CLK

2

4/6/

8/10

N_O

CLK

3

4/6/

8/10

N_M

CLK

4/

6/8/

10

6372 drw27

(12.5-25 MHz)

CK_SEL[1:0] Function00 pll_rclk = REF_CLK01 pll_rclk = I_DCLK/1610 pll_rclk = I_DCLK /811 pll_rclk = I_DCLK /4

CK_SEL[3:2] Function00 E_DCLK = pll_oclk/201 E_DCLK = pll_oclk/410 E_DCLK = pll_oclk/611 E_DCLK = pll_oclk/8

TABLE 14 � CK_SEL[3:0] INPUT PIN ENCODING

Figure 29. Clock generator


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APRIL 10, 2006

7. LOOPBACKSLocal loopbacks are supported of the SPI-3 physical port. The SPI-3 physical

loopback is described below.

7.1 SPI-3 LoopbackA SPI-3 physical port loop back is supported on the SPI-3 interface. In this

mode, the contents of the SPI-3 ingress buffers are directly transferred to theSPI-3 egress buffers. All data and error information received on an ingressinterface of a SPI-3 physical port is transmitted on the egress interface of the SPI-3 physical port.

Figure 30. SPI-3 Loopback diagram

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Interface Block


Interface Block

SPI-3 /LID map

MainMemory

A


SPI-4 /LID map

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8. OPERATION GUIDE8.1 Hardware operation8.1.1 System reset

There are two methods for resetting the device: hardware reset & softwarereset. During reset the output clocks are not toggled.

Hardware resetThe RESETB input requires an active low pulse to reset the internal logic.

Software resetThe software reset is triggered by setting to 1 the SW_RESET field in direct

register Software Reset Register (p.50). The response to a software reset isidentical to a hardware rest except that software reset does not change theN_OCLK[3:0] fields in the Clock Generator Control Register (p.74), so it doesnot impact the clock generators. The SW_RESET field is self-clear to 0 after thedevice initialized itself. After software reset the external microprocessor shouldhave delay of at least 1ms before accessing the device, and then. After the 1msdelay, the user should poll the INIT_DONE field in the Software Reset Register(p.50), and wait till it is 1. When the INIT_DONE field is 1, the user shoulddownload a boot code from the external microprocessor flash to the deviceembedded processor RAM.

8.1.2 Power on sequenceA correct power-on-reset sequence is crucial for the normal behavior of

the device. The power-on-reset sequence includes the following signals:

CLK (REF_CLK or I_DCLK - depends on which of theses pins are selected),VDDT33, VDDC12 and RESETB. Figure 31, Power-on-Reset Sequenceillustrates the recommended implementation for the power-on-reset sequencefor the device. IDT recommends powering up the VDD33 power supply first,and the VDDC18 power supply last. The power supplies can be also poweredup in the same time. There is no requirement for the minimum or maximumdelay between the power-up of the power supplies. The power suppliesshould be powered off in the revers order. The power ramp should not be fastthan 100us, but also not too slow.

When the power supplies are powered up, the RESETB signal should beat low level. During power-on-reset, after the VDDT33, VDDC18, CLK(REF_CLK or I_DCLK - depends on which of theses pins are selected) andthe configuration signals are stable, the RESETB signal should remain at a lowlevel at least 10ms (symbol “T1”) to reset the internal logic. After the RESETBpulse ends, the device starts generating the SPI-4 / SPI-3 external outputclocks & the MCLK internal clock.

After the RESETB pulse ends, a delay of 1ms should be added (symbols“T2”) before accessing the device for initialization and configuration. Thisallows the internal logic to be stable. During T2 (at least 1ms delay) the deviceperforms internal memories initialization.

After T2, the user should poll the INIT_DONE field in the in the SoftwareReset Register (p.50), and wait till it is 1. When the INIT_DONE field is 1, theuser should download a boot code from the external microprocessor flash tothe device embedded processor RAM.

T1

CLK

VDDT33

RESETB

T2

VDDC18

6372 drw28a

Figure 31. Power-on-Reset Sequence

8.1.3 Clock domainsThe chip has several clock domains. The related registers can not be

configured without each clock. It is necessary to supply the clocks that arepertinent to the registers being initialized for the initialization to succeed. In orderto access the microprocessor interface, MCLK must be active, either by selectingand providing a stable REF_CLK input, or by selecting and ensuring that a stableclock is always present on the I_DCLK input. The selection of either theREF_CLK or the I_DCLK clock inputs is described in Table 14 CK_SEL[3:0]input pin decoding.

8.2 Software operation8.2.1 Chip configuration sequence

For proper device operation, it is important to initialize the IDT88P8341 in thecorrect sequence following reset. This sequence is outlined in the followingparagraphs.

1) Reset the IDT88P8341 chip. After reset, the chip will perform autoinitialization. Wait for the chip initialization to complete. The INIT_DONE flag willgo high when initialization has been completed.




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APRIL 10, 2006

2) Configure the clock generator as follows:a) Configure the value for the MCLK divider, OCLK dividers and

enables in the Clock Generator Control Register (refer to Table 121, Clock generator control register (Register_offset 0x10)).

b) Configure the values for I_LOW and E_LOW (refer to Table 89, SPI-4 ingress configuration register (0x00) and Table 104, SPI-4egress configuration register_0 (Register_offset 0x00).

3) Load status channel firmware. See section 8.2.5 for details.4) Configure all PFPs as follows:

a) The NR_LID fields must be configured first. Do not change the NR_LIDfields once configured after reset. The NR_LID fields are in the Table76, SPI-3 to SPI-4 PFP register (register_offset 0x00) and theTable 83, SPI-4 to SPI-3 PFP register (0x00).

b) There are four sets of port descriptor tables: The Table 73, SPI-4egress port descriptor table (64 entries), the Table 75, SPI-3 ingress portdescriptor table (Block_base 0x1200), the Table 80, SPI-3 egress portdescriptor table (64 entries), and the Table 82, SPI-4 ingress portdescriptor tables (64 entries). Configure the M (SPI-4 egress),MAX_BURST_S, MAX_BURST_H, DIRECTION (SPI-4 egress),FREE_SEGMENT, MAX_BURST, DIRECTION (SPI-3 egress), M(SPI-4 ingress), FREE_SEGMENT_S, and FREE_SEGMENT_Hparameters of the port descriptor tables for each LID to be activated. Thetotal buffer segment assignment should not exceed the available buffersegment pool capacity of 508 segments per PFP.

5) Configure the Table 54- SPI-3 egress LID to LP map.6) Configure the Table 49 - SPI-3 ingress LP to LID map.7) The SPI-4 Calendar tables must be configured before the SPI-4 mapping

tables are configured. Do not change the SPI-4 calendar tables once they areconfigured. In LVDS status mode, ensure that the value of (CAL_LEN+1) *(M+1) is at least 4.

a) Configure the SPI-4 ingress calendar or calendars (refer to Table 87,SPI-4 ingress calendar_0 (256 entries) and Table 88, SPI-4 ingresscalendar_1 (256 entries)).

b) Configure the SPI-4 egress calendar or calendars (refer to Table 102,SPI-4 egress calendar_0 (256 locations) and Table 103, SPI-4egress calendar_1 (256 locations)).

8) Configure the Table 101, SPI-4 egress LID to LP map (256 entries).9) Configure the Table 86, SPI-4 ingress LP to LID (256 entries, one per LP).10) Configure the SPI-4 physical interface. The Table 89, SPI-4 ingress

configuration register (0x00), Table 104, SPI-4 egress configuration register_0(Register_offset 0x00), and Table 105, SPI-4 egress configuration register_1(Register_offset 0x01) must be configured before enabling the SPI-4 physicalinterface. Once the SPI-4 interface is enabled, the SPI-4 interface configurationregisters can not be changed unless the chip is reset. Individual LIDs can stillbe enabled or disabled, within the bounds set by NR_LID.

11) Configure the SPI-3 physical interface. The Table 75, SPI-3 ingress portdescriptor table (Block_base 0x1200) must be configured before enabling theSPI-3 physical interface. Once the SPI-3 interface is enabled, Table 80, SPI-3 egress port descriptor table (64 entries) can not be changed unless the chipis reset. Individual LIDs can still be enabled or disabled without a chip reset,within the bounds set by NR_LID.

12) Enable the SPI-3 physical interface. Set the enable bit per LID in Table 46, SPI-3 ingress LP to LID map and Table 54, SPI-3 egress LID to LP map.

13) Enable the SPI-4 physical interface. Set the enable bit per LID in Table82, SPI-4 ingress LP to LID map (256 entries, one per LP) and Table 101, SPI-4 egress LID to LP map (256 entries).

Note: Sufficient edge transitions on the bus are required to cause a change

in the TAP value. Therefore, the adjacent device should send training for atleast 100ms in the end of the initialization sequence & before starting to senddata. The bit alignment will select the best tap for each lane.

8.2.2 Logical Port activation and deactivationDynamically deactivate a logical port

The procedure for deactivating a logical port is outlined as follows:1) Configure the enable bit of the ingress LP to LID map to “disabled”.2) Configure the egress data DIRECTION field in Table 73, SPI-4 egress

port descriptor table (64 entries) or Table 80, SPI-3 egress port descriptor table(64 entries) to “discard”.

3) Wait at least 0.1ms for the flush of the remaining data in the queue.4) Change M to 0 for the LP.

Dynamically activate a logical portThe procedure for activating a logical port is outlined as follows:1) Make sure the LID is inactive.2) Configure M for the desired LID.3) Configure the egress LID to LP map, then enable the LID.4) Configure the egress data direction for the LID.5) Configure the ingress LP to LID map, then enable the LP.

8.2.3 Buffer segment modificationModification of the buffer segment allocation for a LID

The buffer segment allocation can be changed while the corresponding LPis disabled. The amount of buffering available for a LID can be decreased orit can be increased if more buffer segments are available for use. The procedurefor changing the buffer segment allocation for a LID is outlined as follows:

1) Disable the LP corresponding to the LID to undergo buffer segmentmodification.

2) Discard the fragments, by configuring the DIRECTION field for DISCARDfor the LID.

3) Wait at least 0.1ms for the buffer to empty.4) Change M to 0 for the LID.5) Configure the new M value for the LID.6) Configure the DIRECTION field for the LID to restore data flow.7) Enable the LP corresponding to the LID that underwent buffer segment

modification.

8.2.4 Manual SPI-4 ingress LVDS bit alignmentThe procedure for manually adjusting the SPI-4 ingress LVDS bit alignment

is outlined. It is recommended to use automatic alignment in most cases.1) Configure the FORCE bit from Table 99, SPI-4 ingress bit alignment control

register (register_offset 0x11). This puts the SPI-4 ingress under manualcontrol.

2) Configure the SPI-4 ingress data lane to be measured for clock-dataalignment in Table 111, SPI-4 ingress lane measure register(register_offset 0x01), LANE field.

3) Wait for the eye measurement to complete in Table 111, SPI-4 ingresslane measure register (register_offset 0x01), MEASURE_busy field.

4) Read the eye pattern counter in Table 112, SPI-4 ingress bit alignmentcounter register (0x02 to 0x0B).

5) Calculate the proper value.6) Configure the appropriate phase tap in Table 113, SPI-4 ingress manual

alignment phase/result register (0x0C to 0x1F).


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APRIL 10, 2006

8.2.5 SPI-4 status channel softwareThe SPI-4 status channel may be configured to either TTL or LVDS by

loading the appropriate status channel binary file to activate the firmware.Download LVTTL.bin when using LVTTL status mode. Download LVDS.binwhen using LVDS status mode.

The download process is described. Direct write (0x20, 0x01 ); /* Write register 0x20 with 0x01 to reset */ Delay at least 5ms Direct write (0x36, 0x07); ind_write(0x00c8, 0xdcb0);

Open LVTTL.bin or LVDS.bin filenumber = file length addr = 0x0e00; if ( number % 2 == 0 ) number /=2; else number = number/2 + 1;

for ( i = 0; i < number; i ++ ) { scr_fp.Read(ch, 2); data = (ch[1] << 8) | ch[0]; ind_write(addr, data); addr ++; addr ++; } close file ind_write(0x00c6, 0x0e00); ind_write(0x00c8, 0xc860);

Direct write (0x36, 0x00);

8.2.6 IDT88P8341 layout guidelinesSPI-3 LAYOUT GUIDELINES

1) Series terminate SPI-3 traces that are greater than 1/2 inch in end-to-endlength. Place the series resistor as close as possible to the driver, but no morethan 1/2 inch away from the driving end. SPI-3 inputs must have ringingcontrolled to prevent the SPI-3 inputs from going more than 0.5 Volts belowground. Use the IBIS models for more accurate results with the specific devicesbeing used.

2) Minimize all SPI-3 data and control trace lengths to not exceed theTD-MAX - TSETUP requirement. For example, if the SPI-3 clock is 104 MHz, TD-MAX

of a device is 5.65 ns, and TSETUP of the attached device is 1 ns, the maximum

PCB trace delay Table 18 permitted is 3 ns (Unit Interval - TD-MAX - TSETUP). Thistranslates to a maximum PCB trace length for data and control lanes of 13.5inches, if the loaded PCB trace delay is 220 picoseconds per inch. This is forzero TSETUP margin, and does not include any margin for clock driver skew.Clock driver or clock trace skew could reduce the TSETUP margin in this example.

3) Match all SPI-3 clock lengths to within the TD-MIN - THOLD requirement. Forexample, if TD-MIN for the device is 1.5 ns, and THOLD for the attached deviceis 0.5 ns, the worst case PCB clock trace skew for zero THOLD margin (definedin this example as the maximum PCB trace delay that the SPI-3 ingress clockof the attached device can exceed the trace delay of the SPI-3 egress clockof the device and still meet the THOLD requirement of the attached device withzero margin, assuming the fastest device [TD-MIN ] and the worst case THOLD forthe attached device and no trace delay on the data and control lanes) is 1.7ns (Table 15 (TD-MIN - THOLD)), for a maximum PCB clock trace difference of7.6 inches. Trace delay on the data and control lanes would improve the THOLD

margin in this example. This example does not include any margin for SPI-3clock buffer skew.

4) Ensure a few nanoseconds of clock delay between one SPI-3 clock netand other SPI-3 clock nets of the same frequency to minimize simultaneousswitching noise. The IDT88P8341 OCLK[3:0] outputs have skew betweeneach output already built in, and so are useful in lowering simultaneousswitching noise. A SPI-3 clock net is defined to be the SPI-3 egress clock fora device and the SPI-3 ingress clock for the attached device.

5) Route all SPI-3 traces as 50 Ohm embedded stripline (inner layerreferencing ground planes). For example, 8 mil wide 1/2 oz copper tracessandwiched between ground planes with 10 mil dielectric spacing betweenground planes and signal planes yields 52 Ohms single-ended, using FR-4with a relative dielectric constant (εR or DK) of 4.2. If the edge to edge spacingbetween adjacent SPI-3 series terminated signals is 20 mils in this example,crosstalk between adjacent signals can be kept to 2%. Use a field solver formore accurate results.

An example timing budget Table 15, Zero Margin SPI-3 Timing budget, andexample trace lengths to achieve timing margin Table 16, Margin check for SPI-3 timing, are shown. These timing budget tables do not include clock driverrelative skew incurred if different drivers are used for a SPI-3 egress and itsattached SP-3 ingress. These tables are based on timing only and do notinclude such effects as crosstalk and rise time degradation.

SPI-4 LAYOUT GUIDELINES1) Match the P and N trace lengths within an LVDS differential signal pair to

within 100 mils or less.2) Match the group of all differential data, control, and clock signal lengths to

within 1/2 unit interval (DDR), or less, of each other (1/4 clock period). For

SPI-3Clock Tsetup Thold Td, minimum Td, maximum Unit Interval Maximum data Maximum data Maximum Maximum Clocktrace delay trace length clock skew ∆trace length

104 MHz 1 ns 0.65 ns 2.33 ns 5.65 ns 9.6 ns 3 ns 13.5 in 1.7 ns 7.6 in

TABLE 15 - ZERO MARGIN SPI-3 TIMING BUDGET

SPI-3Clock Tsetup Thold Td, minimum Td, maximum Egress Ingress Longest Shortest Tsetup Tholdclock trace clock trace data trace data trace margin margin

104 MHz 1 ns 0.65 ns 2.33 ns 5.65 ns 4 inches 8 inches 6 inches 4 inches 2.33 ns 1.48 ns

TABLE 16 - MARGIN CHECK FOR SPI-3 TIMING




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APRIL 10, 2006

example, a SPI-4 clock of 400 MHz gives a data unit interval of 1.25 ns, so matchthe lengths within the entire signal group to within 625 ps, or 3 inches.

3) Keep P and N signals within a differential pair on the same layer with theminimum trace spacing possible while still being able to get 100 ohms differentialimpedance (tightly edge-coupled pair routing).

4) Route all differential pairs as 100 Ohm embedded differential stripline (onan inner layer, referencing ground planes). For example, 7 mil wide 1/2 ozcopper traces separated by 10 mils, with 10 mil dielectric spacing to groundplanes above and below the traces gives 100 Ohms of differential impedancefor FR-4 with a relative dielectric constant (εR or DK) of 4.2. If the edge to edgespacing between adjacent differential pair traces is 20 mils, crosstalk is 0.6% forsignals terminated to within a 10% impedance match. If the edge to edge spacingbetween a differential pair and an LVTTL signal is 30 mils within the parametersof this example, crosstalk is 0.8% (with the LVTTL signals series terminated).Use a field solver for more accurate results.

5) Follow the SPI-3 layout guidelines for any routed SPI-4 LVTTL statussignals.

GENERAL LAYOUT GUIDELINES1) Keep LVDS signals far from LVTTL signals: at least three times the dielectric

thickness to the reference plane (or three times the trace separation, whicheveris greater) in separation width, to minimize the crosstalk contribution of noise onthe LVDS signals from the noisy LVTTL environment.

2) Separate signals of the same type by at least twice the dielectric thickness(or twice the trace separation, whichever is greater) to the reference plane toreduce crosstalk.

3) The reference planes must extend at least five times the dielectric thicknessfrom either side of the trace and be unbroken.

4) Avoid changing layers on high-speed signals. On a layer change, signalsshould share the same reference (such as ground), connected by referencevias close to the signal vias for good current return. If a different reference plane(such as Vcc) must be used due to a signal layer change, good high-frequency0.01 µF ceramic capacitors must be used to connect the references togetheras close to the signal vias as possible to ensure good transmission line propertiesand current return.

5) Use of a low-jitter (100 picoseconds peak-peak maximum jitter) frequencysource for REF_CLK is important. If I_DCLK is used instead of REF_CLK,ensure that I_DCLK is low in jitter and always available.

6) Keep the power decoupling capacitors as close as possible to the powerpins, using at least 15 mil traces and double vias for reduced inductance wherepossible.

7) Distribute some large-valued capacitors around the board for low-frequency decoupling and to lower the power-supply impedance.

8) TRSTB (JTAG reset) must have a pull down resistor or be connected toRESETB for normal operation.

9) Filter the 1.8 Volt and 3.3 Volt analog power pins to isolate them from thenoisy digital environment. Use ferrite beads and capacitors (Pi filters) forVDDA18_x and VDDA33.

10) Suppress non-functional inner layer pads.

8.2.7 Software Eye-Opening Check on SPI-4Interface

Since the SPI-4 interface is a DDR interface, both rising and falling edgesare used to update or sink data.

dn dn+1

0 1 2 3 4 5 6 7 8 9 a b c

c0 c5 c9

clock

data

over sampleposition

counter c1 c6c4c2 c7c3 c8

6372 drw23b

Figure new32. DDR interface and eye opening check through over sampling

CNT0= Rt.d2^ Rt.d3

CNT1= Rt.d3^ Rt.d4

CNT2= Rt.d4^ Rt.d5

CNT3= Rt.d5^ Rt.d6

CNT4= Rt.d6^ Rt.d7

CNT5= Rt.d7^ Rt.d8

CNT6= Rt.d8^ Rt.d9

CNT7= Rt.d9^ Rt+1.d0

CNT9= Rt+1.d0^ Rt+1.d1

Refer to the IDT88P8342 uses an internal sampling clock cycle which hasa frequency of 10 times SPI-4 clock to over-sample the data on a lane. For eachsampling clock cycle t position n data are sampled and labeled as R

t.d

n. The

following operation is then performed:


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For an ideal case, there is zero jitter on clock an data, zero skew, the clockhigh and low level phase are symmetrical. For random input data on each lane,the counters Cn=CNTn(t)+CNTn(t+1)+. . .+CNTn(t+T), where T is a timewindow to do the statistics computation, will increment as follows:

Counter C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

Value 0 0 P 0 0 0 0 K 0 0

#define SPI-4_ingress_lane_measure_register 0x8801 /* register address in SPI exchange device*/#define SPI-4_ingress_bit_alignment_counter_register(0) 0x8802#define SPI-4_ingress_bit_alignment_counter_register(1) 0x8803#define SPI-4_ingress_bit_alignment_counter_register(2) 0x8804#define SPI-4_ingress_bit_alignment_counter_register(3) 0x8805#define SPI-4_ingress_bit_alignment_counter_register(4) 0x8806#define SPI-4_ingress_bit_alignment_counter_register(5) 0x8807#define SPI-4_ingress_bit_alignment_counter_register(6) 0x8808#define SPI-4_ingress_bit_alignment_counter_register(7) 0x8809#define SPI-4_ingress_bit_alignment_counter_register(8) 0x880a#define SPI-4_ingress_bit_alignment_counter_register(9) 0x880b

For lane=0 to K step 1 /*the number K depend on status mode: K=18 in LVDS status mode*/{ /* K=16otherwise */

write #lane, SPI-4_ingress_lane_measure_ registerwait until BUSY=0 /* BUSY: bit 8 of SPI-4_ingress_lane_measure_register, at address0x8801*/for i=0 to 9 step 1{

read C(i), SPI-4_ingress_bit_alignment_counter_register(i)}

print C(0), C(1), C(2), C(3), C(4), C(5), C(6), C(7), C(8), C(9)}

Where P and K are non-zero and need to be a large enough value markthe transition position of a clock and define the position.

Software for implementing the Eye-Opening CheckIn the IDT88P8342, a set of diagnostic registers are provided for implement-

ing an eye-opening check. The SPI-4 interface has 16 data lanes and onecontrol lane on ingress, 2 status lanes on egress, making a total of 19 lanes.

The SPI-4 ingress bit alignment window register defines the window T statedabove, based on which the signal statistics are computed. It is recommendedto use the default value. The MEASURE_BUSY bit indicates the status of theinternal measurement operation.

The SPI-4 ingress lane measure register selects the lane statistics countersto be read, a write to this register triggers the eye-opening check process to theselected lanes and the MEASURE_BUSY bit will be set accordingly indicatingthe measuring process is active. The MEASURE_BUSY bit is cleared internallywhich indicates that the measuring process is complete. The measured resultof counters C0 through C9 will be available in the SPI-4 ingress bit alignmentcounter registers.

Note that there is one SPI-4 ingress lane measure register and 19 SPI-4ingress bit alignment counter registers.

The following pseudo code shows how to check the eye opening:

Because the SPI-4 ingress bit alighnment counter register has a 10-bit width,the maximum counter value is 0x3ff.

If the counter values of a lane are:0, 0, 0x3ff, 0, 0, 0, 0, 0x3ff, 0, 0

The eye open is perfect; there is very good signal integrity on input signalsof the SPI-4 interface.

In each sample position represents a “tap”. Depending on the delay in a lane,even a small jitter value of 1ps on the lane or the clock, may cause eye closingthat can be detected by observing the counter values. In an ideal case with zero

delay, if the jitter on a data lane or clock is less than one tap interval (peak topeak), the jitter will not be reflected in counters. While the eye open check canindicate excessive jitter there are limitations in providing a accurate measure-ment using this method.

Theoretically as long as one tap accumulates enough non-zero samples foreach 2 bits within a clock cycle the sampled signal position will be correct andthe interface will function correctly. The more counters that have zero values,the better the eye opening.


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Indirect Data Indirect Data Indirect Data Indirect Data(register 0x33) (register 0x32) (register 0x31) (register 0x30)

bit 31…bit 25 bit 24…bit 16 bit 15…bit 8 bit 7…bit 0

TABLE 18 - BIT ORDER WITHIN A 32-BIT DATA REGISTER

Bit 31 is the most significant data bit.

Indirect Data (register 0x30)bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0

TABLE 19 - BIT ORDER WITHIN AN 8-BIT DATA REGISTER


9. REGISTER DESCRIPTIONThere are two distinctly different types of register access in the IDT88P8341.

Direct access registers are used for interrupts and other high-priority registersand for access to the indirect access registers. Direct access registers can beaccessed more quickly than indirect access registers, and are used where thisaccess speed advantage is required. There are only a limited number of directaccess registers due to the six address lines used on the IDT88P8341. All directaccess registers are one byte wide. Most registers within the IDT88P8341 areof the indirect access type. Indirect access registers are used for configuration,maps, etc., that may not need to be accessed as often as the direct registers.

Indirect registers are accessed through special direct access registers designedfor the purpose of allowing indirect access to the large set of registers and mapsthat are needed to configure the IDT88P8341.

9.1 Register access summaryThe SPI Exchange device uses an indirect addressing scheme for most of

the configuration registers. The indirect registers are accessed through aprotocol where interface pins A[5:0], D[7:0], and control pins are mapped intointernal register space A[15:0], D[31:0], and Control[7:0]. The full address ofany indirectly addressed register = Module_base + Block_base + Register_offset.

Direct Register Formatbit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0

TABLE 17 - BIT ORDER WITHIN AN 8-BIT DATA REGISTER


Figure 33. Direct & indirect access

Indirect accessedspace

C[7:0]

8

616

32

6372 drw29

Direct accessed

space

Processor interface

D[7:0]

A[5:0]

C[7:0]

D[31:0]

A[15:0]

9.1.1 Direct register formatAll direct register accesses are one byte. The bit ordering for the direct

access registers is shown.

9.1.2 Indirect register formatThe internal format for 32 and 8 bit registers is shown below. The registers

are accessed from the external processor interface as successive bytes ofindirect data. The indirect register space includes 32-bit data registers and 8-bit data registers. The directly-addressed register space includes directly-addressable 8-bit data registers, four 8-bit data registers for indirect data access,two 8-bit address registers for indirect data access, and an 8-bit control register






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Indirect High Address (register 0x35) Indirect Low Address (register 0x34)bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0

TABLE 20 - BIT ORDER WITHIN A 16-BIT ADDRESS REGISTER


Indirect Control (register 0x3F)bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0

TABLE 21 - BIT ORDER WITHINAN 8-BIT CONTROL REGISTER


Module base address (Module_base)There are two modules defined for indirect data access.

MODULE Module_baseModule A (SPI3-A, PFP-A, PMON-A) 0x0000Common (SPI-4, timing, PMON, clock, GPIO, and version number) 0x8000

TABLE 22 - MODULE BASE ADDRESS (MODULE_BASE)

Block baseThere are block bases defined for SPI-3 modules and also for Common, as

shown in the following tables.

Block_base Function0x0000 SPI-3 ingress LP to LID registers0x0200 SPI-3 ingress general configuration register0x0500 SPI-3 egress LID to LP registers0x0700 SPI-3 egress configuration registers0x0A00 LID associated event counters0x0C00 Non LID associated event counters0x1000 SPI-3 ingress packet length configuration register0x1100 SPI-4 egress port descriptor table0x1200 SPI-3 ingress port descriptor tables0x1300 SPI-3 to SPI-4 PFP and flow control registers0x1600 SPI-4 ingress control registers0x1700 SPI-3 egress port descriptor table0x1800 SPI-4 ingress port descriptor table0x1900 SPI-4 to SPI-3 PFP register

TABLE 23 - INDIRECT ACCESS BLOCK BASES FORMODULE A


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Block_base Function0x0000 SPI-4 ingress LP to LID tables0x0100 SPI-4 ingress calendar_00x0200 SPI-4 ingress calendar_10x0300 SPI-4 ingress registers0x0400 SPI-4 egress LID to LP map0x0500 SPI-4 egress calendar_00x0600 SPI-4 egress calendar_10x0700 SPI-4 egress configuration and status registers0x0800 SPI-4 ingress timing block registers0x0900 PMON timebase control, clock generator control, GPIO register, and version number

TABLE 24 - INDIRECT ACCESS BLOCK BASES FOR COMMON MODULE

Register offsetThe register offset is shown in the section where the register is defined. The

register offset is referred to as, “Register_offset”, in this document. A registerreference takes the form of, “[Register_offset 0xHH]”, where HH is thehexadecimal value of the register offset.

Indirect register accessIndirect register write access

An indirect write access is initiated by first checking for IND_BUSY=0 in theindirect access control register, and then writing data into the indirect access dataregisters. Next, the address is written into the indirect access address registers.Then, 0x00 is written into the indirect access control register. The status of theIND_BUSY flag in the indirect access control register is checked to ensure theprocess has completed before another indirect access can be initiated.

Indirect register read accessAn indirect read access is initiated by first checking for IND_BUSY=0 in the

indirect access control register, and then writing the address into the indirectaccess address registers. Then, 0x40 is written into the indirect access controlregister. The status of the IND_BUSY flag in the indirect access control registeris checked to ensure the process has completed, and then data is read out fromthe indirect access data registers.

The registers for controlling indirect register access are shown below. Theregisters for controlling indirect register access are directly accessible with readand write access.

TABLE 25 - INDIRECT ACCESS DATA REGISTERS(DIRECT ACCESSED SPACE) AT 0x30 to 0x33

Field Bits Length FunctionDATA[7:0] 7:0 8 Indirect Data Register 0x30DATA[15:8] 15:8 8 Indirect Data Register 0x31DATA[23:16] 23:16 8 Indirect Data Register 0x32DATA[31:24] 31:24 8 Indirect Data Register 0x33

TABLE 26 - INDIRECT ACCESS ADDRESS REGISTER(DIRECT ACCESSED SPACE) AT 0x34 to 0x35

Field Bits Length FunctionADDRESS[7:0] 7:0 8 Indirect Low Address Register 0x34ADDRESS[15:8] 15:8 8 Indirect High Address Register 0x35

TABLE 27 - INDIRECT ACCESS CONTROL REGISTER(DIRECT ACCESSED SPACE) AT 0x3F

Field Bits LengthERROR code 5:0 6R/WN 6 1IND_BUSY 7 1

The fields for this register are defined below.


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ERROR code Error code: see Error coding table. This error codepertains to the last indirect access attempted.

ERROR code Error Meaning0x00 Normal indirect access completion0x01 Multiple LP to same LID attempted assignment0x02 Multiple LID to same LP attempted assignment0x03 Buffer segment overflow0x04 Not enough Queue entries0x05 Attempt to modify while active0x06 Address out of bound0x07 Calibration before the chip has finished reset0x08 LP limited0x09 Undefined direction0x3E Undefined address0x3F Time out

TABLE 28 - ERROR CODING TABLE

R/WN This bit defines the read or write access to the indirect register.0=WRITE1=READ

IND_BUSY This bit is an indication of the ability of the indirect registeraccess to accept a new transaction, and of the completion of the currenttransaction.

0=Ready for read or write operation1=Busy indication. Wait before beginning a read or writeoperation


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Module A RegisterSPI-3 data capture control register 0x00SPI-3 data capture register 0x01SPI-4 data insert control register 0x02SPI-4 data insert register 0x03SPI-4 data capture control register 0x04SPI-3 data insert control register 0x05SPI-4 data capture register 0x06SPI-3 data insert register 0x07Module status register 0x24Module enable register 0x28

Other Direct registers AddressSoftware reset 0x20SPI-4 status register 0x22SPI-4 enable register 0x23Primary interrupt status register 0x2CSecondary interrupt status register 0x2DPrimary interrupt enable register 0x2ESecondary interrupt enable register 0x2FIndirect access data[7:0] 0x30Indirect access data[15:8] 0x31Indirect access data[23:16] 0x32Indirect access data[31:24] 0x33Indirect access address[7:0] 0x34Indirect access address[15:8] 0x35Indirect access control[7:0] 0x3F

TABLE 29 - DIRECT MAPPED MODULE A REGISTERS

TABLE 30 - DIRECT MAPPED OTHER REGISTERS

9.2 Direct access registersThe direct access registers are in the directly-addressed access space.

TABLE 31 - SPI-3 DATA CAPTURE CONTROLREGISTER (REGISTER 0x00 )

Field Bits Length Initial ValueDATA_AVAILABLE 0 1 0b0Reserved 7:1 7 0x00

TABLE 32 - SPI-3 DATA CAPTURE REGISTER(REGISTER 0x01)

Field Bits Length Initial ValueDATA 7:0 8 0x00

SPI-3 data capture control register

The SPI-3 Data Capture Control Register has read and write access in thedirect register access space. Write a zero to DATA_AVAILABLE to clear thetransfer. The microprocessor uses these registers to capture data from a SPI-3 ingress.

The bit field of the SPI-3 Data Capture Control Register is described.

DATA_AVAILABLE The SPI-3 capture data buffer is full and ready forreading.

SPI-3 data capture register

The SPI-3 Data Capture Register has read-only access in the direct registeraccess space. The microprocessor uses these registers to capture data froma SPI-3 ingress.

The bit field of the SPI-3 Data Capture Register is described.

DATA The SPI-3 capture data buffer is read from this field.


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TABLE 33 - SPI-4 DATA INSERT CONTROL REGISTER(REGISTER 0x02)


TABLE 34 - SPI-4 DATA INSERT REGISTER(REGISTER 0x03)


SPI-4 data insert control register

The SPI-4 data insert register has write-only access in the direct registeraccess space. The microprocessor uses these registers to insert data into theSPI-3 ingress.

The bit field of the SPI-4 Data Insert Register is described.

DATA The SPI-4 insert data buffer is written to this field.

SPI-4 data capture control register

TABLE 37 - SPI-4 DATA CAPTURE REGISTER(REGISTER 0x06)


TABLE 38 - SPI-3 DATA INSERT REGISTER (REGIS-TER 0x07)


TABLE 36 - SPI-3 DATA INSERT CONTROL REGISTER(REGISTER 0x05)


TABLE 35 - SPI-4 DATA CAPTURE CONTROLREGISTERS (REGISTER 0x04)


The SPI-4 Data Capture Control Register has read and write access in thedirect register access space. The microprocessor uses these registers tocapture data from the SPI-3 ingress.

The bit field of the SPI-4 Data Capture Control Register is described.

DATA_AVAILABLE The SPI-4 capture data buffer is full and ready forreading.

SPI-3 data insert control register

The SPI-3 data insert control register has read and write access in the directregister access space. The microprocessor uses these registers to insert datainto the SPI-4 ingress.

The bit field of the SPI-3 Data Insert Control Register is described.

DATA_AVAILABLE The SPI-3 insert data buffer is empty and available forwriting.

SPI-4 data capture register

The SPI-4 data capture register has read-only access in the direct registeraccess space. The microprocessor uses these registers to capture data froma SPI-4 ingress.


DATA The SPI-4 capture data buffer is read from this field.

SPI-3 data insert register

The SPI-3 Data Insert Register has write-only access in the direct registeraccess space. The microprocessor uses these registers to insert data into theSPI-4 ingress.


DATA The SPI-3 insert data buffer is written from this field.

The SPI-4 data insert control register has read and write access in the directregister access space. The microprocessor uses these registers to insert datainto the SPI-3 ingress.

The bit field of the SPI-4 data insert control register is described.

DATA_AVAILABLE The SPI-4 insert data buffer is empty and ready forwriting.

SPI-4 data insert register


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Software reset

The SPI-4 Status Register (0x22 in the direct accessed space) has readaccess, and interrupt status fields are cleared by a microprocessor write cycle,where a logical one must be written to clear the field(s) targeted.

The SPI-4 Status Register is a secondary interrupt status register and canonly be active if the SPI-4 field is active in the Primary Interrupt Status Register(Direct 0x2C).

I_DIP_ERR_I SPI-4 ingress DIP-4 error interrupt indication.0=No errors1=One or more DIP-4 errors have been registered on the SPI-4 ingress

I_SYNCH_I SPI-4 ingress data path has transitioned from out ofsynchronization to in synchronization condition interrupt indication.

0=No detection, still not in synchronization1=Transition from out of synchronization to in synchronization, or transition

from in synchronization to out of synchronization

I_BUS_ERR_I SPI-4 ingress bus error interrupt indication.0=No errors

1=One or more bus errors have been registered on the SPI-4 ingress

SPI4_INACTIVE_TRANSFER_I SPI-4 ingress inactive transfer inter-rupt indication.

0=No indication1=One or more inactive transfers have been registered on the SPI-4 ingress

DCLK_UN_I SPI-4 ingress data clock has transitioned from availableto an unavailable condition interrupt indication.

0=No detection, I_DCLK is available1=I_DCLK transitioned from available to an unavailable state

E_DIP_ERR_I SPI-4 egress DIP-2 error interrupt indication on the SPI-4 egress status channel.

0=No errors1=One or more DIP-2 errors have been registered

E_SYNCH_I SPI-4 egress status channel has transitioned from out ofsynchronization to an in synchronization condition interrupt indication.

0=No detection, still not in synchronization1=Transition from out of synchronization to in synchronization, or transition

from in synchronization to out of synchronization

SCLK_UN_I SPI-4 egress status clock has transitioned from availableto an unavailable condition interrupt indication.

In LVTTL mode the Bridgeport does not detect the SPI-4 egress status clock(E_SCLK_T). Therefore, for LVTTL mode the software should ignore theSCLK_UN field in the SPI-4 Status Register.

0=No detection, E_SCLK is available1=E_SCLK transitioned from available to an unavailable state

SPI-4 enable register (0x23 in the direct accessedspace)

The SPI-4 Enable Register (0x23 in the direct accessed space) has readand write access. SPI-4 Enable Register is used to bitwise enable the interruptsin the SPI-4 Status Register.

I_DIP4_ERR_EN SPI-4 ingress DIP-4 error interrupt indication enable.0=Disable DIP-4 error interrupt1=Enable DIP-4 error interrupt

I_SYNCH_EN SPI-4 ingress data path has transitioned from out ofsynchronization to in synchronization condition interrupt indication enable.

0=Disable synchronization interrupt1=Enable synchronization interrupt

Field Bits Length Initial ValI_DIP4_ERR_EN 0 1 0I_SYNCH_EN 1 1 0I_BUS_ERR_EN 2 1 0SPI4_INACTIVE_TRANSFER_EN 3 1 0DCLK_UN_EN 4 1 0E_DIP_ERR_EN 5 1 0E_SYNCH_EN 6 1 0SCLK_UN_EN 7 1 0

TABLE 41 - SPI-4 ENABLE REGISTER (0x23 INTHE DIRECT ACCESSED SPACE)

Field Bits Length Initial ValI_DIP_ERR_I 0 1 0I_SYNCH_I 1 1 0I_BUS_ERR_I 2 1 0SPI4_INACTIVE_TRANSFER_I 3 1 0DCLK_UN_I 4 1 0E_DIP_ERR_I 5 1 0E_SYNCH_I 6 1 0SCLK_UN_I 7 1 0

TABLE 40 - SPI-4 STATUS REGISTER (0x22 IN THEDIRECT ACCESSED SPACE)

TABLE 39 - SOFTWARE RESET REGISTER (0x20 inthe direct accessed space)

Field Bits Length Initial ValueSW_RESET 0 1 0INIT_DONE 1 1 0Reserved 7:2 6 0

The software reset bit is writable from the direct accessed memory space.Write a “1” to the SW_RESET bit to initiate the software reset. The SW_RESETbit will clear to a “0” after the chip has initialized itself. The INIT_DONE bit is setto a “1” when the initialization following reset has completed. The software resetis the same as the hardware. The Reserved field must be set to 0.

The Initial Value column in this document is the value of the register after resethas completed.

SW_RESET Setting the SW_RESET bit initiates a software reset of the chip.The SW_RESET bit is self-clearing.

0=No operation is performed1=Initiate a software reset

INIT_DONE Status indication bit following a reset.0=Chip has not completed initialization following reset1= Chip has completed initialization following reset

SPI-4 status register (0x22 in the direct accessedspace)


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I_BUS_ERR_EN SPI-4 ingress bus error interrupt indication enable.0=Disable bus error interrupt1=Enable bus error interrupt

SPI4_INACTIVE_TRANSFER_EN SPI-4 ingress inactive transfer inter-rupt indication enable.

0=Disable inactive transfer interrupt1=Enable inactive transfer interrupt

DCLK_UN_EN SPI-4 ingress data clock has transitioned from availableto an unavailable condition interrupt indication enable.

0=Disable unavailable interrupt1=Enable unavailable interrupt

E_DIP_ERR_EN SPI-4 egress DIP-2 error interrupt indication enableon the SPI-4 egress status channel.

0=Disable DIP-2 error interrupt1=Enable DIP-2 error interrupt

E_SYNCH_EN SPI-4 egress status channel has transitioned from out ofsynchronization to in synchronization condition interrupt indication enable.

0=Disable synchronization interrupt1=Enable synchronization interrupt

SCLK_UN_EN SPI-4 egress status clock has transitioned from availableto an unavailable condition interrupt indication enable. SCLK_UN_EN shouldbe written as a zero if using a SPI-4 egress LVTTL status clock that is less thanone-half of the MCLK frequency. The SCLK_UN_I interrupt indication is notusable in this case.

0=Disable unavailable interrupt1=Enable unavailable interrupt

Module status register (0x24 in the direct ac-cessed space)

Field Bits Length Initial ValueSPI-34_CAPTURE 0 1 0SPI-43_CAPTURE 1 1 0SPI-34_INSERT 2 1 0SPI-43_INSERT 3 1 0PMON 4 1 0Reserved 7:5 3 0

TABLE 42 - MODULE STATUS REGISTER (0x24 INTHE DIRECT ACCESSED SPACE)

The Module Status register (0x24 in the direct accessed space) has read andwrite access, and interrupt status fields are cleared by a microprocessor writecycle, where a logical one must be written to clear the field(s) targeted, exceptfor the PMON field, which can not be cleared.

The Module Status register is a secondary interrupt status register and canonly be active if the corresponding field is active in the primary interrupt statusregister (Direct access register 0x2C).

SPI-34_CAPTURE SPI-3 ingress to SPI-4 egress capture event inter-rupt indication.

0=No capture event1=Buffer is ready for reading by the microprocessor

SPI-43_CAPTURE SPI-4 ingress to SPI-3 egress capture event interruptindication.

0=No capture event1=Buffer is ready for reading by the microprocessor

SPI-34_INSERT SPI-3 ingress to SPI-4 egress insert event interruptindication.

0=No insert event1=Buffer is ready for writing by the microprocessor

SPI-43_INSERT SPI-4 ingress to SPI-3 egress insert event interruptindication.

0=No insert event1=Buffer is ready for writing by the microprocessor

PMON Performance Monitor event interrupt indication. Writing to this field hasno effect.

0=No PMON event1=PMON event is ready for reading by the microprocessor

Module enable register (0x28 in the direct ac-cessed space)

Field Bits Length Initial ValueSPI-34 CAPTURE_EN 0 1 0SPI-43 CAPTURE_EN 1 1 0SPI-34 INSERT_EN 2 1 0SPI-43 INSERT_EN 3 1 0PMON_EN 4 1 0Reserved 7:5 3 0

TABLE 43 - MODULE ENABLE REGISTER (0x28 INTHE DIRECT ACCESSED SPACE)

The Module Enable register (0x28 in the direct accessed space) has readand write access.

SPI-34_CAPTURE_EN SPI-3 ingress to SPI-4 egress capture eventinterrupt enable.

0=Disable capture interrupt1=Enable capture interrupt

SPI-43_CAPTURE_EN SPI-4 ingress to SPI-3 egress capture eventinterrupt enable.

0=Disable capture interrupt1=Enable capture interrupt

SPI-34_INSERT_EN SPI-3 ingress to SPI-4 egress insert event interruptenable.

0=Disable insert interrupt1=Enable insert interrupt

SPI-43_INSERT_EN SPI-4 ingress to SPI-3 egress insert eventinterrupt enable.

0=Disable insert interrupt1=Enable insert interrupt

PMON_EN Performance Monitor event interrupt enable.0=Disable PMON interrupt1=Enable PMON interrupt


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The primary interrupt status register (0x2C in the direct accessed space) hasread-only access. The interrupts for the primary interrupt status register mustbe acknowledged by servicing the corresponding secondary interrupt statusregisters.

MODULE_A When active, the MODULE_A field is responsible forallowing an interrupt in the Module Status Register (secondary interrupt register0x24).

0=No MODULE_A interrupt active1=MODULE_A interrupt is active

SPI-4 When active, the SPI-4 field is responsible for allowing an interruptin the SPI-4 status register (secondary interrupt register 0x22).

0=No SPI-4 interrupt active1=SPI-4 interrupt is active

SECONDARY When active, the SECONDARY field is responsible forallowing an interrupt in the Secondary Interrupt Status Register (secondaryinterrupt register 0x2D).

0=No SECONDARY interrupt active1=SECONDARY interrupt is active

Secondary interrupt status register (0x2D in thedirect accessed space)

Primary interrupt status register (0x2C in thedirect accessed space)

INDIRECT_ACCESS Indirect access completion interrupt indication.0=No indirect access event1=Indirect access has completed

Primary interrupt enable register (0x2E in thedirect accessed space)

Field Bits Length Initial ValueMODULE_A 0 1 0

Reserved 1 1 0 Reserved 2 1 0

Reserved 3 1 0SPI-4 4 1 0SECONDARY 5 1 0Reserved 7:6 2 0

TABLE 44 - PRIMARY INTERRUPT STATUS REGIS-TER (0x2C IN THE DIRECT ACCESSED SPACE)

Field Bits Length Initial ValueTIME_BASE 0 1 0INDIRECT_ACCESS 1 1 0Reserved 7:2 6 0

TABLE 45 - SECONDARY INTERRUPT STATUSREGISTER (0x2D IN THE DIRECT ACCESSED SPACE)

The primary interrupt enable register (0x2E in the direct accessed space)has read and write access.

The Primary Interrupt Enable Register is used to bitwise enable the interruptsin the Primary Interrupt Status Register.

MODULE_A_EN MODULE_A interrupt enable.0=Disable MODULE_A interrupt1=Enable MODULE_A interrupt

SPI-4_EN SPI-4 interrupt enable.0=Disable SPI-4 interrupt1=Enable SPI-4 interrupt

SECONDARY_EN SECONDARY interrupt enable.0=Disable SECONDARY interrupt1=Enable SECONDARY interrupt

Secondary interrupt enable register (0x2F in thedirect accessed space)

The secondary interrupt status register (0x2D in the direct accessed space)has read and write access.

The secondary interrupt status register has read access, and Interrupt statusfields are cleared by a microprocessor write cycle, where a logical one mustbe written to clear the field(s) targeted.

The secondary interrupt status register is a secondary interrupt status registerand can only be active if the SECONDARY_EN field is active in the primaryinterrupt enable register (Direct 0x2C).

TIME_BASE Time base expiration interrupt indication.0=No time base event1=Time base has expired

Field Bits Length Initial ValueMODULE_A_EN 0 1 0

Reserved 1 1 0Reserved 2 1 0Reserved 3 1 0SPI4_EN 4 1 0SECONDARY_EN 5 1 0Reserved 7:6 2 0

TABLE 46 - PRIMARY INTERRUPT ENABLE REGIS-TER (0x2E IN THE DIRECT ACCESSED SPACE)

Field Bits Length Initial ValueTIME_BASE_EN 0 1 0INDIRECT_ACCESS_EN 1 1 0Reserved 7:2 6 0

TABLE 47 - SECONDARY INTERRUPT ENABLEREGISTER (0x2F IN THE DIRECT ACCESSED SPACE)

The secondary interrupt enable register (0x2F in the direct accessed space)has read and write access.

The secondary interrupt enable register is used to bitwise enable theinterrupts in the secondary interrupt enable register.

TIME_BASE_EN Time base expiration interrupt enable.0=Disable time base event interrupt1=Enable time base event interrupt

INDIRECT_ACCESS_EN Indirect access completion interrupt enable.0= Disable indirect access completion event interrupt1=Enable indirect access completion event interrupt


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Table Number, Page Block_base, Register_offset Title of Register

49, page 54 0x0000, 0x00-0xFF SPI-3 ingress LP to LID map

50, page 54 0x0200, 0x00 SPI-3 general configuration register

51, page 55 0x0200, 0x01 SPI-3 ingress configuration register

52, page 55 0x0200, 0x02 SPI-3 ingress fill level register

53, page 55 0x0200, 0x03 SPI-3 ingress max fill level register

54, page 55 0x0500, 0x00-0x3F SPI-3 egress LID to LP map

55, page 56 0x0700, 0x00 SPI-3 egress configuration register

56, page 56 0x0700, 0x01 SPI-4 ingress to SPI-4 egress flow control register

57, page 56 0x0700, 0x02 SPI-3 egress test register

58, page 57 0x0700, 0x03 SPI-3 egress fill level register

59, page 57 0x0700, 0x04 SPI-3 egress max fill level register

60, page 58 0x0A00, 0x00-0x17F LID associated event counters

61, page 58 0x0C00, 0x00-0x0B Non LID associated event counters

62, page 59 0x0C00, 0x0C Non LID associated interrupt indication register

63, page 59 0x0C00, 0x0D Non LID associated interrupt enable register

64, page 59 0x0C00, 0x0E LID associated interrupt indication register

65, page 59 0x0C00, 0x0F LID associated interrupt enable register

66, page 60 0x0C00, 0x10-0x15 Non critical LID associated capture table

67, page 60 0x0C00, 0x16-0x17 SPI-3 to SPI-4 critical LID interrupt indication registers

68, page 60 0x0C00, 0x18-0x19 SPI-3 to SPI-4 critical LID interrupt enable registers

69, page 60 0x0C00, 0x1A-0x1B SPI-4 to SPI-3 critical LID interrupt indication registers

70, page 60 0x0C00, 0x1C-0x1D SPI-4 to SPI-3 critical LID interrupt enable registers

71, page 60 0x0C00, 0x1E Critical events source indication register

72, page 61 0x1000, 0x00-0x3F SPI-3 ingress packet length configuration register

73, page 61 0x1100, 0x00-0x3F SPI-4 egress port descriptor table

74, page 61 ———————- SPI-4 egress direction code assignment

75, page 61 0x1200, 0x00-0x3F SPI-3 ingress port descriptor table

76, page 62 0x1300, 0x00 SPI-3 to SPI-4 PFP register

77, page 62 ———————- NR_LID field encoding

78, page 62 0x1300, 0x01 SPI-3 to SPI-4 flow control register

79, page 63 0x1600, 0x00-0x3F SPI-4 ingress packet length register

80, page 63 0x1700, 0x00-0x3F SPI-3 egress port descriptor table

81, page 63 ———————- SPI-3 egress direction code assignment

82, page 63 0x1800, 0x00-0x3F SPI-4 ingress port descriptor table

83, page 64 0x1900, 0x00 SPI-4 to SPI-3 PFP register

84, page 64 ———————- NR_LID field encoding

TABLE 48 - MODULE A INDIRECT REGISTER

9.3 Indirect registers for SPI-3A module

Module A is at Module_base 0x0000


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TABLE 50 - SPI-3 GENERAL CONFIGURATIONREGISTER (REGISTER_OFFSET=0x00)

Field Bits Length Initial ValueLINK 0 1 0b0PACKET 1 1 0b1SPI3_ENABLE 2 1 0b0BUSWIDTH 3 1 0b0EVEN_PARITY 4 1 0b0PARITY_EN 5 1 0b1Reserved 6 1 0b0Reserved 7 1 0b0WATERMARK 12:8 5 0x0FReserved 31:13 19 0x000

9.3.1 Block base 0x0000 registersSPI-3 ingress LP to LID map (Block_base 0x0000 +Register_offset 0x00 to 0xFF)

TABLE 49 - SPI-3 INGRESS LP TO LID MAPField Bits Length Initial Value

LID 5:0 6 0x00ENABLE 6 1 0b0BIT_REVERSAL 7 1 0b0

There are 256 SPI-3 ingress Logical Port (LP) to Logical Identifier (LID)registers, one per potential SPI-3 LP. Only 64 LPs per SPI-3 physical interfacecan be enabled. An attempt to enable more than 64 LPs per SPI-3 physicalinterface or to assign an identical LID to more than one LP will be discardedand an error code will be returned. The ENABLE bit is used to enable SPI-3 logical ports. All data from non-enabled SPI-logical ports is discarded andan inactive SPI-3 logical port event is generated. This event is directed towardsthe PMON & DIAG module. Disabled ports always generate available status.

The Table 49 - SPI-3 ingress LP to LID Map assigns a LID to a SPI-3 logicalport. LID mapping for 64 out of 256 SPI-3 logical ports is supported on the SPI-3 physical port. LPs in the SPI Exchange are 8 bits wide[7:0] and range from0 to 255. An example of mapping SPI-3 physical interface, LP 0x08 to LID 0x05,activating the LID, and not using bit reversal is outlined.

Perform an indirect write of 0x45 to register address Module_base 0x0000+ Block_base 0x0000 + Register_offset 0x08 = 0x0008.

The Initial Value column is the value of the register after reset.

LID The LID programmed is associated to the LP with the samenumber as the register address. Six bits support the 64 simultaneously activeLIDs on the SPI-3 physical interface.

ENABLE This bit is used to enable or disable the connection of this LPto this LID.

0=LID disabled1=LID enabled

BIT_REVERSAL This bit is used to reverse the bit ordering of each byteof the SPI-3 interface on a per-LID basis.

0=Disable bit reversal for this LID1=Enable bit reversal for this LID

9.3.2 Block base 0x0200 registersSPI-3 general configuration register (Block_base0x0200 + Register_offset 0x00)

There is one register for SPI-3 general configuration for the SPI-3 interface.The SPI-3 general configuration register has read and write access. Theaddress for the SPI-3 general configuration register is 0x0200. The bit fields ofthe SPI-3 general configuration register are described in the following para-graphs.

LINK A SPI-3 interface can be used either in Link or PHY modes. Forconnecting to a transmission line-interface PHY, program the SPI Exchange forLink mode. For connecting the SPI-3 interface to an NPU or other Link-modedevice, program the SPI-3 interface for PHY mode. The SPI-3 ingress andegress of a given SPI-3 physical port will always be in the same mode.

0= SPI-3 interface in PHY mode1= SPI-3 interface in Link mode

PACKET A SPI-3 interface can be used either in BYTE or PACKETmodes. A SPI-3 interface acting as a Link layer device can poll the attached PHYdevice for up to 64 LPs if the attached PHY device supports the polling interface.When attached to a PHY device that only supports byte mode, the four directstatus indicators can be used. When the SPI Exchange is in PHY mode, thePACKET bit is used to select either a polled or direct status response to theattached Link device.

0 = BYTE mode with direct status indication for up to 4 LPs [3:0]1= PACKET mode with polled status for up to 64 LPs

SPI3_ENABLE The SPI-3 interface can be enabled or disabled accordingto the state programmed into this bit. A port should be disabled to save powerif it is not used.

0=SPI-3 Physical port disabled, outputs are in tristate1=SPI-3 Physical port enabled

BUSWIDTH The SPI-3 interface can be used as either a single 8-bit or32-bit interface, according to the needs of the attached device. The SPI-3 ingressand egress of a given SPI-3 physical port will always be of the same bus width.

0=32 bit SPI-3 interface1=8 bit SPI-3 interface

EVEN_PARITY The SPI-3 interface is provisioned to generate and tocheck for odd or even parity. The PARITY_EN bit must be set for this to becomeeffective. Odd parity is standard for SPI-3 interfaces.


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0=Odd parity on this port1=Even parity on this port

PARITY_EN The SPI-3 interface is provisioned to enable or disable paritygeneration and checking, according to the state of the EVEN_PARITY bit.

0=Disable parity on this SPI-3 port1=Enable parity on this SPI-3 port

WATERMARK The SPI-3 interface can be set to a SPI-3 ingress portwatermark value. The value of 0x10 is the highest watermark that can be set,meaning all ingress buffers will be full before backpressure will be initiated onthe SPI-3 ingress interface. The WATERMARK field value of 0x08 is used toset the watermark for a half-full ingress buffer before tripping backpressure. Theunits of WATERMARK are one-sixteenth of the available ingress buffering perunit. Each unit is equal to 128 bytes. BACKPRESSURE_EN must be set[Register_offset 0x01] for the watermark to become effective. The watermarkfield is usually set to 0x10, and the FREE_SEGMENT field of Table 75, SPI-3 ingress port descriptor tables (Block_base 0x1200) is used for per LIDbackpressure.

SPI-3 ingress configuration register (Block_base0x0200 + Register_offset 0x01)

There is one SPI-3 ingress configuration register for the SPI-3 interface. Theregister has read and write access.

The bit fields for the SPI-3 ingress configuration register are described in thefollowing paragraphs.

BACKPRESSURE_EN the SPI-3 interface can have backpressureenabled or disabled. Disabling backpressure means that data coming into theingress may be lost if the SPI-3 interface ingress buffers overflow. The SPI-3interface can run at full-rate, however, since there will be no backpressure.Attached devices that do not respond properly to backpressure should beinterfaced by disabling backpressure.

Enabling backpressure will cause the I_ENB signal to be asserted when theingress buffer fill level is equal to the WATERMARK value [Register_offset 0x00],or the free segment buffer threshold Table 75, SPI-3 ingress port descriptor table(Block_base 0x1200) has been reached for any active LID.

0=Disable backpressure on the SPI-3 ingress.1=Enable backpressure on the SPI-3 ingress interface.

FIX_LP The SPI-3 interface can fix the logical port address to 0x00. Thisis useful when there is only one LP on an interface, such as with some single-PHY devices.

0= Do not fix logical port address to 0x00, but use the actualLP found in the packet fragments.1= Fix logical port address to 0x00

SPI-3 ingress fill level register (Block_base 0x0200+ Register_offset 0x02)

TABLE 51 - SPI-3 INGRESS CONFIGURATIONREGISTER (REGISTER_OFFSET=0x01)

Field Bits Length Initial ValueBACKPRESSURE_EN 0 1 0b1FIX_LP 1 1 0b0Reserved 31:2 30 0x0000

There is one register for SPI-3 ingress fill level register for the SPI-3 interface.The register has read-only access. The bit fields of the SPI-3 ingress fill levelregister are described.

FILL_CUR Current SPI-3 ingress buffer fill level. Since this is a real-timeregister, the value read from it will change rapidly and is used for internaldiagnostics only.

I_FCLK_AV Current SPI-3 ingress clock availability is checked here.0=SPI-3 ingress clock not detected on a SPI-3 port1=SPI-3 ingress clock transitions detected on a SPI-3 port

SPI-3 ingress max fill register (Block_base 0x0200+ Register_offset 0x03)

TABLE 52 - SPI-3 INGRESS FILL LEVEL REGISTER(REGISTER_OFFSET=0x02)

Field Bits Length Initial ValueFILL_CUR 4:0 5 0x00I_FCLK_AV 5 1 0b1

TABLE 53 - SPI-3 INGRESS MAX FILL LEVELREGISTER (REGISTER_OFFSET=0x03)

Field Bits Length Initial ValueFILL_MAX 4:0 5 0x00

There is one register for SPI-3 ingress max fill level register per SPI-3interface. Each register has read-only access, and is cleared after reading.0x10 is the highest filling level, meaning all ingress buffers had been full at sometime since the last read of the FILL_MAX field. The units of FILL_MAX are one-sixteenth of the available ingress buffering. Each unit is equal to 128 bytes. Thebit field of a SPI-3 ingress max fill level register is described. The Table 53 - SPI-3 ingress max fill level register (Register_offset=0x03) is for diagnostics only.

FILL_MAX Maximum SPI-3 ingress buffer fill level since the last read ofthe SPI-3 ingress max fill level register.

9.3.3 Block base 0x0500 registers

SPI-3 egress LID to LP map (Block_base 0x0500 +Register_offset 0x00-0x3F)TABLE 54 - SPI-3 EGRESS LID TO LP MAP

Field Bits Length Initial ValueLP 7:0 8 0x00ENABLE 8 1 0b0BIT_REVERSAL 9 1 0b0There are 64 SPI-3 egress LID to LP maps for the SPI-3 interface, one per

potential SPI-3 LID.The SPI-3 egress LID to LP maps have read and write access. The SPI-

3 egress LID to LP maps are used to map SPI-3 egress logical identifiers to SPI-3 logical port addresses that are in-band with the SPI-3 egress packet fragments.

LP The LP programmed is associated to the LID with the same numberas the register address.


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TABLE 56 - SPI-4 INGRESS TO SPI-3 EGRESS FLOWCONTROL REGISTER (REGISTER_OFFSET=0x01)

Field Bits Length Initial ValueCREDIT_EN 0 1 0b0BURST_EN 1 1 0b0LOOP_BACK 2 1 0b0Reserved 31:3 29 0x00

TABLE 57 - SPI-3 EGRESS TEST REGISTER(REGISTER_OFFSET=0x02)

Field Bits Length Initial ValueADD_PAR_ERR 0 1 0b0DAT_PAR_ERR 1 1 0b0Reserved 7:2 6 0x00PORT_ADDRESS 15:8 8 0x0F

ENABLE This bit is used to enable or disable the connection of a LID toan LP.

0=LP disabled1=LP enabled

BIT_REVERSAL This bit is used to reverse the bit ordering of each byteof the SPI-3 interface on a per-LP basis.

0=Disable bit reversal for an LP1=Enable bit reversal for an LP


SPI-3 egress configuration register (Block_base0x0700 + Register_offset 0x00)

There is one SPI-3 egress configuration register per SPI-3 interface. TheSPI-3 egress configuration registers have read and write access. A SPI-3egress configuration registers is used to control the poll sequence length of aSPI-3 egress interface when the SPI-3 interface is in Link mode. The SPI-3egress configuration register is used to add two cycles to STX or EOP asrequired to interface to the attached device.

POLL_LENGTH Link layer poll sequence length when in Link mode. Thepoll sequence is from the LP associated with LID0 to the LP associated with theLID for POLL_LENGTH - 1.

STX_SPACING This bit is used to enable or disable the adding of twodummy STX cycles to the SPI-3 egress interface to meet the needs of an attacheddevice.

0= No dummy STX cycles are added to the SPI-3 egress.1= Two dummy STX cycles are added to the SPI-3 egress

EOP_SPACING This bit is used to enable or disable the adding of twodummy EOP cycles to the SPI-3 egress interface to meet the needs of an attacheddevice.

0= No dummy EOP cycles are added to the SPI-3 egress.1= Two dummy EOP cycles are added to the SPI-3 egress

SPI-4 ingress to SPI-3 egress flow control register(Block_base 0x0700 + Register_offset 0x01)

The SPI-4 ingress to SPI-3 egress flow control register has read and writeaccess. The bit fields of the SPI-4 ingress to SPI-3 egress flow control registerare described.

CREDIT_EN CREDIT_EN The flow control information received fromthe attached SPI-3 device is interpreted as status or credit information as selectedby the CREDIT_EN bit in the SPI-4 ingress to SPI-3 egress flow control Register.If the status mode is used, data will be egressed until the status is changed bythe attached SPI-3 device. If the credit mode is used, the SPI-3 egress willtransmit only one packet fragment and then wait for an update in the internal buffersegment pool status before sending another packet fragment.

0=Status mode1=Credit mode

BURST_EN Multiple Burst Enable allows more than one burst to be sentto an LP. When this feature is not enabled, only one burst per LP is allowed intothe SPI-3 egress buffers.

0=Disable burst enable1=Enable burst enable

LOOP_BACK In this mode the contents of a SPI-3 ingress are directlytransferred to a SPI-3 egress buffers of the same port. This mode is useful foroff-line diagnostics.

0=Disable loopback1=Enable loopback

SPI-3 egress test register (Block_base 0x0700 +Register_offset 0x02)

TABLE 55 - SPI-3 EGRESS CONFIGURATIONREGISTER (REGISTER_OFFSET=0x00)

Field Bits Length Initial ValuePOLL_LENGTH 5:0 6 0x0FReserved 7:6 2 0b00STX_SPACING 8 1 0b0EOP_SPACING 9 1 0b0Reserved 31:10 22 0x00

The SPI-3 egress test register has read and write access. A single addressparity error is introduced on the SPI-3 egress LP through the ADD_PAR_ERRbit field. A single data parity error is introduced on the SPI-3 egress LP throughthe DAT_PAR_ERR bit field. The LP affected by these two parity error bit fieldsis enumerated in the PORT_ADDRESS field. The bit fields of SPI-3 egress testregister are described. The bit fields are automatically cleared following thegeneration of the associated error.

ADD_PAR_ERR A single address parity error is introduced on the SPI-3 egress LP through the ADD_PAR_ERR bit field. The LP affected by theADD_PAR_ERR bit field is enumerated in the PORT_ADDRESS field.

0=No parity error introduced1=Introduce a single address parity error on the SPI-3 egress LP

DAT_PAR_ERR A single data parity error is introduced on the SPI-3egress LP through the DAT_PAR_ERR bit field. The LP affected by theDAT_PAR_ERR bit field is enumerated in the PORT_ADDRESS field.

0=No parity error introduced1=Introduce a single data parity error on the SPI-3 egress LP

PORT_ADDRESS The LP affected by both the ADD_PAR_ERRand the DAT_PAR_ERR bit fields is enumerated in the PORT_ADDRESS field.The value of the PORT_ADDRESS is set from 0x00 to 0xFF.


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There is one register for SPI-3 egress fill level register for the SPI-3 interface.The register has read-only access. The bit fields of the SPI-3 egress fill levelregister are described.

FILL_CUR Current SPI-3 egress buffer fill level. Since this is a real-timeregister, the value read from it will change rapidly and is used for internaldiagnostics only.

I_FCLK_AV Current SPI-3 egress clock availability is checked here.0=SPI-3 egress clock transitions were not detected on aSPI-3 port1=SPI-3 egress clock transitions were detected on a SPI-3 port

SPI-3 egress fill level register (Block_base 0x0700+ Register_offset 0x03)

SPI-3 egress max fill level register (Block_base0x0700 + Register_offset 0x04)

TABLE 58 - SPI-3 EGRESS FILL LEVEL REGISTER(REGISTER_OFFSET=0x03)

Field Bits Length Initial ValueFILL_CUR 3:0 4 0x0

Reserved 4 1 0x0E_FCLK_AV 5 1 0b0

TABLE 59 - SPI-3 EGRESS MAX FILL LEVEL REGIS-TER (REGISTER_OFFSET=0x04)


There is one register for SPI-3 egress max fill Level for the SPI-3 interface.The register has read-only access, and is cleared after reading. 0xF is thehighest filling level, meaning all egress buffers had been full at some time sincethe last read of the FILL_MAX field. The units of FILL_MAX are one-sixteenthof the available egress buffering. Each unit is equal to 128 bytes. The bit fieldof the SPI-3 egress max fill Level register is described.

FILL_MAX Maximum SPI-3 egress buffer fill level since the last readof the SPI-3 egress Max Fill Level Register


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Performance monitor countersTwo categories of events are captured: LID and non LID associated events.

If at least one event is captured in one of the interrupt indication registers, an activePMON service request is directed towards the interrupt module.

All events and diagnostics data are accumulated during an interval definedby the time base event. The data accumulated during the previous time periodcan be accessed by the indirect access scheme. The counters are cleared whenthe time base expires. All counters are saturating, and will not overflow.

9.3.5 Block base 0x0A00 registers

LID associated event counters (Block_base0x0A00 + Register_offset 0x000 to 0x17F)

A set of event counters is provided for each of the 64 LIDs on the SPI-3

TABLE 60 - LID ASSOCIATED EVENT COUNTERS(0x000-0x17F)

Offset Counter Counterlength (bits)

LID*6+0 SPI-3 ingress good packet counter 24LID*6+1 SPI-3 ingress bad packet counter(error tagged) 24LID*6+2 SPI-4 ingress good packet counter 24LID*6+3 SPI-4 ingress bad packet counter(abort) 24LID*6+4 SPI-3 egress packet counter 24LID*6+5 SPI-4 egress packet counter 24

interface and for each LID to or from a SPI-4 module. LID associated eventcounters keep track of packets, packets not delineated by an SOP and an EOP,or error-tagged packets.

TABLE 61 - NON LID ASSOCIATED EVENT COUNTERS (0x00 - 0x0B)Offset Counters Subject to accumulation Width

0x00 SPI-3 ingress bytes All bytes of transfers for active SPI-3 (excluding 29address parity error)

0x01 SPI-3 ingress transfers All transfers for active SPI-3 260x02 PFP3-4 ingress too long packet SPI-3 ingress packets longer than MAX_LENGTH 80x03 PFP3-4 ingress too short packet SPI-3 ingress packets shorter than MIN_LENGTH 80x04 SPI-3 ingress error tagged packet Parity error on SPI-3 ingress 80x05 Reserved 80x06 SPI-4 ingress bytes All bytes of transfers for SPI-4 29

0x07 SPI-4 ingress transfers All transfers for active SPI-4 26

0x08 PFP4-3 ingress too long packet SPI-4 ingress packets longer than MAX_LENGTH 80x09 PFP4-3 ingress too short packet SPI-4 ingress packets shorter than MIN_LENGTH 80x0A SPI-4 ingress error tagged packet DIP-4 error on ingress 80x0B Reserved 8

Non LID Associated Event Counters are associated with SPI-3 and SPI-4 physical interfaces. The register offset is shownin the Offset column.

9.3.6 Block base 0x0C00 registers

Non LID associated event counters (Block_base 0x0C00 + Register_offset0x00 to 0x0B)


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Non LID associated interrupt indication register(Block_base 0x0C00 + Register_offset 0x0C)TABLE 62 - NON LID ASSOCIATED INTERRUPTINDICATION REGISTER (REGISTER_OFFSET0x0C)

Field Bits Length Initial ValueSPI4_LOCK_UN 0 1 0b0SPI3_LOCK_UN 1 1 0b0SPI3_ICLK_UN 2 1 0b0SPI3_ECLK_UN 3 1 0b0SPI3_FLUSH 4 1 0b0Reserved 31:5 27 0x0

The Non LID associated interrupt indication register is at Block_Base0x0C00. The Non LID interrupt indication register is used to determine the statusof SPI-3 and SPI-4 port interrupts. The Non LID associated interrupt indicationregister is read and subsequently a “1” is written to acknowledge individualinterrupts in this register. An interrupt is generated when enabled by thecorresponding enable flag in the Non LID associated interrupt indicationregister. The bit fields in the Non LID associated interrupt indication register aredescribed.

SPI4_LOCK_UN The SPI-4 interface can create an event indicating thatthe SPI-4 ingress has dropped data due the unavailability of ingress buffering.

0=No operation1=The SPI-4 interface has dropped data due theunavailability of ingress buffering.

SPI3_LOCK_UN A SPI-3 interface can create an event indicating that aSPI-3 ingress has dropped data due the unavailability of ingress buffering.

0=No operation1=A SPI-3 interface has dropped data due theunavailability of ingress buffering.

SPI3_ICLK_UN A SPI-3 interface can create an event indicating that aSPI-3 ingress clock has failed. No transitions were detected on a SPI-3 ingressclock (I_FCLK)

0=No operation1=A SPI-3 ingress clock has failed.

SPI3_ECLK_UN A SPI-3 interface can create an event indicating that aSPI-3 egress clock has failed. No transitions were detected on a SPI-3 egressclock (E_FCLK)

0=No operation1=A SPI-3 egress clock has failed.

SPI3_FLUSH A SPI-3 interface can create an event indicating that aSPI-3 buffer has been flushed and data has been lost. A buffer is flushed if anaddress parity error is detected, or if an ingress buffer is not available at the timeit is requested.

0=No operation1=A SPI-3 buffer has been flushed.

Non LID associated interrupt enable register(Block_base 0x0C00 + Register_offset 0x0D)TABLE 63 - NON LID ASSOCIATED INTERRUPTENABLE REGISTER(REGISTER_OFFSET 0x0D)

Field Bits Length Initial ValueSPI4_LOCK_UN 0 1 0b0SPI3_LOCK_UN 1 1 0b0SPI3_ICLK_UN 2 1 0b0SPI3_ECLK_UN 3 1 0b0SPI3_FLUSH 4 1 0b0Reserved 31:5 27 0x0000

The Non LID associated interrupt enable register is at Block_Base 0x0C00+ Register_offset 0x0D. The Non LID associated interrupt enable register isused to mask the status of SPI-3 and SPI-4 port interrupts in the Non LIDassociated interrupt indication register. The Non LID associated interrupt enableregister has read and write access. The bit fields in the Non LID associatedinterrupt enable register are active “1” interrupt enables for the correspondingbit fields in the Non LID associated interrupt indication register.

LID associated interrupt indication register(Block_base 0x0C00 + Register_offset 0x0E)

TABLE 64 - LID ASSOCIATED INTERRUPT INDICA-TION REGISTER (REGISTER_OFFSET 0x0E)

Field Bits Length Initial ValueEVENT_TYPE 5:0 6 0x00Reserved 31:6 26 0x0

The LID associated interrupt indication register is at Block_Base 0x0C00 +Register_offset 0x0E. The LID associated interrupt indication register is usedto determine the EVENT_TYPE of SPI-3 and SPI-4 interrupts. TheEVENT_TYPE coding is given in the Table 66 - Non critical LID associatedcapture table (0x10-0x15). The LID associated interrupt indication register isread and subsequently a 0xFF must be written for interrupt acknowledge. AnEVENT_TYPE interrupt is generated when enabled by the EVENT_TYPEenable flag in the LID associated interrupt enable register.

LID associated interrupt enable register(Block_base 0x0C00 + Register_offset 0x0F)

TABLE 65 - LID ASSOCIATED INTERRUPT ENABLEREGISTER (REGISTER_OFFSET 0x0F)

Field Bits Length Initial ValueEVENT_TYPE 5:0 6 0x00Reserved 31:6 26 0x0

The LID associated interrupt enable register is at Block_Base 0x0C00 +Register_offset 0x0F. The LID associated interrupt enable register is used tomask the EVENT_TYPE of SPI-3 and SPI-4 per-LID interrupts. The LIDassociated interrupt enable register has read and write access.


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Non critical LID associated capture table(Block_base 0x0C00 + Register_offset 0x10-0x15)

The Non critical LID associated capture table is at Block_Base 0x0C00 +Register_Offset 0x10-0x15. The Non critical LID associated capture table isused to determine the EVENT_TYPE of SPI-3 and SPI-4 per-LID or per-LPinterrupts. The EVENT_TYPE coding is used to indicate which event or eventsare pertinent to the interrupt in the Table 64 - LID associated interrupt indicationregister(0x0E). The Non critical LID associated capture table is used todetermine the EVENT, and multiple bits can be active at the same time. The Noncritical LID associated capture table is read-only.

SPI-3 to SPI-4 critical LID interrupt indicationregisters (Block_base 0x0C00 + Register_offset0x16-0x17)

The SPI-3 to SPI-4 critical LID interrupt indication registers are at Block_Base0x0C00 + Register_offset 0x10-0x15.

Critical events are captured per LID in the SPI-3 to SPI-4 critical LID interruptindication registers. An interrupt is generated when enabled by the enable flagin the SPI-3 to SPI-4 critical LID interrupt enableregisters. A SPI-3 to SPI-4 criticalLID interrupt indication register has read and write access. An interrupt indicationis cleared by writing a logical one to the appropriate bit of a SPI-3 to SPI-4 criticalLID interrupt indication register. Only one kind of critical event is defined-bufferoverflow. Each bit of the LID field set to logical one indicates the presence of abuffer overflow event. A summary indication of as to which of the two sources,SPI-3 to SPI-4 or SPI-4 to SPI-3, is responsible for the critical interrupt is indicatedin the Table 71 Critical events source indication register (0x1E).

SPI-3 to SPI-4 critical LID interrupt enable regis-ters (Block_base 0x0C00 + Register_offset 0x18-0x19)

TABLE 66 - NON CRITICAL LID ASSOCIATEDCAPTURE TABLE (REGISTER_OFFSET 0x10-0x15)

Register EVENT_TYPE Associatedfield

0x00 Inactive ingress SPI-3 logical port event LP (8 bits)0x01 SPI-3 ingress data parity error LID (6 bits)0x02 SPI-4 illegal SOP sequence event LID (6 bits)0x03 SPI-4 illegal EOP sequence event LID (6 bits)0x04 SPI-3 illegal SOP sequence event LID (6 bits)0x05 SPI-3 illegal EOP sequence event LID (6 bits)

TABLE 67 - SPI-3 TO SPI-4 CRITICAL LID INTER-RUPT INDICATION REGISTERS(REGISTER_OFFSET 0x16-0x17)

Register Field Bits Length Initial Value0x16 LID[31:0] 31:0 32 0x000x17 LID[63:32] 31:0 32 0x00

TABLE 68 - SPI-3 TO SPI-4 CRITICAL LID INTERRUPTENABLE REGISTERS (REGISTER_OFFSET 0x18-0x19)

Register Field Bits Length Initial Value0x18 LID[31:0] 31:0 32 0x000x19 LID[63:32] 31:0 32 0x00

The SPI-3 to SPI-4 critical LID interrupt enable registers have read and writeaccess. A SPI-3 to SPI-4 critical LID interrupt enable register bits enable thecorresponding bits in a SPI-3 to SPI-4 critical LID interrupt indication register.

SPI-4 to SPI-3 critical LID interrupt indicationregisters (Block_base 0x0C00 + Register_offset0x1A-0x1B)TABLE 69 - SPI-4 TO SPI-3 CRITICAL LID INTERRUPTINDICATION REGISTERS (REGISTER_OFFSET0x1A-0x1B)

Register Field Bits Length Initial Value0x1A LID[31:0] 31:0 32 0x000x1B LID[63:32] 31:0 32 0x00

The SPI-4 to SPI-3 critical LID interrupt indication registers are at Block_Base0x0C00 + Register_offset 0x1A-0x1B.

Critical events are captured per LID in a SPI-4 to SPI-3 critical LID interruptindication register. An interrupt is generated when enabled by the enable flagin the SPI-4 to SPI-3 critical LID interrupt enableregister. The SPI-4 to SPI-3critical LID interrupt indication registers have read and write access. An interruptindication is cleared by writing a logical one to the appropriate bit of a SPI-4 toSPI-3 critical LID interrupt indication register. Only one kind of critical event isdefined-buffer overflow. Each bit of a LID field set to logical one indicates thepresence of a buffer overflow event. A summary indication of as to which of thetwo sources, SPI-3 to SPI-4 or SPI-4 to SPI-3, is responsible for the criticalinterrupt is indicated in the Table 71 Critical events source indication register(0x1E).

SPI-4 to SPI-3 critical LID interrupt enable regis-ters (Block_base 0x0C00 + Register_offset 0x1C-0x1D)TABLE 70 - SPI-4 TO SPI-3 CRITICAL LID INTER-RUPT ENABLE REGISTERS (REGISTER_OFFSET0x1C-0x1D)

Register Field Bits Length Initial Value0x1C LID[31:0] 31:0 32 0x000x1D LID[63:32] 31:0 32 0x00

The SPI-4 to SPI-3 critical LID interrupt enable registers have read and writeaccess. The SPI-4 to SPI-3 critical LID interrupt enable register bits enable thecorresponding bits in the SPI-4 to SPI-3 critical LID interrupt indication registers.

Critical events source indication register(Block_base 0x0C00 + Register_offset 0x1E)

TABLE 71 - CRITICAL EVENTS SOURCE INDICA-TION REGISTER (REGISTER_OFFSET 0x1E)

Field Bits Length Initial ValueSPI34_OVR 0 1 0b0SPI43_OVR 1 1 0b0Reserved 31:2 30 0x0

The bits in the Critical events source indication register are read only. BitSPI34_OVR reflects the logical OR result of all bits in the SPI-3 to SPI-4 criticalLID associated interrupt indication registers. Bit SPI43_OVR reflects the logicalOR result of all bits in the SPI-4 to SPI-3 critical LID interrupt indication registers.


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9.3.7 Block base 0x0100 registersSPI-3 ingress packet length configuration register(Block_base 0x1000 + Register_offset 0x00-0x3F)

TABLE 72 - SPI-3 INGRESS PACKET LENGTHCONFIGURATION REGISTER

Field Bits Length Initial ValueMIN_LENGTH 7:0 8 0x40Reserved 15:8 8 0x00MAX_LENGTH 29:16 14 0x5EE

There is one set of SPI-3 ingress packet length configuration registers for theSPI-3 ingress interface. The SPI-3 ingress interface has 64 registers, one foreach of the allowed LIDs supported by the SPI-3 interface. Each register hasread and write access. The minimum and maximum packet lengths per LID areprovisioned using the SPI-3 ingress packet length configuration register. Thebit fields of a SPI-3 ingress packet length configuration register are described.

MIN_LENGTH SPI-3 ingress minimum packet length. The minimumpacket length is programmed from 0 to 255 bytes. The resolution of the minimumpacket length is one byte.

MAX_LENGTH SPI-3 ingress maximum packet length. The maximumpacket length is programmed from 0 to 16,383 bytes. The resolution of themaximum packet length is one byte.

9.3.8 Block base 0x1100 registersSPI-4 egress port descriptor table (Block_base0x1100 + Register_offset 0x00-0x3F)TABLE 73 - SPI-4 EGRESS PORT DESCRIPTORTABLE (64 ENTRIES)

Field Bits Length Initial ValueMAX_BURST_H 3:0 4 0xFMAX_BURST_S 7:4 4 0xFDIRECTION 9:8 2 0x3Reserved 31:10 22 0x000

There is one set of SPI-4 egress port descriptor tables for the SPI-4 egressinterface. The SPI-4 egress interface has 64 SPI-4 egress port descriptor tables,one for each allowed SPI-3 LID. The minimum and maximum SPI-4 egress burstlengths per LID are provisioned using the SPI-4 egress port descriptor table.Each SPI-4 egress port descriptor table has read and write access.The bit fieldsof the SPI-4 egress port descriptor table are described. These fields need tobe programmed only for SPI-4 egress (DIRECTION=0 in Table 74-SPI-4egress direction code assignment).

MAX_BURST_H SPI-4 egress per-LID burst length when the attacheddevice has declared hungry through the FIFO status channel. The number inthe MAX_BURST_H field is taken to mean that one more than that numbermultiplied by 16 is the maximum hungry burst length. For example, programmingthe number 3 into the MAX_BURST_H field results in a maximum hungry burstsize of (3 + 1) 9.3.9 Block base 0x1200 registers

MAX_BURST_S SPI-4 egress per-LID burst length when the attacheddevice has declared starving through the FIFO status channel. The number in

the MAX_BURST_S field is taken to mean that one more than that numbermultiplied by 16 is the maximum starving burst length. For example, program-ming the number 7 into the MAX_BURST_S field results in a maximum starvingburst size of (7 + 1) x 16 = 128 bytes. The MAX_BURST_S field should not beset to less than the MAX_BURST_H field.

DIRECTION The SPI-4 egress traffic can be captured by the micropro-cessor, directed to a SPI-3 egress port, to the SPI-4 egress port, or discarded.The Path selection is defined for each of the 64 LIDs by the associatedDIRECTION field as shown in the following table.

DIRECTION Path00 SPI-401 Reserved10 Capture to microprocessor11 Discard

TABLE 74 - SPI-4 EGRESS DIRECTION CODEASSIGNMENT

TABLE 75 - SPI-3 INGRESS PORT DESCRIPTORTABLE (BLOCK_BASE 0x1200)

Field Bits Length Initial ValueM 8:0 9 0x000Reserved 15:9 7 0x00Reserved 20:16 5 0x00Reserved 23:21 3 0x0FREE_SEGMENT 28:24 5 0x00Reserved 31:29 3 0x0

There is one set of 64 SPI-3 ingress port descriptor tables for the SPI-3 ingressinterface. The SPI-3 ingress port descriptor tables are at Block_base 0x1200and have read and write access. The SPI-3 ingress interface has 64 tableentries for per-LID provisioning of M and FREE_SEGMENT fields. The SPI-3 ingress port descriptor tables are used to control the amount of buffering andthe free segment backpressure threshold of the available buffer segment poolfor the SPI-3 ingress on a per-LID basis.

The SPI-3 ingress buffer segment pool is 128 Kbytes, divided into 508segments of 256 bytes per segment. These 508 segments are shared amongthe LIDs initially programmed into the NR_LID fields. A SPI-3 ingress LID canbe allocated the maximum number of segments out of the available buffersegments, or can be programmed to fewer segments by decreasing the M field.

The FREE_SEGMENT field is used, along with the M field, to set the freesegment backpressure threshold for a LID on a SPI-3 ingress.

M The number of 256-byte buffer pool segments on a SPI-3 ingress portallocated to a LID. The range of M is 0x000 to 0x1FC (508 base 10), but cannot exceed the number set by the choice of NR_LID [Block_base 0x1300 +Register_offset 0x00].


SPI-3 ingress port descriptor tables (Block_base0x1200 + Register_offset 0x00-0x3F)


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An example of the use of the buffer segment pool follows. For a SPI-3 ingressinterface that will never have more than four LIDs, set the NR_LID field for thisinterface to 0x01. This allows 256 buffer segments for a LID, with the total numberof buffer segments for all 4 LIDs equal to 508. Let’s say you want only 64 buffersegments for one of the LIDs. Program field M for that LID to 0x040 (64 base10). Let’s say you want to backpressure the SPI-3 ingress interface when 48of the 64 allocated buffers for this LID are full. In other words, you want to exertSPI-3 ingress backpressure when only 16 segments remain for this LID. SinceM=0x040, N=4 from the description of the M field above [Block_base 0x1200].Setting the FREE_SEGMENT field to 4 then yields the desired THRESHOLDof 16.

TABLE 77 - NR_LID FIELD ENCODING

NR_LID Maximum Number Maximum Buffer Segmentsof LIDs for a LID

0b000 1 5080b001 4 2560b010 8 1280b011 16 640b100 32 320b101 64 16

SPI-3 to SPI-4 flow control register (Block_base0x1300 + Register_offset 0x01)

TABLE 78 - SPI-3 TO SPI-4 FLOW CONTROL REG-ISTER (REGISTER_OFFSET 0x01)

Field Bits Length Initial ValueCREDIT_EN 0 1 0b1BURST_EN 1 1 0b0Reserved 7:3 6 0x00

The SPI-3 to SPI-4 flow control register has read and write access. Thereis one SPI-3 to SPI-4 flow control register for the SPI-3 ingress.The bit fields ofthe SPI-3 to SPI-4 flow control register are described.

CREDIT_EN The information received over the FIFO status channel isinterpreted as status or credit information as selected by the CREDIT_EN flagin the SPI-3 to SPI-4 flow control Register. If the status mode is used, data willbe egressed until the status is changed by the attached device. If the credit modeis used, the SPI-4 egress will issue only one credit’s worth data burst and thenwait for another credit from the status channel before issuing another LID burst.

0=Status mode1=Credit mode

BURST_EN Multiple Burst Enable allows more than one burst to be sentto an LP. This feature is included to relieve systems with long latency betweenupdates. When this feature is not enabled, only one burst per LP is allowed intothe SPI-4 egress buffers.

0=Disable burst enable1=Enable burst enable

FREE_SEGMENT The FREE_SEGMENT field is used to define the SPI-3 ingress per-LID free segment backpressure threshold based on the numberof free buffer segments (M) available, as follows:

THRESHOLD = N * FREE_SEGEMENT,

Where the value of N is defined as a function of the domain of M:

M[8:0] N (base 10)0x1FC to 0x100 160x0FF to 0x080 80x07F to 0x040 40x03F to 0x020 20x01F to 0x000 1

The THRESHOLD thus defined is the number of free segments available fora LID at the time of backpressure initiation.


The SPI-3 ingress to SPI-4 egress Packet Fragment Processor and flowcontrol registers are at Block_Base 0x1300.

SPI-3 to SPI-4 PFP register (Block_base 0x1300 +Register_offset 0x00)TABLE 76 - SPI-3 TO SPI-4 PFP REGISTER(REGISTER_OFFSET 0x00)

Field Bits Length Initial ValueNR_LID 2:0 3 0b011Reserved 7:3 5 0x0

A SPI-3 ingress to SPI-4 egress PFP (Packet Fragment Processor) Registerhas read and write access. There is one SPI-3 to SPI-4 PFP Register per SPI-3 ingress. The bit fields of a SPI-3 to SPI-4 PFP Register are described.

NR_LID The maximum number of LIDs per SPI-3 physical ingressinterface that will ever be used is programmed into the NR_LID field. Onceconfigured after reset, this value can not be changed. Fewer LIDs can be usedby not activating some of the LIDs, but more LIDs than the value in NR_LID arenot allowed and will generate an error. The NR_LID field is important, as thebuffer segment pool is divided among the number of LIDs programmed into theNR_LID field.

A 128 Kbyte SPI-3 to SPI-4 buffer segment pool for storing data bursts forthe SPI-4 egress is available for each SPI-3 physical port. A configurable partof this buffer segment pool can be assigned to each of the possible LIDs allowedby the NR_LID field value per SPI-3 physical interface. The buffer size for a LIDcan be configured in multiples (M) of 256 bytes. Modifications of the buffer sizeallocated to a LID are supported only when the logical port associated to the LIDis disabled. Attempts to allocate more memory than available will generate anallocation error event. The indirect access module will discard the attempt.

A 128 Kbyte SPI-3 to SPI-4 buffer segment pool is divided into 508 buffersegments. Each buffer segment is equal to 256 bytes. The buffer segments areshared among the number of logical ports defined by the static NR_LIDconfiguration. The buffer segments do not have to be equally shared amongthe LIDs. One buffer segment corresponds to a data burst to be forwarded tothe SPI-4 egress interface.


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9.3.11 Block base 0x1600 registersThe SPI-4 ingress registers are at Block_base 0x1600.

SPI-4 ingress packet length configuration(Block_base 0x1600 + Register_offset 0x00-0x3F)TABLE 79 - SPI-4 INGRESS PACKET LENGTHCONFIGURATION (64 ENTRIES CONFIGURABLE)

Field Bits Length Initial ValueMIN_LENGTH 7:0 8 0x40Reserved 15:8 8 0x0MAX_LENGTH 29:16 14 0x5EEThere is oneset of 64 registers for SPI-4 ingress packet length configuration

associated with the SPI-3 interface. The register has read and write access. Theminimum and maximum packet lengths per LID are provisioned using the SPI-4 ingress packet length configuration register. The bit fields of a SPI-4 ingresspacket length configuration register are described.

MIN_LENGTH SPI-4 ingress minimum packet length. The minimumpacket length is programmed from 0 to 255 bytes. The resolution is one byte.

MAX_LENGTH SPI-4 ingress maximum packet length. The maximumpacket length is programmed from 0 to 16,383 bytes. The resolution is one byte.

9.3.12 Block base 0x1700 registersSPI-3 egress port descriptor table (Block_base0x1700 + Register_offset 0x00-0x3F)

There are 64 SPI-3 egress port descriptor tables for the SPI-3 egress port.The SPI-3 egress port descriptor table has read and write access. The SPI-3 egress per LID packet fragment length and direction are provisioned usingthe SPI-3 egress port descriptor tables. The bit fields of the SPI-3 egress portdescriptor table are described.

MAX_BURST SPI-3 packet fragment length for a SPI-3 egress LP. Onemore than MAX_BURST field multiplied by sixteen is the packet fragment lengthfor the LP. For example, programming the number 3 into the MAX_BURST fieldresults in a packet fragment length of (3+1) x 16 = 64 bytes. The MAX_BURSTfield is used to prioritize traffic.

DIRECTION The SPI-3 egress traffic is directed to a SPI-3 egress port.The Path selection is defined for each of the 64 LIDs by the associatedDIRECTION field as shown in the following table.

TABLE 80 - SPI-3 EGRESS PORT DESCRIPTORTABLE (64 ENTRIES)

Field Bits Length Initial ValueMAX_BURST 3:0 4 0x0FReserved 7:4 4 0x0DIRECTION 8:9 2 0b11Reserved 31:10 22 0x00

9.3.13 Block base 0x1800 registersSPI-4 ingress port descriptor table (Block_base0x1800 + Register_offset 0x00-0x3F)

There is one set of 64 registers for SPI-4 ingress port descriptors for the SPI-3 interface. The SPI-4 ingress port descriptor tables are 32 bits wide and haveread and write access. Each of the SPI-4 ingress port descriptor tables is usedto control the amount of buffering and the backpressure threshold of the availablebuffer segment pool for the SPI-4 ingress.

Each SPI-4 ingress buffer segment pool is 128 Kbytes, divided into 508 buffersegments of 256 bytes per segment. The 508 buffer segments can be sharedamong the LIDs initially programmed by the numerical field NR_LID. Of the shareof the buffer memory, a SPI-4 LID can be allocated the maximum number ofsegments permitted, or can be programmed to fewer segments by decreasingthe M field. Decreasing M increases the chance of backpressure and possiblybuffer overflow, but can result in lower latency.

The FREE_SEGMENT_S (starving threshold) and FREE_SEGMENT_H(hungry threshold) fields are used, along with the M field, to set the twobackpressure settings per LID on the SPI-4 ingress. The FREE_SEGMENT_Sfield must always be greater than the FREE_SEGMENT_H field.

M The number of 256-byte buffer pool segments allocated to a LID. Therange of M is 0x000 to 0x1FC (508 base 10), but can not exceed the numberdictated by NR_LID [Block_base 0x1900 + Register_offset 0x00].

FREE_SEGMENT_SThis field is used to define the SPI-4 ingress per-LID starving backpressure

threshold based on the number of free buffer pool segments (M) available, asfollows:

THRESHOLD_S = N * FREE_SEGEMENT_S, where the value of N isdefined as:

DIRECTION Path00 SPI-3 physical01 Reserved10 Capture11 Discard

TABLE 81 - SPI-3 EGRESS DIRECTION CODEASSIGNMENT

TABLE 82 - SPI-4 INGRESS PORT DESCRIPTORTABLES (64 ENTRIES)

Field Bits Length Initial ValueM 8:0 9 0x000Reserved 15:9 7 0x00FREE_SEGMENT_S 20:16 5 0x00Reserved 23:21 3 0x0FREE_SEGMENT_H 28:24 5 0x00Reserved 31:29 3 0x0

M[8:0] N0x1FF to 0x100 160x0FF to 0x080 80x07F to 0x040 40x03F to 0x020 20x01F to 0x000 1

FREE_SEGMENT_HThis field is used to define the SPI-4 ingress per-LID hungry backpressure

threshold based on the number of free buffer pool segments (M) available, asfollows:

THRESHOLD_H = N * FREE_SEGEMENT_H, where the value of N is asdefined for FREE_SEGEMENT_S.


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TABLE 83 - SPI-4 TO SPI-3 PFP REGISTER (0x00)Field Bits Length Initial Value

NR_LID 2:0 3 0b011Reserved 7:3 5 0x00

TABLE 84 - NR_LID FIELD ENCODING

NR_LID Maximum Number Maximum Buffer Segmentsof LIDs for a LID

0b000 1 5080b001 4 2560b010 8 1280b011 16 640b100 32 320b101 64 16

9.3.14 Block base 0x1900 registersSPI-4 to SPI-3 PFP register (Block_base 0x1900 +Register_Offset 0x00)

The SPI-4 ingress to SPI-3 egress Packet Fragment Processor registers areat Block_Base 0x1900 + Register_offset 0x00. A SPI-4 to SPI-3 PFP Registerhas read and write access. The bit fields of a SPI-4 to SPI-3 PFP Register aredescribed.

NR_LID The maximum number of LIDs for the SPI-3 physicalinterface that will ever be used is programmed into the NR_LID field. Onceconfigured after reset, this value can not be changed. Fewer LIDs can be usedby not activating some of the LIDs, but more LIDs than the value in NR_LID arenot allowed and will generate an error. The NR_LID field is important, as thebuffer segment pool is divided among the number of LIDs programmed into theNR_LID field.

The 128 Kbyte SPI-4 to SPI-3 buffer segment pool for storing packetfragments for the SPI-3 egress is available for the SPI-3 physical port. Aconfigurable part of the buffer segment pool can be assigned to each of the LIDs,as determined by the NR_LID value, for the SPI-3 physical interface. The buffersize (M) for a LID can be configured in multiples of 256 bytes. Modifications ofthe buffer size allocated to a LID are supported only when the logical portassociated to the LID is disabled. Attempts to allocate more memory thanavailable will generate an allocation error event. The indirect access modulewill discard the attempt.

The 128 Kbyte SPI-4 to SPI-3 buffer segment pool is divided into 508 buffersegments. Each buffer segment is equal to 256 bytes. The buffer segments areshared among the number of logical ports defined by the static NR_LIDconfiguration. The buffer segments do not have to be equally shared amongthe allocated LIDs. One buffer segment corresponds to a packet fragment to beforwarded to the SPI-3 egress physical interface.

An example of the use of the buffer segment pool follows. For a SPI-3 egressinterface that will never have more than eight LIDs, set the NR_LID field for thisinterface to 0x02. This allows 128 buffer segments for a LID with the total numberof buffer segments for all eight LIDs equal to 508.

Let’s say you want only 24 (base 10) buffer segments for one of the LIDs.Program field M for that LID to 0x018 (24 base 10). Let’s say you want to setthe per-LID starving backpressure for the SPI-4 ingress interface when 20 ofthe 24 allocated buffers for this LID are full. In other words, you want to assertSPI-4 ingress starving when only 4 segments remain for this LID. SinceM=0x018, N=1 from the description of the M field above [Block_base 0x1800].Setting the FREE_SEGMENT_S field to 4 then yields the desiredTHRESHOLD_S of 4. Similarly, to set the per-LID SPI-4 ingress hungrythreshold, THRESHOLD_H, to trip when only 6 buffer segments remain for thisLID, program the FREE_SEGMENT_H field for this LID to 6.


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Table Number, Page Block_base, Register_offset Title of Register

86, page 66 0x0000, 0x00-0xFF SPI-4 ingress LP to LID map

87, page 66 0x0100, 0x00-0xFF SPI-4 ingress calendar_0

88, page 66 0x0200, 0x00-0xFF SPI-4 ingress calendar_1

89, page 66 0x0300, 0x00 SPI-4 ingress configuration register

90, page 67 0x0300, 0x01 SPI-4 ingress status configuration register

91, page 67 0x0300, 0x02 SPI-4 ingress status register

92, page 67 0x0300, 0x03 SPI-4 ingress inactive transfer port

93, page 68 0x0300, 0x04-0x05 SPI-4 ingress calendar configuration register

94, page 68 0x0300, 0x06 SPI-4 ingress watermark register

95, page 68 0x0300, 0x07-0x0A SPI-4 ingress fill level register

96, page 68 0x0300, 0x0B-0x0E SPI-4 ingress max fill level register

97, page 68 0x0300, 0x0F SPI-4 ingress diagnostics register

98, page 69 0x0300, 0x10 SPI-4 ingress DIP-4 error counter

99, page 69 0x0300, 0x11 SPI-4 ingress bit alignment control register

100, page 69 0x0300, 0x12 SPI-4 ingress start up training threshold register

101, page 69 0x0400, 0x00-0xFF SPI-4 egress LID to LP map

102, page 69 0x0500, 0x00-0xFF SPI-4 egress calendar_0

103, page 70 0x0600, 0x00-0xFF SPI-4 egress calendar_1

104, page 70 0x0700, 0x00 SPI-4 egress configuration register_0

105, page 70 0x0700, 0x01 SPI-4 egress configuration register_1

106, page 71 0x0700, 0x02 SPI-4 egress status register

107, page 71 0x0700, 0x03-0x04 SPI-4 egress calendar configuration register

108, page 71 0x0700, 0x05 SPI-4 egress diagnostics register

109, page 71 0x0700, 0x06 SPI-4 egress DIP-2 error counter

110, page 72 0x0800, 0x00 SPI-4 ingress bit alignment window register

111, page 72 0x0800, 0x01 SPI-4 ingress lane measure register

112, page 72 0x0800, 0x02-0x0B SPI-4 ingress bit alignment counter register

113, page 72 0x0800, 0x0C-0x1F SPI-4 ingress manual alignment phase/result register

114, page 72 0x0800, 0x2A SPI-4 egress data lane timing register

115, page 73 0x0800, 0x2B SPI-4 egress control lane timing register

116, page 73 0x0800, 0x2C SPI-4 egress data clock timing register

117, page 73 0x0800, 0x2D SPI-4 egress status timing register

118, page 73 0x0800, 0x2E SPI-4 egress status clock timing register

119, page 74 0x0900, 0x00 PMON timebase control register

120, page 74 0x0900, 0x01 Timebase register

121, page 74 0x0900, 0x10 Clock generator control register

122, page 74 ———————- OCLK and MCLK frequency select encoding

123, page 75 0x0900, 0x20 GPIO register

124, page 75 0x0900, 0x21– 0x25 GPIO monitor table

125, page 75 0x0900, 0x30 Version number register

TABLE 85 -COMMON MODULE (MODULE_BASE0x8000) INDIRECT REGISTER TABLE

9.4 Common module indirect registers(Module_base 0x8000)


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TABLE 86 - SPI-4 INGRESS LP TO LID MAP(256 ENTRIES, ONE PER LP)

Field Bits Length Initial ValueLID 5:0 6 0x00PFP 7:6 2 0x0

ENABLE 8 1 0x0

9.4.1 Common module block base 0x0000 registersSPI-4 ingress LP to LID maps (Block_base 0x0000+ Register_offset 0x00 to 0xFF)

There are 256 SPI-4 ingress LP to LID maps for the SPI-4 ingress interfaceat Block_base 0x0000. The SPI-4 ingress LP to LID maps have read and writeaccess. The SPI-4 ingress LP to LID maps are used to map SPI-4 ingress logicalports to logical identifiers used internally.

Data for an inactive LP having an entry in the calendar is forwarded toLID0. Therefore all the LPs that have entries in the calendar tables should beenabled.

LID The LID programmed is associated to the LP with the same numberas the register address. Six bits support the 64 simultaneously active LIDs perSPI-3 physical interface.

PFP The PFP field is used to select among SPI-4 ingress to SPI-3 egressPacket Processing Engines. The number in the PFP field selects the PFPmodule to be used.

0x0=Select PFP Module A0x1=Reserved0x2=Reserved0x3=Reserved

ENABLE The Enable is used to enable or disable the connection of an LPto a LID.

0=LP is disabled1=LP is enabled

9.4.2 Common module block base 0x0100 registersSPI-4 ingress calendar_0 (Block_base 0x0100 +Register_offset 0x00 to 0xFF)TABLE 87 - SPI-4 INGRESS CALENDAR_0(256 ENTRIES)

Field Bits Length Initial ValueLP 7:0 8 0xFF

The SPI-4 ingress calendar_0 is at Block_base 0x0100 and has read andwrite access. When the SPI-4 ingress calendar_0 is selected, SPI-4 ingresscalendar_0 is in use. There are 256 entries in the SPI-4 ingress calendar_0to schedule the updating of the FIFO status channel LPs to the attached device.If less than the maximum 256 LPs are needed on the SPI-4 interface, thecalendar entries should be used for scheduling more frequent status updatesfor higher-speed LPs. The value of time-critical LPs must appear multiple timesin the table. For example, a multi-PHY SPI-4 could have OC-48 channelsappear in the calendar at four times the rate of OC-12 channels, since the higherdata rate of the OC-48 channels would benefit from more frequent FIFO statuschannel updates. The LP field values range from 0x00 to 0xFF. TheIDT88P8341 and the attached device must have identical calendars for ingressand the attached egress device. The ingress and egress calendars of theIDT88P8341 device do not have to match.

LP The LP value programmed schedules a status channel updateaccording to the calendar sequence.

9.4.3 Common module block base 0x0200 registersSPI-4 ingress calendar_1 (Block_base 0x0200 +Register_offset 0x00 to 0xFF)

TABLE 88 - SPI-4 INGRESS CALENDAR_1(256 ENTRIES)


The SPI-4 ingress calendar_1 is at Block_base 0x0200 and has read andwrite access. When the SPI-4 ingress calendar_1 is selected, SPI-4 ingresscalendar_1 is in use. There are 256 entries in the SPI-4 ingress calendar_1to schedule the updating of the FIFO status channel LPs to the attached device.If less than the maximum 256 LPs are needed on the SPI-4 interface, thecalendar entries should be used for scheduling more frequent status updatesfor higher-speed LPs. The value of time-critical LPs must appear multiple timesin the table. For example, a multi-PHY SPI-4 could have OC-48 channelsappear in the calendar at four times the rate of OC-12 channels, since the higherdata rate of the OC-48 channels would benefit from more frequent FIFO statuschannel updates. The LP field values range from 0x00 to 0xFF. TheIDT88P8341 and the attached device must have identical calendars for ingressand the attached egress device. The ingress and egress of the IDT88P8341do not have to match, however.


9.4.4 Common module block base 0x0300 registersSPI-4 ingress configuration register (Block_base0x0300 + Register_offset 0x00)

TABLE 89 - SPI-4 INGRESS CONFIGURATIONREGISTER (0x00)

Field Bits Length Initial ValueSPI-4_EN 0 1 0b0Reserved 1 1 0x0Reserved 2 1 0x0I_CLK_EDGE 3 1 0x0I_DSC 4 1 0x0I_INSYNC_THR 9:5 5 0x1FI_OUTSYNC_THR 13:10 4 0xFI_CSW_EN 14 1 0x0CAL_SEL 15 1 0x0I_LOW 16 1 0b1

The SPI-4 ingress configuration register is at Block_base 0x0300 and hasread and write access.

The SPI-4 ingress configuration register is used to set the state of the SPI-4 ingress interface. The bit fields of the SPI-4 ingress configuration register aredescribed.






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SPI-4_EN The SPI-4 ingress path is enabled using this field. The SPI-4path is disabled during reset and while configuring the port, and then is enabledfor normal use.

0=SPI-4 ingress is disabled1= SPI-4 ingress is enabled

I_CLK_EDGE The SPI-4 ingress LVTTL clock active clock edge isselected using the I_CLK_EDGE field.

0=SPI-4 ingress clock uses the rising edge1= SPI-4 ingress clock uses the falling edge

I_DSC The I_DSC bit is used to protect against a random data errorduring de-skew.

0= One de-skew result is needed for data de-skew1= Two consecutive de-skew results are needed for data de-skew

(recommended setting)

I_INSYNC_THR The SPI-4 ingress DIP-4 in synchronization thresholdis controlled using the I_INSYNC_THR field. It is recommended to use the initialvalue.

I_OUTSYNC_THR The SPI-4 ingress DIP-4 out-of synchronizationthreshold is controlled using the I_OUTSYNC_THR field. It is recommended touse the initial value.

I_CSW_EN The ingress calendar switch enable bit is used to enable theswitching of the active calendars. It is recommended to use the initial value.

0=Ingress calendar switch disabled. Only SPI-4 ingress calendar_0is used.1=Ingress calendar switch enabled. Calendar_0 or calendar_1 canbe used.

CAL_SEL The calendar select bit selects between SPI-4 ingresscalendar_0 and SPI-4 ingress calendar_1. The CAL_SEL bit is only valid if theI_CSW_EN bit is set to a logic one.

0=SPI-4 ingress calendar_0 is selected1=SPI-4 ingress calendar_1 is selected if the I_CSW_EN bit is set toa logic one

I_LOW The I_LOW field selects the SPI-4 ingress clock frequency range.0=SPI-4 ingress clock is greater than or equal to 200 MHz1=SPI-4 ingress clock is less than 200 MHz

SPI-4 ingress status configuration register(Block_base 0x0300 + Register_offset 0x01)

FIFO_MAX_T The SPI-4 ingress FIFO_MAX_T field is the maximum timeinterval between scheduling of training sequences on the FIFO status pathinterface. The units are the number of times the calendar is sent beforescheduling the training sequence.

ALPHA_FIFO The SPI-4 ingress ALPHA_FIFO field is the number ofrepetitions of the status training sequence that must be scheduled everyFIFO_MAX_T cycles. The value for alpha used is actually one more than theALPHA_FIFO value programmed into the ALPHA_FIFO field.

SPI-4 ingress status register (Block_base 0x0300 +Register_offset 0x02)

TABLE 90 - SPI-4 INGRESS STATUS CONFIGURA-TION REGISTER (REGISTER_OFFSET 0x01)

Field Bits Length Initial ValueFIFO_MAX_T 23:0 24 0ALPHA_FIFO 31:24 8 0

The SPI-4 ingress status configuration register is at Block_base 0x0300 andhas read and write access.

The SPI-4 ingress status configuration register is used to set the state of theSPI-4 ingress FIFO status path interface. The bit fields of the SPI-4 ingress statusconfiguration register are described.

TABLE 91 - SPI-4 INGRESS STATUS REGISTER(REGISTER_OFFSET 0x02)

Field Bits Length Initial ValueI_SYNCH 0 1 0I_DSK_OOR 1 1 0DCLK_AV 2 1 0

The SPI-4 ingress status register is at Block_base 0x0300 and has read-onlyaccess.

The SPI-4 ingress status register is used to set the state of the SPI-4 ingresssynchronization.

The bit fields of the SPI-4 ingress status register are described.

I_SYNCH The SPI-4 ingress I_SYNCH field describes the synchroniza-tion state of the SPI-4 ingress data path.

0=SPI-4 ingress data path is out of synchronization1=SPI-4 ingress data path is in synchronization

I_DSK_OOR The SPI-4 ingress I_DSK_OOR field describes the de-skewstate of the SPI-4 ingress data path.

0=SPI-4 ingress data path de-skew is within range1= SPI-4 ingress data path de-skew is out of range

DCLK_AV The SPI-4 ingress DCLK_AV field describes the availabilitystate of the SPI-4 ingress clock.

0=SPI-4 ingress clock is not available1= SPI-4 ingress clock is available

SPI-4 ingress inactive transfer port (Block_base0x0300 + Register_offset 0x03)TABLE 92 - SPI-4 INGRESS INACTIVE TRANSFERPORT (REGISTER_OFFSET 0x03)

Field Bits Length Initial ValueINACT_LP 7:0 8 0

The SPI-4 ingress inactive transfer port is at Block_base 0x0300 and hasread-only access.

The SPI-4 ingress inactive transfer port INACT_LP field is used to monitorthe LP associated with the latest inactive transfer. The INACT_LP field canchange at any time and is used for diagnostics only.

INACT_LP The SPI-4 ingress INACT_LP field contains the numeric valueof the LP associated with the last inactive LP transfer, used for diagnostics only.


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SPI-4 ingress calendar configuration register(Block_base 0x0300 + Register_offset 0x04 - 0x05)

TABLE 93 - SPI-4 INGRESS CALENDAR CONFIGU-RATION REGISTER (0x04 to 0x05)

Field Bits Length Initial ValueI_CAL_M 7:0 8 0I_CAL_LEN 13:8 6 0x01

The SPI-4 ingress calendar configuration registers are at Block_base0x0300 and have read and write access. The Register_offset for calendar_0is 0x04. The Register_offset for calendar_1 is 0x05.

The bit fields of a SPI-4 ingress calendar configuration register are described.Some devices have a fixed calendar length and a fixed calendar M, while

the Bridgeport calendar length has to be multiply of 4, and the calendar M isprogrammable. Therefore, the user may need to add an FPGA between theBridgeport & the adjacent device SPI-4 status signals.

I_CAL_M The I_CAL_M value programmed defines the number of timesthe calendar sequence is repeated before a DIP-2 parity and “1 1” framingwords are inserted. The actual calendar_M value used is one more than thevalue programmed into the I_CAL_M field.

I_CAL_LEN The I_CAL_LEN value programmed defines the length ofthe SPI-4 ingress calendar. The actual length of the calendar is four times thevalue of one more than the I_CAL_LEN field: (I_CAL_LEN + 1)*4. For example,if the I_CAL_LEN field is programmed to 0x04, the actual value used is 0x14.The calendar length must be at least as large as the number of active SPI-4ingress LPs.

SPI-4 ingress watermark register (Block_base0x0300 + Register_offset 0x06)

SPI-4 ingress fill level register (Block_base 0x0300+ Register_offset 0x07)

TABLE 94 � SPI-4 INGRESS WATERMARK REGIS-TER (REGISTER_OFFSET 0x06)

Field Bits Length Initial Value FunctionWATERMARK 4:0 5 0x0D Watermark for PFP AReserved 7:5 3 0Reserved 12:6 5 0x0Dreserved 15:13 3 0Reserved 20:16 5 0x0DReserved 23:21 3 0Reserved 28:24 5 0x0DReserved 31:29 3 0

SPI-4 ingress Watermark Register is at Block_base 0x0300, Register_offset0x06. The SPI-4 ingress Watermark Register has read and write access. A SPI-4 interface can be set to a Watermark Value per PFP. 0x1F is the highestwatermark that can be set, meaning all ingress buffers will be full beforebackpressure will be initiated on a SPI-4 ingress interface PFP. A WATER-MARK field value of 0x0F is used to set a watermark for a half-full ingress bufferbefore tripping backpressure. The units of WATERMARK are one-thirty-second of the available ingress buffering per unit. Each unit is equal to 128 bytes.

TABLE 95 - SPI-4 INGRESS FILL LEVEL REGISTER(REGISTER_OFFSET 0x07)

Field Bits Length Initial ValueFILL_CUR 5:0 6 0x0

TABLE 96 - SPI-4 INGRESS MAX FILL LEVELREGISTER (REGISTER_OFFSET 0x0B)


There is one register for SPI-4 ingress max fill level register for the SPI-3interface at Block_base 0x0300. The register has read-only access, and iscleared after reading. 0x20 is the highest filling level, meaning all ingress bufferson a PFP had been full at some time since the last read of the FILL_MAX field.The units of FILL_MAX are one-thirty-second of the available ingress bufferingper PFP. Each unit is equal to 128 bytes.

The bit field of a SPI-4 ingress max fill level register is described.

FILL_MAX Maximum SPI-4 ingress buffer fill level since the last read of theSPI-4 ingress max fill level register.

SPI-4 ingress diagnostics register (Block_base0x0300 + Register_offset 0x0F)TABLE 97 - SPI-4 INGRESS DIAGNOSTICS REGIS-TER (REGISTER_OFFSET 0x0F)

Field Bits Length Initial ValueI_FORCE_TRAIN 0 1 0I_ERR_INS 1 1 0I_DIP_NUM 5:2 4 0

The SPI-4 ingress Diagnostics Register is addressed from Block_base0x0300 + Register_offset 0x0F. The SPI-4 ingress Diagnostics Register hasread and write access. The SPI-4 ingress Diagnostics Register is used in portdiagnostics to force continuous training on the SPI-4 ingress status interface,insert a DIP-2 error on the SPI-4 ingress status interface, and read the numberof DIP-2 errors seen on the SPI-4 egress status interface.

There is one register for SPI-4 ingress fill level register for the SPI-3 interfaceat Block_base 0x0300. The register has read-only access.

The bit fields of a SPI-4 ingress fill level register are described.

FILL_CUR Current SPI-4 ingress buffer fill level. Since this is a real-timeregister, the value read from it will change rapidly and is used for internaldiagnostics only.

SPI-4 ingress max fill level register (Block_base0x0300 + Register_offset 0x0B)


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I_FORCE_TRAIN The I_FORCE_TRAIN field is used to force continu-ous training on the SPI-4 ingress status interface.

0=Normal status channel operation1=Force continuous training on the SPI-4 ingress status interface

I_ERR_INS The I_ERR_INS field is used to insert the number of DIP-2 errors on the SPI-4 ingress status interface programmed into the I_DIP_NUMfield. After the DIP-2 errors are inserted, the I_ERR_INS field will clear itself.

0=Normal status channel operation1= Insert DIP-2 errors on the SPI-4 ingress status interface

I_DIP_NUMThe I_DIP_NUM field is used to create the number of DIP-2 errors

programmed into the I_DIP_NUM field on the SPI-4 egress status interface..

SPI-4 ingress DIP-4 error counter (Block_base0x0300 + Register_offset 0x10)

TABLE 98 - SPI-4 INGRESS DIP-4 ERRORCOUNTER (REGISTER_OFFSET 0x10)

Field Bits Length Initial ValueDIP_4 15:0 16 0

The SPI-4 ingress DIP-4 error counter is addressed from Block_base0x0300 + Register_offset 0x10. The SPI-4 ingress DIP-4 error counter hasread access, and automatically clears itself after a read. The SPI-4 ingress DIP-4 error counter is used in port diagnostics to verify the integrity of the SPI-4ingress data path.

DIP_4 The DIP_4 field is used to read the number of DIP-4 errors seen onthe SPI-4 egress status interface. The DIP_4 field saturates at the value0xFFFF, and is automatically cleared after reading to re-start DIP-4 errorcounter accumulation.

SPI-4 ingress bit alignment control register(Block_base 0x0300 + Register_offset 0x11)TABLE 99 - SPI-4 INGRESS BIT ALIGNMENTCONTROL REGISTER (REGISTER_OFFSET 0x11)

Field Bits Length Initial ValueFORCE 0 1 0

The SPI-4 ingress bit alignment control register is addressed from Block_base0x0300 + Register_offset 0x11. The SPI-4 ingress bit alignment control registerhas read and write access. The SPI-4 ingress bit alignment control register isused to overrule the automatically selected bit phase alignments and go tomanual mode. In manual mode, the PHASE_ASSIGN field [Block_base 0x0800+ Register_offset 0x0c – 0x1F] now defines the selected phase.

FORCE The FORCE field is used to manually align the SPI-4 ingress data.0=Normal bit alignment operation 1= Force to manual bit alignment mode on SPI-4 ingress data usingthe PHASE_ASSIGN field.

SPI-4 ingress start up training threshold register(Block_base 0x0300 + Register_offset 0x12)

TABLE 101 - SPI-4 EGRESS LID TO LP MAP(256 ENTRIES)

Field Bits Length Initial ValueLP 7:0 8 0x00EN 8 1 0b0

There are 64 entries in the SPI-4 egress LID to LP map for the SPI-4 ingressinterface. The entries are at Block_base 0x0400 + LID. For example, LID 0x00is at Block_base 0x0400 + 0x00. A SPI-4 egress LID to LP map has read andwrite access. A SPI-4 egress LID to LP map is used to map a logical identifierused internally to a SPI-4 egress logical port.

Data for an inactive LP having an entry in the calendar is forwarded toLID0. Therefore all the LPs that have entries in the calendar tables should beenabled.

LP The LP programmed is associated to the LID with the same number asthe register address. Eight bits support the 256 possible LPs on the SPI-4physical interface. Only 64 LPs are supported in the IDT88P8341 device.

EN The EN bit is used to enable or disable the connection of a LID to an LP.0=LP is disabled1=LP is enabled

9.4.6 Common module block base 0x0500 registersSPI-4 egress calendar_0 (Block_base 0x0500 +Register_offset 0x00 – 0xFF)TABLE 102 - SPI-4 EGRESS CALENDAR_0(256 LOCATIONS)


The SPI-4 egress calendar_0 is at Block_base 0x0500 and has read andwrite access. When the SPI-4 egress calendar_0 is selected, calendar_0 isin use. There are 256 entries in the SPI-4 egress calendar_0 to schedule theupdating of the FIFO status channel LPs to the attached device. If less than themaximum 256 LPs are needed on the SPI-4 interface, the calendar entriesshould be used for scheduling more frequent status updated for higher-speedLPs. The value of time-critical LPs must appear multiple times in the table. Forexample, a multi-PHY SPI-4 could have OC-48 channels appear in thecalendar at four times the rate of OC-12 channels, since the higher data rateof the OC-48 channels would benefit from more frequent FIFO status channelupdates. The LP field values range from 0x00 to 0xFF. The IDT88P8341 andthe attached devices must have identical calendars.

The SPI-4 ingress start up training threshold register is addressed fromBlock_base 0x0300 + Register_offset 0x12. The SPI-4 ingress start up trainingthreshold register has read and write access. The SPI-4 ingress start up trainingthreshold register is used to set the number of consecutive training patterns thatwill lead to OUT_OF_SYNCH on the SPI-4 ingress data. If the STRT_TRAINfield is set to zero, then the OUT_OF_SYNCH feature is disabled.

STRT_TRAIN The STRT_TRAIN field is used to set the number ofconsecutive training patterns that will lead to OUT_OF_SYNCH on the SPI-4ingress data interface.

9.4.5 Common module block base 0x0400 registersSPI-4 egress LID to LP map (Block_base 0x0400 +Register_offset 0x00 - 0x3F)

TABLE 100 - SPI-4 INGRESS START UP TRAININGTHRESHOLD REGISTER (REGISTER_OFFSET 0x12)

Field Bits Length Initial ValueSTRT_TRAIN 7:0 8 0




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9.4.7 Common module block base 0x0600 registersSPI-4 egress calendar_1 (Block_base 0x0600 +Register_offset 0x00 – 0xFF)

TABLE 103 - SPI-4 EGRESS CALENDAR_1(256 LOCATIONS)


The SPI-4 egress calendar_1 is at Block_base 0x0600 and had read andwrite access. When the SPI-4 egress calendar_1 is selected, calendar_1 is inuse. There are 256 entries in the SPI-4 egress calendar_1 to schedule theupdating of the FIFO status channel LPs to the attached device. If less than themaximum 256 LPs are needed on the SPI-4 interface, the calendar entriesshould be used for scheduling more frequent status updated for higher-speedLPs. The value of time-critical LPs must appear multiple times in the table. Forexample, a multi-PHY SPI-4 could have OC-48 channels appear in thecalendar at four times the rate of OC-12 channels, since the higher data rate ofthe OC-48 channels would benefit from more frequent FIFO status channelupdates. The LP field values range from 0x00 to 0xFF. The IDT88P8341 andthe attached devices must have identical calendars.


9.4.8 Common module block base 0x0700 registersSPI-4 egress configuration register_0 (Block_base0x0700 + Register_offset 0x00)

The SPI-4 egress configuration register_0 is at Block_base 0x0700 and hasread and write access.

The SPI-4 egress configuration register_0 is used to set the state of the SPI-4 egress interface. The bit fields of the SPI-4 egress configuration register_0 aredescribed.

E_CLK_EDGE The SPI-4 egress clock active clock edge is selected usingthe E_CLK_EDGE field.

0=SPI-4 egress clock uses the rising clock edge1=SPI-4 egress clock uses the falling clock edge

TABLE 104 � SPI-4 EGRESS CONFIGURATIONREGISTER_0 (REGISTER_OFFSET 0x00)

Field Bits Length Initial ValueReserved 2:0 3 0E_CLK_EDGE 3 1 0E_DSC 4 1 0E_INSYNC_THR 9:5 5 0x1FE_OUTSYNC_THR 13:10 4 0xFE_CSW_EN 14 1 0Reserved 15 1 0E_LOW 16 1 1NOSTAT 17 1 0

E_DSC The E_DSC bit enables or disables de-skewing of the SPI-4egress data lines.

0=Data de-skewing is disabled1=Data de-skewing is enabled (recommended setting)

E_INSYNC_THR The SPI-4 egress DIP-2 in-synchronization thresh-old is controlled using the E_INSYNC_THR field. It is recommended to use theinitial value.

E_OUTSYNC_THR The SPI-4 egress DIP-2 out-of-synchronizationthreshold is controlled using the E_OUTSYNC_THR field. It is recommendedto use the initial value.

E_CSW_EN The ingress calendar switch enable bit is used to enablethe switching of the active calendars following the reception of the calendarselection word on the status channel. It is recommended to use the initial value.

0=Egress calendar switch is disabled. Only SPI-4 egress calen-dar_0 is used.1=Egress calendar switch is enabled. Calendar_0 or calendar_1will be used.

E_LOW The E_LOW field selects the SPI-4 egress clock frequencyrange.

0=SPI-4 egress clock is greater than or equal to 200 MHz1=SPI-4 egress clock is less than 200 MHz

NOSTAT The NOSTAT bit enables the no status channel option. OnceNOSTAT is set, the status channel is ignored. There is no DIP-2 error checking,and no status channel updating. The received status is fixed to starving. Thedata channel is put into the IN_SYNCH state.

0=Normal status channel operation1=No status channel option is selected

SPI-4 egress configuration register_1 (Block_base0x0700 + Register_offset 0x01)TABLE 105 - SPI-4 EGRESS CONFIGURATIONREGISTER_1 (REGISTER_OFFSET 0x01)

Field Bits Length Initial ValueDATA_MAX_T 23:0 24 0ALPHA 31:24 8 0

The SPI-4 egress configuration register_1 is at Block_base 0x0700 and hasread and write access.

The SPI-4 egress configuration register_1 is used to set the state of the SPI-4 egress FIFO status path interface. The bit fields of the SPI-4 egressconfiguration register_1 are described.

DATA_MAX_T The SPI-4 egress DATA_MAX_T field is the maximumtime interval between scheduling of training sequences on the egress data pathinterface. The purpose of the data training interval is to allow the de-skewingof plus or minus one bit time on the egress data interface if needed. The time isset for the DATA_MAX_T field multiplied by 128 cycles.

ALPHA The SPI-4 egress ALPHA field is the number of repetitions of thedata training sequence that must be scheduled every DATA_MAX_T cycles.The value for alpha used is actually one more than the ALPHA valueprogrammed into the ALPHA field.



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SPI-4 egress status register (Block_base 0x0700 +Register_offset 0x02)

E_CAL_LEN The E_CAL_LEN value programmed defines the length ofthe SPI-4 egress calendar. The actual length of the calendar is four times onemore than the value programmed into the E_CAL_LEN field. For example, ifthe E_CAL_LEN field is programmed to 0x3F, the actual value used is 0x100.The calendar length must be at least as large as the number of active SPI-4egress LPs.

SPI-4 egress diagnostics register (Block_base0x0700 + Register_offset 0x05)

TABLE 106 - SPI-4 EGRESS STATUS REGISTER(REGISTER_OFFSET 0x02)

Field Bits Length Initial ValueE_SYNCH 0 1 0E_DSK_OOR 1 1 0SCLK_AV 2 1 0

SPI-4 egress status registerThe SPI-4 egress status register is at Block_base 0x0700 and has read-only

access.The SPI-4 egress status register is used to set the state of the SPI-4 egress

synchronization.The bit fields of the SPI-4 egress status register are described.

E_SYNCH The SPI-4 egress E_SYNCH field describes the synchro-nization state of the SPI-4 egress data path.

0=SPI-4 egress data path is out of synchronization1=SPI-4 egress data path is in synchronization

E_DSK_OOR The SPI-4 egress E_DSK_OOR field describes the de-skew state of the SPI-4 egress data path.

0=SPI-4 egress data path de-skew is within range1=SPI-4 egress data path de-skew is out of range

SCLK_AV The SPI-4 egress SCLK_AV field describes the availabilitystate of the SPI-4 egress status channel clock. This function is not available ifSCLK < 0.5 MCLK.

0=SPI-4 egress status channel clock is not available1=SPI-4 egress status channel clock is available

SPI-4 egress calendar configuration register(Block_base 0x0700 + Register_offset 0x03 - 0x04)

TABLE 107 - SPI-4 EGRESS CALENDAR CONFIGU-RATION REGISTER (REGISTER_OFFSET 0x03 -0x04)

Field Acc Bits Length InitialValue

E_CAL_M RW 7:0 8 0E_CAL_LEN RW 13:8 6 0x01

The SPI-4 egress calendar configuration registers are at Block_base0x0300 and has read and write access. The Register_offset for calendar_0 is0x03. The register offset for calendar_1 is 0x04.

The bit fields of the SPI-4 egress calendar configuration register aredescribed.

The IDT88P8341 calendar length can be programmed to any multiple of 4using suitable values for the calendar entries, calendar length and calendarM. If the adjacent device is unable to configure its calendar to be a multiple of4, conversion logic may be needed between the adjacent device SPI-4status signals and the 88P8341 signals.

E_CAL_M The E_CAL_M value programmed defines the number oftimes the calendar sequence is repeated before a DIP-2 parity and “1 1” framingwords are inserted. The actual calendar_M value used is one more than thevalue programmed into the E_CAL_M field.

Field Bits Length InitialValue

E_FORCE_TRAIN 0 1 0E_ERR_INS 1 1 0E_DIP_NUM 5:2 4 0BIT_DELAY 7:6 2 0

The SPI-4 egress diagnostics register is addressed from Block_base 0x0700+ Register_offset 0x05. The SPI-4 egress diagnostics register has read andwrite access.

E_FORCE_TRAIN The E_FORCE_TRAIN field is used to force continu-ous training on the SPI-4 egress status interface.

0=Normal status channel operation1=Force continuous training on the SPI-4 egress status interface

E_ERR_INS The E_ERR_INS field is used to insert the number of DIP-4 errors on the SPI-4 egress data interface that have been programmed intothe E_DIP_NUM field. After the DIP-4 errors are inserted, the E_ERR_INS fieldwill clear itself.

0=Normal status channel operation1= Insert DIP-4 errors on the SPI-4 egress data interface

E_DIP_NUM The E_DIP_NUM field is used to create DPI-4 errors on theSPI-4 egress data interface. The number of errors generated is equal to thevalue of the E_DIP_NUM field.

BIT_DELAY The BIT_DELAY field is used to delay SPI-4 egress data bitline 0 by the number of bits programmed into the BIT_DELAY field. This maybe used for diagnostics.

SPI-4 egress DIP-2 error counter (Block_base0x0700 + Register_offset 0x06)

TABLE 109 - SPI-4 EGRESS DIP-2 ERRORCOUNTER (REGISTER_OFFSET 0x06)

Field Bits Length Initial ValueDIP_2 15:0 16 0

The SPI-4 egress DIP-2 error counter is addressed from Block_base0x0700 + Register_offset 0x06. The SPI-2 egress DIP-2 error counter has readaccess, and automatically clears itself after a read. The SPI-4 egress DIP-2 errorcounter is used in port diagnostics to verify the integrity of the SPI-4 egress statuschannel.

DIP_2 The DIP_2 field is used to read the number of DIP-2 errors seen onthe SPI-4 egress status interface. The DIP_2 field saturates at the value

TABLE 108 - SPI-4 EGRESS DIAGNOSTICS REGIS-TER (REGISTER_OFFSET 0x05)




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0xFFFF, and is automatically cleared after reading to re-start DIP-2 errorcounter accumulation.

9.4.9 Common module block base 0x0800 registersSPI-4 ingress bit alignment window register(Block_base 0x0800 + Register_offset 0x00)

The SPI-4 ingress bit alignment window register is addressed from Block_base0x0800 + Register_offset 0x00. The SPI-4 ingress bit alignment window registerhas read and write access. The SPI-4 ingress bit alignment window register isused in manual bit alignment procedures and it is recommended to leave theW field at its initial value.

W The W field is used to set the width of the SPI-4 ingress window bysetting the time between bit alignment operations. The initial value gives onemillion cycles per bit alignment adjustment opportunity.

SPI-4 ingress lane measure register (Block_base0x0800 + Register_offset 0x01)

The SPI-4 ingress lane measure register is addressed from Block_base0x0800 + Register_offset 0x01. The SPI-4 ingress lane measure register hasread and write access. SPI-4 ingress lane measure register is used in manualbit alignment procedures and it is recommended to leave the SPI-4 ingress lanemeasure register at its initial value.

LANE The LANE field is used to manually control the measurement of SPI-4 ingress data lane alignment. The LANE field is intended for diagnostics onlyand is not needed in normal operation.

0=DATA0 lane selected for measurementx=DATAx lane selected for measurement15=DATA15 lane selected for measurement16=CTL selected for measurement17=Egress status 0 selected for measurement18=Egress status 1 selected for measurement19=Chip test feature not available for diagnostics

MEASURE_BUSY The MEASURE_BUSY field is used to observewhen the LANE process is busy for manual lane assignment procedures. TheMEASURE_BUSY field is intended for diagnostics only and is not needed fornormal operation.

0=Normal operation1=Lane process is busy

SPI-4 ingress bit alignment counter register(Block_base 0x0800 + Register_offset 0x02 – 0x0B)

The SPI-4 ingress bit alignment counter registers at Block_base 0x0800 areread-only and contains the values of the bit alignment counters used for manuallane alignment . The registers are intended for diagnostics only and are not needed innormal operation.

SPI-4 ingress manual alignment phase/resultregister (Block_base 0x0800 + Register_offset0x0C – 0x1F)

TABLE 110 - SPI-4 INGRESS BIT ALIGNMENTWINDOW REGISTER (REGISTER_OFFSET 0x00)

Field Bits Length Initial ValueLANE 4:0 5 0Reserved 7:5 3 0MEASURE_BUSY 8 1 0

TABLE 111 - SPI-4 INGRESS LANE MEASUREREGISTER (REGISTER_OFFSET 0x01)

Field Bits Length Initial ValueW 15:0 16 0xFFFF

TABLE 112 - SPI-4 INGRESS BIT ALIGNMENTCOUNTER REGISTER (0x02 to 0x0B)

Field Bits Length Initial ValueC[n] 9:0 10 0

TABLE 113 - SPI-4 INGRESS MANUAL ALIGNMENTPHASE/RESULT REGISTER (0x0C to 0x1F)

Field Bits Length Initial ValueDTC0[1:0] 1:0 2 0DTC1[1:0] 3:2 2 0… .. 2 0DTC15[1:0] 31:30 2 0

TABLE 114 - SPI -4 EGRESS DATA LANE TIMINGREGISTER (REGISTER_OFFSET 0x2A)

Field Bits Length Initial ValuePHASE_ASSIGN 7:0 8 0

The SPI-4 ingress manual alignment phase/result registers at Block_base0x0800 have read and write access. A SPI-4 ingress manual alignment phase/result register is used to manually align the phase of the data lane, control lane,status lanes, and a test lane corresponding to its register in turn and is intendedfor diagnostics only and is not needed in normal operation. If the FORCE fieldof Table 99, SPI-4 ingress bit alignment control register (register_offset 0x11)is set to a logic one, manual phase alignment is enabled. If the FORCE field isset to a logic zero, normal automatic phase alignment is enabled, and the resultcan be viewed here. There are five center taps to choose from, plus two guardtaps on either side of the center, per data bit sampled. The oldest data sampleis at tap 8 ("right"), while the newest data sample is at tap 0 ("left"). Taps 0 and1 are the left margin taps for tracking purposes, while taps 7 and 8 are the rightmargin taps. A tap between 2 to 7 is initially selected in automatic mode. SeeFigure 7-Data sampling diagram. Register 0x0C is used for lane DATA0.

PHASE_ASSIGN [3:0]Used for selecting the bit phase corresponding to the rising clock edge of

I_DCLK. The four bits number the phases from 0 to 8, relative to the positively-clocked bit.

PHASE_ASSIGN [7:4]Used for selecting the bit phase corresponding to the falling clock edge of

I_DCLK. The four bits number the phases from 0 to 8, relative to the negatively-clocked bit.

SPI-4 egress data lane timing register (Block_base0x0800 + Register_offset 0x2A)

The SPI-4 egress data lane timing register at Block_base 0x0800 +Register_offset 0x2A has read and write access. The SPI-4 egress data lanetiming register is used to manually align the phase of data lane n by adding from0.1 clock cycle to 0.3 clock cycles of delay.


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TABLE 115 - SPI-4 EGRESS CONTROL LANETIMING REGISTER (REGISTER_OFFSET 0x2B)

Field Bits Length Initial ValueCTLTC[1:0] 1:0 2 0

TABLE 116 - SPI-4 EGRESS DATA CLOCK TIMINGREGISTER (REGISTER_OFFSET 0x2C)

Field Bits Length Initial ValueDCTC[3:0] 3:0 4 0

TABLE 117 - SPI-4 EGRESS STATUS TIMINGREGISTER (REGISTER_OFFSET 0x2D)

Field Bits Length Initial ValueSTC0[1:0] 1:0 2 0STC1[1:0] 3:2 2 0

TABLE 118 - SPI-4 EGRESS STATUS CLOCK TIM-ING REGISTER (REGISTER_OFFSET 0x2E)

Field Bits Length Initial ValueSCTC[3:0] 3:0 4 0

DTCn [1:0] Used for adding 0.1 clock cycles of output delay to SPI-4 egress data lane n.

[1:0]=0=No added delay[1:0]=1=Add 0.1 clock cycle of delay to data lane n

[1:0]=2=Add 0.2 clock cycles of delay to data lane n[1:0]=3=Add 0.3 clock cycles of delay to data lane n

SPI-4 egress control lane timing register(Block_base 0x0800 + Register_offset 0x2B)

SPI-4 egress status timing register (Block_base0x0800 + Register_offset 0x2D)

The SPI-4 egress control lane timing register at Block_base 0x0800 has readand write access. The SPI-4 egress controllane timing register is used tomanually align the phase of the control lane by adding from 0.1 clock cycle to0.3 clock cycles of delay.

CTLTC [1:0] Used for adding 0.1 clock cycles of output delay to the SPI-4 egress control output.

[1:0]=0=No added delay[1:0]=1=Add 0.1 clock cycle of delay to the control output[1:0]=2=Add 0.2 clock cycles of delay to the control output[1:0]=3=Add 0.3 clock cycles of delay to the control output

SPI-4 egress data clock timing register(Block_base 0x0800 + Register_offset 0x2C)

The SPI-4 egress data clock timing control register at Block_base 0x0800has read and write access. The SPI-4 egress data clock timing control registeris used to manually align the phase of the SPI-4 egress data clock to the dataand control lanes by adding from 0.1 clock cycle to 0.9 clock cycles of delay tothe data clock. Note that tap selection is not monotonic with the number in bit field[3:0].

DCTC [3:0] Used for adding 0.1clock cycles of output delay to the SPI-4 egress data clock.

[3:0]=0=No added delay[3:0]=1=Add 0.1 clock cycle of delay to the SPI-4 egress data clock[3:0]=3=Add 0.2 clock cycles of delay to the SPI-4 egress data clock[3:0]=2=Add 0.3 clock cycles of delay to the SPI-4 egress data clock[3:0]=7=Add 0.4 clock cycles of delay to the SPI-4 egress data clock[3:0]=6=Add 0.5 clock cycles of delay to the SPI-4 egress data clock[3:0]=4=Add 0.6 clock cycles of delay to the SPI-4 egress data clock[3:0]=5=Add 0.7 clock cycles of delay to the SPI-4 egress data clock[3:0]=F=Add 0.8 clock cycles of delay to the SPI-4 egress data clock[3:0]=E=Add 0.9 clock cycles of delay to the SPI-4 egress data clock

The SPI-4 egress status timing register at Block_base 0x0800 + Register_offset0x2D has read and write access. The SPI-4 egress status timing register is usedto manually align the phase of the status lane n by adding from 0.1 clock cycleto 0.3 clock cycles of delay. The STC0[1:0] and STC1[1:0] fields are valid onlyfor LVDS status, not for LVTTL status.

STCn [1:0] Used for adding 0.1 clock cycles of output delay to SPI-4 egress status lane n.

[1:0]=0=No added delay[1:0]=1=Add 0.1 clock cycle of delay to status lane n[1:0]=2=Add 0.2 clock cycles of delay to status lane n[1:0]=3=Add 0.3 clock cycles of delay to status lane n

SPI-4 egress status clock timing register(Block_base 0x0800 + Register_offset 0x2E)

The SPI-4 egress status clock timing register at Block_base 0x0800 +Register_offset 0x2E has read and write access. The SPI-4 egress status clocktiming register is used to manually align the phase of the SPI-4 egress status clockto the status outputs by adding from 0.1 clock cycle to 0.9 clock cycles of delayto the status clock output. Note that tap selection is not monotonic with the numberin bit field [3:0].

SCTC [3:0] Used for adding 0.1 clock cycles of output delay to the SPI-4 egress status clock output.

[3:0]=0=No added delay[3:0]=1=Add 0.1 clock cycle of delay to the SPI-4 egress status clock[3:0]=3=Add 0.2 clock cycles of delay to the SPI-4 egress status clock[3:0]=2=Add 0.3 clock cycles of delay to the SPI-4 egress status clock[3:0]=7=Add 0.4 clock cycles of delay to the SPI-4 egress status clock[3:0]=6=Add 0.5 clock cycles of delay to the SPI-4 egress status clock[3:0]=4=Add 0.6 clock cycles of delay to the SPI-4 egress status clock[3:0]=5=Add 0.7 clock cycles of delay to the SPI-4 egress status clock[3:0]=F=Add 0.8 clock cycles of delay to the SPI-4 egress status clock[3:0]=E=Add 0.9 clock cycles of delay to the SPI-4 egress status clock


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TABLE 122 - OCLK AND MCLK FREQUENCYSELECT ENCODING

N_MCLK & N_OCLK[k] Frequency Selects Frequency00 pll_oclk / 401 pll_oclk / 610 pll_oclk / 811 pll_oclk / 10

TABLE 121 - CLOCK GENERATOR CONTROLREGISTER (REGISTER_OFFSET 0x10)

Field Bits Length Initial ValueOCLK0_EN 0 1 0b01N_OCLK0 2:1 2 0b11Reserved 3 1 0b0OCLK1_EN 4 1 0b1N_OCLK1 6:5 2 0b11Reserved 7 1 0b0OCLK2_EN 8 1 0b1N_OCLK2 10:8 2 0b11Reserved 11 1 0b0OCLK3_EN 12 1 0b1N_OCLK3 14:13 2 0b11Reserved 16:15 2 0b0N_MCLK 18:17 2 0b11

Field Bits Length Initial ValueINTERNAL 0 1 0b0TIMER 1 1 0b0MANUAL 2 1 0b0

TABLE 119 - PMON TIMEBASE CONTROL REGIS-TER (REGISTER_OFFSET 0x00)

9.4.10 Common module block base 0x0900 registersPMON timebase control register (Block_base0x0900 + Register_offset 0x00)

A single PMON timebase module is available in the IDT88P8344. The PMONtimebase module directs a timebase event to all PMON modules in the device.The timebase period can be internally or externally generated. The selectionis made by the INTERNAL flag in the PMON update control register. A snapshotof the counters is taken when the timebase expires and the counters are cleared.The PMON update control register is at common module 0x8000 + Block_base0x0900 + Register_offset 0x00 = 0x8900 and has read and write access.

INTERNAL Selects between internal or external timebases for perfor-mance monitoring. The internal timebase is either generated by the internalprocessor or by a free running timer. The selection is made by the TIMER flagin the PMON update control register. When the time interval expires, theTIMEBASE pin is asserted for sixteen MCLK cycles. The timebase event iscaptured by the timebase status in the support interrupt status register.

0= External timebase from the TIMEBASE pin is selected. The externallygenerated timebase signal is applied to the TIMEBASE pin. A positive edgedetector generates the timebase event.

1=Internal timebase is selected. When the time interval expires, the TIMEBASEpin is driven high for sixteen MCLK cycles.

TIMER Selects between the internal free-running timebase or a micropro-cessor-controlled write to generate the timebase event. The TIMER field is validonly when the INTERNAL field is a logic one.

0=Selects the microprocessor generated timebase1=Selects the internal free-running timebase

MANUAL The microprocessor generates an internal timebase eventby a write access with a logical one to the MANUAL flag in the PMON UpdateControl Register if the microprocessor timebase is selected. The MANUAL bitis self-clearing. The MANUAL field is only valid if the TIMER field is a logic zero.

0=No operation1=A timebase event is generated

Timebase register (Block_base 0x0900 +Register_offset 0x01)TABLE 120 - TIMEBASE REGISTER(REGISTER_OFFSET 0x01)

Field Bits Length Initial ValuePERIOD 26:0 27 0x4A2 8600

The timebase register is at Block_base 0x0900 + Register_offset 0x01 andhas read and write access.

The timebase period for free-running timers is configured by the PERIOD fieldin the timebase register. The PERIOD field specifies the number of MCLK clockcycles required for a single event. The PERIOD field is only valid if both theINTERNAL and TIMER fields are a logic one.

Clock generator control register (Block_base0x0900 + Register_offset 0x010)

The clock generator control register is at common module Block_base0x0900 + Register_offset 0x010.

The clock generator provides four clock outputs on the OCLK[3:0] pins,MCLK for internal use, and SPI-4 data and FIFO status channel egress clocks.The OCLK[3:0] clock frequencies can be selected independently of each other.OCLK[3:0] outputs can be used as SPI-3 clock sources. The OCLK[3:0] pinsare separately enabled by setting each associated enable flag in Table 121 -Clock generator control register (Register_offset 0x10). When an OCLK[3:0]output is not enabled, it is in a logic low state. MCLK is the internal processingclock, and is always enabled. Refer to Table 122 - OCLK and MCLK frequencyselect encoding, for selecting the frequencies of MCLK and OCLKs.

During either a hardware or a software reset, the OCLK[3:0] pins are all logiclow. Immediately following reset, all OCLK[3:0] outputs are active with the outputfrequency defined by pll_oclk divided by the initial value in the Table 121 - Clockgenerator control register (Block_base 0x0900 + Register_offset 0x10).

The clock generator control register at indirect address 0x8910 has read andwrite access. The clock generator control register is used to set the frequencyof MCLK and the OCLK outputs, as well as to enable the OCLK outputs. Notethat divider values should be chosen so that OCLK[3:0] and MCLK are withintheir specified operating range provided in Table 136, OCLK[3:0] clock outputsand MCLK internal clock.

OCLK[k]_EN Used for enabling the kth OCLK output0=OCLK[k] is not enabled and OCLK[k] is at a logic zero1=OCLK[k] is enabled and active

N_OCLK[k] [1:0] Select the OCLK[k] frequency according to Table 122-OCLK and MCLK frequency select encoding.

N_MCLK[k] Select the MCLK frequency according to Table 122-OCLKand MCLK frequency select encoding.


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TABLE 125 - VERSION NUMBER REGISTER(REGISTER_OFFSET 0x30)

Field Bits Length Initial ValueVersion 7:0 8 0x01ID 15:8 8 0xF8

TABLE 123 - GPIO REGISTER (REGISTER_OFFSET0x20)

Field Bits Length Initial ValueADDRESS 15:0 16 0x0000Reserved 23:16 8 0x00BIT 28:24 5 0x00Reserved 31:29 3 0x0

TABLE 124 - GPIO MONITOR TABLE (5 ENTRIES0x21-0x25 FOR GPIO[0] THROUGH GPIO[4])

Field Bits Length InitialValue

DIR_OUT 4:0 5 0x00Reserved 7:5 3 0x0LEVEL 12:8 5 0x00Reserved 15:13 3 0x0MONITOR_EN 20:16 5 0x00

The version number register is a read-only sixteen-bit register atCommon_module 0x8000 + Block_base 0x0900 + Register_offset 0x30 =0x8930 in the indirect register access space. The version number registercontains hard-coded values that can be read to verify the microprocessor readpath is correct, and that the correct part is installed.

VERSION The hardware version is read from this field.

ID The hardware identification is read from this field.

General purpose I/O (Block_base 0x0900 +Register_offset 0x20)

Five general purpose I/O pins are provided. Each pin I/O direction iscontrolled by the DIR_OUT field in the GPIO register. The logical level on a GPIOpin is controlled by the LEVEL field in the GPIO register if DIR_OUT=1(pin=output), or sensed if DIR_OUT=0 (pin=input). Optionally, the LEVEL bitcan monitor the logic level of any bit selected from the indirect access space ifMONITOR_EN is set high. With MONITOR_EN set high, bits in the indirectaccess space can be selected for monitoring by the ADDRESS and BIT fieldsin the GPIO monitor table.

The general purpose I/O registers are at common module Block_base0x0900 and have read and write access.

DIR_OUT[4:0] Used for configuring each GPIO pin as either an input oran output

0=GPIO pin is an input1=GPIO pin is an output

LEVEL[4:0] Used for sensing or driving each GPIO pin0=GPIO pin is sensed as a logic zero if an input , or driven to a logic zero if

an output1=GPIO pin is sensed as a logic one if an input , or driven to a logic one if

an output

MONITOR_EN [4:0] Used for enabling the monitor output function for eachGPIO pin. GPIO pins used as monitors must also be configured to be outputs.All GPIO pins must be used as either monitors or as normal I/O; no mixing ofthe monitoring function and the normal I/O function is permitted.

0=GPIO pin is used as an I/O pin1=GPIO pin is used as a monitor pin

GPIO monitor table (Block_base 0x0900 +Register_offset 0x21 - 0x25)

A bit in the indirect access space can be selected for monitoring by theADDRESS and BIT fields in the GPIO monitor table.

The GPIO Monitor Table for GPIO[0] is at Common_Module 0x8000+Block_base 0x0900 + Register_offset 0x21 = 0x8921.





ADDRESS[15:0] Used for configuring the indirect address select whenthe GPIO pins are put into monitor mode.

BIT[4:0] Used for selecting the register bit (1 of 32) for a GPIO put intomonitor mode.

BIT[4:0]=0x00 selects data bit 0.…BIT[4:0]=0x1F selects data bit 31.

Version number register (common moduleBlock_base 0x0900 + Register_offset 0x30)


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Code Instruction Function000 EXTEST JTAG function001 IDCODE JTAG function010 SAMPLE JTAG function011 CLAMP JTAG function100 HIGHZ JTAG function101 Private Private function111 BYPASS JTAG function

TABLE 126 � JTAG INSTRUCTIONS

10. JTAG INTERFACEThe device supports the optional TRST input signal. It supports a TCKclock frequency up to 10MHz.

Version field equals 0JTAG ID #0x044E MANUFACTURER ID 0x033 LAST BIT IS 1.

Parameter Symbol Conditions Min.(1) Max.(1) UnitCore Digital Supply Voltage VDDC18 VSS=0, AVSS=0, Tj=25°C -0.3 2.2 VI/O Digital Supply Voltage VDDT33 -0.3 4.6 VAnalog Supply Voltage VDDA18 -0.3 3.6 VAnalog Supply Voltage VDDA33 -0.3 3.6 VI/O Input Voltage for CMOS VinL -0.5 6.0 VI/O Input Voltage for LVTTL VinL -0.5 6.0 VI/O Output Voltage Vout -0.5 4.6 VLatch-up Current IO - 100 mAESD Performance (HBM) - 2000 VAmbient Operating Temperature Ta(Industrial) -40 +85 °CAmbient Operating Temperature Ta(Commercial) 0 +70 °CStorage Temperature TS -65 +150 °C

11.1 Absolute maximum ratings

11. ELECTRICAL AND THERMAL SPECIFICATIONS

NOTE:1. Functional and tested operating conditions are given in Table Absolute Maximum Ratings are stress ratings only, and functional operation

at the maximum is not guaranteed. Stresses beyaond those listed may affect device reliability or cause permament damage to the device.

TABLE 127 � ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Conditions Min. Typ. Max. UnitCore Digital Supply Voltage VDDC18 VSS=0 1.68 1.8 1.96 VI/O Digital Supply Voltage VDDT33 VSS=0 3.0 3.3 3.6 VAnalog Supply Voltage VDDA18 VSS=0 1.68 1.8 1.96 VAnalog Supply Voltage VDDA33 VSS=0 3.0 3.3 3.6 VAmbient Operating Temperature Ta(Industrial) -40 25 +85 °CAmbient Operating Temperature Ta(Commercial) 0 25 +70 °CJunction Temperature TJ - - +110 °C

TABLE 128 � RECOMMENDED OPERATING CONDITIONS

11.2 Recommended Operating Conditions


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Parameter Symbol Conditions Min. Typ. Max. UnitInput Capacitance CI Measured at Vin=Vout=VSS - - 8 pFLoad Capacitance CO Ta=25°C - - 20 pFLoad Capacitance for OCLK CO - - 30 pF[3:0] signalsLoad Capacitance for CO - - 100 pFmicroprocessor interface

11.3 Terminal CapacitanceTABLE 129 � TERMINAL CAPACITANCE

Parameter Symbol Conditions ValueTypical Power Dissipation total PT Ta=25°C 3.5WTypical Power Dissipation from 1.8V PVDD18 Ta=25°C 1.9WTypical Power Dissipation from 3.3V PVDD33 Ta=25°C 1.6WThermal Resistance (Junction to case) ΘJC 4.5 °C/WThermal Resistance (Junction to board) ΘJB 4.1 °C/WThermal Resistance (Ambient) ΘJA Air flow 0.0m/s 15.4 °C/W

Air flow 1.0m/s 11.7 °C/WAir flow 2.0m/s 10.2 °C/W

TABLE 130 � THERMAL CHARACTERISTICS11.4 Thermal Characteristics


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11.5 DC Electrical characteristics

Parameter Description Min. Typ. Max. Unit Test Conditions

CMOS I/OVIL Input Low Voltage -0.3 — 0.8 VVIH Input High Voltage 2.0 — VD33+0.3 VVOL Output Low Voltage VSS — 0.4 V VD33=min, IOL= max_load (Note 1)VOH Output High Voltage 2.4 — VD33 V VD33=min, IOH= max_load (Note 1)VRESETBH RESETB Reset Input High Voltage 1.47 — — VVRESETBL RESETB Reset Input Low Voltage — — 0.95 VVRESETBHYST RESETB Reset Input Hysteresis Voltage 0.53 — — VIILPU Input Low Current (with pullups) -100 -50 -4 µA VIL=VSS

IILPU Input High Current (with pullups) -10 0 +10 µA VIL=VD33

IIL Input Low Current (without pullups) -10 0 +10 µA VIL=VSS

IIH Input High Current (without pullups) -10 0 +10 µA VIH=VD33

IOZ Off state output current -10 0 +10 µA VD33=MAXLVTTL I/OVIL Input Low Voltage -0.3 — 0.8 VVIH Input High Voltage 2.0 — VD33+0.3 VVOL Output Low Voltage VSS — 0.4 V VD33=MIN, IOL= 8mAVOH Output High Voltage 2.4 — VD33 V VD33=MIN, IOH= -8mAIL Input Current -5 0 +5 µA VD33=MAXIOZ Off state output current -10 0 +10 µA VD33=MAXSPI-4 LVDS I/OInput CharacteristicsVIN Input Voltage Range, VP or VN 0 — 2400 mV |VGPG| < 925 mV|VIDTH | Differential Voltage Required to Toggle Input 100 — — mV |VGPG| < 925 mVVHYST Input Differential Hysteresis, VIDTHH - VIDTHL 25 — — mVRIN Input Differential Impedance 90 100 110 Ohms P to N inputOutput CharacteristicsVOL Output Low Voltage, VP or VN 925 — — mV RDIFF_TERM = 100VOH Output High Voltage, VP or VN — — 1475 mV RDIFF_TERM = 100VOS Output Offset Voltage 1125 — 1375 mV RDIFF_TERM = 100delta VOS Change in VOS between “0” and “1” — — 25 mV RDIFF_TERM = 100|VOD| Output Differential Voltage 250 — 450 mV RDIFF_TERM = 100|delta VOD| Change in |VOD| between “0” and “1” 50 (DC) — 150 (AC) mV RDIFF_TERM = 100Ro Output Single-ended Impedance 40 100 140 Ohmsdelta Ro Ro mismatch between P and N — — 10 %ISP, ISN Output Short Circuit Current — — 40 mA P or N output shorted to VSS

ISPN Output Short Circuit Current — — 12 mA P and N outputs shorted together|IXP|, |IXN| Power-off output leakage — — 10 µA VD33 = VSS

NOTE:1. Maximum load = 8 mA for microprocessor data bus DBUS[7:0]; maximum load= 4 mA for all other CMOS outputs.

TABLE 131 � DC ELECTRICAL CHARACTERISTICS


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11.6 AC characteristics11.6.1 SPI-3 I/O timing

Refer to [SPI-3 in Glossary] for logical timing diagrams of the SPI-3 and SPI-4 interfaces. Note that underclocking and overclocking for the SPI-4 and SPI-3 interfaces is supported.

Figure 34. SPI-3 I/O timing diagram

SPI-3 Input / OutputSPI-3 input and output timing is shown in the following paragraph.

6372 drw30

I_F C LK, E_F CLK

SPI3_I_DAT

SPI3_E_D AT

TsuTh

T d

TABLE 132 � SPI-3 AC INPUT / OUTPUT TIMING SPECIFICATIONSI_FCLK, E_FCLK Unit Min. Typ. Max. DescriptionDuty cycle % 30 — 70 Input SPI-3 clock duty cycleFrequency MHz MCLK/4 — 133 I_FCLK, E_FCLKTR, TF ns — — 2 Rise fall time ( 20%, 80% )All outputsTD ns 2.33 — 5.65 Output delay after E_FCLKTR, TF ns — — 2 Rise fall time ( 20%, 80% )All inputsTSU ns 1 — — Input setup before I_FCLKTH ns 0.65 — — Input hold after I_FCLK


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11.6.2 SPI-4 LVDS Input / OutputSPI-4 input and output timing is shown in the following paragraph. Double

Data Rate protocol is used for data and status transfer. The SPI-4 LVDS signalsuse a dynamic data alignment at the ingress.

Figure 35. SPI-4 I/O timing diagram

6372 drw31

S PI4_ I_D C LK,S PI4_E_D C LK

SPI4_ I_D AT ,S PI4_E _ST A T

T suT h

Td

S PI4_E_D AT ,S PI4_I_S T A T

T suT h

T d


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Inputs Unit Min. Typ. Max. DescriptionDuty cycle % 45 50 55 I_DCLK ingress clock duty cycleFrequency (DDR) MHz 80 — 200 Ingress clock frequency, I_LOW=1Frequency (DDR) MHz 200 311 400 Ingress clock frequency, I_LOW=0TR, TF ps 300 — 500 Input rise or fall time ( 20%, 80% )Deskew UI — — +/- 1 Bit line deskewOutputsDuty cycle % 45 50 55 E_DCLK Egress clock duty cycleFrequency (DDR) MHz 80 — 200 Egress clock frequency, E_LOW=1Frequency (DDR) MHz 200 311 400 Egress clock frequency, E_LOW=0TR, TF ps 300 — 500 Output rise or fall time ( 20%, 80% )Tskew ps — — 50 Output differential skew, P to NSYNTH Jitter UI — — 0.1 PLL jitter as a fraction of the clock cycleTD ns — — — Adjustable

TABLE 133 � SPI-4.2 LVDS AC INPUT / OUTPUT TIMING SPECIFICATIONS

REF_CLK Unit Min. Typ. Max.Duty cycle % 30 50 70 REF_CLK clock input duty cycleFREF_CLK MHz 12.5 19.44 25 Main reference clock inputTR, TF ns — — 5 Rise fall time ( 20%, 80% )

11.6.4 REF_CLK clock input

11.6.5 MCLK internal clock and OCLK[3:0] clock outputs

11.6.6 Microprocessor interface

All outputs Unit Min. Typ. Max. DescriptionTR, Tf ns 10 Rise, fall time (20%, 80%)All inputsTR, TF ns 10 Rise, fall time (20%,80%)

Parameter Symbol Conditions Min Typ Max Unit

SPI-4 LVTTL Status(1)

STAT_T[1:0] to SCLK_T setup time TSU 2 nsSCLK_T to STAT_T [1:0] hold time TH 0.5 nsSCLK_T to STAT_T [1:0] delay TD 1 1.2 ns

11.6.3 SPI-4 LVTTL Status AC characteristics

TABLE 134 � SPI-4 LVTTL STATUS AC CHARACTERISTICS

TABLE 135 � REF_CLK CLOCK INPUT

TABLE 137 � MICROPROCESSOR INTERFACE

NOTE:1. For the SPI-4 LVTTL valid, hold & setup the edge is configurable. The SPI-4 ingress LVTTL status clock active edge isconfigured by I_CLK_EDGE field in Table 89-SPI-4 Ingress Configuration Register on page 66. The SPI-4 egress LVTTLstatus clock active edge is configured by E_CLK_EDGE field in Table 104-SPI-4 Egress Configuration Register on page 70.

OCLK[3:0] Unit Min. Typ. Max. DescriptionDuty cycle % 45 50 55 OCLK[3:0] outputs, clock duty cycleFrequency MHz 40 104 133 OCLK[3:0], programmableOutput skew One pll_oclk cycle of deliberatebetween OCLKs skew between each OCLK[3:0]TR, TF ns 1 2 OCLK[3:0] rise, fall time (20%,80%)MCLKFrequency MHz 80 — 100 Programmable

TABLE 136 � OCLK[3:0] CLOCK OUTPUTS AND MCLK INTERNAL CLOCK


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Figure 36. Microprocessor parallel port Motorola read timing diagram

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Valid Address

READ DBUS[7:0] Valid Data

tRecovery

ADD[5:0]

R/WB

DSB + CSB

tDW

tRC

tRWH

tRWV

tAV

tADH

tPRDtDAZ

11.6.6.1 Microprocessor parallel port AC timingspecifications

Be sure to connect SPI_EN to a logic low when using the parallel µP interfacemode.

Read cycle specification Motorola non-multiplexed (MPM=0)

Symbol Parameter MIN MAX UnitT Internal main clock period (MCLK) 80 100 MHztRC Read cycle time 5.5T+25 nstDW Valid DSB width 5.5T+20 nstRWV Delay from DSB to valid read signal T/2-4 nstRWH R/WB to DSB hold time 2T+10 nstAV Delay from DSB to Valid Address T/2-4 nstADH Address to DSB hold time 2T+10 nstRPD DSB to valid read data propagation delay 5.5T+20 nstDAZ Delay from read data active to high Z 12 nstRecovery Recovery time from read cycle 5 ns

TABLE 138 � MICROPROCESSOR PARALLEL PORT MOTOROLA READ TIMING


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Figure 37. Microprocessor parallel port Motorola write timing diagram

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Valid Address

DSB + CSB

R/WB

Valid Data

tRecovery

ADD[5:0]

Write DBUS[7:0]

tRWH

tDW

tWC

tRWV

tAH

tAV

tDVtDHW

Write cycle specification Motorola non-multiplexed (MPM=0)

Symbol Parameter MIN MAX UnitT Internal main clock period (MCLK) 80 100 MHztWC Write cycle time 2.5T+17 nstDW Valid DSB width 2.5T+12 nstRWV Delay from DSB to valid write signal T/2-4 nstRWH R/WB to DSB hold time 2.5T+12 nstAV Delay from DSB to Valid Address T/2-4 nstAH Address to DSB hold time 2.5T+12 nstDV Delay from DSB to valid write data T/2-4 nstDHW Write data to DSB hold time 2.5T+12 nstRecovery Recovery time from write cycle 5 ns

TABLE 139 � MICROPROCESSOR PARALLEL PORT MOTOROLA WRITE TIMING


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Valid Address

CSB + RDB

tRecovery

tRC

tRDW

tDAZ

tAV

tRPD

Valid Data

ADD[5:0]

Read DBUS[7:0]

Read cycle specification Intel non-multiplexed bus (MPM=1)

NOTE:1. WRB should be tied to High.

Figure 38. Microprocessor parallel port Intel mode read timing diagram

Symbol Parameter MIN MAX UnitT Internal main clock period (MCLK) 80 100 MHztRC Read cycle time 5.5T+25 nstRDW Valid RDB width 5.5T+20 nstAV Delay from RDB to Valid Address T/2-4 nstAH Address to RDB hold time 2.5T+12 nstRPD RDB to valid read data propagation delay 5.5T-20 nstDAZ Delay from read data active to High-Z 12 nstRecovery Recovery time from read cycle 5 ns

TABLE 140 � MICROPROCESSOR PARALLEL PORT INTEL MODE READ TIMING


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Valid Address

tRecoverytWC

tWRW

tAH

tAV

tDHW

tDV

Write DBUS[7:0]

ADD[5:0]

WRB + CSB

Write cycle specification Intel non-multiplexed bus (MPM=1)

NOTE:1. RDB should be tied to a logic one.

Figure 39. Microprocessor parallel port Intel mode write timing diagram

Symbol Parameter MIN MAX UnitT Internal main clock period (MCLK) 80 100 MHztWC Write cycle time 2.5T+19 nstWRW Valid WRB width 2.5T+14 nstAV Delay from WRB to Valid Address T/2-2 nstAH Address to WRB hold time 2.5T+12 nstDV Delay from WRB to valid write data T/2-2 nstDHW Write data to WRB hold time 2.5T+12 nstRecovery Recovery time from read cycle 5 ns

TABLE 141 � MICROPROCESSOR PARALLEL PORT INTEL MODE WRITE TIMING


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SCLK

tCSH

High Impedance

Valid Input

tCLDtCSDtCLLtCLHtCSS

tDIS tDIH

tPD

Valid Output

tDF

High Impedance

SDI

SDO

CSB

11.6.6.2 Serial microprocessor interface (serialperipheral interface mode)Timing Characteristics

The maximum SPI Data transfer clock frequency is 2 MHz. The detailinformation of the timing characteristics is shown in below and timing diagram isshown in Figure 40, Microprocessor serial peripheral interface timing diagram.

Figure 40. Microprocessor serial peripheral interface timing diagram

Symbol Description Min. Max. UnitfOP SCLK Frequency 2.0 MHzfCSH Minimum CSB High Time 100 nstCSS CSB Setup Time 50 nstCSD CSB Hold Time 100 nstCLD SCLK Clock Disable Time 50 nstCLH SCLK Clock High Time 205 nstCLL SCLK Clock Low Time 205 nstDIS SDI Data Setup Time 50 nstDIH SDI Data Hold Time 150 nstPD SDO Output Delay 150 nstDF SDO Output Disable Time 50 ns

TABLE 142 � MICROPROCESSOR SERIAL PERIPHERAL INTERFACE TIMING


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12.1 Device overview

PBGA (BH820-1, order code: BH)TOP VIEW

12. MECHANICAL CHARACTERISTICS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

A A

B B

C C

D D

E E

F F

G G

H H

J J

K K

L L

M M

N N

P P

R R

T T

U U

V V

W W

Y Y

AA AA

AB AB

AC AC

AD AD

AE AE

AF AF

AG AG

AH AH

AJ AJ

AK AK

AL AL

AM AM

AN AN

AP AP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VDD VDDA33 VDDA18 VD33 SPI3_INGRESS SPI3_EGRESS

VSSA18 VSS SPI4_INGRESS SPI4_EGRESS PROCESSOR TEST, CONFIG, MISC

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RESERVED A4RESERVED E5RESERVED B4RESERVED D4RESERVED A3RESERVED C4RESERVED B3RESERVED C2RESERVED C1RESERVED C3RESERVED D3RESERVED D1RESERVED F5RESERVED D2RESERVED E3RESERVED E1RESERVED F4RESERVED E2RESERVED F3RESERVED F2RESERVED G4RESERVED F1RESERVED G5RESERVED G3RESERVED H5RESERVED G2RESERVED G1RESERVED H4RESERVED H2RESERVED H3RESERVED H1RESERVED J5RESERVED J4RESERVED J3RESERVED J2RESERVED J1RESERVED K5RESERVED K4RESERVED K3RESERVED K2RESERVED K1RESERVED L5RESERVED L4RESERVED L3RESERVED M5RESERVED L2RESERVED L1RESERVED M4RESERVED M3RESERVED M2RESERVED M1RESERVED N4

SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL12.2 Pin name/ball location table

RESERVED N5RESERVED N3RESERVED N2RESERVED N1RESERVED R5RESERVED P5RESERVED P4RESERVED P2RESERVED P1RESERVED P3RESERVED R4RESERVED R3RESERVED T5RESERVED R2RESERVED R1RESERVED T4RESERVED U5RESERVED T3RESERVED T2RESERVED T1RESERVED U3RESERVED U4RESERVED U2RESERVED U1RESERVED V5RESERVED V1RESERVED V2RESERVED V4RESERVED W3RESERVED W1RESERVED V3RESERVED W2RESERVED W5RESERVED W4RESERVED Y1RESERVED Y2RESERVED Y5RESERVED Y3RESERVED Y4RESERVED AA1RESERVED AA5RESERVED AA2RESERVED AA3RESERVED AA4RESERVED AB4RESERVED AB1RESERVED AB2RESERVED AC2RESERVED AB5RESERVED AB3RESERVED AC1RESERVED AC3

RESERVED AC5RESERVED AC4RESERVED AD1RESERVED AD2RESERVED AD5RESERVED AD4RESERVED AD3RESERVED AE1RESERVED AE3RESERVED AE2RESERVED AE4RESERVED AF3RESERVED AE5RESERVED AF1RESERVED AF2RESERVED AF5RESERVED AF4RESERVED AG2RESERVED AG1RESERVED AG4RESERVED AG3RESERVED AH1RESERVED AH2RESERVED AH3RESERVED AG5RESERVED AH4RESERVED AJ1RESERVED AJ4RESERVED AJ2RESERVED AJ3RESERVED AK1RESERVED AK2RESERVED AH5RESERVED AK4RESERVED AL1RESERVED AL2RESERVED AK3RESERVED AM1RESERVED AM2RESERVED AM3RESERVED AL3RESERVED AP3RESERVED AL4RESERVED AM4RESERVED AN4RESERVED AP4RESERVED AK5RESERVED] AL5RESERVED AN5RESERVED AM5RESERVED AK6RESERVED AP5

RESERVED AM6RESERVED AL6RESERVED AP6RESERVED AN6RESERVED AL7RESERVED AK7RESERVED AN7RESERVED AM7RESERVED AK8RESERVED AP7RESERVED AM8RESERVED AL8RESERVED AK9RESERVED AN8RESERVED AP8RESERVED AL9RESERVED AK10RESERVED AM9RESERVED AN9RESERVED AP9RESERVED AL10RESERVED AM10RESERVED AN10RESERVED AP10RESERVED AK12RESERVED AK11RESERVED AL11RESERVED AN11RESERVED AP11RESERVED AM11RESERVED AL12RESERVED AM12RESERVED AK13RESERVED AN12RESERVED AP12RESERVED AL13RESERVED AM13RESERVED AN13RESERVED AP13RESERVED AN14RESERVED AK14RESERVED AL14RESERVED AM14RESERVED AP14RESERVED AM15RESERVED AL15RESERVED AN15RESERVED AP15RESERVED AK15RESERVED AL16RESERVED AK16RESERVED AM16


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RESERVED AK17RESERVED AN16RESERVED AP16RESERVED AL17RESERVED AK18RESERVED AM17RESERVED AN17RESERVED AP17RESERVED AK20RESERVED AL18RESERVED AM18RESERVED AP18RESERVED AK19RESERVED AP19RESERVED AN18RESERVED AN19RESERVED AK22RESERVED AL19RESERVED AP20RESERVED AM20RESERVED AM19RESERVED AL20RESERVED AN20RESERVED AP21RESERVED AK21RESERVED AN21RESERVED AM21RESERVED AL21RESERVED AP22RESERVED AN22RESERVED AM22RESERVED AL22RESERVED AK23RESERVED AP23RESERVED AN23RESERVED AL23RESERVED AM23RESERVED AP24RESERVED AM24RESERVED AN24RESERVED AK24RESERVED AL24RESERVED AP25RESERVED AN25RESERVED AK25RESERVED AL25RESERVED AM25RESERVED AP26RESERVED AN26RESERVED AP27RESERVED AM26RESERVED AK26

RESERVED AL26RESERVED AM27RESERVED AN27RESERVED AK27RESERVED AL27RESERVED AN28RESERVED AP28RESERVED AL28RESERVED AM28RESERVED AP29RESERVED AK28RESERVED AM29RESERVED AN29REF_CLK AP30TCK AL29LVDS_STA AN30TDI AM30TDO AP32TMS AN32GPIO[4] AM31GPIO[3] AM33GPIO[2] AM34CLK_SEL[3] AL31GPIO[1] AL30CLK_SEL[2] AK29GPIO[0] AL32CLK_SEL[1] AK30OCLK[3] AK31CLK_SEL[0] AH31OCLK[2] AJ30TIMEBASE AH34OCLK[1] AH32OCLK[0] AH33SPI4_I_STAT_T[1] AH30SPI4_I_STAT_T[0] AG32SPI4_I_SCLK_T AG33BIAS AJ31SPI4_I_STAT_P[1] AG31SPI4_I_STAT_P[0] AF31SPI4_I_STAT_N[1] AG30SPI4_I_STAT_N[0] AF30SPI4_I_SCLK_P AF33SPI4_I_SCLK_N AF32SPI4_E_DCLK_P AE34SPI4_E_DCLK_N AE33SPI4_E_DAT_P[15] AE30SPI4_E_DAT_N[15] AE31SPI4_E_DAT_P[14] AD31SPI4_E_DAT_N[14] AD30SPI4_E_DAT_P13] AD34SPI4_E_DAT_N[13] AD33SPI4_E_DAT_P[12] AC32

SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL12.2. Pin name/ball location table (continued)

SPI4_E_DAT_N[12] AC31SPI4_E_DAT_P[11] AC34SPI4_E_DAT_N[11] AC33SPI4_E_DAT_P[10] AB31SPI4_E_DAT_N[10] AB30SPI4_E_DAT_P[9] AB34SPI4_E_DAT_N[9] AB33SPI4_E_DAT_P[8] AA31SPI4_E_DAT_N[8] AA30SPI4_E_DAT_P[7] AA34SPI4_E_DAT_N[7] AA33SPI4_E_DAT_P[6] Y32SPI4_E_DAT_N[6] Y31SPI4_E_DAT_P[5] Y34SPI4_E_DAT_N[5] Y33SPI4_E_DAT_P[4] W31SPI4_E_DAT_N[4] W30SPI4_E_DAT_P[3] W34SPI4_E_DAT_N[3] W33SPI4_E_DAT_P[2] V31SPI4_E_DAT_N[2] V30SPI4_E_DAT_P[1] V34SPI4_E_DAT_N[1] V33SPI4_E_DAT_P[0] U32SPI4_E_DAT_N[0] U31SPI4_E_CTRL_P U34SPI4_E_CTRL_N U33SPI4_I_DCLK_P T34SPI4_I_DCLK_N T33SPI4_I_DAT_P[15] T31SPI4_I_DAT_N[15] T30SPI4_I_DAT_P[14] R34SPI4_I_DAT_N[14] R33SPI4_I_DAT_P[13] R31SPI4_I_DAT_N[13] R30SPI4_I_DAT_P[12] P34SPI4_I_DAT_N[12] P33SPI4_I_DAT_P[11] P32SPI4_I_DAT_N[11] P31SPI4_I_DAT_P[10] N34SPI4_I_DAT_N[10] N33SPI4_I_DAT_P[9] N31SPI4_I_DAT_N[9] N30SPI4_I_DAT_P[8] M34SPI4_I_DAT_N[8] M33SPI4_I_DAT_P[7] M32SPI4_I_DAT_N[7] M31SPI4_I_DAT_P[6] L34SPI4_I_DAT_N[6] L33SPI4_I_DAT_P[5] K33SPI4_I_DAT_N[5] K34SPI4_I_DAT_P[4] L31

SPI4_I_DAT_N[4] K31SPI4_I_DAT_P[3] K30SPI4_I_DAT_N[3] J30SPI4_I_DAT_P[2] J32SPI4_I_DAT_N[2] J33SPI4_I_DAT_P[1] J34SPI4_I_DAT_N[1] H34SPI4_I_DAT_P[0] H32SPI4_I_DAT_N[0] H33SPI4_I_CTRL_P H30SPI4_I_CTRL_N H31SPI4_E_SCLK_P G31SPI4_E_SCLK_N G32SPI4_E_STAT_P[1] F33SPI4_E_STAT_N[1] F34SPI4_E_STAT_P[0] F32SPI4_E_STAT_N[0] E32SPI4_E_STAT_T[1] L30SPI4_E_STAT_T[0] M30SPI4_E_SCLK_T E31SPI_EN E29DBUS[7] E30ADD[5] D33DBUS[6] D34ADD[4] D31DBUS[5] D32ADD[3] C34DBUS[4] D30WRB C33DBUS[3] C32CSB B32DBUS[2] C31DBUS[1] A32RESETB C30INTB A31DBUS[0] A30ADD[2] B30RDB E28ADD[1] D29TRSTB D28ADD[0] B28MPM C28SPI3A_E_SOP A28SPI3A_E_ERR E27SPI3A_E_MOD[1] C27SPI3A_E_MOD[0] D27SPI3A_E_EOP B27SPI3A_E_ENB A27SPI3A_E_SX D26SPI3A_E_PRTY E26SPI3A_E_DAT[31] C26SPI3A_E_DAT[30] B26


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SPI3A_E_DAT[29] A26SPI3A_E_DAT[28] E25SPI3A_E_DAT[27] D25SPI3A_E_DAT[26] C25SPI3A_E_DAT[25] A25SPI3A_E_DAT[24] B25SPI3A_E_DAT[23] C24SPI3A_E_DAT[22] D24SPI3A_E_DAT[21] D23SPI3A_E_DAT[20] E23SPI3A_E_DAT[19] B24SPI3A_E_DAT[18] A24SPI3A_E_DAT[17] C23SPI3A_E_DAT[16] E24SPI3A_E_DAT[15] B23SPI3A_E_DAT[14] A23SPI3A_E_DAT[13] D22SPI3A_E_DAT[12] E22SPI3A_E_DAT[11] C22SPI3A_E_DAT[10] B22SPI3A_E_DAT[9] A22SPI3A_E_DAT[8] E21SPI3A_E_DAT[7] D21SPI3A_E_DAT[6] C21SPI3A_E_DAT[5] B21SPI3A_E_DAT[4] E20SPI3A_E_DAT[3] A21

SPI3A_E_DAT[2] C20SPI3A_E_DAT[1] B20SPI3A_E_DAT[0] D20SPI3A_E_FCLK A20SPI3A_PTPA C19SPI3A_TADR[7] B19SPI3A_TADR[6] D19SPI3A_TADR[5] A19SPI3A_TADR[4] A18SPI3A_TADR[3] B18SPI3A_TADR[2] E19SPI3A_TADR[1] C18SPI3A_TADR[0] D18SPI3A_STPA A17SPI3A_DTPA[3] E18SPI3A_DTPA[2] B17SPI3A_DTPA[1] C17SPI3A_DTPA[0] D17SPI3A_I_ENB E17SPI3A_I_SX A16SPI3A_RVAL B16SPI3A_I_ERR C16SPI3A_I_FCLK D16SPI3A_I_SOP B15SPI3A_I_PRTY A15SPI3A_I_MOD[1] C15SPI3A_I_MOD[0] E16

SPI3A_I_EOP D15SPI3A_I_DAT[31] E15SPI3A_I_DAT[30] A14SPI3A_I_DAT[29] E14SPI3A_I_DAT[28] B14SPI3A_I_DAT[27] C14SPI3A_I_DAT[26] D14SPI3A_I_DAT[25] E13SPI3A_I_DAT[24] A13SPI3A_I_DAT[23] B13SPI3A_I_DAT[22] C13SPI3A_I_DAT[21] E12SPI3A_I_DAT[20] D13SPI3A_I_DAT[19] A12SPI3A_I_DAT[18] B12SPI3A_I_DAT[17] E11SPI3A_I_DAT[16] D12SPI3A_I_DAT[15] C12SPI3A_I_DAT[14] A11SPI3A_I_DAT[13] C11SPI3A_I_DAT[12] D11SPI3A_I_DAT[11] B11SPI3A_I_DAT[10] A10SPI3A_I_DAT[9] B10SPI3A_I_DAT[8] C10SPI3A_I_DAT[7] E10SPI3A_I_DAT[6] D10

SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL SIGNAL PIN NAME BALL12.2 Pin name/ball location table (continued)

SPI3A_I_DAT[5] A9SPI3A_I_DAT[4] B9SPI3A_I_DAT[3] D9SPI3A_I_DAT[2] E9SPI3A_I_DAT[1] C9SPI3A_I_DAT[0] A8RESERVED C8RESERVED D8RESERVED B8RESERVED E8RESERVED B7RESERVED C7RESERVED A7RESERVED A6RESERVED D7RESERVED B6RESERVED E7RESERVED E6RESERVED C6RESERVED A5RESERVED D6RESERVED B5RESERVED D5RESERVED C5

VDDA18_CLKGEN AF28VSSA18_CLKGEN AA20VDDA18_ISTX AD28VSSA18_ISTX Y21VDDA18_EDTX AE28VSSA18_EDTX AA21VDDA18_IDRX P28VSSA18_IDRX R21VDDA18_ESRX L28VSSA18_ESRX P21VSS (GND) A29, B29, C29, E4, F6, F7, F17, F18, F28, F29, F31, G6, G7, G17, G18, G28, G29, G33, G34, J31, L32, N32, P14 - P20,

R14- R20, T14 - T21, T32, U6, U7, U14 - U21, U28, U29, V6, V7, V14 - V21, V28, V29, V32, W14 - W21, Y14 - Y20, Y30,AA14 - AA19, AA32, AC30, AD32, AF34, AG34, AH6, AH7, AH17, AH18, AH28, AH29, AJ5 - AJ7, AJ17, AJ18, AJ28, AJ29,AJ32 - AJ34, AK32, AK33, AN3, AP31, AN31, B31, AM32

VDD18 (1.8 VOLTS) A1, A2, A33, A34, B1, B2, B33, B34, E33, E34, F8, F9, F12, F13, F15, F16, F19, F20, F22, F23, F26, F27, F30, G8, G9, G12,G13, G15, G16, G19, G20, G22, G23, G26, G27, G30, H6, H7, H28, H29, J6, J7, J28, J29, K32, M6, M7, M28, M29, N6, N7,N28, N29, R6, R7, R28, R29, R32, T6, T7, T28, T29, W6, W7, W28, W29, W32, Y6, Y7, Y28, Y29, AB6, AB7, AB28, AB29, AB32,AC6, AC7, AC28, AC29, AE32, AF6, AF7, AH25, AF29, AG6, AG7, AG28, AG29, AH8, AH9, AH12, AH13, AH15, AH16, AH19,AH20, AH22, AH23, AH26, AH27, AJ8, AJ9, AJ12, AJ13, AJ15, AJ16, AJ19, AJ20, AJ22, AJ23, AJ26, AJ27, AK34, AL33, AL34,AN1, AN2, AN33, AN34, AP1, AP2, AP33, AP34

VD33 (3.3 VOLTS) F10, F11, F14, F21, G10, G11, G14, G21, K6, K7, L6, L7, P6, P7, AA6, AA7, AD6, AD7, AE6, AE7, AH10, AH11, AH14, AH21,AJ10, AJ11, AJ14, AJ21

VDDA33 (3.3 VOLTS) F24, F25, G24, G25, K28, K29, L29, P29, P30, U30, AA28, AA29, AD29, AE29, AJ24, AH24, AJ25

POWER PIN NAME BALL(S)


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12.3 Device packageThe SPI Exchange IDT88P8341 device is packaged in a 35 mm by 35 mm

820-ball one millimeter ball pitch thermally-enhanced plastic ball grid array. Allballs, whether used or unused, must be soldered to pads.

Figure 41. IDT88P8341 820PBGA package, bottom view




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Figure 42. IDT88P8341 820PBGA package, top and side views



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ACRONYM MEANINGFIFO First In First Out memoryLID Logical IDentifier See also Logical Port (LP)

The entity associated with a flow of data between a SPI-3 LP to a SPI-4 LP, or a SPI-4 LP to a SPI-3 LP.LP Logical Port. See also Logical Identifier (LID)

The entity associated with a SPI-3 or SPI-4 address.OIF Optical Internetworking ForumSPI-3 System Packet Interface Level 3

This interface is defined by the OIF implementation agreement OIF-SPI3-01.0 - SPI-3 Packet Interface forPhysical and Link Layers for OC-48 available at http://www.oiforum.com/public/impagreements.html

SPI-4 System Packet Interface Level 4 phase 2This interface is defined by the OIF implementation agreement OIF-SPI4-02.1 - System Packet InterfaceLevel 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices availableat http://www.oiforum.com/public/impagreements.html

13. GLOSSARY


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ISSUE DATE DESCRIPTION

0.7 05/21/04 • General Release

0.8 10/01/04 • AG30 ball location changed to SPI4_I_STAT_N[1] and AF31 ball location changed to SPI4_I_STAT_P[0] on Pin name/ball location table (Table 12.2) on page 88.

0.9 03/01/05 • Updated Chip Configuration Sequence (p. 40)• Update Table 21: “BIT Order Within a 16-BIT Address Register” (p. 44)• Update Table 27: “Indirect Access Address Register” (p. 45)• Updated Direct Access Registers (p. 47-48)• Updated Common Module Indirect Registers (p. 64)• Updated Electrical and Thermal Specification (p. 75) (the section name changed from Electrical Characteristics to Electrical and Thermal Specification). Updated JTAG Instructions.• Added Document Revision History (p. 93)

0.91 05/09/05 • Added sections System Reset and Power on Sequence (p.40).• Updated PFR to PFP in Table 49: "Module A indirect register" (p.53)• Updated Table 80: "SPI-4 ingress packet length configuration" (p.63)• Updated length for Reserved in Table 83: "SPI-4 ingress port descriptor" (p.63)• Updated Table 87: "SPI-4 ingress LP to LID map" (p.66)• Added Green to Ordering information (p.94)

0.92 08/05/05 • Updated Table 128: "Absolute maximum ratings" (p.76)

0.93 10/20/05 • Updated Table 7: "Parallel microprocessor interface" (p.12)• Updated Table 131: "Thermal Characteristics" (p.77)• Updated Microprocessor parallel port section (p.82-85)

0.94 11/09/05 • Updated Table 126: "Version number register (register_offset 0x30)" (p.75)

0.95 12/01/05 • Updated 8.2.5 SPI-4 status channel software (p.42)

0.96 01/05/06 • Updated Figure 4: "PHY mode SPI-3 ingress interface" (p.14)• Deleted Table 13: "NR_LID Field Encoding". Updated SPI-4 egress queues, Normal operation section (p.26)• Updated Section 8.2.5 "SPI-4 status channel software" (p.42)• Updated Table 26 title: "Indirect access address register at 0x34 to 0x35" (p.46)• Updated 9.3 section title: "Indirect registers for SPI-3A module" (p.53)• Updated Table 127: "Absolute maximum ratings" (p.76)• Updated Table 129: "Terminal Capacitance" (p.77)

1.0 04/10/06 • Initial Release of Final Datasheet with new section 8.2.7 "Software Eye-Opening Check on SPI-4" & new Figure 32. "DDR interface and eye opening check through over sampling" (p.43-44)• Updated Clock generator (pg. 38)• Updated SPI-4 ingress watermark register (pg. 69)• Updated Clock generator control register (pg. 75)• Updated Table 130: Thermal Characteristics (pg. 78)• Updated Table 132: SPI-3 AC Input/Output timing specifications (pg. 80)• Updated Table 136: OCLK[3:0] outputs and MCLK internal clock (pg. 82)

14. DATASHEET DOCUMENT REVISION HISTORY


CORPORATE HEADQUARTERS for SALES: for Tech Support:6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1716San Jose, CA 95138 fax: 408-284-2775 email: [email protected]

www.idt.com

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15. ORDERING INFORMATION

Plastic Ball Grid Array (PBGA, BH820-1)

Industrial (-40C to +85C)

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IDT X

Device Type

X

Package

XProcess /

TemperatureRange

I

88P8341 SPI Exchange SPI-3 to SPI-4

BH

X

G Green

NOTE:1. Green parts are available.


SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 IDT88P8341

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Transcript of SPI EXCHANGE SPI-3 TO SPI-4 Issue 1.0 IDT88P8341