UM1855 User manual - Farnell element14 · such as USB, USART, digital microphones, A DC and DAC,...

July 2015 DocID027351 Rev 2 1/100

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UM1855User manual

Evaluation board with STM32L476ZGT6 MCU

Introduction

The STM32L476G-EVAL evaluation board is designed as complete demonstration and development platform for STMicroelectronics ARM® Cortex®-M4-core-based STM32L476ZGT6 microcontroller with three I²C buses, three SPI and six USART ports, CAN port, SWPMI, two SAI ports, 12-bit ADC, 12-bit DAC, LCD driver, internal 128-Kbyte SRAM and 1-Mbyte Flash memory, Quad-SPI port, touch sensing capability, USB OTG FS port, LCD controller, flexible memory controller (FMC), JTAG debug port.STM32L476G-EVAL, shown in Figure 1(1), can be used as reference design for user application development, although it is not considered as final application.

A full range of hardware features on the board helps users evaluate all on-board peripherals such as USB, USART, digital microphones, ADC and DAC, dot-matrix TFT LCD, LCD glass module, IrDA, LDR, SRAM, NOR Flash memory device, Quad-SPI Flash memory device, microSD card, sigma-delta modulators, smartcard with SWP, CAN transceiver, EEPROM, RF-EEPROM. Extension headers allow connecting daughterboards or wrapping boards.

ST-LINK/V2-1 in-circuit debugger and flashing facility is integrated on the mainboard.

Figure 1. STM32L476G-EVAL evaluation board

1. Picture not contractual.

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Contents UM1855

2/100 DocID027351 Rev 2

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2 Demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4 Unpacking recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Hardware layout and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 ST-LINK/V2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1 Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.2 ST-LINK/V2-1 firmware upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 Supplying the board through ST-LINK/V2-1 USB port . . . . . . . . . . . . . . 15

2.3.2 Using ST-LINK/2-1 along with powering through CN22 power jack . . . 16

2.4 Clock references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.5 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6 Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.6.1 Boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.6.2 Bootloader limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7.1 Digital microphones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7.2 Headphones outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7.3 Limitations in using audio features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.8 USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.8.1 STM32L476G-EVAL used as USB device . . . . . . . . . . . . . . . . . . . . . . . 23

2.8.2 STM32L476G-EVAL used as USB host . . . . . . . . . . . . . . . . . . . . . . . . 24

2.8.3 Configuration elements related with USB OTG FS port . . . . . . . . . . . . 24

2.8.4 Limitations in using USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.8.5 Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.9 RS-232 and IrDA ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.9.1 RS-232 port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.9.2 IrDA port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.9.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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2.10 LPUART port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.11 microSD card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.11.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27


2.12 Motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.12.1 Board modifications to enable motor control . . . . . . . . . . . . . . . . . . . . 29

2.12.2 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.13 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.13.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32


2.14 Extension connectors CN6 and CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.15 LCD glass module daughterboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.15.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.16 TFT LCD panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.17 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.18 Physical input devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.18.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.19 Operational amplifier and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.19.1 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.19.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.20 Analog input, output, VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.21 SRAM device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.21.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43


2.22 NOR Flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.22.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44


2.23 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44


2.24 RF-EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.25 Quad-SPI Flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.25.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46


2.26 Touch-sensing button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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2.26.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.27 Smartcard, SWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.27.1 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50


2.28 Near-field communication (NFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.29 Dual-channel sigma-delta modulators STPMS2L . . . . . . . . . . . . . . . . . . 51

2.29.1 STPMS2L presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.29.2 STPMS2L settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.29.3 STPMS2L power metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.29.4 STPMS2 for PT100 measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.29.5 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.30 MCU current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.30.1 IDD measurement principle - analog part . . . . . . . . . . . . . . . . . . . . . . . 55

2.30.2 Low-power-mode IDD measurement principle - logic part . . . . . . . . . . . 56

2.30.3 IDD measurement in dynamic run mode . . . . . . . . . . . . . . . . . . . . . . . . 58

2.30.4 Calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.1 RS-232 D-sub male connector CN9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.2 Power connector CN22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.3 LCD daughterboard connectors CN11 and CN14 . . . . . . . . . . . . . . . . . . 61

3.4 Extension connectors CN6 and CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.5 ST-LINK/V2-1 programming connector CN16 . . . . . . . . . . . . . . . . . . . . . 65

3.6 ST-LINK/V2-1 Standard-B USB connector CN17 . . . . . . . . . . . . . . . . . . . 65

3.7 JTAG connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.8 Trace debugging connector CN12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.9 microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.10 ADC/DAC connector CN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.11 RF-EEPROM daughterboard connector CN3 . . . . . . . . . . . . . . . . . . . . . 69

3.12 Motor control connector CN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.13 USB OTG FS Micro-AB connector CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.14 CAN D-sub male connector CN5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.15 NFC connector CN13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Appendix A Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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Appendix B FCC and IC compliance statements . . . . . . . . . . . . . . . . . . . . . . . . . 98

B.1 FCC (Federal Communications Commission) compliance statement. . . . 98

B.1.1 Part 15.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

B.1.2 Part 15.105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

B.1.3 Part 15.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

B.2 IC (Industry Canada) compliance statement . . . . . . . . . . . . . . . . . . . . . . . 98

B.2.1 Industry Canada . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

List of tables UM1855

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List of tables

Table 1. Setting of configuration elements for trace connector CN12 . . . . . . . . . . . . . . . . . . . . . . . 14Table 2. Power-supply-related jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 3. X1-crystal-related solder bridge settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 4. X2-crystal-related solder bridge settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 5. Boot selection switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 6. Bootloader-related jumper setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 7. Digital microphone-related jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 8. Configuration elements related with USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Table 9. Settings of configuration elements for RS-232 and IrDA ports . . . . . . . . . . . . . . . . . . . . . . 26Table 10. Hardware settings for LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 11. Terminals of CN18 microSD slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 12. Motor control terminal and function assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 13. CAN related jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Table 14. LCD-daughterboard-related configuration elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Table 15. LCD glass element mapping - segments 0 to 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 16. LCD glass element mapping - segments 10 to 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 17. LCD glass element mapping - segments 20 to 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 18. LCD glass element mapping - segments 30 to 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Table 19. Access to TFT LCD resources with FMC address lines A0 and A1 . . . . . . . . . . . . . . . . . . 39Table 20. Assignment of CN19 connector terminals of TFT LCD panel . . . . . . . . . . . . . . . . . . . . . . . 39Table 21. Port assignment for control of LED indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Table 22. Port assignment for control of physical input devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Table 23. Setting of jumpers related with potentiometer and LDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Table 24. SRAM chip select configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 25. NOR Flash memory-related configuration elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 26. Configuration elements related with Quad-SPI device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Table 27. Touch-sensing-related configuration elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 28. Assignment of ports for ST8024CDR control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Table 29. Configuration elements related with smartcard and SWP . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 30. CN13 NFC connector terminal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 31. JP11 jumper settings during IDD measurement with calibration . . . . . . . . . . . . . . . . . . . . 59Table 32. RS-232 D-sub (DE-9M) connector CN9 with HW flow control and ISP support . . . . . . . . . 60Table 33. CN11 and CN14 daughterboard connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 34. Daughterboard extension connector CN6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 35. Daughterboard extension connector CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Table 36. USB Standard-B connector CN17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 37. JATG debugging connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 38. Trace debugging connector CN12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Table 39. microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Table 40. Analog input-output connector CN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 41. RF-EEPROM daughterboard connector CN3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 42. Motor control connector CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Table 43. USB OTG FS Micro-AB connector CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Table 44. CAN D-sub (DE-9M) 9-pins male connector CN5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 45. NFC CN13 terminal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 46. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

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List of figures

Figure 1. STM32L476G-EVAL evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 2. STM32L476G-EVAL hardware block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 3. STM32L476G-EVAL main component layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 4. USB Composite device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 5. CN22 power jack polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 6. CN20, CN21 top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 7. PCB top-side rework for motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 8. PCB underside rework for motor control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 9. LCD glass module daughterboard in display position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 10. LCD glass module daughterboard in I/O-bridge position . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 11. LCD glass display element mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 12. NFC board plugged into STM32L476G-EVAL board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Figure 13. Routing of STPMS2L dual-channel sigma-delta modulators . . . . . . . . . . . . . . . . . . . . . . . 52Figure 14. Power measurement principle schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 15. STPMS2L power metering schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 16. Temperature measurement principle schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 17. Schematic diagram of the analog part of IDD measurement . . . . . . . . . . . . . . . . . . . . . . . 56Figure 18. Schematic diagram of logic part of low-power-mode IDD measurement . . . . . . . . . . . . . . 57Figure 19. Low power mode IDD measurement timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Figure 20. RS-232 D-sub (DE-9M) 9-pole connector (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 21. Power supply connector CN2 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 22. USB type B connector CN17 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Figure 23. JTAG debugging connector CN15 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Figure 24. Trace debugging connector CN12 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Figure 25. microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 26. Analog input-output connector CN8 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 27. RF EEPROM daughterboard connector CN3 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . 69Figure 28. Motor control connector CN2 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Figure 29. USB OTG FS Micro-AB connector CN1 (front view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 30. CAN D-sub (DE-9M) 9-pole male connector CN5 (front view) . . . . . . . . . . . . . . . . . . . . . . 71Figure 31. NFC female connector CN13 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 32. STM32L476G-EVAL top schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Figure 33. MCU, LCD daughterboard and I/O expander interfaces - schematic diagram . . . . . . . . . 74Figure 34. STM32L476G-EVAL MCU part 1 - schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 35. STM32L476G-EVAL MCU part 2 - schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 36. LCD glass module daughterboard connectors - schematic diagram . . . . . . . . . . . . . . . . . 77Figure 37. I/O expander schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Figure 38. Power supply schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 39. Smartcard, SWP and NFC - schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 40. USART and IrDA - schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Figure 41. SRAM and NOR Flash memory devices - schematic diagram . . . . . . . . . . . . . . . . . . . . . . 82Figure 42. TFT LCD schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Figure 43. Extension connector schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 44. Quad-SPI Flash memory device schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Figure 45. microSD card schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Figure 46. Physical control peripherals - schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Figure 47. CAN transceiver schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Figure 48. Touch-sensing device schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

List of figures UM1855

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Figure 49. USB_OTG_FS port schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Figure 50. IDD measurement schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 51. Audio codec device schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Figure 52. STPMS2L and PT100 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Figure 53. RF-EEPROM and EEPROM schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Figure 54. Motor control connector schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Figure 55. JTAG and trace debug connectors - schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 96Figure 56. ST-LINK/V2-1 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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UM1855 Overview

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1 Overview

1.1 Features

STM32L476ZGT6 microcontroller with 1-Mbyte Flash memory and 128-Kbyte RAM

four power supply options: power jack, ST-LINK/V2-1 USB connector, USB OTG FS connector, daughterboard

microcontroller supply voltage: 3.3 V or range from 1.71 V to 3.6 V

two MEMS digital microphones

two stereo audio headphones jack outputs with independent audio content

slot for microSD card supporting SD, SDHC, SDXC

4-Gbyte microSD card bundled

16-Mbit (1M x 16 bit) SRAM device

128-Mbit (8M x 16 bit) NOR Flash memory device

256-Mbit Quad-SPI Flash memory device with double transfer rate (DTR) support

RF-EEPROM with I²C bus

EEPROM supporting 1 MHz I²C-bus communication speed

RS-232 port configurable for communication or MCU flashing

IrDA transceiver

USB OTG FS Micro-AB port

CAN 2.0A/B-compliant port

joystick with four-way controller and selector

reset and wake-up / tamper buttons

touch-sensing button

light-dependent resistor (LDR)

potentiometer

coin battery cell for power backup

LCD glass module daughterboard (MB979) with 40x8-segment LCD driven directly by STM32L476ZGT6

2.8-inch 320x240 dot-matrix color TFT LCD panel with resistive touchscreen

smartcard connector and SWP support

NFC transceiver connector

connector for ADC input and DAC output

power-metering demonstration with dual-channel sigma-delta modulator

PT100 thermal sensor with dual-channel sigma-delta modulator

MCU current consumption measurement circuit

access to comparator and operational amplifier of STM32L476ZGT6

extension connector for motor control module

JTAG/SWD, ETM trace debug support, user interface through USB virtual COM port, embedded ST-LINK/V2-1 debug and flashing facility

extension connector for daughterboard

Overview UM1855

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1.2 Demonstration software

Demonstration software is preloaded in the STM32L476ZGT6 Flash memory, for easy demonstration of the device peripherals in stand-alone mode. For more information and to download the latest available version, refer to the STM32L476G-EVAL demonstration software available on www.st.com.

1.3 Order code

To order the evaluation board based on the STM32L476ZGT6 MCU, use the order code STM32L476G-EVAL.

1.4 Unpacking recommendations

Before the first use, make sure that, no damage occurred to the board during shipment and no socketed components are loosen in their sockets or fallen into the plastic bag.

In particular, pay attention to the following components:

1. quartz crystal (X2 position)

2. microSD card in its CN18 receptacle

3. RF-EEPROM board (ANT7-M24LR-A) in its CN3 connector

For product information related with STM32L476ZGT6 microcontroller, visit www.st.com.

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UM1855 Hardware layout and configuration

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2 Hardware layout and configuration

The STM32L476G-EVAL evaluation board is designed around STM32L476ZGT6 target microcontroller in LQFP 144-pin package. Figure 2 illustrates STM32L476ZGT6 connections with peripheral components. Figure 3 shows the location of main components on the evaluation board.

Figure 2. STM32L476G-EVAL hardware block diagram

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Figure 3. STM32L476G-EVAL main component layout

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2.1 ST-LINK/V2-1

ST-LINK/V2-1 facility for debug and flashing of the target MCU, STM32L476ZGT6, is integrated on the STM32L476G-EVAL evaluation board.

Compared to ST-LINK/V2 stand-alone tool available from ST, ST-LINK/V2-1 offers new features and drops some others.

New features:

USB software re-enumeration

Virtual COM port interface on USB

Mass storage interface on USB

USB power management request for more than 100mA power on USB

Features dropped:

SWIM interface

The USB connector CN17 can be used to power STM32L476G-EVAL regardless ofST-LINK/V2-1 facility use for debugging or for flashing the target MCU. This holds also when ST-LINK/V2 stand-alone tool is connected to CN12 or CN15 connector and used for debugging or flashing the target MCU, STM32L476ZGT6. Section 2.3 provides more detail on powering STM32L476G-EVAL.

For full detail on both versions of the debug and flashing tool, the stand-alone ST-LINK/V2 and the embedded ST-LINK/V2-1, refer to www.st.com.

2.1.1 Drivers

Before connecting STM32L476G-EVAL to a Windows 7, Windows 8 or Windows XP PC via USB, a driver for ST-LINK/V2-1 must be installed. It can be downloaded from www.st.com.

In case the STM32L476G-EVAL evaluation board is connected to the PC before installing the driver, the Windows device manager may report some USB devices found on STM32L476G-EVAL as “Unknown”. To recover from this situation, after installing the dedicated driver downloaded from www.st.com, the association of “Unknown” USB devices found on STM32L476G-EVAL to this dedicated driver must be updated in the device manager manually. It is recommended to proceed using USB Composite Device line, as shown in Figure 4.

Figure 4. USB Composite device


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2.1.2 ST-LINK/V2-1 firmware upgrade

ST-LINK/V2-1 facility for debug and flashing of the target microcontroller STM32L476ZGT6 is integrated on STM32L476G-EVAL board. For its own operation, ST-LINK/V2-1 employs a dedicated MCU with Flash memory. Its firmware determines ST-LINK/V2-1 functionality and performance. The firmware may evolve during the life span of STM32L476G-EVAL to include new functionality, fix bugs or support new target microcontroller families. It is therefore recommended to keep ST-LINK/V2-1 firmware up to date. The latest version is available from www.st.com. ST-LINK/V2-1 supports a mechanism that allows flashing its dedicated MCU via the USB interface on the hosting board, here STM32L476G-EVAL. The whole process is controlled from a Windows PC application also available from www.st.com.

2.2 Trace

The connector CN12 can output trace signals used for debug. By default, the evaluation board is configured such that, the target MCU signals PE2 through PE5 are not connected to trace outputs Trace_D0, Trace_D1, Trace_D2, Trace_D3 and Trace_CK of CN12. They are used for other functions.

Table 1 shows the setting of configuration elements to shunt PE2, PE3, PE4 and PE5 MCU ports to CN12 connector, to use them as debug trace signals. The default settings do not allow the use of these ports for trace purposes.

Warning: Enabling the CN12 trace outputs through hardware modifications described in Table 1 results in reducing the memory address bus width to 19 binary lines and so the

Table 1. Setting of configuration elements for trace connector CN12

Element Setting Use of PE2, PE3, PE4, PE5 terminals of target MCU

R103SB26

R103 inSB26 open

Default setting.PE2 connected to LCDSEG38 and memory address line A23.

R103 outSB26 closed

PE2 connected to TRACE_CK on CN12. A23 pulled down.

R104R104 in

Default setting.PE3 connected to LCDSEG39 and memory address line A19.

R104 out PE3 connected to TRACE_D0 on CN12. A19 pulled down.

R84SB40

R84 inSB40 open

Default setting.PE4 connected to memory address line A20.

R84 outSB40 closed

PE4 connected to TRACE_D1 on CN12. A20 pulled down.

R85SB38

R85 inSB38 open

Default setting.PE5 connected to memory address line A21.

R85 outSB38 closed


R86SB39

R86 inSB39 open

Default setting.PE6 is used for address bit A22.

R86 outSB39 closed


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addressable space to 512 Kwords of 16 bits. As a consequence, the on-board SRAM and NOR Flash memory usable capacity is reduced to 8 Mbits.

2.3 Power supply

STM32L476G-EVAL evaluation board is designed to be powered from 5 V DC power source. It incorporates a precise polymer Zener diode (Poly-Zen) protecting the board from damage due to wrong power supply. One of the following four 5V DC power inputs can be used, upon an appropriate board configuration:

Power jack CN22, marked PSU_E5V on the board. A jumper must be placed in PSU location of JP17. The positive pole is on the center pin as illustrated in Figure 5.

Standard-B USB receptacle CN17 of ST-LINK/V2-1, offering enumeration feature described in Section 2.3.1.

Micro-AB USB receptacle CN1 of USB OTG interface, marked OTG_FS on the board. Up to 500mA can be supplied to the board in this way.

Pin 28 of CN6 extension connector for custom daughterboards, marked D5V on the board.

No external power supply is provided with the board.

LD7 red LED turns on when the voltage on the power line marked as +5V is present. All supply lines required for the operation of the components on STM32L476G-EVAL are derived from that +5V line.

Table 2 describes the settings of all jumpers related with powering STM32L476G-EVAL and extension board. VDD_MCU is the target MCU digital supply voltage line. It can be connected to either fixed 3.3 V or to an adjustable voltage regulator controlled with RV1 potentiometer and producing a range of voltages between 1.71 V and 3.6 V.

2.3.1 Supplying the board through ST-LINK/V2-1 USB port

To power STM32L476G-EVAL in this way, the USB host (a PC) gets connected with the STM32L476G-EVAL board’s Standard-B USB receptacle, via a USB cable. This event starts the USB enumeration procedure. In its initial phase, the host’s USB port current supply capability is limited to 100 mA. It is enough because only ST-LINK/V2-1 part of STM32L476G-EVAL draws power at that time. If the jumper header JP18 is open, the U37 ST890 power switch is set to OFF position, which isolates the remainder ofSTM32L476G-EVAL from the power source. In the next phase of the enumeration procedure, the host PC informs the ST-LINK/V2-1 facility of its capability to supply up to 300 mA of current. If the answer is positive, the ST-LINK/V2-1 sets the U37 ST890 switch to ON position to supply power to the remainder of the STM32L476G-EVAL board. If the PC USB port is not capable of supplying up to 300 mA of current, the CN22 power jack can be used to supply the board.

The ST890 power switch protects the host’s USB port against current demand exceeding 600 mA, should a short-circuit occur on the board. In such an event, the LD9 LED lights on.

The STM32L476G-EVAL board can also be supplied from a USB power source not supporting enumeration, such as a USB charger. In this particular case, the JP18 header must be fitted with a jumper as shown in Table 2. ST-LINK/V2-1 turns the ST890 power switch ON regardless of enumeration procedure result and passes the power unconditionally to the board.


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The LD7 red LED turns on whenever the whole board is powered.

2.3.2 Using ST-LINK/2-1 along with powering through CN22 power jack

It can happen that the board requires more than 300 mA of supply current. It cannot be supplied from host PC connected to ST-LINK/2-1 USB port for debugging or flashing the target MCU. In such a case, the board can be supplied through CN22 (marked PSU _E5V on the board).

To do this, it is important to power the board before connecting it with the host PC, which requires the following sequence to be respected:

1. set the jumper in JP15 header in PSU position

2. connect the external 5 V power source to CN22

3. check the red LED LD7 is turned on

4. connect host PC to USB connector CN17

In case the board demands more than 300 mA and the host PC is connected via USB before the board is powered from CN22, there is a risk of the following events to occur, in the order of severity:

1. The host PC is capable of supplying 300 mA (the enumeration succeeds) but it does not incorporate any over-current protection on its USB port. It is damaged due to over-current.

2. The host PC is capable of supplying 300 mA (the enumeration succeeds) and it has a built-in over-current protection on its USB port, limiting or shutting down the power out of its USB port when the excessive current demand from STM32L476G-EVAL is detected. This causes an operating failure to STM32L476G-EVAL.

3. The host PC is not capable of supplying 300 mA (the enumeration fails) soST-LINK/V2-1 does not supply the remainder of STM32L476G-EVAL from its USB port VBUS line.

Figure 5. CN22 power jack polarity

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Table 2. Power-supply-related jumper settings

Jumper array Jumper setting Configuration

JP17

Power source selector

JP17STM32L476G-EVAL is supplied through CN22 power jack (marked PSU_E5V). CN6 extension connector does not pass the 5 V of STM32L476G-EVAL to daughterboard.

JP17

STM32L476G-EVAL is supplied through CN1 Micro-AB USB connector. CN6 extension connector does not pass the 5 V of STM32L476G-EVAL to daughterboard.

JP17 Default setting.STM32L476G-EVAL is supplied through CN17 Standard-B USB connector. CN6 extension connector does not pass the 5 V of STM32L476G-EVAL to daughterboard.Check JP18 setting in Table 2.

JP17

STM32L476G-EVAL is supplied through pin 28 of CN6 extension connector.

JP17 STM32L476G-EVAL is supplied through CN22 power jack (marked PSU_E5V). CN6 extension connector passes the 5 V of STM32L476G-EVAL to daughterboard. Make sure to disconnect from the daughterboard any power supply that could generate conflict with the power supply on CN22 power jack.

JP12

Vbat connection

JP12

Vbat is connected to battery.

JP12Default setting.Vbat is connected to VDD.


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JP2

VDD_MCU connection

JP2 Default setting.VDD_MCU (VDD terminals of STM32L476ZGT6) is connected to fixed +3.3 V.

JP2VDD_MCU is connected to voltage in the range from +1.71 V to +3.6 V, adjustable with potentiometer RV1.

JP10

VDDA connection

JP10 Default setting.VDDA terminal of STM32L476ZGT6 is connected with VDD_MCU.

JP10VDDA terminal of STM32L476ZGT6 is connected to +3.3 V.

JP1

VDD_USB connection

JP1 Default setting.VDD_USB (VDDUSB terminal of STM32L476ZGT6) is connected with VDD_MCU.

JP1

VDD_USB is connected to +3.3V.

JP3

VDD_IO connection

JP3 Default setting.VDD_IO (VDDIO2 terminals of STM32L476ZGT6) is connected with VDD_MCU

JP3

VDD_IO is open.

JP18

Powering through USB of ST-LINK/V2-1

JP18Default setting.Standard-B USB connector CN17 of ST-LINK/V2-1 can supply power to the STM32L476G-EVAL board remainder, depending on host PC USB port’s powering capability declared in the enumeration.

JP18 Standard-B USB connector CN17 of ST-LINK/V2-1 supplies power to the STM32L476G-EVAL board remainder. Setting for powering the board through CN17 using USB charger.

Table 2. Power-supply-related jumper settings (continued)

Jumper array Jumper setting Configuration

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2.4 Clock references

Two clock references are available on STM32L476G-EVAL for the STM32L476ZGT6 target microcontroller:

32.768 kHz crystal X1, for embedded RTC

8 MHz crystal X2, for main clock generator

The main clock can also be generated using an internal RC oscillator. The X2 crystal is in a socket. It can be removed when the internal RC oscillator is used.

2.5 Reset sources

Reset signal of the STM32L476G-EVAL board is active low.

Table 3. X1-crystal-related solder bridge settings

Solder bridge

Setting Description

SB41

OpenDefault setting.PC14-OSC32_IN terminal is not routed to extension connector CN7. X1 is used as clock reference.

ClosedPC14-OSC32_IN is routed to extension connector CN7.R87 must be removed, for X1 quartz circuit not to disturb clock reference or source on daughterboard.

SB33

OpenDefault setting.PC15-OSC32_OUT terminal is not routed to extension connector CN7. X1 is used as clock reference.

ClosedPC15-OSC32_OUT is routed to extension connector CN7.R88 must be removed, for X1 quartz circuit not to disturb clock reference on daughterboard.

Table 4. X2-crystal-related solder bridge settings

Solder bridge

Setting Configuration

SB24

OpenDefault setting.PH0-OSC_IN terminal is not routed to extension connector CN7. X2 is used as clock reference.

ClosedPH0-OSC_IN is routed to extension connector CN7.X2 and C54 must be removed, in order not to disturb clock reference or source on daughterboard.

SB23

OpenDefault setting.PH1-OSC_OUT terminal is not routed to extension connector CN7. X2 is used as clock reference.

ClosedPH1-OSC_OUT is routed to extension connector CN7.R95 must be removed, in order not to disturb clock reference or source on daughterboard.


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Sources of reset are:

reset button B1

JTAG/SWD connector CN15 and ETM trace connector CN12 (reset from debug tools)

through extension connector CN7, terminal 32 (reset from daughterboard)

ST-LINK/V2-1

RS-232 connector CN9, terminal 8 (CTS signal), if JP9 is closed

2.6 Boot

2.6.1 Boot options

After reset, the STM32L476ZGT6 MCU can boot (start code execution) from the following embedded memory locations:

main (user, non-protected) Flash memory

system (protected) Flash memory

RAM, for debugging

The microcontroller is configured to one of the listed boot options by setting the MCU port BOOT0 level by the switch SW1 and by setting nBOOT1 bit of FLASH_OPTR option bytes register, as shown in Table 5. Depending on JP8, BOOT0 level can be forced high and, SW1 action overruled, by DSR line of RS-232 connector CN9, as shown in Table 6. This can be used to force the execution of bootloader and start user Flash memory flashing process (ISP) from RS-232 interface.

The option bytes of STM32L476ZGT6 and their modification procedure are described in the reference manual RM0351. The application note AN2606 details the bootloader mechanism and configurations.

Table 5. Boot selection switch

Switch Setting Description

SW1

Default setting.BOOT0 line is tied low. STM32L476ZGT6 boots from user Flash memory.

BOOT0 line is tied high. STM32L476ZGT6 boots from system Flash memory (nBOOT1 bit of FLASH_OPTR register is set high) or from RAM(nBOOT1 is set low).

Table 6. Bootloader-related jumper setting

Jumper Setting Description

JP8

JP8Default setting.BOOT0 level only depends on SW1 switch position

JP8 BOOT0 can be forced high with terminal 6 of CN9 connector (RS-232 DSR line). This configuration is used to allow the computer connected via RS-232 to initiate the MCU flashing process.

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2.6.2 Bootloader limitations

Boot from system Flash memory results in executing bootloader code stored in the system Flash memory protected against write and erase. This allows in-system programming (ISP), that is, flashing the MCU user Flash memory. It also allows writing data into RAM. The data come in via one of communication interfaces such as USART, SPI, I²C bus, USB or CAN.

Bootloader version can be identified by reading Bootloader ID at the address 0x1FFF6FFE.

The STM32L476ZGT6 part soldered on the STM32L476G-EVAL main board is marked with a date code corresponding to its date of manufacture. STM32L476ZGT6 parts with the date code prior or equal to week 22 of 2015 are fitted with bootloader V 9.0 affected by the limitations to be worked around, as described hereunder. Parts with the date code starting week 23 of 2015 contain bootloader V9.2 in which the limitations no longer exist.

To locate the visual date code information on the STM32L476ZGT6 package, refer to its datasheet (DS10198) available on www.st.com, section Package Information. Date code related portion of the package marking takes Y WW format, where Y is the last digit of the year and WW is the week. For example, a part manufactured in week 23 of 2015 bares the date code 5 23.

Bootloader ID of the bootloader V 9.0 is 0x90.

The following limitations exist in the bootloader V 9.0:

1. RAM data get corrupted when written via USART/SPI/I2C/USB interface

Description:

Data write operation into RAM space via USART, SPI, I²C bus or USB results in wrong or no data written.

Workaround:

To correct the issue of wrong write into RAM, download STSW-STM32158 bootloader V 9.0 patch package from www.st.com and load "Bootloader V9.0 SRAM patch" to the MCU, following the information in readme.txt file available in the package.

2. User Flash memory data get corrupted when written via CAN interface

Description:

Data write operation into user Flash memory space via CAN interface results in wrong or no data written.

Workaround:

To correct the issue of wrong write into Flash memory, download STSW-STM32158 bootloader V 0.9 patch package from www.st.com and load "Bootloader V9.0 CAN patch" to the MCU, following the information in readme.txt file available in the package.

2.7 Audio

A codec connected to SAI interface of STM32L476ZGT6 supports TDM feature of the SAI port. TDM feature offers to STM32L476ZGT6 the capability to stream two independent stereo audio channels to two separate stereo analog audio outputs, simultaneously.

There are two digital microphones on board of STM32L476G-EVAL.


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2.7.1 Digital microphones

U35 and U36 on board of STM32L476G-EVAL are MP34DT01TR MEMS (microelectromecanical systems) digital omni-directional microphones providing PDM (pulse density modulation) outputs. To share the same data line, their outputs are interlaced. The combined data output of the microphones is directly routed to STM32L476ZGT6 terminals, thanks to the integrated input digital filters. The microphones are supplied with programmable clock generated directly by STM32L476ZGT6.

As an option, the microphones can be connected to U29, Wolfson audio codec IC, WM8994. In that configuration, U29 also supplies the PDM clock to the microphones.

Regardless of where the microphones are routed to, STM32L476ZGT6 or WM8994, they can be power-supplied from either VDD or MICBIAS1 output of the WM8994 codec IC.

Table 7 shows settings of all jumpers associated with the digital microphones on the board.

2.7.2 Headphones outputs

The STM32L476G-EVAL evaluation board can drive two sets of stereo headphones. Identical or different stereo audio content can be played back in each set of headphones. The STM32L476ZGT6 target MCU sends up to two independent stereo audio channels, via its SAI1 TDM port, to the WM8994 codec IC. The codec IC converts the digital audio stream to stereo analog signals. It then boosts them for direct drive of headphones connecting to 3.5 mm stereo jack receptacles on the board, CN20 for Audio-output1 and CN21 for Audio_output2. Figure 6 shows a top view of the CN20 and CN21 headphones jack receptacles.

The CN21 jack takes its signal from the WM8994 codec IC’s output intended for driving an amplifier for loudspeakers. A hardware adaptation is incorporated on the board to make it compatible with a direct headphone drive. The adaptation consists of coupling capacitors blocking the DC component of the signal, attenuator and anti-pop resistors. The WM8994 codec IC loudspeaker output must be configured by software in linear mode called “class AB” and not in switching mode called “class D”.

The I²C-bus address of WM8994 is 0b0011010.

Table 7. Digital microphone-related jumper settings

Jumper Setting Configuration

JP14

JP14Default setting.PDM clock for digital microphones comes from STM32L476ZGT6

JP14

PDM clock for digital microphones comes from WM8994 codec.

JP16

JP16Default setting.Power supply of digital microphones is VDD.

JP16

Power supply of digital microphones is generated by WM8994 codec.

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Figure 6. CN20, CN21 top view

2.7.3 Limitations in using audio features

Due to the share of some terminals of STM32L476ZGT6 by multiple peripherals, the following limitations apply in using the audio features:

If the SAI1_SDA is used as part of SAI1 port, it cannot be used as FMC_NWAIT signal for NOR Flash memory device. However, FMC_NWAIT is not necessary for operating the NOR Flash memory device. More details on FMC_NWAIT are available in Section 2.22: NOR Flash memory device.

If the SAI1 port of STM32L476ZGT6 is used for streaming audio to the WM8994 codec IC, STM32L476ZGT6 cannot control the motor.

If the digital microphones are attached to STM32L476ZGT6, the LCD glass module cannot be driven.

2.8 USB OTG FS port

The STM32L476G-EVAL board supports USB OTG full-speed (FS) communication.The USB OTG connector CN1 is of Micro-AB type.

2.8.1 STM32L476G-EVAL used as USB device

When a “USB host” connection to the CN1 Micro-AB USB connector of STM32L476G-EVAL is detected, the STM32L476G-EVAL board starts behaving as “USB device”. Depending on the powering capability of the USB host, the board can take power from VBUS terminal of CN1. In the board schematic diagrams, the corresponding power voltage line is called U5V. Section 2.3 provides information on how to set associated jumpers for this powering option. The JP19 jumper must be left open to prevent STM32L476G-EVAL from sourcing 5 V to VBUS terminal, which would cause conflict with the 5 V sourced by the USB host. This may


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happen if the PC6 GPIO is controlled by the software of STM32L476ZGT6 such that, it enables the output of U1 power switch.

2.8.2 STM32L476G-EVAL used as USB host

When a “USB device” connection to the CN1 Micro-AB USB connector is detected, the STM32L476G-EVAL board starts behaving as “USB host”. It sources 5 V on the VBUS terminal of CN1 Micro-AB USB connector to power the USB device. For this to happen, the STM32L476ZGT6 MCU sets the U1 power switch STMPS2151STR to ON state. The LD6 green LED marked VBUS indicates that the peripheral is supplied from the board. The LD5 red LED marked FAULT lights up if over-current is detected. The JP19 jumper must be closed to allow the PC6 GPIO to control the U1 power switch.In any other STM32L476G-EVAL powering option, the JP19 jumper should be open, to avoid accidental damage caused to an external USB host.

2.8.3 Configuration elements related with USB OTG FS port

The following STM32L476ZGT6 terminals related with USB OTG FS port control are shared by other resources of the STM32L476G-EVAL board:

PB12, used as USB over-current input (USBOTG_OVRCR signal); it is shared with SWP, touch sensing, LCD glass module and motor control resources

PB13, used as USB power ready input (USBOTG_PRDY signal); it is shared with NFC, touch sensing and LCD glass module resources

PC6, used as USB power switch control (USBOTG_PPWR signal); it is shared with touch sensing, LCD glass module and motor control

Configuration elements related with the USB OTG FS port, such as jumpers, solder bridges and zero-ohm resistors, shunt the shared ports toward different resources or determine the operation mode of the USB OTG FS port. By default, they are set such as to enable the USB OTG FS port operation where STM32L476G-EVAL plays USB device role and can be connected to a USB host. Table 8 gives an overview of all configuration elements related with the USB OTG FS port. The LCD glass module daughterboard should be connected in I/O position.

USBOTG_OVRCR and USBOTG_PPDY signals, requiring the PB12 and PB13 ports of STM32L476ZGT6, are only exploited when STM32L476G-EVAL acts as USB host. That is why, the USB host function of STM32L476G-EVAL is exclusive with alternate functions also requiring PB12 and PB13 ports of STM32L476ZGT6 - NFC, touch sensing, motor control, SWP.

The PB12 and PB13 ports of STM32L476ZGT6 are not required for the USB OTG FS port operating as USB device. They can serve for controlling one of alternate functions, such as NFC, for example, while the USB OTG FS port is in operation.

Table 8. Configuration elements related with USB OTG FS port

Element Setting Description

JP19

Open

Default setting.USB OTG FS port can be connected with a USB host and get power from it. If connected with USB device, STM32L476G-EVAL cannot supply power to it.

ClosedUSB OTG FS port can be connected with a USB device and supply power to it. It must not be connected with USB host.

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2.8.4 Limitations in using USB OTG FS port

The USB OTG FS port operation as USB host is exclusive with NFC, SWP, LCD glass module, touch sensing, motor control

The USB OTG FS port operation as USB device is exclusive with LCD glass module, touch sensing, motor control

2.8.5 Operating voltage

The USB-related operating supply voltage of STM32L476ZGT6 (VDD_USB line) must be within the range from 3.0 V to 3.6 V.

2.9 RS-232 and IrDA ports

The STM32L476G-EVAL board offers one RS-232 communication port and one IrDA port.

2.9.1 RS-232 port

The RS-232 communication port uses the DE-9M 9-pole connector CN9. RX, TX, RTS and CTS signals of USART1 port of STM32L476ZGT6 are routed to CN9. Bootloader_RESET_3V3 and Bootloader_BOOT0_3V3 signals can also be routed to CN9, for ISP (in-system programming) support. To route Bootloader_RESET_3V3 to CN9, the R93 resistor must be removed and the JP9 jumper closed. To route Bootloader_BOOT0_3V3 to CN9, the JP8 jumper must be closed.

R36

In

Default settingPC6 is shunted to control the U1 power switch, transiting through the LCD glass module daughterboard connector.LCD glass module daughterboard should be in I/O position, with SB2 and SB27 open.

OutPC6 is disconnected from the LCD glass module daughterboard connector. It can be shunted to one of alternate resources, either touch sensing (SB2 closed) or motor control (SB27 closed).

R39

In

Default setting.PB12 receives USBOTG_OVRCR signal from U1 power switch, transiting through the LCD glass module daughterboard connector.SB3 should be open, R109 in, no smartcard in CN23 slot.

OutPB12 is disconnected from the LCD glass module daughterboard connector. It can be shunted to one of alternate resources, either touch sensing or motor control (SB3 closed).

R38

In

Default setting.PB13 receives USBOTG_PRDY signal from CN1 connector, transiting through the LCD glass module daughterboard connector.SB6 should be open and no daughterboard inserted in CN13 NFC connector.

OutPB13 s disconnected from the LCD glass module daughterboard connector. It can be shunted to touch sensing (SB6 closed).

Table 8. Configuration elements related with USB OTG FS port (continued)



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For configuration elements related with the RS-232 port operation, refer to Table 6 and Table 9.

Section 2.10 brings information on using the LPUART port of STM32L476ZGT6 for RS-232, instead of its USART1 port.

2.9.2 IrDA port

The IrDA communication port uses an IrDA transceiver (U11). Table 9 shows the configuration elements related with the IrDA port operation

.

2.9.3 Limitations

The operation of RS-232 and IrDA ports is mutually exclusive. The operation of either port is also mutually exclusive with the NFC peripheral operation.


The RS-232- and IrDA-related operating supply voltage of STM32L476ZGT6 (VDD line) must be within the range from 1.71 V to 3.6 V.

2.10 LPUART port

On top of USART1 port for serial communication, the STM32L476ZGT6 target MCU offers LPUART, a low-power UART port.

Table 9. Settings of configuration elements for RS-232 and IrDA ports


JP15

JP15

Default setting.RS-232 selected: PB7 port of STM32L476ZGT6 receives signal originating from RXD terminal of CN9.

JP15

IrDA selected: PB7 port of STM32L476ZGT6 is connected with RxD terminal of the IrDA transceiver U11.

JP15

NFC selected: PB7 port of STM32L476ZGT6 receives NFC_IRQOUT signal from NFC peripheral. Section 2.28 provides more detail on the NFC peripheral.

R93, R118, R116

In Required for IrDA operation

R158, R119 Out Required for IrDA operation

31

546

2

31

546

2

31

546

2

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In the default configuration of STM32L476G-EVAL, the Rx and Tx terminals of the LPUART port are routed to the USB virtual COM port of ST-LINK/V2-1 and, the Rx and Tx terminals of USART1 port to the RS-232 connector CN9.

For specific purposes, the Tx and Rx of the LPUART port of STM32L476ZGT6 can be routed to the RS-232 connector CN9 instead. As RTS and CTS terminals of CN9 keep routed to USART1 port, they may block the LPUART communication flow. To avoid this, set the USART1 hardware flow control off.

The default settings of LPUART are: 115200b/s, 8bits, no parity, 1 stop bit, no flow control.

2.11 microSD card

The CN18 slot for microSD card is routed to STM32L476ZGT6’s SDIO port, accepting SD (up to 2 Gbytes), SDHC (up to 32 Gbytes) and SDXC (up to 2 Tbytes) cards. One 4-Gbyte microSD card is delivered as part of STM32L476G-EVAL. The card insertion switch is routed to the PA8 GPIO port.

For microSD card operation, the LCD glass module daughterboard must be plugged into CN11 and CN14 in I/O-bridge position, as explained in Section 2.15.

2.11.1 Limitations

Due to the share of SDIO port and PA8 terminals, the following limitations apply:

The microSD card cannot be operated simultaneously with LCD glass module or with motor control.

The microSD card insertion cannot be detected when the PA8 is used as microcontroller clock output (MCO), one of alternate functions of PA8.


The supply voltage for STM32L476G-EVAL microSD card operation must be within the range from 2.7 V to 3.6 V.

Table 10. Hardware settings for LPUART

LPUART port use R188 R189 R158 R119 R118 JP15 1-2

Default settingUSB virtual COM port of ST-LINK/V2-1

In In Out Outdon’tcare

don’tcare

RS-232 (Rx and Tx) Out Out In In Out Closed

Table 11. Terminals of CN18 microSD slot

Terminal Terminal name (MCU port) Terminal Terminal name (MCU port)

1 SDIO_D2 (PC10) 6 Vss/GND

2 SDIO_D3 (PC11) 7 SDIO_D0 (PC8)

3 SDIO_CMD (PD2) 8 SDIO_D1 (PC9)

4 VDD 9 GND

5 SDIO_CLK (PC12) 10 MicroSDcard_detect (PA8)


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2.12 Motor control

The CN2 connector is designed to receive a motor control (MC) module. Table 12 shows the assignment of its CN2 and target MCU terminals and peripherals on the silicon.

Table 12 also lists the modifications to be made on the board versus its by-default configuration. See Section 2.12.1 for further details.

Table 12. Motor control terminal and function assignment

Motor control connector CN2

STM32L476ZGT6 microcontroller

TerminalTerminal

namePort name Function

Alternate function

Board modifications for enabling motor control

1Emergency

StopPC9 TIM8_BKIN2 -

Close SB29Remove MB979 daughterboard

2 GND - GND - -

3 PWM_1H PC6 TIM8_CH1 -Close SB27Open SB2

Remove MB979 daughterboard

4 GND - GND - -

5 PWM_1L PA7 TIM8_CH1N -Close SB19Open SB18

Remove R66

6 GND - GND - -

7 PWM_2H PC7 TIM8_CH2 -Close SB30Open SB4

Remove R33

8 GND - GND - -

9 PWM_2L PB0 TIM8_CH2N -Close SB15Open SB14

Remove R62

10 GND - GND - -

11 PWM_3H PC8 TIM8_CH3 -Close SB28


12 GND - GND - -

13 PWM_3L PB1 TIM8_CH3N -Close SB13Open SB12

14 Bus Voltage PC5 ADC12_IN -Close SB16


15PhaseA current+

PC0 ADC123_IN -Close SB34


16PhaseA current-

- GND - -

17PhaseB current+

PC1 ADC123_IN - Close SB36

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2.12.1 Board modifications to enable motor control

Figure 7 (top side) and Figure 8 (bottom side) illustrate the board modifications listed in Table 12, required for the operation of motor control. Red color denotes a component to remove. Green color denotes a component to be fitted.

18PhaseB current-

- GND - -

19PhaseC current+

PC2 ADC123_IN -Close SB42


20PhaseC current-

- GND - -

21 ICL Shutout PG6 GPIO -Close SB5

Remove R35

22 GND - GND - -

23Dissipative

BrakePB2 GPIO -

Close SB11Remove R54

24PFC ind.

curr.PC4 ADC12_IN -


25 +5V - +5V - -

26Heatsink

Temp.PA3 ADC12_IN -


27 PFC Sync PF9 TIM15_CH1 -Close SB25Remove R90

28 +3.3V - +3.3V - -

29 PFC PWM PF10 TIM15_CH2 -Close SB37Remove R91

30PFC

ShutdownPB12 TIM15_BKIN -


31 Encoder A PA0 TIM2_CH1 ADC12_INClose SB35Remove R83

32 PFC Vac PA6 ADC12_IN -Close SB20Open SB21


33 Encoder B PA1 TIM2_CH2 ADC12_INClose SB32


34Encoder

IndexPA2 TIM2_CH3 ADC12_IN


Table 12. Motor control terminal and function assignment (continued)

Motor control connector CN2

STM32L476ZGT6 microcontroller

TerminalTerminal

namePort name Function

Alternate function

Board modifications for enabling motor control


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Figure 7. PCB top-side rework for motor control

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Figure 8. PCB underside rework for motor control

2.12.2 Limitations

Motor control operation is exclusive with LCD glass module, Quad-SPI Flash memory device, audio codec, potentiometer, LDR, smartcard, LED1 drive and the use of sigma-delta modulators.

2.13 CAN

The STM32L476G-EVAL board supports one CAN2.0A/B channel compliant with CAN specification. The CN5 9-pole male connector of DE-9M type is available as CAN interface. A 3.3 V CAN transceiver is fitted between the CN5 connector and the CAN controller port of STM32L476ZGT6.

The JP4 jumper allows selecting one of high-speed, standby and slope control modes of the CAN transceiver. The JP6 jumper can fit a CAN termination resistor in.


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2.13.1 Limitations

CAN operation is exclusive with LCD glass module operation.


The supply voltage for STM32L476G-EVAL CAN operation must be within the range from 3.0 V to 3.6 V.

2.14 Extension connectors CN6 and CN7

The CN6 and CN7 headers complement the LCD glass module daughterboard connector, to give access to all GPIOs of the STM32L476ZGT6 microcontroller. In addition to GPIOs, the following signals and power supply lines are also routed on CN6 or CN7:

GND

+3V3

DSV

RESET#

VDD

Clock terminals PC14-OSC32_IN, PC15-OSC32_OUT, PH0-OSC_IN, PH1-OSC_OUT

Each header has two rows of 20 pins, with 1.27 mm pitch and 2.54 mm row spacing. For extension modules, SAMTEC RSM-120-02-L-D-xxx and SMS-120-x-x-D can be recommended as SMD and through-hole receptacles, respectively (x is a wild card).

2.15 LCD glass module daughterboard

The MB979 daughterboard delivered in the STM32L476G-EVAL package bears a segmented LCD glass module. The daughterboard inserts into CN11 and CN14 extension headers of the main board, each having two rows of pins. The corresponding female

Table 13. CAN related jumpers

Jumper Setting Configuration

JP4

JP4Default settingCAN transceiver operates in high-speed mode

JP4

CAN transceiver is in standby mode

JP6

JP6Default settingNo termination resistor on CAN physical link

JP6

Termination resistor fitted on CAN physical link

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connectors on the daughterboard have three rows of holes each. One raw is routed to segments of the LCD. The other two rows are interconnected and form a series of jumpers.

The way of inserting the LCD glass module daughterboard into CN11 and CN14 headers determines two functions of LCD glass module daughterboard. In its display function, the target MCU terminals are routed to LCD segments. In its I/O-bridge function, they are not. Instead, they transit from one row of CN11 pins to the other and from one row of CN14 pins to the other, thanks to interconnections fitted by the LCD glass module daughterboard.

Figure 9 shows how the LCD glass module daughterboard must be positioned for display function. This position is designated in the document as display position.

Figure 10 shows how the LCD glass module daughterboard must be positioned for I/O-bridge function. This position is designated in the document as I/O-bridge position.

The arrow indicates the side of the CN11 and CN14 headers where the extra row of holes of each female counterpart on the LCD glass module daughterboard has to protrude.

When the LCD glass module daughterboard is not plugged in, CN11 and CN14 give access to ports of the target microcontroller. Figure 36 shows the related schematic diagram.

Table 14 shows the default settings of board configuration elements linked with CN11 and CN14 extension connectors and LCD glass module daughterboard.

Figure 9. LCD glass module daughterboard in display position


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Figure 10. LCD glass module daughterboard in I/O-bridge position

Table 14. LCD-daughterboard-related configuration elements

LCD segment

ElementSetting to enable

LCD glass module

Description

SEG0R82 In PA1 routed to LCDSEG0

SB32 Open PA1 not routed to motor control





SEG3

R68 In PA6 routed to LCDSEG3

SB21 Open PA6 not routed to Quad-SPI Flash memory device


SEG4

R66 In PA7 routed to LCDSEG4

SB18 Open PA7 not routed to Quad-SPI Flash memory device


SEG5

R62 In PB0 routed to LCDSEG5

SB14 Open PB0 not routed to Quad-SPI Flash memory device

SB15 Open PB0 not routed to motor control

SEG6

R56 In PB1 routed to LCDSEG6


SB13 Open PB1 not routed to motor control

SEG10R50 In PB10 routed to LCDSEG10


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The custom LCD glass module used on MB979 daughterboard is XHO5002B. To optimize the number of driving signals, the display elements are connected to eight common planes called COMx (LCDCOMx in the schematic digrams), where “x” can be substituted with figures from “0” to “7”. The other pole of each display element is called segment, SEGy (LCDSEGy in the schematic diagrams), where “y” can be substituted with figures from “0” to “39”. Each combination of COMx and SEGy addresses one display element. Table 15, Table 16, Table 17 and Table 22 show the LCD element mapping. COMx are ordered in rows, SEGy in columns. The table cells then display the display element names






SB6 Open PB13 not routed to Touch sensing

SEG18R97 In PC0 routed to LCDSEG18

SB34 Open PC0 not routed to motor control









SEG24

R36 In PC6 routed to LCDSEG24

SB2 Open PC6 not routed to Touch sensing

SB27 Open PC6 not routed to for motor control

SEG25

R33 In PC7 routed to LCDSEG25

SB4 Open PC7 not routed to Touch sensing

SB30 Open PC7 not routed to for motor control

SEG26 SB28 Open PC8 not routed to motor control

SEG27 SB29 Open PC9 not routed to motor control

SEG38R103 In PE2 routed to LCDSEG38

SB26 Open PE2 not routed to Trace

SEG39 R104 In PE3 routed to LCDSEG39

Table 14. LCD-daughterboard-related configuration elements (continued)

LCD segment

ElementSetting to enable

LCD glass module

Description


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corresponding to each COMx and SEGy combination. Names in quoting marks denote elements forming textual symbols, for example “µA” or “+”. Figure 11 shows the physical location and shape of each segment on the LCD glass module.

Table 15. LCD glass element mapping - segments 0 to 9

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9

COM0 O1 5D Q4 O4 6D Q5 ST 7D Q6 S5

COM1 O2 5K 5L O3 6K 6L “nA” 7K 7L S6

COM2 13b 12b 11b 16b 15b 14b 19b 18b 17b 1b

COM3 13a 12a 11a 16a 15a 14a 19a 18a 17a 1a

COM4 5I 5A 5G 6I 6A 6G 7I 7A 7G 1I

COM5 5B 5H 5F 6B 6H 6F 7B 7H 7F 1B

COM6 5C 5M P4 6C 6M P5 7C 7M P6 1C

COM7 5J 5N 5E 6J 6N 6E 7J 7N 7E 1J



COM0 1D “-” C1 2D Q1 C4 3D Q2 “µA” 4D

COM1 1K 1L C2 2K 2L C3 3K 3L “mA” 4K

COM2 S4 S2 4b 3b 2b 7b 6b 5b 10b 9b

COM3 S3 S1 4a 3a 2a 7a 6a 5a 10a 9a

COM4 1A 1G 2I 2A 2G 3I 3A 3G 4I 4A

COM5 1H 1F 2B 2H 2F 3B 3H 3F 4B 4H

COM6 1M “+” 2C 2M P1 3C 3M P2 4C 4M

COM7 1N 1E 2J 2N 2E 3J 3N 3E 4J 4N



COM0 Q3 1e 2e 3e 4e 5e 6e 7e 8e 9e

COM1 4L 1f 2f 3f 4f 5f 6f 7f 8f 9f

COM2 8b 1c 2c 3c 4c 5c 6c 7c 8c 9c

COM3 8a 1d 2d 3d 4d 5d 6d 7d 8d 9d

COM4 4G 1j 2j 3j 4j 5j 6j 7j 8j 9j

COM5 4F 1i 2i 3i 4i 5i 6i 7i 8i 9i

COM6 P3 1h 2h 3h 4h 5h 6h 7h 8h 9h

COM7 4E 1g 2g 3g 4g 5g 6g 7g 8g 9g

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2.15.1 Limitations

LCD glass module operation is exclusive with all other features of the board.



COM0 10e 11e 12e 13e 14e 15e 16e 17e 18e 19e

COM1 10f 11f 12f 13f 14f 15f 16f 17f 18f 19f

COM2 10c 11c 12c 13c 14c 15c 16c 17c 18c 19c

COM3 10d 11d 12d 13d 14d 15d 16d 17d 18d 19d

COM4 10j 11j 12j 13j 14j 15j 16j 17j 18j 19j

COM5 10i 11i 12i 13i 14i 15i 16i 17i 18i 19i

COM6 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h

COM7 10g 11g 12g 13g 14g 15g 16g 17g 18g 19g

Hard

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re layo

ut an

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ratio

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855

38/1

00D

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Figure 11. LCD glass display element mapping

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2.16 TFT LCD panel

STM32L476G-EVAL is delivered with MB989P, a daughterboard plugged into the CN19 extension connector. It bears a TFT 2.8-inch color LCD panel with resistive touchscreen and an on-board controller. Section 2.18 provides further information.

Thanks to level shifters on all signal lines, the TFT LCD panel can operate with the entire operating voltage range of STM32L476G-EVAL.

The TFT LCD panel is attached to the 16-bit data bus and accessed with FMC. The base address is 0x6800 0000, corresponding to NOR/SRAM3 BANK1. The panel is selected with LCD_NE3 chip select signal generated by PG10 port of the target MCU. Address lines A0 and A1 determine the panel resources addressed, as depicted in Table 19.

Table 20 gives the CN19 extension connector terminal assignment.

Table 19. Access to TFT LCD resources with FMC address lines A0 and A1

Address A1 A0 Usage

0x6800_0000 0 0 Read register

0x6800_0002 0 1 Read Graphic RAM (GRAM)

0x6800_0004 1 0 Write register

0x6800_0006 1 1 Write graphic RAM (GRAM)

Table 20. Assignment of CN19 connector terminals of TFT LCD panel

CN19terminal

Terminalname

MCUport

CN19terminal

Terminalname

MCUport

1 CSN PG10 2 RS PF0

3 WRN PD5 4 RDN PD4

5 RSTN RESET# 6 D0 PD14

7 D1 PD15 8 D2 PD0

9 D3 PD1 10 D4 PE7

11 D5 PE8 12 D6 PE9

13 D7 PE10 14 D8 PE11

15 D9 PE12 16 D10 PE13

17 D11 PE14 18 D12 PE15

19 D13 PD8 20 D14 PD9

21 D15 PD10 22 BL_GND -

23 BL_CONTROL - 24 +3V3 -

25 +3V3 - 26 26 -

27 GND - 28 BL_VDD -

29 SDO - 30 SDI -

31 XL I/O expander_X- 32 XR I/O expander_X+

33 YD I/O expander_Y- 34 YU I/O expander_Y+


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2.17 User LEDs

Four general-purpose color LEDs (LD1, LD2, LD3, LD4) are available as light indicators. Each LED is in light-emitting state with low level of the corresponding control port. They are controlled either by the STM32L476ZGT6 target MCU or by the I/O expander IC U32, named IOExpander1 in the schematic diagram. Table 21 gives the assignment of control ports to the LED indicators.

2.18 Physical input devices

The STM32L476G-EVAL board provides a number of input devices for physical human control. These are:

four-way joystick controller with select key (B3)

wake-up/ tamper button (B2)

reset button (B1)

resistive touchscreen of the TFT LCD panel

10 kΩ potentiometer (RV3)

light-dependent resistor, LDR (R52)

Table 22 shows the assignment of ports routed to the physical input devices. They are either ports of the STM32L476ZGT6 target MCU or of one of the two /O expander ICs on the board, named, in the schematic diagrams, IOExpander1 and IOExpander2.

Table 21. Port assignment for control of LED indicators

User LED Control port Control device

LED1 (Green) PB2 target MCU

LED2 (Orange) GPIO0 IOExpander1

LED3 (Red) PC1 target MCU

LED4 (Blue) GPIO2 IOExpander1

Table 22. Port assignment for control of physical input devices

Input device Control port Control device

Joystick SEL GPIO0 IOExpander2

Joystick DOWN GPIO1 IOExpander2

Joystick LEFT GPIO2 IOExpander2

Joystick RIGHT GPIO3 IOExpander2

Joystick UP GPIO4 IOExpander2

Wake-up/ tamper B2 PC13 target MCU

Reset B1 NRST target MCU

Resistive touch screen X+ X+ IOExpander1

Resistive touch screen X- X- IOExpander1

Resistive touch screen Y+ Y+ IOExpander1

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The potentiometer and the light-dependent resistor can be routed, mutually exclusively, to either PB4 or to PA0 port of the target MCU. Table 23 depicts the setting of associated configuration jumpers.

As illustrated in the schematic diagram in Figure 46, the PB4 port is routed, in the STM32L476ZGT6 target MCU, to the non-inverting input of comparator Comp2. The PA0 is routed to non-inverting input of operational amplifier OpAmp1. However, depending on register settings, it can also be routed to ADC1 or to ADC2.

2.18.1 Limitations

The potentiometer and the light-dependent resistor are mutually exclusive.

2.19 Operational amplifier and comparator

2.19.1 Operational amplifier

STM32L476ZGT6 provides two on-board operational amplifiers, one of which, OpAmp1, is made accessible on STM32L476G-EVAL. OpAmp1 has its inputs and its output routed to I/O ports PA0, PA1 and PA3, respectively. The non-inverting input PA0 is accessible on the terminal 1 of the JP7 jumper header. On top of the possibility of routing either of the

Resistive touch screen Y- Y- IOExpander1

Potentiometer PB4 or PA0 target MCU

LDR PA0 or PB4 target MCU

Table 23. Setting of jumpers related with potentiometer and LDR

Jumper Setting Routing

JP5JP7

JP5 JP7

Potentiometer is routed to pin PB4 of STM32L476ZGT6.

JP5JP7

JP5 JP7Default setting.Potentiometer is routed to pin PA0 of STM32L476ZGT6.

JP5JP7

JP5 JP7

LDR is routed to pin PB4 of STM32L476ZGT6.

JP5JP7

JP5 JP7

LDR is routed to pin PA0 of STM32L476ZGT6.

Table 22. Port assignment for control of physical input devices (continued)

Input device Control port Control device


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potentiometer or LDR to PA0, en external source can also be connected to it, using the terminal 1 of JP7.

The PA3 output of the operational amplifier can be accessed on test point TP9. Refer to the schematic diagram in Figure 46.

The gain of OpAmp1 is determined by the ratio of the variable resistor RV2 and the resistor R121, as shown in the following equation:

With the RV2 ranging from 0 to 10 kΩ and R121 being 1 kΩ, the gain can vary from 1 to 11.

The R63 resistor in series with PA0 is beneficial for reducing the output offset.

2.19.2 Comparator

STM32L476ZGT6 provides two on-board comparators, one of which, Comp2, is made accessible on STM32L476G-EVAL. Comp2 has its non-inverting input and its output routed to I/O ports PB4 and PB5, respectively. The input is accessible on the terminal 3 of the JP7 jumper header. On top of the possibility of routing either of the potentiometer or LDR to PB4, en external source can also be connected to it, using the terminal 3 of JP7.

The PB5 output of the comparator can be accessed on test point TP6. Refer to the schematic diagram in Figure 46.

2.20 Analog input, output, VREF

STM32L476ZGT6 provides on-board analog-to-digital converter, ADC and, digital-to-analog converter, DAC. The port PA4 can be configured to operate either as ADC input or as DAC output. PA4 is routed to the two-way header CN8 allowing to fetch signals to or from PA4 or to ground it by fitting a jumper into CN8.

Parameters of the ADC input low-pass filter formed with R72 and C47 can be modified by replacing these components according to application requirements. Similarly, parameters of the DAC output low-pass filter formed with R73 and C47 can be modified by replacing these components according to application requirements.

The VREF+ terminal of STM32L476ZGT6 is used as reference voltage for both ADC and DAC. By default, it is routed to VDDA through a jumper fitted into the two-way header CN10. The jumper can be removed and an external voltage applied to the terminal 1 of CN10, for specific purposes.

2.21 SRAM device

IS61WV102416BLL, a 16-Mbit static RAM (SRAM) silicon device, 1 M x16 bit, is fitted on the STM32L476G-EVAL main board, in U2 position. The PCB of STM32L476G-EVAL main board as well as the addressing capabilities of FMC allow hosting SRAM devices up to 64 Mbytes. This is the reason why the schematic diagram in Figure 41 mentions several SRAM devices.

The SRAM device is attached to the 16-bit data bus and accessed with FMC. The base address is 0x6000 0000, corresponding to NOR/SRAM1 BANK1. The SRAM device is

Gain 1 RV2 R121 +=

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selected with FMC_NE1 chip select. FMC_NBL0 and FMC_NBL1 signals allow selecting 8-bit and 16-bit data word operating modes.

By removal of R18, a zero-ohm resistor, the SRAM is deselected and the target MCU ports PD7, PE0 and PE1 corresponding to FMC_NE1, FMC_NBL0 and FMC_NBL1 signals, respectively, can be used for other application purposes.

2.21.1 Limitations

The SRAM addressable space is limited if some or all of A19, A20,A21, A22, A23 FMC address lines are shunted to the CN12 connector for debug trace purposes. In such a case, the disconnected addressing inputs of the SRAM device are pulled down by resistors. Section 2.2 provides information on the associated configuration elements.


The SRAM device operating voltage is in the range from 2.4 V to 3.6 V.

2.22 NOR Flash memory device

M29W128GL70ZA6E, a 128-Mbit NOR Flash memory silicon device, 8 M x16 bit, is fitted on the STM32L476G-EVAL main board, in U5 position. The PCB of STM32L476G-EVAL main board as well as the addressing capabilities of FMC allow hosting M29W256GL70ZA6E, a 256-Mbit NOR Flash memory device. This is the reason why the schematic diagram in Figure 41 mentions both devices.

The NOR Flash memory device is attached to the 16-bit data bus and accessed with FMC. The base address is 0x6400 0000, corresponding to NOR/SRAM2 BANK1. The NOR Flash memory device is selected with FMC_NE2 chip select signal. 16-bit data word operation mode is selected by a pull-up resistor connected to BYTE terminal of NOR Flash memory. The jumper JP13 is dedicated for write protect configuration.

By default, the FMC_NWAIT signal is not routed to RB port of the NOR Flash memory device, and, to know its ready status, its status register is polled by the demo software fitted in STM32L476G-EVAL. This can be modified with configuration elements, as shown in Table 25.

Table 24. SRAM chip select configuration

Resistor Fitting Configuration

R18In

Default setting.SRAM chip select is controlled with FMC_NE1

Out SRAM is deselected. FMC_NE1 is freed for other application purposes.


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2.22.1 Limitations

FMC_NWAIT and SAI1_SDA signals are mutually exclusive.

The NOR Flash memory device’s addressable space is limited if some or all of A19, A20,A21, A22, A23 FMC address lines are shunted to the CN12 connector for debug trace purposes. In such a case, the disconnected addressing inputs of the NOR Flash memory device are pulled down by resistors. Section 2.2 provides information on the associated configuration elements.


NOR Flash memory device’s operating voltage must be in the range from 1.65 V to 3.6 V.

2.23 EEPROM

M24128-DFDW6TP, a 128-Kbit I²C-bus EEPROM device, is fitted on the main board of STM32L476G-EVAL, in U6 position. it is accessed with I²C-bus lines I2C2_SCL and I2C2_SDA of STM32L476ZGT6. It supports all I²C-bus modes with speeds up to 1 MHz. The base I²C-bus address is 0xA0. Write-protecting the EEPROM is possible through opening the SB7 solder bridge. By default, SB7 is closed and writing into the EEPROM enabled.


The M24128-DFDW6TP EEPROM device’s operating voltage must be in the range from 1.7 V to 3.6 V

2.24 RF-EEPROM

RF-EEPROM daughterboard, ANT7-M24LR-A, can be connected to CN3 connector of the STM32L476G-EVAL board. STM32L476ZGT6 can access the RF-EEPROM in two ways,

Table 25. NOR Flash memory-related configuration elements

Element Setting Configuration

JP13

JP13Default setting.NOR Flash memory write is enabled.

JP13

NOR Flash memory write is inhibited. Write protect is activated.

R53SB10

R53 InSB10 open

Default setting.PD6 port of target MCU is used for SAI1_SDA signal and routed to audio codec.NOR Flash memory device’s status register can be accessed.

R53 OutSB10 closed

PD6 port of target MCU is used for FMC_NWAIT signal and routed to NOR Flash memory device’s RB port.NOR Flash memory device’s status register cannot be accessed.

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wired through I²C bus or wireless using 13.56 MHz RF band reserved for RFID and NFC equipment. For wireless access, CR95HF reader daughterboard plugged in the CN13 connector can be used, for example.

I²C address of RF-EEPROM device MB1020 A-02 is 0xA6.

2.25 Quad-SPI Flash memory device

N25Q256A13EF840E, a 256-Mbit Quad-SPI Flash memory device, is fitted on the STM32L476G-EVAL main board, in U9 position. It allows evaluating the STM32L476ZGT6 target MCU’s Quad-SPI Flash memory device interface.

N25Q256A13EF840E can operate in single transfer rate (STR) and double transfer rate (DTR) modes.

By default, the Quad-SPI Flash memory device is not accessible. Table 26 shows the configuration elements and their settings allowing to access the Quad-SPI Flash memory device. The LCD glass module daughterboard MB979 takes active part in the configuration. It must be removed from the main board (denoted as “MB979 out”), to operate the Quad-SPI Flash memory device. Section 2.12: Motor control provides additional information.

Table 26. Configuration elements related with Quad-SPI device


SB12SB13

MB979

SB12 openSB13 open

Default setting.QSPI_D0 data line is not available at Quad-SPI Flash memory device:PB1 port of target MCU is only routed to CN11 connector for the MB979 daughterboard.

SB12 closedSB13 openMB979 out

QSPI_D0 data line is available at Quad-SPI Flash memory device:PB1 port of target MCU is routed to DQ0 port of Quad-SPI Flash memory device.

SB14SB15

MB979

SB14 openSB15 open

Default setting.QSPI_D1 data line is not available at Quad-SPI Flash memory device:PB0 port of target MCU is only routed to CN11 connector for the MB979 daughterboard.


QSPI_D1 data line is available at Quad-SPI Flash memory device:PB0 port of target MCU is routed to DQ1 port of Quad-SPI Flash memory device.

SB18SB19

MB979

SB18 openSB19 open

Default setting.QSPI_D2 data line is not available at Quad-SPI Flash memory device:PA7 port of target MCU is only routed to CN11 connector for the MB979 daughterboard.


QSPI_D2 data line is available at Quad-SPI Flash memory device:PA7 port of target MCU is routed to DQ2 port of Quad-SPI Flash memory device.


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2.25.1 Limitations

Quad-SPI operation is exclusive with LCD glass module and with motor control.


Voltage of Quad-SPI Flash memory device N25Q256A13EF840E is in the range of 2.7 V to 3.6 V.

2.26 Touch-sensing button

The STM32L476G-EVAL evaluation board supports a touch sensing button based on either RC charging or on charge-transfer technique. The latter is enabled, by default.

The touch sensing button is connected to PB12 port of the target MCU and the related charge capacitor is connected to PB13.

An active shield is designed in the layer two of the main PCB, under the button footprint. It allows reducing disturbances from other circuits to prevent from false touch detections.

The active shield is connected to PC6 port of the target MCU through the resistor R37.The related charge capacitor is connected to PC7.

Table 27 shows the configuration elements related with the touch sensing function. Some of them serve to enable or disable its operation. However, most of them serve to optimize the touch sensing performance, by cutting copper tracks to avoid disturbances due to their antenna effect.

SB21SB20

MB979

SB21 openSB20 open

Default setting.QSPI_D3 data line is not available at Quad-SPI Flash memory device:PA6 port of target MCU is only routed to CN11 connector for the MB979 daughterboard.


QSPI_D3 data line is available at Quad-SPI Flash memory device:PA6 port of target MCU is routed to DQ3 port of Quad-SPI Flash memory device.

SB9MB979

SB9 open

Default setting.QSPI_CLK clock line is not available at Quad-SPI Flash memory device:PB10 port of target MCU is only routed to CN11 connector for the MB979 daughterboard.

SB9 closedMB979 out

QSPI_CLK clock line is available at Quad-SPI Flash memory device:PB10 port of target MCU is routed to C port of Quad-SPI Flash memory device.

SB8MB979

SB8 open

Default setting.QSPI_CS line is not available at Quad-SPI Flash memory device:PB11 port of target MCU is only routed to CN11 connector for the MB979 daughterboard.

SB8 closedMB979 out

QSPI_CS line is available at Quad-SPI Flash memory device:PB11 port of target MCU is routed to S# port of Quad-SPI Flash memory device.

Table 26. Configuration elements related with Quad-SPI device (continued)


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Table 27. Touch-sensing-related configuration elements


R39

InDefault setting. PB12 port is routed to CN11 connector for LCD glass module daughterboard.This setting is not good for robustness of touch sensing.

OutPB12 port is cut from CN11.This setting is good for robustness of touch sensing.

SB3

OpenDefault setting. PB12 is not routed to motor control.This setting is good for robustness of touch sensing.

ClosedPB12 is routed to motor control.This setting is not good for robustness of touch sensing.

R38

InDefault setting. PB13 port is routed to CN11 connector for LCD glass module daughterboard.This setting is not good for robustness of touch sensing.

OutPB13 port is cut from CN11.This setting is good for robustness of touch sensing.

SB6Open

Default setting. PB13 is not routed to sampling capacitor. Touch sensing cannot operate.

Closed PB13 is routed to sampling capacitor. Touch sensing can operate.

R36

InDefault setting. PC6 port is routed to CN14 connector for LCD glass module daughterboard.This setting is not good for robustness of touch sensing.

OutPC6 port is cut from CN14.This setting is good for robustness of touch sensing.

SB2

OpenDefault setting. PC6 is not routed to active shield under the touch-sensing button.This setting is not good for robustness of touch sensing.

ClosedPC6 is routed to active shield under the touch-sensing button.This setting is good for robustness of touch sensing.

SB27

OpenDefault setting. PC6 port of target MCU is not routed to motor control. This setting is good for robustness of touch sensing.

ClosedPC6 is routed to motor control.This setting is not good for robustness of touch sensing.

R33

InDefault setting. PC7 port is routed to CN14 connector for LCD glass module daughterboard.This setting is not good for robustness of touch sensing.

OutPC7 port is cut from CN14.This setting is good for robustness of touch sensing.

SB4

OpenDefault setting. PC7 port of target MCU is not routed to sampling capacitor of the active shield under the touch-sensing button.This setting is not good for robustness of touch sensing.

ClosedPC7 is routed to sampling capacitor of the active shield under the touch-sensing button.This setting is good for robustness of touch sensing.


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2.26.1 Limitations

Touch sensing button is exclusive with LCD glass module, thermal sensor PT100 via sigma-delta conversion, USB OTG FS port operating as USB host, SWP, NFC.

2.27 Smartcard, SWP

ST8024CDR, an interface IC for 3 V and 5 V asynchronous smartcards, is fitted on the STM32L476G-EVAL main board, in U30 position. ST8024CDR performs all supply protection and control functions of the smartcard.

ST8024CDR is controlled, on its turn, by the target MCU, directly through its ports or indirectly through ports of the U33 I/O expander IC (IOExpander2), as shown in Table 28.

The SWIO port of the smartcard for single-wire protocol (SWP) communication is managed directly by PB12 port of the target MCU.

Table 29 provides information on configuration elements related with smartcard operation. Refer to Table 8, Table 12,Table 26 andTable 27 for complementary information. Bridging of CN11 and CN14 rows of I/Os can be done by means of the MB979 daughterboard plugged into CN11 and CN14 in I/O-bridge position, as explained in Section 2.15.

SB30

OpenDefault setting. PC7 port of target MCU is not routed to motor control.This setting is good for robustness of touch sensing.

ClosedPC7 is routed to motor control. This setting is not good for robustness of touch sensing.

Table 27. Touch-sensing-related configuration elements (continued)


Table 28. Assignment of ports for ST8024CDR control

ST8024CDR port

Function Control port

5V/3V Smartcard power supply selection pin. IOexpander2 GPIO7

I/OUC Data I/O line target MCU PC4

XTAL1 Quartz crystal or external clock input target MCU PB0

OFF Card presence detect IOexpander2 GPIO8

RSTIN Card reset command input IOexpander2 GPIO5

CMDVCC Activation sequence start command input (active low) IOexpander2 GPIO6

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Table 29. Configuration elements related with smartcard and SWP


R39SB3R109CN11

R109 inR39 in

SB3 openCN11 I/O-bridged

Default setting.Smartcard SWP cannot be handled:PB12 is routed to USB OTG FS port as USBOTG_OVRCR line, on top of being routed to SWIO port of smartcardConfiguration dedicated for USB OTG FS operation.

R109 outR39 in

SB3 openCN11 I/O-bridged

Smartcard SWP can be handled:PB12 is routed to SWIO port of smartcard. It is disconnected from any other resource that could affect the SWP operationConfiguration dedicated for smartcard SWP operation

R39 outSB3 closed

Smartcard SWP cannot be handled:PB12 is routed to motor control as MC_PFC_ShutdownConfiguration dedicated for motor control operation

R39 outSB3 open

Smartcard SWP cannot be handled:PB12 is only routed to touch-sensing button and it is disconnected from any other resource.Configuration dedicated for touch-sensing button operation.

R62SB14SB15

R62 inSB14 openSB15 open

CN11 I/O-bridged

Default setting.Smartcard controller U30 is supplied with clock:PB0 port is routed to XTAL1 of U30, as SmartCard_CLK line and it is not routed to other resources.Configuration dedicated for smartcard operation.

R62 outSB14 closedSB15 open

Smartcard controller U30 is not supplied with clock:PB0 is routed to Quad-SPI Flash memory device as QSPI_D1 and it is not routed to other resources.Configuration dedicated for Quad-SPI Flash memory device operation.

R62 outSB14 open

SB15 closed

Smartcard controller U30 is not supplied with clock:PB0 is routed to motor control as MC_PWM_2L line and it is not routed to other resources.Configuration dedicated for motor control operation.

R65SB17CN14

R65 inSB17 open

CN14 I/O-bridged

Default setting.Smartcard controller gets SmartCard_IO line:PC4 port of MCU is routed to IOUC port of U30, as SmartCard_IO line and it is not routed to other resources.Configuration dedicated for smartcard operation.

R65 outSB17 closed

Smartcard controller does not get SmartCard_IO line:PC4 port of MCU is routed to motor control as MC0PFC0IndCur line and it is not routed to other resources.Configuration dedicated for motor control operation.


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2.27.1 Limitations

The following limitations apply for the smartcard operation:

Smartcard operation is mutually exclusive with LCD glass module, Quad-SPI Flash memory device and motor control operation.

SWP operation is mutually exclusive with LCD glass module, touch-sensing button, motor control and USB OTG FS port operation, if the last operates as USB host. SWP can operate concurrently with USB OTG FS port acting as USB device.


Smartcard operating ranging from VDD = 2.7 V to VDD = 3.6 V. However, the SWP only operates with the supply voltage of 3.3 V.

2.28 Near-field communication (NFC)

The STM32L476G-EVAL board can host an NFC transceiver board plugged in CN13 extension connector. CR95HF-B NFC board can be used, for example.

Figure 12 illustrates the way of attaching an NFC board.

Figure 12. NFC board plugged into STM32L476G-EVAL board

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Table 30 shows the assignment of signals to CN13 connector.

The serial communication with the module plugged in CN13 can either used SPI lines and communication protocol (default) or, UART_RX and UART_Tx lines and UART communication protocol.

2.29 Dual-channel sigma-delta modulators STPMS2L

2.29.1 STPMS2L presentation

With its DFSDM interface, the STM32L476ZGT6 microcontroller can directly interact with sigma-delta modulator ICs, such as STPMS2L.

STPMS2L comprises two analog measuring channels based on second-order sigma-delta modulators. Typically, it can be used in power metering where both voltage and current need to be known.One channel measures the voltage, the other channel measures the current.

DAT port outputs converted measurement data on the DFSDM_DATIN1 line, received by the target MCU’s DFSDM controller. The data from STPMS2L are synchronized with DFSDM_CKOUT clock generated by the target MCU DFSDM controller and received on CLK terminal of STPMS2L.

There are two STPMS2L ICs on STM32L476G-EVAL, sharing the DFSDM clock. One is wired such as to support a power-metering demonstrator. The other allows measuring temperature using the PT100 sensor.

Table 30. CN13 NFC connector terminal assignment

CN13 terminal

NFC line name MCU port Function

1NFC_IRQOUTN or

UART_TXPB7

Interrupt output for NFC deviceConnected to STM32L476ZGT6 UART RX

2NFC_IRQINN or

UART_RXPB6

Interrupt input for NFC device

Connected to STM32L476ZGT6 UART TX

3 NFC_NSS PF11 SPI slave select

4 NFC_MISO PB14 SPI data, slave output

5 NFC_MOSI PB15 SPI data, slave input

6 NFC_SCK PB13 SPI serial clock

7 +3V3 - Main power supply/power supply for RF drivers

8 GND - Ground


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Figure 13. Routing of STPMS2L dual-channel sigma-delta modulators

2.29.2 STPMS2L settings

STPMS2L operating parameters are set through its configuration terminals MS0, MS1, MS2 and MS3. On STM32L476G-EVAL, both ICs are configured as follows:

voltage channel range: differential voltage +/- 300mV

current channel range: differential voltage +/- 300mV

internal voltage reference is used

input bandwidth: 0 to 1 kHz

temperature compensation: flattest +30ppm/°C

DAT output: voltage and current samples multiplexed

DATn output: not used

HW mode selected for settings

2.29.3 STPMS2L power metering

STPMS2L in U3 position simulates low-voltage AC power metering, with capacitive load impedance, to give different phase to voltage and current.

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Figure 14. Power measurement principle schematic diagram

A low-voltage AC generator is to be applied by the user as shown in Figure 14. The shunt resistor is connected in series with the load to provide current measurement points to one of STPMS2L input channels. The voltage measurement points for the other input channel are taken across the load. Figure 15 shows an extract of the corresponding schematic diagram.

Warning: do not connect AC mains!

Test example:

The output of a low-voltage AC generator is connected to CN4, terminals 1 and 3. The amplitude is set between 200 mV and 300 mV and the frequency adjustable between 10 Hz and 100 Hz.

With 34 Hz frequency and the load formed of R27 of 1 kΩ in parallel with C29 of 4.7 µF, the voltage and current phases are theoretically 45 degrees apart.

Figure 15. STPMS2L power metering schematic diagram

STPMS2 power metering

R261K

GND

GND

GND

GND

C26

100nF

GND

GND

R271K

GNDR+jX Load

current shunt

external generator input: pins 1 and 3voltage of complex load: pins 2 and 3 shunt voltage : pins 1 and 2

VDD

VCC

1

VDDAC

2

VDDA

3

VBG

4

DATn 16

DAT 15

CLK 14

MS3 13

MS2

12

MS1

11

MS0

10

VDDAV

9

VIP8

VIN7

CIP6

CIN5

GND

17

AV

Exposed pad GND

U3STPMS2L-PUR

32

1

CN4

GND C29

4.7u

F

C27

1uF

C22

1uF

C24

1uF


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2.29.4 STPMS2 for PT100 measurement

PT100 is a resistor with temperature-dependent resistance.

Usually, one of two methods is used for measuring temperature with a temperature-dependent resistor. In the first method, a known current is driven through the measuring resistor. The temperature is represented by the voltage measured across the resistor. In the second method, a known voltage is applied on the resistor and the current flowing through is measured, representing the temperature. In these methods, either an accurate current source or an accurate voltage source is required.

With the dual-input measurement with STPMS2L in U4 position, no such accurate current or voltage sources are required. Instead, a precision shunt resistor is required. One channel of the STPMS2L measures the voltage across the precise shunt resistor, representing the current flowing through PT100. The other channel measures the voltage across PT100.

Figure 16. Temperature measurement principle schematic diagram

With voltage across and current through the PT100 resistor, the STM32L476ZGT6 microcontroller computes resistance PT100.

For temperatures lower than +100°C, the temperature is given by the following equation, where PT100 is resistance of the PT100 resitor and T is temperature in degrees centigrade:

2.29.5 Limitations

Operating voltage must be in the range from 3.2 V to 3.6 V.

2.30 MCU current consumption measurement

The STM32L476ZGT6 target MCU has a built-in circuit allowing to measure its own current consumption (IDD) in Run and Low-power modes, except for Shutdown mode.

It is strongly recommended that, the MCU supply voltage (VDD_MCU line) does not exceed 3.3 V. This is because there are components on STM32L476G-EVAL supplied from 3.3 V

T PT100 100– 0.385 =

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that communicate with the MCU through I/O ports. Voltage exceeding 3.3 V on the MCU output port may inject current into 3.3 V-supplied peripheral I/Os and false the MCU current consumption measurement.

2.30.1 IDD measurement principle - analog part

The analog part is based on measuring voltage drop across a shunt resistor, amplified with a differential amplifier. The STM32L476ZGT6 microcontroller supply current is shunted, by jumper settings, to flow through the measurement 1 Ω resistor R135: JP11 terminals 1 and 2 are to be open, terminals 3 and 4 closed. When the transistor T2 is in conductive state, the MCU supply current is proportional to the voltage across R135. When T2 is in high-impedance state, the MCU supply current is proportional to the voltage across the series of R135 and R123. The former state is used for measuring the current consumption in dynamic run mode, the latter in Low-power mode.

The differential amplifier uses three stages U15B, U15C, U15D of quadruple operational amplifier device U15, TSZ124. The gain is set to 50, so every 1 mA of supply current is represented by additional 50 mV at the U15C output, terminal 8 of U15.

The resistance formed with the series of R135 and R123, when T2 is in high-impedance state, is of 1001 Ω. It makes the voltage on terminal 8 of U15 increase by approximately 50 mV for every µA of MCU power consumption. The full-scale range, with VDD at 1.8 V is about 30 µA.

Even with precision resistors R136, R125, R129, R132 to set the gain of the differential amplifier, the output voltage may theoretically become negative. To avoid the need of negative power supply, a positive offset of about 220 mV is created at the output, at zero current consumption of the MCU. This offset does not need to be precise. Any dispersion is compensated through a calibration procedure detailed in Section 2.30.4.

For allowing the IDD measurement, the jumper in the JP11 header must be placed such as to short its terminals 3 and 4.


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Figure 17. Schematic diagram of the analog part of IDD measurement

2.30.2 Low-power-mode IDD measurement principle - logic part

The target microcontroller can only carry out actions for measuring a voltage when in dynamic run mode. This is the reason why, voltage representing the current consumed by the microcontroller when in low-power mode needs to be held by a sample-and-hold circuit, for being exploited by the microcontroller at a later time, when back in dynamic run mode. The sample-and-hold (S&H) circuit is built with U13 switch, R122 resistor and C73 sampling capacitor.

The measurement of low-power-mode current consumption is started and end by the microcontroller in its dynamic run mode. As, between the start and end event, the microcontroller must transit through one of its low-power modes, an extra logic is required to time and control events during this state. It consists of U14 counter, U16 inverter and the transistor T3. Figure 18 shows the corresponding schematic diagram.

VDD

R1351[1%]

R1231K[1%]3

4

5G

SD 1

26

T2

FDC606P

VDD_MCU

R136

3K6 0.1%

R125

3K6 0.1%

R129

180K 0.1%

R132

180K 0.1%

GND

+5V

C75100nF

GND

GND

decoupling capacitorclose from TSZ124 part

1

4

3

2

11

V+

V-

U15ATSZ124IPT

75

6

U15BTSZ124IPT

1412

13

U15DTSZ124IPT

810

9

U15CTSZ124IPT

R12822K

R1241K

Shunt_x1000

Current direction

to MCU

bypass path currentmeasurement path

differentialamplifier

shunts

C144100nF

GND

1 2 3 4JP11

Current direction

VDD from power supply

DocID027351 Rev 2 57/100


99

Figure 18. Schematic diagram of logic part of low-power-mode IDD measurement

The measurement process consists of 3 phases:

Phase 1 - start and transiting to low-power modeWhile in dynamic run mode, the MCU sets IDD_CNT_EN signal on its PF10 port low, starting the measurement process. This makes the counters in U14 start counting the clock pulses generated with an own RC oscillator. At about 150 ms from the start, the Q12 output of U14 goes high, terminating the phase 1. After starting the measurement process, the MCU transits to low-power mode. The duration of the phase 1 of about 150ms allows the MCU enough time for transiting into low-power mode.

Phase 2 - samplingThe MCU is now in low-power mode. The phase 2 starts with the Q12 port of U14 going high, 150 ms after the MCU, at that time in dynamic run mode, started the low-power-mode consumption current measurement process. The transistor T2 goes in high-impedance mode, which results in setting the analog part in high sensitivity state, needed for measuring very low currents. The Q13 port of U14 keeps the path between ports I/O and O/I of U13 conductive. The sampling capacitor C73 is charged through the resistor R122 to the voltage at the output of the differential analog amplifier, representing the current consumed by the MCU in low-power mode. The duration of the phase 2 is about 150 ms. This time is needed to allow the voltage on the sampling capacitor C73 to stabilize.

Phase 3 - exiting low-power mode, measurement and endThe MCU is in low-power mode. The voltage across C73 capacitor is now stabilized so it represents the current consumed by the MCU in low-power mode. The phase 3 starts with setting the U13 path between ports O/I and I/O to non-conductive state, for the voltage across C73 to hold. The same event causes the IDD_WAKEUP signal for the MCU to change state, to signal to the MCU that the voltage on C73 is now ready for being measured. The MCU transits from low-power mode to dynamic run mode. The voltage on C73 representing the current the MCU consumed when it was in low-power mode, is now measured by the MCU, using the ADC port PA5, and stored. The Q12 port transits to low state at the same time as the Q13 goes high. As a consequence, the analog part of the IDD measurement circuit is back to low-sensitivity mode adapted for measuring the microcontroller supply current in its dynamic run mode. The phase 3 and the whole measurement process ends with the microcontroller setting the IDD_CNT_EN signal back high. Figure 19 illustrates the timing of the low-power-mode current consumption measurement process.

IDD_Measurement

IDD_CNT_EN

IDD_WAKEUP

2

3

4

5

U16SN74LVC1G04DCKT

I/O1 O/I 2

GND3 C4

VCC 5

U13

SN74LVC1G66DCKT3

4

5G

SD 1

26

T3

FDC606P

VDD

Q111

Q122

Q133

Q54

Q45

Q66

Q37

GND8 Ctc 9Rtc 10RS 11MR 12Q8 13Q7 14Q9 15VCC 16U14

74LV4060PW

VDD

VDD

R127

220K

R122

10KVDD

C771nF

R13415K

R13030K

Oscillator frequency 30KHz

VDDC72100nF

PC5

PF10

PA58

U15CTSZ124IPT

Shunt_x1000

C73

1uF

R137220K

C74

100nF

C76

100nF


58/100 DocID027351 Rev 2

Figure 19. Low power mode IDD measurement timing

2.30.3 IDD measurement in dynamic run mode

In dynamic run mode, the IDD_CNT_EN remains high. The T2 is in conductive state, setting the shunt resistor to 1 Ω. The U13 path from port 1 to 2 is permanently conductive and the voltage on the capacitor C73 follows the MCU current consumption. R122 allows filtering fast changes.

2.30.4 Calibration procedure

For the measurement to be precise, it is mandatory to perform a calibration before the measurement. The calibration allows subtracting, from the voltage measured across C73, the offset at the differential amplifier output, described in Section 2.30.1.

The calibration procedure consists in measuring the offset voltage when the current through the shunt resistor is zero. The current consumption values measured by the microcontroller are then compensated for offset, by subtracting the now-known offset number from the measured number. Setting the current through the shunt resistor to zero is reached through appropriate setting jumpers in the JP11 jumper header.

DocID027351 Rev 2 59/100


99

Calibration procedure and current measurement compensation steps:

On JP11, short terminals 1,2 and open terminals 3,4. The current through the shunt resistor is now zero.

Run low-power-mode IDD measurement as described in Section 2.30.2. The value Voffset measured corresponds to offset of the differential amplifier.

On JP11, add a second jumper, to short terminals 3 and 4, then remove the jumper from terminals 1,2 of JP11. The MCU supply has not been interrupted and the supply current now passes through the shunt resistor.

Run low-power-mode IDD measurement as described in Section 2.30.2. The value Vmeasured obtained corresponds to the sum of MCU supply current and the differential amplifier’s offset Voffset.

The software computes a Vout number representing the MCU supply current asVout = Vmeasured - Voffset

Table 31. JP11 jumper settings during IDD measurement with calibration

Jumper Setting Description

JP11

JP11 Default setting.Configuration used to measure Voffset.STM32L476ZGT6 supply current does not flow through shunt resistor.

JP11Configuration to transit from direct to shunted supply to STM32L476ZGT6, without ever interrupting the MCU supply.

JP11Configuration used to measure the MCU supply current.STM32L476ZGT6 supply current flows through shunt resistor.

1 2 3 4

1 2 3 4

1 2 3 4

Connectors UM1855

60/100 DocID027351 Rev 2

3 Connectors

3.1 RS-232 D-sub male connector CN9

Figure 20. RS-232 D-sub (DE-9M) 9-pole connector (front view)

3.2 Power connector CN22

The STM32L476G-EVAL board can be powered from a DC-5V external power supply via the CN2 jack illustrated in Figure 21. The central pin of CN22 must be positive.

Figure 21. Power supply connector CN2 (front view)

Table 32. RS-232 D-sub (DE-9M) connector CN9 with HW flow control and ISP support

Terminal Terminal name Terminal Description

1 NC 6 Bootloader_BOOT0

2 RS232_RX (PB7) 7 NC

3 RS232_TX (PG12) 8 Bootloader_RESET

4 NC 9 NC

5 GND - -

DocID027351 Rev 2 61/100

UM1855 Connectors

99

3.3 LCD daughterboard connectors CN11 and CN14

Two 48-pin male headers CN11 and CN14 are used to connect to LCD glass module daughterboard MB979. The type of connectors, their mutual orientation, distance and terminal assignment are kept for a number of ST MCU evaluation boards. This standardization allows developing daughterboards that can be used in multiple evaluation kits. The width between CN11 pin1 and CN14 pin1 is 700 mils (17.78 mm).

MCU ports routed to these two connectors can be accessed on odd CN11 and CN14 pins (the row of pin 1), when no daughterboard is plugged in.

Daughterboards plugging into CN11 and CN14 must keep the even terminals of CN11 and CN14 open.

Table 33 shows the signal assignment to terminals.

Table 33. CN11 and CN14 daughterboard connectors

CN11 CN14

Odd pin MCU port Odd pin MCU port

1 PA9 1 PD2

3 PA8 3 PC12

5 PA10 5 PC11

7 PB9 7 PC10

9 PB11 9 PC3

11 PB10 11 PC4

13 PB5 13 PC5

15 PB14 15 PC6

17 PB13 17 PC7

19 PB12 19 PC8

21 PA15 21 PC9

23 PB8 23 PD8

25 PB15 25 PD9

27 PC2 27 PD10

29 PC1 29 PD11

31 PC0 31 PD12

33 PA3 33 PD13

35 PA2 35 PD14

37 PB0 37 PD15

39 PA7 39 PE0

41 PA6 41 PE1

43 PB4 43 PE2

Connectors UM1855

62/100 DocID027351 Rev 2

3.4 Extension connectors CN6 and CN7

45 PB3 45 PE3

47 PB1 47 PA1

Table 33. CN11 and CN14 daughterboard connectors (continued)

CN11 CN14

Odd pin MCU port Odd pin MCU port

Table 34. Daughterboard extension connector CN6

Pin DescriptionAlternative Functions

How to disconnect Alternative functions to use on the extension connector

1 GND - -

3 PG6CODEC_INT,

MC_ICL_ShutoutRemove R35, Open SB5

5 PA13 TMS/SWDIODon’t use Trace connector CN12 and JTAG connector CN15

7 PA12 USBOTG_DP Remove R4

9 PG8 LPUART_RX_3V3 Remove R158, R188

11 GND - -

13 PG2 A12Remove R18 to deselect SRAM U2Remove R43 to deselect Flash memory U5

15 PD3 DFSDM_DATIN1 Remove R23

17 PD0 D2Remove R18 to deselect SRAM U2Remove R43 to deselect Flash memory U5

19 PD5 FMC_NWECan not be disconnected from SRAM and Flash memory, but is an input for SRAM and Flash memory

21 PG10 LCD_NE3Can not be disconnected from TFT LCD level shifters U21 and U22, but is an input for TFT LCD.

23 PD7 FMC_NE1 Remove R18

25 PF0 A0Remove R18 to deselect SRAM U2Remove R43 to deselect Flash memory U5

27 PG11 USART1_CTS_3V3 Remove R93

29 PG13 I2C_SDA Remove R58

31 PG12 USART1_RTS Remove R116

33 PG14 I2C_SCL Remove R61

35 PG15 IOExpander_INT Remove R228


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UM1855 Connectors

99

39 GND - -

2 +3V3 - -

4 PG7 LPUART_TX Remove R119, R189

6 PA11 USBOTG_DM Remove R3

8 PA14 TCK/SWCLKDon’t use Trace connector CN12 and JTAG connector CN15




16 PD1 D3Remove R18 to deselect SRAM U2Remove R43 to deselect Flash memory U5

18 PD4 FMC_NOERemove R18 to deselect SRAM U2Remove R43 to deselect Flash memory U5

20 PG9 FMC_NE2 Remove R43

22 GND - -

24 PD6SAI1_SDA,

FMC_NWAITRemove R53, open SB10


28 D5V - -

30 PC13 Wake-up Remove R244



36 GND - -


40 PB6 USART1_TX Remove R118

Table 35. Daughterboard extension connector CN7



1 GND - -

3 PE14 D11 -

Table 34. Daughterboard extension connector CN6 (continued)



Connectors UM1855

64/100 DocID027351 Rev 2

5 PE12 D9 -

7 PE10 D7 -

9 PE8 D5 -

11 PG1 A11 -

13 PB2LED1,

MC_DissipativeBrakeRemove R54, SB11

15 GND - -

17 PF12 A6 -

19 PF11 NFC_NSSDon’t connect the NFC daughterboard to connector CN13

21 PE4 A20, TRACE_D1 Remove R84, SB40


25 PC14 OSC32_IN Remove R87, Close SB41

27 PF6 SAI1_SDB Remove R105

29 PF9SAI1_FSB,

MC_PFC_syncRemove R90, SB25

31 PF10IDD_CNT_EN,

MC_PFC_PWMRemove R91, SB37

33 PH1 OSC_OUT Remove R95, close SB23

35 PA5 IDD_Measurement Remove R69

37 PA0OpAmp1_INP,

MC_EncARemove R83, SB35

39 GND - -

2 PE15 D12 -

4 PE13 D10 -

6 PE11 D8 -

8 PE9 D6 -

10 PE7 D4 -

12 PG0 A10 -

14 PF15 A9 -

16 PF14 A8 -

18 PF13 A7 -

20 BOOT0BootLoader from

UARTRemove JP8


24 PC15 OSC32_OUT Remove R88, close SB33




DocID027351 Rev 2 65/100

UM1855 Connectors

99

3.5 ST-LINK/V2-1 programming connector CN16

The connector CN16 is used only for embedded ST-LINK/V2-1 programming, during board manufacture. It is not populated by default and not for use by the end user.

3.6 ST-LINK/V2-1 Standard-B USB connector CN17

The USB connector CN17 is used to connect the on-board ST-LINK/V2-1 facility to PC for flashing and debugging software.

Figure 22. USB type B connector CN17 (front view)

26 GND - -

28 PF7 SAI1_MCKB Remove R106

30 PF8 SAI1_SCKB Remove R89

32 RESET# - -

34 PH0 OSCIN Remove crystal X2, C54, close SB24

36 PC3 VLCD Remove R94

38 PA4 ADC_DAC Remove R73

40 VDD - -




Connectors UM1855

66/100 DocID027351 Rev 2

3.7 JTAG connector CN15

Figure 23. JTAG debugging connector CN15 (top view)

Table 36. USB Standard-B connector CN17

Terminal Description Terminal Description

1 VBUS(power) 4 GND

2 DM 5,6 Shield

3 DP - -

Table 37. JATG debugging connector CN15

Terminal Function / MCU port Terminal Function / MCU port

1 VDD power 2 VDD power

3 PB4 4 GND

5 PA15 6 GND

7 PA13 8 GND

9 PA14 10 GND

11 RTCK 12 GND

13 PB3 14 GND

15 RESET# 16 GND

17 DBGRQ 18 GND

19 DBGACK 20 GND

DocID027351 Rev 2 67/100

UM1855 Connectors

99

3.8 Trace debugging connector CN12

Figure 24. Trace debugging connector CN12 (top view)

Table 38. Trace debugging connector CN12


1 VDD power 2 TMS/PA13

3 GND 4 TCK/PA14

5 GND 6 TDO/PB3

7 KEY 8 TDI/PA15

9 GND 10 RESET#

11 GND 12 TraceCLK/PE2

13 GND 14 TraceD0/PE3 or SWO/PB3

15 GND 16 TraceD1/PE4 or nTRST/PB4

17 GND 18 TraceD2/PE5

19 GND 20 TraceD3/PE6

Connectors UM1855

68/100 DocID027351 Rev 2

3.9 microSD card connector CN18

Figure 25. microSD card connector CN18

3.10 ADC/DAC connector CN8

Figure 26. Analog input-output connector CN8 (top view)

Table 39. microSD card connector CN18


1 SDIO_D2 (PC10) 6 Vss/GND

2 SDIO_D3 (PC11) 7 SDIO_D0 (PC8)

3 SDIO_CMD (PD2) 8 SDIO_D1 (PC9)

4 VDD 9 GND

5 SDIO_CLK (PC12) 10 MicroSDcard_detect (PA8)

DocID027351 Rev 2 69/100

UM1855 Connectors

99

3.11 RF-EEPROM daughterboard connector CN3

Figure 27. RF EEPROM daughterboard connector CN3 (front view)

3.12 Motor control connector CN2

Figure 28. Motor control connector CN2 (top view)

Table 40. Analog input-output connector CN8


1 GND 2 analog input-output PA4

Table 41. RF-EEPROM daughterboard connector CN3


1 I2C_SDA (PG13) 5 +3V3

2 NC 6 NC

3 I2C_SCL (PG14) 7 GND

4 EXT_RESET(PC6) 8 +5 V

Connectors UM1855

70/100 DocID027351 Rev 2

3.13 USB OTG FS Micro-AB connector CN1

Figure 29. USB OTG FS Micro-AB connector CN1 (front view)

Table 42. Motor control connector CN1

CN2 terminal

Description MCU portCN2

terminalMCU port Description

1 Emergency STOP PC9 2 - GND

3 PWM_1H PC6 4 - GND

5 PWM_1L PA7 6 - GND


9 PWM_2L PB0 10 - GND


13 PWM_3L PB1 14 PC5 BUS VOLTAGE

15 CURRENT A PC0 16 - GND

17 CURRENT B PC1 18 - GND

19 CURRENT C PC2 20 - GND

21 ICL Shutout PG6 22 - GND

23DISSIPATIVE

BRAKE PB2 24 PC4 PCD Ind Current

25 +5V power - 26 PA3Heat sink

temperature

27 PFC SYNC PF9 28 - 3.3 V power

29 PFC PWM PF10 30 PB12 PFC Shut Down

31 Encoder A PA0 32 PA6 PFC Vac

33 Encoder B PA1 34 PA2 Encoder Index

Table 43. USB OTG FS Micro-AB connector CN1


1 VBUS (PA9 & PB13) 4 ID (PA10)

2 D- (PA11) 5 GND

3 D+ (PA12) - -

DocID027351 Rev 2 71/100

UM1855 Connectors

99

3.14 CAN D-sub male connector CN5

Figure 30. CAN D-sub (DE-9M) 9-pole male connector CN5 (front view)

3.15 NFC connector CN13

Figure 31. NFC female connector CN13 (top view)

Table 44. CAN D-sub (DE-9M) 9-pins male connector CN5

Terminal Terminal name Terminal Terminal name

1,4,8,9 NC 7 CANH

2 CANL 3,5,6 GND

Table 45. NFC CN13 terminal assignment

CN13terminal

NFC signal MCU port Description

1NFC_IRQOUTN or

UART_TXPB7

Interrupt output for NFCConnected to STM32L476ZGT6 UART RX

2NFC_IRQINN or

UART_RXPB6

Interrupt input for CR95HFConnected to STM32L476ZGT6 UART TX

Connectors UM1855

72/100 DocID027351 Rev 2

3 NFC_NSS PF11 SPI slave select

4 NFC_MISO PB14 SPI data, slave output

5 NFC_MOSI PB15 SPI data, slave input

6 NFC_SCK PB13 SPI serial clock

7 +3V3 PB6 Main power supply/power supply for RF drivers

8 GND PB7 Ground

Table 45. NFC CN13 terminal assignment (continued)

CN13terminal

NFC signal MCU port Description

UM

18

55S

che

matic

dia

gra

ms

DocID

027351 R

ev 2

73/100

Appendix A Schematic diagrams

Figure 32. STM32L476G-EVAL top schematic diagram

1 25

Top schematic

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:

STM32L476G-EVALProject:

FMC_NWAIT

FMC_NOEFMC_NWE

FMC_NE1FMC_NE2

LCD_NE3

LED1LED2

LPUART_TX

USART1_TX

USART1_RTS

TMS/SWDIOTCK/SWCLK

TDITRST

Key

DFSDM_DATIN1

IDD_Measurement

CODEC_INT

USBOTG_PRDYUSBOTG_OVRCR

DMIC_DATIN

PT100_DATIN

USBOTG_VBUSUSBOTG_ID

IDD_WAKEUP

OpAmp1_INM

Comp2_INP

TDO/SWO

TRACE_D1TRACE_D2TRACE_D3

IDD_CNT_EN

USBOTG_PPWRTRACE_CK

TRACE_D0

SmartCard_CLK

OpAmp1_OUTADC_DAC

USBOTG_DPUSBOTG_DM

SmartCard_IO

QSPI_D0QSPI_D1QSPI_D2QSPI_D3

uSD_D0uSD_D1uSD_D2uSD_D3

MC_DissipativeBrakeMC_PFC_sync

MC_PWM_1HMC_PWM_1LMC_PWM_2HMC_PWM_2LMC_PWM_3HMC_PWM_3L

MC_ICL_Shutout

MC_PFC_PWM

MC_PFC_Vac

QSPI_CLKQSPI_CS

FMC_NBL0FMC_NBL1

CAN_TX

MC_EncAMC_EncB

MC_EncIndex

MC_CurrentBMC_CurrentC

MC_TemperatureMC_PFC_Shutdown

CAN_RX

uSD_DETECTuSD_CMDuSD_CLK

SWP_IO

IOExpander_X+IOExpander_X-IOExpander_Y+IOExpander_Y-

JOY_SELJOY_DOWNJOY_LEFT

JOY_RIGHTJOY_UP

SmartCard_OFFLED4LED3

SmartCard_RST

SmartCard_CMDVCCSmartCard_3/5V

D[0..15]A[0..23]

PA[0..15]PB[0..15]PC[0..15]PD[0..15]PE[0..15]PF[0..15]PG[0..15]

MC_CurrentA

MC_EmergencySTOP

MC_BusVoltageMC_PFC_IndCurr

RESET#

DFSDM_CKOUT

I2C_SCLI2C_SDA

PH1

PH0

SHIELD

SAI1_MCKBSAI1_SCKB

SAI1_FSB

SAI1_SDBSAI1_SDA

OpAmp1_INPComp2_OUT

TKEYTKEY_CS

SHIELD_CS

Bootloader_RESET_3V3Bootloader_BOOT0_3V3

LPUART_RX_3V3

USART1_CTS_3V3

USART1/IrDA_RX_3V3

BL_Control

EXT_RESET

BOOT0

NFC_NSS

NFC_MOSI

NFC_SCKNFC_MISO

I2C2_SDAI2C2_SCL

U_MCU_LCDGlass_SymbolMCU_LCDGlass_Symbol.SchDoc

FMC_NWEFMC_NOE

FMC_NWAIT

FMC_NBL0FMC_NBL1

D[0..15]A[0..23]

FMC_NE1FMC_NE2

U_SRAM&FlashSRAM&Flash.SchDoc

MC_EmergencySTOP

MC_CurrentAMC_CurrentBMC_CurrentC

MC_PFC_sync

MC_PWM_3L

MC_PWM_2HMC_PWM_2L

MC_PWM_1HMC_PWM_1L

MC_PWM_3H

MC_ICL_ShutoutMC_DissipativeBrake

MC_PFC_PWMMC_EncAMC_EncBMC_BusVoltage

MC_EncIndex

MC_PFC_IndCurrMC_TemperatureMC_PFC_ShutdownMC_PFC_Vac

U_MotorControlMotorControl.SchDoc

uSD_CLKuSD_CMD


uSD_DETECT

U_MicroSDMicroSD.SchDoc

QSPI_D0

QSPI_D3QSPI_D2QSPI_D1

QSPI_CLKQSPI_CS

U_QSPIQSPI.SchDoc

PA[0..15]PB[0..15]PC[0..15]PD[0..15]PE[0..15]

RESET#

PF[0..15]PG[0..15]PH

1

PH0

BOOT0

U_Extension connectorExtension connector.SCHDOC

TDI

RESET#TRACE_D3TRACE_D2TRACE_D1TRACE_D0

TRACE_CK

TRST

TMS/SWDIOTCK/SWCLK

TDO/SWO

U_JTAG&TraceJTAG&Trace.SchDoc

TDO/SWO

RESET#TDI

TRST

TMS/SWDIOTCK/SWCLK

LPUART_RX_3V3LPUART_TX

U_ST_LINKST_LINK.SCHDOC

USART1/IrDA_RX_3V3

Bootloader_BOOT0_3V3Bootloader_RESET_3V3

USART1_CTS_3V3

USART1_TX

USART1_RTS

LPUART_RX_3V3LPUART_TX

NFC_IRQINNNFC_IRQOUTN

U_USART_IrDAUSART_IrDA.SchDoc

SWP_IO

SmartCard_3/5V

SmartCard_IO

SmartCard_RST

SmartCard_CLK

SmartCard_OFF

SmartCard_CMDVCC

NFC_IRQINNNFC_IRQOUTN

NFC_NSS

NFC_MOSINFC_MISONFC_SCK

U_SWP_SmartCard_NFCSWP_SmartCard_NFC.SchDoc

DFSDM_CKOUTDFSDM_DATIN1PT100_DATIN

U_STPMS2&PT100STPMS2&PT100.SchDoc

IDD_MeasurementIDD_CNT_ENIDD_WAKEUP

U_IDD_measurementIDD_measurement.SchDoc

USBOTG_VBUS

USBOTG_PRDY

USBOTG_DMUSBOTG_DP

USBOTG_OVRCR

USBOTG_PPWR

USBOTG_ID

U_USB_OTG_FSUSB_OTG_FS.SchDoc

SHIELDSHIELD_CS

TKEY_CSTKEY

U_Touch SensingTouch Sensing.SchDoc

CAN_TXCAN_RX

U_CANCAN.SchDoc

ADC_DAC

LED4LED3

LED1LED2

JOY_SELJOY_DOWNJOY_LEFTJOY_RIGHTJOY_UPKEY

VREF+

Comp2_INP

OpAmp1_OUTOpAmp1_INMOpAmp1_INPComp2_OUT

U_peripheralsperipherals.SchDoc

VREF+

U_PowerPower.SchDoc

SAI1_SCKB

SAI1_FSB

SAI1_SDB

CODEC_INT

I2C_SCL

SAI1_MCKB

I2C_SDA

DMIC_DATINDFSDM_CKOUT

SAI1_SDA

U_AudioAudio.SchDoc

RESET#

FMC_NWELCD_NE3

FMC_NOE

D[0..15]A[0..23]

IOExpander_Y+IOExpander_Y-

IOExpander_X+IOExpander_X-

BL_Control

U_LCD_TFTLCD_TFT.SchDoc

I2C_SCLI2C_SDA

EXT_RESETI2C2_SDAI2C2_SCL

U_RF_I2C_EEPROMRF_I2C_EEPROM.SchDoc

Note: In all sheets, Italic format is used to differentiate text from schematic Net labels.

iMatched Net Lengths [Tolerance = 100mil]

i

i PCB Rule

Clearance Constraint [Clearance = 10mil]

i PCB Rule

BoM history for PCB B boards:

B01: creationB02: added micro SD card, changed reference of crystal X1, and values of C56, C57

Sc

he

ma

tic d

iag

ram

sU

M1

855

74/1

00D

ocID027

351 Re

v 2

Figure 33. MCU, LCD daughterboard and I/O expander interfaces - schematic diagram

2 25

MCU_LCDGlassl

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


PA[0..15]PB[0..15]PD[0..15]PE[0..15]

USBOTG_DMUSBOTG_DP

TMS/SWDIOTCK/SWCLK

DFSDM_DATIN1

FMC_NOEFMC_NWE

FMC_NWAITFMC_NE1

TRACE_D3

TRACE_D1

TRST

D[0..15]

IDD_Measurement

USART1_TX

LED1

MC_DissipativeBrake

TRACE_D2

MC_EncA

TDITDO/SWO

ADC_DAC

RESET#


QSPI_CLKQSPI_CS

TRACE_D0

TRACE_CK

SAI1_SDA

OpAmp1_INP

MC_PFC_VacMC_Temperature

MC_EncBMC_EncIndex

TKEYTKEY_CS

MC_PWM_1LMC_PWM_2LMC_PWM_3L

MC_PFC_Shutdown

A[20..22]

LCDCOM[0..3]LCDCOM7

LCDSEG[0..17]

LCDSEG[28..39]LCDSEG21

U_MCUMCU.SchDoc

uSD_CMDuSD_CLK

uSD_D3uSD_D2

IDD_WAKEUP

PT100_DATIN

uSD_D0uSD_D1OpAmp1_INM

FMC_NBL0FMC_NBL1

LCDSEG[0..39]LCDCOM[0..7]


CAN_TX

SWP_IO

CAN_RX

DMIC_DATIN

OpAmp1_OUTComp2_INP

SmartCard_CLKSmartCard_IO

uSD_DETECT

DFSDM_CKOUT

D[0..15]

USBOTG_PRDYUSBOTG_OVRCRUSBOTG_PPWR

Comp2_OUT

USART1/IrDA_RX_3V3A[16..19]A23

NFC_MISONFC_SCK

NFC_MOSI

I2C2_SDAI2C2_SCL

LED3

U_LCD_GlassLCD_Glass.SchDoc

IOExpander_Y+IOExpander_Y-

IOExpander_X+IOExpander_X-

IOExpander_INT I2C_SDA

JOY_SELJOY_DOWNJOY_LEFTJOY_RIGHTJOY_UP

LED4

SmartCard_RST


SmartCard_OFF

I2C_SCL

LED2

BL_Control

EXT_RESET

U_IO_ExpandorIO_Expandor.SchDoc

Bootloader_RESET_3V3Bootloader_BOOT0_3V3

FMC_NWAIT

LPUART_RX_3V3

USART1_CTS_3V3

FMC_NOEFMC_NWEFMC_NE1

FMC_NE2LCD_NE3

LED1

NFC_NSS

LPUART_TX

USART1_TX

USART1_RTS

TMS/SWDIOTCK/SWCLK

TDITRST

Key

DFSDM_DATIN1IDD_Measurement

CODEC_INT

OpAmp1_INP

DMIC_DATINPT100_DATIN


IDD_WAKEUP

OpAmp1_INM

Comp2_INP

TDO/SWO

TRACE_D1TRACE_D2TRACE_D3

IDD_CNT_EN

TRACE_CK

TRACE_D0

SmartCard_CLK

OpAmp1_OUT

Comp2_OUT

ADC_DAC

USBOTG_DPUSBOTG_DM

SmartCard_IO



MC_BusVoltage

MC_DissipativeBrake

MC_PFC_sync

MC_PWM_1H

MC_PWM_1L

MC_PWM_2H

MC_PWM_2L

MC_PWM_3H

MC_PWM_3L

MC_ICL_ShutoutMC_PFC_IndCurr

MC_PFC_PWM

MC_PFC_Vac

MC_EmergencySTOP

QSPI_CLKQSPI_CS

FMC_NBL0FMC_NBL1

NFC_MOSI

NFC_SCK

CAN_TX

MC_EncAMC_EncBMC_EncIndex


MC_Temperature

MC_PFC_Shutdown

USART1/IrDA_RX_3V3

CAN_RX

uSD_DETECT

NFC_MISO

uSD_CMDuSD_CLK

SWP_IO

IOExpander_X+IOExpander_X-IOExpander_Y+IOExpander_Y-


SmartCard_OFF

LED4

LED3

SmartCard_RST


D[0..15]A[0..23]

PA[0..15]PB[0..15]

PC[0..15]

PD[0..15]PE[0..15]

PF[0..15]PG[0..15]

MC_CurrentA

RESET#

I2C_SCLI2C_SDA

DFSDM_CKOUT

PH1PH0

TKEYTKEY_CS

SHIELDSHIELD_CS

LED2SAI1_SDB

SAI1_SDA

SAI1_MCKBSAI1_SCKBSAI1_FSB

USBOTG_PRDYUSBOTG_OVRCRUSBOTG_PPWR

BL_Control

PC[0..15]

Bootloader_BOOT0_3V3Bootloader_RESET_3V3

Key

CODEC_INT

USART1_CTS_3V3

FMC_NE2

USART1_RTS

PF[0..15]PG[0..15]

D[0..15]MC_PFC_sync

IDD_CNT_EN

LPUART_TXLPUART_RX_3V3

LCD_NE3

IOExpander_INTI2C_SCLI2C_SDA

RESET#

PH1PH0

SHIELD

SAI1_SDBSAI1_MCKBSAI1_SCKBSAI1_FSB

MC_ICL_Shutout

MC_PFC_PWM


MC_CurrentA

MC_PFC_IndCurr

MC_BusVoltage

MC_PWM_1H

SHIELD_CS

MC_PWM_2HMC_PWM_3H

MC_EmergencySTOP

A[0..15]


LCDSEG[22..27]

BOOT0

NFC_NSS

U_MCU2MCU2.SchDoc

A[0..15]

A[16..19]

A[20..22]

A[0..23]

A23

D[0..15]

D[0..15]

D[0..15]

D[0..15]

LCDSEG[0..39]

LCDSEG[28..39]


LCDCOM[0..3]

LCDCOM[0..7]

LCDSEG[22..27]

LCDSEG21

LCDCOM7

LCDSEG[0..17]

BOOT0

EXT_RESET

I2C2_SDAI2C2_SCL

UM

18

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Figure 34. STM32L476G-EVAL MCU part 1 - schematic diagram

3 25

MCU

MB1144 B-02

7/10/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


PE0

PE1

PE2

PE4

PE5

PE6

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PA[0..15] PA[0..15]

PB[0..15] PB[0..15]

PD[0..15] PD[0..15]

PE[0..15] PE[0..15]

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB12

PB13

PB14

PB15

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

USBOTG_DM

USBOTG_DP

TMS/SWDIO

TCK/SWCLK

D2

D3

DFSDM_DATIN1

FMC_NOE

FMC_NWE

FMC_NWAITFMC_NE1

TRACE_D3

TRACE_D1TRST

D4

D5

D6

D7

D8

D9

D10

D11

D12

D[0..15]

A[20..22]

D[0..15]

A[20..22]

R83 0

IDD_Measurement

USART1_TX

LED1

MC_DissipativeBrake

R54 0

A20

A22

TRACE_D2

A21

MC_EncA

R84 0

R86 0

R85 0

TDI

TDO/SWO

R102

100KGND

R100

100KGND

R101

100KGND

ADC_DAC

RESET# RESET#

LCDCOM7

LCDSEG28

LCDSEG29

LCDSEG30

LCDSEG31

LCDSEG32

LCDSEG33

LCDSEG34

LCDSEG35

LCDSEG36

LCDSEG37

LCDSEG38

LCDSEG0

LCDSEG1

LCDSEG2

LCDSEG3

LCDSEG4

LCDCOM0

LCDCOM1

LCDCOM2

LCDSEG17

LCDSEG5

LCDSEG6

LCDSEG7

LCDSEG8

LCDSEG9

LCDSEG21

LCDSEG16

LCDCOM3

LCDSEG12

LCDSEG13

LCDSEG14

LCDSEG15

LCDCOM[0..3]LCDCOM[0..3]

TKEY

TKEY_CS

QSPI_D3

QSPI_D2

QSPI_D1

QSPI_D0

R680

R66 0

R62 0

R560

R82 0

R1030

TRACE_CK

R53 0 SAI1_SDA

R69 0

OpAmp1_INP

R39 0

R38 0

MC_PFC_Vac

MC_Temperature

R78 0

MC_EncB

R81 0

MC_EncIndex

MC_PWM_1L

MC_PWM_2L

MC_PWM_3L

PB10

PB11

LCDSEG10

LCDSEG11

QSPI_CLK

QSPI_CS

R50 0

R48 0

MC_PFC_Shutdown

TRACE_D0

PE3 LCDSEG39R1040

LCDCOM7LCDCOM7

LCDSEG[0..17]LCDSEG[0..17]


LCDSEG21LCDSEG21

PE2 1

PE3 2

PE4 3

PE5 4

PE6 5

PA0-WKUP134

PA135

PA236

PA337

PA440

PA541

PA642

PA743

PB046

PB147

PB248

PE7 58

PE8 59

PE9 60

PE10 63

PE11 64

PE12 65

PE13 66

PE14 67

PE15 68

PB1069

PB1170

PB1273

PB1374

PB1475

PB1576

PD8 77

PD9 78

PD10 79

PD11 80

PD12 81

PD13 82

PD14 85

PD15 86

PA8100

PA9101

PA10102

PA11103

PA12104

PA13105

PA14109

PA15110

PD0 114

PD1 115

PD2 116

PD3 117

PD4 118

PD5 119

PD6 122

PD7 123

PB3133

PB4134

PB5135

PB6136

PB7137

PB8139

PB9140

PE0 141

PE1 142

U7A

STM32L476ZGT6U

SB35Open by default

SB32Open by default

SB22Open by default

SB31Open by default

SB21Open by default

SB20Open by default

SB18Open by default

SB19Open by default

SB14Open by default

SB15Open by default

SB12Open by default

SB13Open by default

SB11Open by default

SB9Open by default

SB8Open by default

SB3Open by default

SB6Open by default

SB10Open by default

SB26Open by default

SB40

Open by default

SB38

Open by default

SB39

Open by default

Sc

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Figure 35. STM32L476G-EVAL MCU part 2 - schematic diagram

4 25

MCU2

MB1144 B-02

7/10/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


PC[0..15] PC[0..15]

C141100nF

R96[N/A]

C55

20pF

C5420pF

X28MHz (with socket)

R95390

R6710K

231

SW1

09.032

90.01

D3

BAT60JFILM

D4BAT60JFILM

PH0

PH1

JP8

Header 2X1

R59150

1 432

B1RESET

VDD

VDD

Bootloader_BOOT0_3V3

Bootloader_RESET_3V3

C57

2.7pF

C56

2.7pF

R88

0

R87

0

PC1

PC2

PC6

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

Key

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PF10

PF11

PF12

PF13

PF14

PF15

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PG9

PG10

PG11

PG12

PG13

PG14

PG15

CODEC_INT

USART1_CTS_3V3

FMC_NE2

USART1_RTS

PF[0..15] PF[0..15]

PG[0..15] PG[0..15]

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

D[0..15]

A[0..15]

D[0..15]

A[0..15]

MC_PFC_sync

C581uF

IDD_CNT_EN

NFC_NSS

LPUART_TX

LPUART_RX_3V3

LCD_NE3

VLCD input

TP7 VLCD

IOExpander_INT

I2C_SCL

I2C_SDA

R94 0

R105 0

R106 0

R89 0

JP9

Header 2X1

R58 0

R34 0

R90 0

RESET#

RESET# RESET#

LCDSEG19

LCDSEG20

LCDSEG24

LCDSEG26

LCDSEG27

LCDCOM4

LCDCOM5

LCDCOM6



PH1

PH0PH0

PH1

SHIELD

R57

1K2

R60

1K2

R61 0

VDD

SAI1_SDB

SAI1_MCKB

SAI1_SCKB

SAI1_FSB

MC_ICL_Shutout

R35 0

R91 0

MC_PFC_PWM

R36 0

MC_CurrentB

MC_CurrentC

R99 0

PC3

R98 0

32.768 kHz crystal

PC0LCDSEG18

MC_CurrentA

R97 0

MC_PFC_IndCurr

PC4LCDSEG22 R65 0

PC5LCDSEG23 R64 0

MC_BusVoltage

MC_PWM_1H

PC7LCDSEG25

SHIELD_CS

R33 0

MC_PWM_2H

MC_PWM_3H

MC_EmergencySTOP

PG8


BOOT0

BOOT0

PH0-OSC_IN23

PH1-OSC_OUT24

NRST25

BOOT0138

PC13-WKUP27

PC14-OSC32_IN8

PC15-OSC32_OUT9

PC026

PC127

PC228

PC329

PC444

PC545

PC696

PC797

PC898

PC999

PC10111

PC11112

PC12113

PF2 12

PF3 13

PF4 14

PF5 15

PF6 18

PF7 19

PF8 20

PF9 21

PF10 22

PF11 49

PF12 50

PF13 53

PF14 54

PF15 55

PF0 10

PF1 11

PG2 87

PG3 88

PG4 89

PG5 90

PG6 91

PG7 92

PG8 93

PG9 124

PG10 125

PG11 126

PG12 127

PG13 128

PG14 129

PG15 132

PG0 56

PG1 57

U7C

STM32L476ZGT6U

SB34Open by default

SB36Open by default

SB42Open by default

SB17Open by default

SB16Open by default

SB2Open by default

SB27Open by default

SB4Open by default

SB30Open by default

SB28Open by default

SB29Open by default

SB25Open by default

SB37Open by default

SB5Open by default

X1

NDK NX3215SA-32.768KHZ-EXS00A-MU00525

UM

18

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Figure 36. LCD glass module daughterboard connectors - schematic diagram

5 25

LCD_Glass

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


A[16..19]

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 48

CN14

Header 24X2

LCD Glass Connector

uSD_CMD

uSD_CLK

uSD_D3

uSD_D2

USART1/IrDA_RX_3V3

R144 0 IDD_WAKEUP

R145 0

R146 0

R147 0

PT100_DATIN

uSD_D0

uSD_D1

D13D14D15A16

R151 0 A17

A18D0D1

R150 0 A19

R149 0 A23

R138

100KGND

R139

100KGND

OpAmp1_INM

PD11PD12PD13PD14PD15

PD10PD9PD8

PD2PC12PC11PC10

PC4PC5PC6PC7PCPC8PC9

PB7

PE0PE1PE2PE3PA1

LCDSEG21LCDSEG22LCDSEG23LCDSEG24LCDSEG25LCDSEG26LCDSEG27LCDSEG28LCDSEG29LCDSEG30LCDSEG31LCDSEG32LCDSEG33LCDSEG34LCDSEG35LCDSEG36LCDSEG37LCDSEG38LCDSEG39LCDSEG0

LCDCOM7LCDCOM6LCDCOM5LCDCOM4

FMC_NBL0FMC_NBL1



1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 48

CN11

Header 24X2

LCD Glass Connector

USBOTG_VBUSuSD_DETECTUSBOTG_IDCAN_TX

NFC_MISO

NFC_SCK

SWP_IO

CAN_RXNFC_MOSI

DFSDM_CKOUT

DMIC_DATIN

OpAmp1_OUT

R107 0

Comp2_INP

R111 0

LCDCOM1 PA9PA8PA10

PA15

PA3PA2

PA7PA6

PB9PB11PB10PB5PB14PB13PB12

PB8

PB0

PB4PB3PB1

PB15PC2PC1PC0

LCDCOM0LCDCOM2LCDCOM3LCDSEG11LCDSEG10LCDSEG9LCDSEG14LCDSEG13LCDSEG12LCDSEG17LCDSEG16LCDSEG15LCDSEG20LCDSEG19LCDSEG18LCDSEG2LCDSEG1LCDSEG5LCDSEG4LCDSEG3LCDSEG8LCDSEG7LCDSEG6

SmartCard_CLK

SmartCard_IOR143 0

D[0..15]D[0..15]

USBOTG_PRDYR108

0

R1090 USBOTG_OVRCR

USBOTG_PPWR

R148 0

Comp2_OUT

R140 0

R142 0R141 0

A[16..19]

A23A23

R265 0

R266 0

R264

1K2

VDD

R263

1K2

I2C2_SDA

I2C2_SCL

LED3

Sc

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Figure 37. I/O expander schematic diagram

6 25

IO_Expandor

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


Y- 1

INT2

A0/Data Out3

SCLK4

SDAT5

VCC6

Data in7

IN0 8IN1 9

GND10

IN2 11IN3 12X+ 13

Vio14

Y+ 15X- 16

U32

STMPE811QTRI2C device address:0x82

VDD

R239100K

R228 0

C134100nF

PG13PG14

PG15

IOExpander_Y+

IOExpander_Y-

IOExpander_X+

IOExpander_X-

IOExpander_INT

I2C_SCLI2C_SDA


LED4

GPIO01

INT 22

A0 18

SCL19

SDA20

VCC21 A2 24

GPIO78 GPIO67

GND9

GPIO56 GPIO45 GPIO34

A1 23

GPIO23 GPIO12 GPIO8 10

GPIO15 17GPIO14 16GPIO13 15GPIO12 14GPIO11 13GPIO10 12GPIO9 11

TAB25

U33

STMPE1600QTR

VDD

C132100nF

Default I2C Address:1000010X

R243 10KR232 10KR230 10K

R237[N/A]

R233[N/A]

R231[N/A]

VDD

SmartCard_RSTSmartCard_CMDVCCSmartCard_3/5V

SmartCard_OFF

R229100K

IOExpander1

IOExpander2

LED2

BL_ControlEXT_RESET

UM

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Figure 38. Power supply schematic diagram

7 25

Power

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


SV1

SG2

CV 3

CG1 4

CG2 5

CG3 6

L2

BNX002-01

C100220uF

E5V

C13110uF[ESR<0.2ohm]

VDD_ADJ

+5VVDD_ADJ

TP13

1

32

CN22

DC-10BZ1SMAJ5.0A-TR C124

100nF

1

2

3

U31ZEN056V130A24LS

13

2RV1

3386P-503H[5%]

R235

10.2K[1%]

Power Supply VDD_ADJ [1.7V to 3.61V]

R236

20K[1%]C1404.7uF

Vout=1.22*(1+R1/R2)

C133100nF

VDD_MCUVDD

BT1

CR1220 holder

L1

BEAD

32

1

JP2 VDDTP5

+3V3

VDD_ADJ

C45100nF

C42100nF

VDD_MCU

C35100nF

5VTP10

+5VR1651K

1 2

LD7Red

TP1

D5V

U5V_STLINK

U5V 78563412

JP17

Header 4X2

E5V

EN1

GND

2

VO 4

ADJ 5GND

7

VI6 PG 3

U34ST1L05BPUR

VDD_IO

+5V+3V3TP17

C1164.7uF

R204

20.5K[1%]

R20311.8K[1%]

C9810uF[ESR<0.2ohm]

EN1

GND

2

VO 4

ADJ 5GND

7

VI6 PG 3

U28ST1L05BPUR

Power Supply 3.3VVout=1.22*(1+R1/R2)

C101100nF

+3V3

TP11

C38100nF

VDD_IOVDD_IOTP4

VDDA

32

1

JP10

VDDATP8

+3V3

VDD_USB

32

1

JP1

VDD_USBTP2

+3V3

VDD

C591uF

C60100nF

GND GND

TP18 TP3

VREF+

Vin3 Vout 2

1

Tab 4

U27LD1117S18TR

C10710uF

+1V81V8TP16

+3V3

connected by shunt of IDD_measurement circuitry

to use a supercapacitor:remove the jumper, and connect positive terminalof the supercapacitor to pin 2 of the jumper.

VDD_MCU

VDD_MCU

VDD_MCU

C36100nF

VDD_USB

R202

[N/A]

32

1JP12

JP3

Header 2X1

R206[N/A]

R234

[N/A]

R240[N/A]

C46

1uF

C33

1uFC321uF

C50100nF

C41100nF

C48100nF

C51100nF

Recommendation:100nF decoupling capacitor for each VDD pin

R207124[1%]

R209232[1%]

+5V

C9910uF

+3V63V6TP12

Vout=1.25*(1+232/124)=3.589V

C114100nF

+ -

Vin3 Vout 2

1

Tab 4

U26LD1117STR

VBAT6

VSS 16VDD17

VSSA 30

VREF- 31VREF+32

VDDA33

VSS 38VDD39

VSS 71VDD72

VSS 107VDD108

VSS 143VDD144

VDDIO295

VDD52

VDD62

VDD84

VDDIO2131

VSS 120

VSS 94

VSS 51

VSS 61

VSS 83

VSS 130

VDDUSB106 VDD121

U7B

STM32L476ZGT6U

C43100nF

Sc

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Figure 39. Smartcard, SWP and NFC - schematic diagram

8 25

SWP_SmartCard_NFC

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


SWP_IO

NFC_IRQINNNFC_IRQOUTNNFC_NSS

NFC_MOSI PB15PF11 PB14 NFC_MISO

NFC_SCKPB13

+3V3

GND

C78100nF

SmartCard and SWP

NFC

PB7 PB6

CLKDIV11

CLKDIV22

5V/3V3

PGND4

C1+5

Vddp6

C1-7

Vup8

PRES9

PRES10

I/O11

AUX212

AUX113

CGND14 CLK 15RST 16Vcc 17PORADJ 18CMDVCC 19RSTIN 20Vdd 21GND 22OFF 23XTAL1 24XTAL2 25I/OUC 26AUX1UC 27AUX2UC 28U30

ST8024CDR

C136 100nF

C135100nF

+5V

C137 100nF

C117

100nF

R242100K

+3V3

R2164K7

+3V3

R21810K

R21710K

+3V3

C119100nF

VDD

R21110K

+3V3

R210 0

R21210K

AUX2TP14AUX1TP15

SmartCard_3/5V

SmartCard_IO

SmartCard_RST

SmartCard_CLKSmartCard_OFF

SmartCard_CMDVCC

PB0

PC4

IOExpander1

IOExpander1

IOExpander1IOExpander1

PB12

NFC kit reference: CR95HF-B

C1124.7uF

C1384.7uF

VCC 1

RST 2

CLK 3

NC 4

GND5

SWIO6

I/O7

NC8

18

17

CN23

C816

SmartCard Connector

Operating range: 2.7<VDD<3.6V

Operating Voltage: +3.3V

R215100K

R241100K

R213100K

R214100K

+3V3

7 85 63 41 2

CN13

female conn 4X2

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Figure 40. USART and IrDA - schematic diagram

9 25

USART_IrDA

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


SD5

TxD3

GND8

Anode (VCC2)1

Cathode2

RxD4

VCC16

Vlogic7

U11

TFDU6300

+3V3

C674.7uF

C714.7uF

162738495

CN9DB9-male

USART1/IrDA_RX_3V3

USART

Bootloader_BOOT0_3V3

Bootloader_RESET_3V3

C2+1

C2-2 V- 3

R1IN 4

R2IN 5

R3IN 6

R4IN 7

R5IN 8

T1OUT 9

T2OUT 10

T3OUT 11T3IN12 T2IN13 T1IN14

R5OUT15 R4OUT16 R3OUT17 R2OUT18 R1OUT19 R2OUTB20 R1OUTB21

nSHDN 22nEN23

C1-24 GND 25VCC 26

V+ 27

C1+28U10

ST3241EBPR

C62100nF

C64100nF

C61100nF

C65100nFC63100nF

+3V3

+3V3

RXDRTSTXDCTS

DSR

R113

0

USART1_CTS_3V3 PG11

R112 5.1

R115 47

PB7

USART1_RTS_3V3

PG12

VCCA1

A12

A23

GND4 DIR 5B2 6B1 7VCCB 8U12

SN74LVC2T45DCUT

+3V3VDD

VDD

C66100nF

C69100nF

R114100K

R117100K

VDD

USART1_RTS_3V3

R93 0

R118 0

R116 0

C70100nF

C68100nF

USART1_TX

IRDA

USART1_RTS

PB6

NFC_IRQINN

NFC_IRQOUTN

LPUART_RX_3V3 PG8

R119 [N/A]LPUART_TX PG7

IRDA_RX

R158[N/A]

GND

GND

654321

JP15

Header 3X2

Sc

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Figure 41. SRAM and NOR Flash memory devices - schematic diagram

10 25

SRAM&Flash

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


VDD

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22

VDD

FMC_NWEFMC_NOEFMC_NWAIT

VDDVDD

VDD

JP13Header 2X1

A0

A0

A17A18

VDD

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

VDD

Default setting: Open

PE1PE0

PD5PG9

PD6PD4

PD7

FMC_NBL0FMC_NBL1

A19A20 A23

VDD

2Mx16: CY7C1071DV33-12BAXI

A22B8

A15D7

A14C7

A13A7

A12B7

A11D6

A10C6

A9A6

A8B6

A19D5 A20D4

WA5

RPB5

A21C5

Vpp/WPB4

RBA4

A18C4

A17B3

A7A3

A6C3

A5D3

A4B2

A3A2

A2C2

A1D2

VCCQ D8

A0E2

EF2

VSS E8

GG2

DQ0 E3

DQ8 F3

DQ1 H3

DQ9 G3

DQ2 E4

DQ10 F4

DQ3 H4

DQ11 G4

VCCQ F1

DQ4 H5

DQ12 F5

DQ5 E5

DQ13 G6

DQ6 H6

DQ14 F6

DQ7 E6

DQ15A-1 G7

VSS H7BYTEF7

A16E7

VCC G5

VSS H2

A23C8U5

M29W128GL70ZA6EM29W256GL70ZA6E

D[0..15]

A[0..23]

D[0..15]

A[0..23]

R180

R430

C30100nF

C20100nF

C18100nF

C40100nF

C19100nF

C31 100nF

C12 100nF

R28

10K

R2210K

R2510K

R4110K

R3210K

R133

10K

SRAM Nor Flash

A21

FMC_NE1

512kx16: IS61WV51216BLL-10MLI

4Mx16: CY62187EV30LL

FMC_NE2

+3V6


512x16: IS61WV51216BLL-10MLI VDD: 2.4V to 3.6V

2Mx16: CY7C1071DV33-12BAXI VDD: 3.0V to 3.6V4Mx16: CY62187EV30LL VDD: 2.2V to 3.7V

Operating Voltages :

1Mx16: IS61WV102416BLL-10MLI VDD: 2.4V to 3.6V

1Mx16: IS61WV102416BLL

A4B4

A3B3

A2A5

A1A4

A0A3

CEB5

I/O0 B6I/O1 C5I/O2 C6I/O3 D5

VCC D6

VSS D1

I/O4 E5I/O5 F5I/O6 F6I/O7 G6

WEG5

A16E4

A15F4

A14F3

A13G4

A12G3

A11H5

A10H4

A9H3

A8H2 I/O8 B1I/O9 C1I/O10 C2I/O11 D2

VCC E1

I/O12 E2I/O13 F2I/O14 F1I/O15 G1

BLEA1

BHEB2

OEA2

A7D4

A6C4

A5C3

A17D3 A18H1

VSS E6

A20H6

A19G2

CE2 A6

A21E3U2

IS61WV102416BLL-10MLI

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Figure 42. TFT LCD schematic diagram

11 25

LCD_TFT

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


PG10PD5PD4

D0D1D2D3D4D5D6D7

D8D9D10D11D12D13D14D15

LCD_D0LCD_D1LCD_D2LCD_D3LCD_D4LCD_D5LCD_D6LCD_D7


C79100nF

VDD

C85100nF

+3V3

LCD_RS

LCD_CSN

LCD_WRNLCD_RDNLCD_RSTN

OE48

A147 B1 2

A246 B2 3

A344 B3 5

A443 B4 6

A541 B5 8

A640 B6 9

A738 B7 11

A837 B8 12

OE25

A136 B1 13

A235 B2 14

A333 B3 16

A432 B4 17

A530 B5 19

A629 B6 20

A727 B7 22

A826 B8 23

DIR 24

VCCB 18VCCB 7

GND4

GND10

GND15

GND21

DIR 1

VCCA42 VCCA31

GND 45GND 39GND 34GND 28

U21

SN74LVC16T245DGGR

C83100nF

VDD

C84100nF

+3V3

VDD

RESET#

FMC_NWELCD_NE3

FMC_NOE

OE48

A147 B1 2

A246 B2 3

A344 B3 5

A443 B4 6

A541 B5 8

A640 B6 9

A738 B7 11

A837 B8 12

OE25

A136 B1 13

A235 B2 14

A333 B3 16

A432 B4 17

A530 B5 19

A629 B6 20

A727 B7 22

A826 B8 23

DIR 24

VCCB 18VCCB 7

GND4

GND10

GND15

GND21

DIR 1

VCCA42 VCCA31

GND 45GND 39GND 34GND 28

U22

SN74LVC16T245DGGR

A1_BUF

A1_BUF

PF0

D[0..15]

A[0..23]

D[0..15]

A0LCD_NE3

VDD VDD

R16110K

R16610K

+3V3

TFT LCD



LCD_RSLCD_CSN

LCD_WRNLCD_RDNLCD_RSTN

+5V

C115

10uF

L4BEAD

C113

100nF

L3BEAD

R223

0

+3V3R219

[N/A]

CS1

RS2

WR/SCL3

RD4

RESET5

VDD24

VCI25

GND26

GND27

BL_VDD28

BL_Control23 BL_GND22

PD1 6

PD2 7

PD3 8

PD4 9

PD5 10

PD6 11

PD7 12

PD8 13

PD10 14

PD11 15

PD12 16

PD13 17

PD14 18

PD15 19

PD16 20

PD17 21

SDO29

SDI30 XL 31

XR 32

YD 33

YU 34

CN19

16-bit connector

IOExpander_Y+IOExpander_Y-IOExpander_X+IOExpander_X-

BL_Control

2.8'' LCD TFT board MB989P

A[0..23]

3

1

2

T69013-SOT23

R260

1K

R25947K

BL_VDD

BL_VDD

VDD

SB44Open by default

SB45Closed by default

A0_1DELAY

A0_1DELAY A0_2DELAY

A0_1DELAY

A0_2DELAY

SB46Open by default


SB49Open by default


SB51Open by default


NE3_1DELAY NE3_2DELAY

NE3_1DELAY

NE3_2DELAY

NE3_1DELAY

LCD_NE3

NE3_1DELAY LCD_NE3_BUF

LCD_NE3_BUF

LCD_NE3_BUF

A1

A1_1DELAY A1_BUF

A1 A1_1DELAY

VDD

R26722K

Sc

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Figure 43. Extension connector schematic diagram

12 25

Extension connector

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


R79 820R80

820

+3V3

PA[0..15] PA[0..15]

PB[0..15] PB[0..15]

PC[0..15] PC[0..15]

PD[0..15] PD[0..15]

PE[0..15] PE[0..15]

RESET# RESET#

Left Right

PG9PG10

PG11

PA4PA5

PF11

PG12

PD5

PD6

PD1

PE6

PF1PF0

PF3PF2

PF4

PC13

PF14

PG1 PG0PE7PE8PE9

RESET#

PB2

PH1

PH0

close to MCU

D5V

PA13PA12

PA11

PG8

PG7PG6

PD7

PG15

PB6

BOOT0PE4PE5

PE10PE11PE12

PG2PG3PG4

PG5

PF[0..15] PF[0..15]

PG[0..15] PG[0..15]

R44 0

VDD

PD3PD4

PG13

PG14

PE15PE13PE14

PF15

PF13PF12

PA0PC3

PF10PF9

PF7PF8

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

CN7

P1039-2*20MGF-089-1A

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

CN6

P1039-2*20MGF-089-1Atownes townes

PC14

PC15

PH1

PH0PH0

PH1

PF5

PF6

PD0

PA14

BOOT0BOOT0

SB33Open by default

SB41Open by default

SB23Open by default

SB24Open by default

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Figure 44. Quad-SPI Flash memory device schematic diagram

13 25

QSPI

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A4 Revision:


VDD

Quad SPI Memory

QSPI_D0

QSPI_D3

QSPI_D2

QSPI_D1

GND PB1

PB0

PA7

PA6

QSPI_CLKPB10

QSPI_CS

R710

VDD

R7410K

PB11

C44100nF

GND

MICRON


HOLD#/DQ3 7

VCC 8S#1

DQ12

C 6

DQ0 5Vss4

W#/Vpp/DQ23

HOLD#/DQ3

VCCS#

DQ1

C

DQ0Vss

W#/Vpp/DQ2

U9

N25Q256A13EF840E

Sc

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Figure 45. microSD card schematic diagram

14 25

MicroSD

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A4 Revision:


MicroSD card

uSD_CLKuSD_CMD

uSD_D0uSD_D1

uSD_D2uSD_D3

R18247K

R18547K

R1940

R17647K

R17847K

R17547K

VDD

PC9PC8

PC10PC11

PC12PD2

PA8

Operating Voltage: VDD no Lower than 2.7V

uSD_DETECT

C90

100nF

RVS

1

CS

2

DI

3

Vdd

4

SCLK

5

Vss

6

DO

7

RVS

8SW

29

SW1

10

CN18PJS008-2000 (SMS064FF or SMS128FF)

ZZ1

micro SD card

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Figure 46. Physical control peripherals - schematic diagram

15 25

peripherals

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


13

2

RV33386P-103(10K)

VDD

ADC_DAC

ADC&DAC connector and Reference Voltage

Potentiometer/LDR

1 2

LD3Red

1 2

LD2Orange

1 2

LD4Blue

1 2

LD1Green+3V3

R258510

R257680

R256680

R255680

LED4

LED3

LED1

LED2

R24

710

KR24

810

KR24

910

KR25

010

K

R24

610

K

VDD

R251100

COMMON5

Selection2

DWON3

LEFT1

RIGHT4

UP6

B3

MT008-A


Joystick

WKUP/TAMPER Button LEDs

R518.2K

PB2

C47[N/A]

R72 0R730

R245220K

143 2

B2WKUP

VDD

R244330

KEY

Close to MCU on PCB

PA4

VDD

CN8Header 2X1

PC13

R920

C52100nF

VREF+

Comp2_INP

Close to MCU on PCB

32

1

JP5

32

1

JP7

R631K

R121

1K

OpAmp1_INP

OpAmp1_INM

R120 [N/A]OpAmp1_OUT

OA1_OUTTP9

+

-

OpAmp1

13

2

RV23314J-1-103

STM32L

PA0

PA1PA3

VDD

VDDA

Potentiometer

LDR

Comparator

OpAmp/ADC

COMP2_OUTTP6

OpAmp1_OUT

OpAmp1_INM

OpAmp1_OUT

OpAmp1_INM

OpAmp1_INP OpAmp1_INP

I/Oexpander

PC1

I/Oexpander

PA3

PA0

PA1

STM32L

Comp2Comp2_INP

Comp2_INP

PB4 Comp2_OUT

Comp2_OUT Comp2_OUT

PB5

PB4

PB5

C53

1uF

Variable gain

CN10Header 2X1

R52VT9ON1

12

1 2

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Figure 47. CAN transceiver schematic diagram

16 25

CAN

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A4 Revision:


D1

GND2

VCC3

R4 Vref 5CANL 6CANH 7RS 8U8

SN65HVD230

+3V3

VDD

R55120

JP6Header 2X1

32

1

JP4

R4510K

VDD

C49

100nF

R460

R770

R70[N/A]

Default setting: 1<->2Default setting: Open

162738495

CN5DB9-male

PB9

PB8

CAN_TX

R76 0CAN_RX

R75 0

31 2

D2ESDCAN24-2BLY

Optional

Operating voltage range: 3.0<VDD<3.6V

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Figure 48. Touch-sensing device schematic diagram

17 25

Touch Sensing

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A4 Revision:


<----Touch Sensing diameter 10mm min on active shield diameter 12mm min

R40

10K

SHIELDSHIELD_CS

TS1TS_PAD

ESD resistor close to MCU pad

TKEY_CS

C3722nF(COG)GRM3195C1H223JA01L

R371K

C34220nF

TKEY PB12

PB13

PC6PC7

Sc

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Figure 49. USB_OTG_FS port schematic diagram

18 25

USB_OTG_FS

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A4 Revision:


+5V

+3V3

R5 0

GND2

IN5

EN4 OUT 1FAULT 3U1

STMPS2151STR

VBUS1

DM2

DP3

ID4

GND5

Shield6

USB

_Micro-A

B re

ceptacle

Shield7

Shield8

Shield9

EXP10

CN1

475900001

PA9

PA10

PA11PA12

R3 0R4 0

DzA2

ID A3

Pd1 B1

PupB2

VbusB3

D+in C1

Pd2 C2

D+outC3

D-in D1

GND D2

D-outD3

D1

EMIF02-USB03F2

12

LD5Green

PC6

R2110K

R847K

USBOTG_VBUS

VBUS OK

USBOTG_PRDY PB13

U5V

USBOTG_DMUSBOTG_DPUSBOTG_ID

USBOTG_OVRCRPB12

USBOTG_PPWR

MIC

ROAB_N

MIC

ROAB_P

R20

12

LD6Red

R9620

C15

4.7uF

3

1

2

T19013-SOT23

R1

47K

R6330

+3V3

transistor pins numbers follow SOT23 JEDEC standard,

USB Full Speed operating range voltage: 3.0V<VDDUSB<3.6V

R26122K

JP19

Header 2X1

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Figure 50. IDD measurement schematic diagram

19 25

IDD_measurement

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


IDD_Measurement

IDD_CNT_EN

IDD_WAKEUP

2

3

4

5

U16SN74LVC1G04DCKT

I/O1 O/I 2

GND3 C4

VCC 5

U13

SN74LVC1G66DCKT

VDD

R1351[1%]

R1231K[1%]3

4

5G

SD 1

26

T2

FDC606P 3

4

5G

SD 1

26

T3

FDC606P

VDD

Q111

Q122

Q133

Q54

Q45

Q66

Q37

GND8 Ctc 9Rtc 10RS 11MR 12Q8 13Q7 14Q9 15VCC 16U14

74LV4060PW

VDD

VDD

R127

220K

R122

10KVDD

VDD_MCU

C771nF

R13415K

R13030K

Oscillator frequency 30KHz

VDDC72100nF

PC5

PF10

PA5

R136

3K6 0.1%

R125

3K6 0.1%

R129

180K 0.1%

R132

180K 0.1%

GND

+5V

C75100nF

GND

GND

decoupling capacitorclose from TSZ124 part

1

4

3

2

11

V+

V-

U15ATSZ124IPT

75

6

U15BTSZ124IPT

1412

13

U15DTSZ124IPT

810

9

U15CTSZ124IPT

R12822K

R1241K

Shunt_x1000

Shunt_x1000

Current direction

to MCU

bypass path currentmeasurement path

differentialamplifier

shunts

C73

1uF

R137220K

C74

100nF

C76

100nF

C144100nF

GND

1 2 3 4JP11

Current direction

VDD from power supply

Sc

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Figure 51. Audio codec device schematic diagram

20 25

Audio

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


SAI1_SCKB

Default I2C Address:0011010

PD6 ADCDAT1F2

ADCLRCLK1/GPIO1G3

AGND D6

CPVDDG9

CPVOUTN H7

CPVOUTP G7

CS/ADDR G2

DACDAT1E4

CPGND H9

DCVDDF1

DBVDDD2 DGND E2

CPCB H8

AVDD1D9

BCLK1G1

CIFMODE A4

CPCA G8

DMICCLKC6

AGND E7

AGND E8

AVDD2D8

GPIO2/MCLK2 E1

GPIO3/BCLK2H2

GPIO4/LRCLK2F4

GPIO5/DACDAT2H3

GPIO6/ADCLRCLK2G4 GPIO7/ADCDAT2E5

GPIO8/DACDAT3H4

GPIO9/ADCDAT3F5

GPIO10/LRCLK3H5 GPIO11/BCLK3F6

HP2GND F7

HPOUT1FB G5

HPOUT1L H6HPOUT1R G6

HPOUT2N F9

HPOUT2P F8

IN1LND7 IN1LPC8

IN1RNB7 IN1RPC7

IN2LN/DMICDAT1B9 IN2LP/VRXNB8

IN2RN/DMICDAT2A9 IN2RP/VRXPA8

LDO1ENAD4

LDO1VDDE9

LDO2ENAD5

LDO2VDDD1

LINEOUT1N C5

LINEOUT1P B5

LINEOUT2N C4

LINEOUT2P B4

LINEOUTFB A6

LRCLK1E3

MCLK1 D3

MICBIAS1 A7

MICBIAS2 B6

REFGND A5

SCLK H1SDA F3

SPKGND1 A1

SPKGND2 C1

SPKMODE A3

SPKOUTLN B1

SPKOUTLP A2

SPKOUTRN C3

SPKOUTRP B3

SPKVDD1B2

SPKVDD2C2

VMIDC C9

VREFCE6

U29

WM8994ECS/R

C11

110

0nF

C12

310

0nF

VDD

+1V8

VDD

SAI1_FSBSAI1_SDB

PF8PF9PF6

CODEC_INT

I2C_SCL

PG13PG14

SAI1_MCKBPF7

C10

510

0nF

C10

610

0nF

R19520

R19620

C103 2.2uF

C102 2.2uF

C104 2.2uF

GND5 DOUT 4CLK 3VDD1 LR 2U35

MP34DT01TR

GND5 DOUT 4CLK 3VDD1 LR 2U36

MP34DT01TR

32

1 JP16

32

1

JP14

MICBIAS1

VDD

C14

210

0nF

PC0

+3V3

C12

110

0nF

+1V8

+3V3

+1V8

C10

910

0nF

C13

910

0nF

R197[N/A] VDD

PG6

R200 10K

R238 10K

C108 1uF

C11

01u

F

C11

81u

F

C12

64.7u

F

C12

04.7u

F

C12

24.7u

F

C1254.7uF

C1274.7uF

C1284.7uF

PC2

R2241K

R225

180

GND

R2261K

R227

180

GNDGND

I2C_SDA

DMIC_DATIN

GND

DFSDM_CKOUT

R205 0

R2220

R198 0R208 0R201 0

R199 0SAI1_SDA

C129

4.7uF

C130

4.7uF


2

6

4

3 CN20

PJ3028B-3

2

6

4

3 CN21

PJ3028B-3

R191

0GND

R192

0GND

R2210

R220

0GND

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Figure 52. STPMS2L and PT100 schematic diagram

21 25

STPMS2&PT100

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


STPMS2 power metering

R261K

GND

GND

GND

GND

C26

100nF

GND

GND

R271K

GNDR+jX Load

current shunt

external generator input: pins 1 and 3voltage of complex load: pins 2 and 3 shunt voltage : pins 1 and 2

R31100 1%

GND

GND

GND

GND

C25

100nF

GND

GNDVCC

1

VDDAC

2

VDDA

3

VBG

4

DATn 16

DAT 15

CLK 14

MS3 13

MS2

12

MS1

11

MS0

10

VDDAV

9

VIP8

VIN7

CIP6

CIN5

GND

17

AV

Exposed pad GND

U4STPMS2L-PUR

GND

current shunt

PT100 measurement using SigmaDelta STPMS2

R293K3

VDD

VDD

VDD

PC2

PD3

PC7

DFSDM_CKOUT

DFSDM_DATIN1R23 0

R24 0 PT100_DATIN

VCC

1

VDDAC

2

VDDA

3

VBG

4

DATn 16

DAT 15

CLK 14

MS3 13

MS2

12

MS1

11

MS0

10

VDDAV

9

VIP8

VIN7

CIP6

CIN5

GND

17

AV

Exposed pad GND

U3STPMS2L-PUR

32

1

CN4

GND C29

4.7u

F

C27

1uF

C22

1uF

C24

1uF

C28 1uF

C21

1uF

C23

1uF


R30PT100

Sc

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Figure 53. RF-EEPROM and EEPROM schematic diagram

22 25

RF_I2C_EEPROM

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A4 Revision:


1 23 45 67 8

CN3

F206A-2*04MGF-A

VDD

EXT/RFEEPROM Connector

+5V

SSM-104-L-DH (Samtec)

I2C_SCLI2C_SDA PG14

PG13

EXT_RESET

E01

E12

E23

VSS4 SDA 5SCL 6WC 7VCC 8U6

M24128-DFDW6TP

GND

PB11PB10

R4210K

VDDC39

100nFGND

GND

I2C_SDAI2C_SCL

I2C EEPROM

M24C64-FDW6TP

operating voltage ranges:1MHz 64Kbit I2C memory M24C64-FDW6TP: 1.7 to 5.5V1MHz 128Kbit I2C memory M24128-FDW6TP: 1.7 to 5.5V

GPIO10_IOExpander2


SB43Open by default

I2C2_SDAI2C2_SCL

I2C address: 0xA0

RFEEPROM module MB102 A02I2C address: 0xA6

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Figure 54. Motor control connector schematic diagram

23 25

MotorControl

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A4 Revision:


R143K3

C71nF

+3V3

+3V3+5V

R11 0

C14[N/A]

C2[N/A]

R10 0

R17 0

R130

R160

MC_EmergencySTOP

MC_CurrentA

MC_CurrentB

MC_CurrentC

MC_PFC_sync

MC_PWM_3L

MC_PWM_2HMC_PWM_2L

MC_PWM_1HMC_PWM_1L

MC_PWM_3H

MC_ICL_ShutoutMC_DissipativeBrake

MC_PFC_PWMMC_EncAMC_EncB

MC_BusVoltage

MC_EncIndex

Motor control connector

PA6

PA3

PC0

PC1

PC2

PG6

PF9

PA1

PB2

PA2

PA7

PB0

PB1

PA0

PC9PC6

PC7

PC8

C13[N/A]

C10[N/A]

C16[N/A] C9

[N/A]C1[N/A]

C4[N/A]

PF10

C810nF

C11100nF

C17100nF

R19100K

EMERGENCY STOP1

PWM_1H3

PWM_1L5

PWM_2H7

PWM_2L9

PWM_3H11

PWM_3L13

PHASE A CURRENT +15

PHASE C CURRENT +19 PHASE B CURRENT +17

ICL shut out21

DISSIPATIVE BRAKE23

+5V POWER25

PFC SYNC27

PFC PWM29

Encoder A31

Encoder B33

GND 2

GND 4

GND 6

GND 8

GND 10

GND 12

BUS VOLTAGE 14

PHASE A CURRENT - 16

PHASE B CURRENT - 18

PHASE C CURRENT - 20

GND 22

PFC Inductor current 24

Heatsink Temperature 26

3.3V Power 28

PFC Shut down 30

PFC Vac 32

Encoder Index 34

CN2

MC_connector

R70

PC4

C3100nF

MC_PFC_IndCurr

MC_Temperature

R15 0

R120

C6[N/A]

MC_PFC_ShutdownPB12

PC5

MC_PFC_Vac

+3V3

R203K3

C51nF

SB1

Open by

default

Sc

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Figure 55. JTAG and trace debug connectors - schematic diagram

24 25

JTAG&Trace

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


1234567891011121314151617181920

CN12FTSH-110-01-L-DV

VDD

R153[N/A]

R160[N/A]

R152[N/A]

R157[N/A]

VDD

1234567891011121314151617181920

CN15JTAG VDD

VDD

R163 10K

R164 10K

R15910K

R1540R162[N/A]R1560R131[N/A]

TDI

RESET#

TRACE_D3TRACE_D2TRACE_D1TRACE_D0TRACE_CK

TRST

TMS/SWDIOTCK/SWCLKTDO/SWO

Trace connector

JTAG connector

KEY

PA13PA14PB3PA15PB4

PE6PE5PE4PE3PE2

R126[N/A]

RS1

22

GND

GND

GND

IO11

IO23

GND2

IO3 4

IO4 5U17

ESDALC6V1W5

IO11

IO23

GND2

IO3 4

IO4 5U18

ESDALC6V1W5

IO11

IO23

GND2

IO3 4

IO4 5U19

ESDALC6V1W5

R155[N/A]

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Figure 56. ST-LINK/V2-1 schematic diagram

25 25

ST_LINK

MB1144 B-02

6/24/2015

Title:

Size: Reference:

Date: Sheet: of

A3 Revision:


VBAT1

PC132

PC143

PC154

OSC_IN5

OSC_OUT6

/RST7

VSSA8

VDDA9

PA010

PA111

U2_TX12

U2_

RX

13

U2_

CK

14

S1_C

K15

S1_M

ISO

16

S1_M

OSI

17

PB0

18

PB1

19

PB2/BOOT1

20

PB10

21

VSS

_123

VDD_1

24

PB12 25

PB11

22

S2_CK 26S2_MISO 27S2_MOSI 28PA8 29PA9 30PA10 31PA11 32PA12 33JTMS 34VSS_2 35VDD_2 36

JTCK

37JT

DI

38JT

DO

39JN

RST

40PB

541

PB6

42PB

743

BOOT0

44PB

845

PB9

46VSS

_347

VDD_3

48

U23STM32F103CBT6

1 2X3

8MHz

STL_USB_DMSTL_USB_DP

STM_RST

T_JT

CK

T_JTCK

T_JT

DO

T_JT

DI

T_JTMS

STM_JTMS_SWDIO

STM_JTCK_SWCLK

LED_STLINK

OSC_INOSC_OUT

T_NRST

T_JR

ST

LED_STLINK

T_JTCKT_JTDI

T_JTDO

T_NRSTT_JTMS

T_JRST

R186

4K7

R183

4K7

AIN_1

C91100nF

R181

100K

VDD

AIN_1

STL_USB_DMSTL_USB_DP

C93100nF

C87100nF

C86100nF

C94100nF

R180 22R179 22

MCU

USB

STM_JTMS_SWDIOSTM_JTCK_SWCLK

VUSB_ST_LINK

C95

100nF

C92

100nF

TDITRST

TMS/SWDIO

TCK/SWCLK

TDO/SWO

RESET#

SWIM_PU_CTRL

R168

100K

VccA1

A12

A23

GND4 DIR 5B2 6B1 7VccB 8U24

SN74LVC2T45DCUT

VDD

T_SWO

T_SWDIO_IN

T_SWDIO_IN

T_SWO

R177

1.5K

R16710K

R17136K

R174

[N/A]

R172

10K

R187100K

MCO

21 4

3

Red Yellow

LD8HSMF-A201-A00J1

R253100

R254100

R2520

LPUART_RX_3V3

PWR_E

XT

PG8

LPUART_TX PG7

R1880

R169 2K2

JP18

Header 2X1

GND+5V

R173

100USB_RENUMn

USB_RENUMn

51

2

GND3

4

BYPASSINH

Vin Vout

U20LD3985M33R

C82

10nF

GNDGND

GND

+3V3_STLINK

+3V3_STLINK

+3V3_STLINK

+3V3_STLINK

+3V3_STLINK

+3V3_STLINK +3V3_STLINK

+3V3_STLINK

+3V3_STLINK

+3V3_STLINK

+3V3_STLINK

+3V3_STLINK

PWR_ENn

VUSB_ST_LINK

R170 4K7

C80

1uFC811uF

C89

20pF

C88

20pF

VCCA1

A12

A23

GND4 DIR 5B2 6B1 7VCCB 8U25

SN74LVC2T45DCUT

VDD

VDD

C97100nF

C96100nF

R193100K

R190100K

3

1

2

T49013-SOT23

transistor pins numbers follow SOT23 JEDEC standard,

+3V3_STLINK

R1890

STLINK virtual comport using LPUART: R182/R187 not fitted, R58/R178 fitted.

D5

BAT60JFILMD6

BAT60JFILMD7

BAT60JFILMD8

BAT60JFILM

U5V

D5V

E5V

VUSB_ST_LINK

1 23 45

CN16

[N/A]

VCC 1

D- 2

D+ 3

GND 4

SHELL 6

SHELL 5

CN17

USB-typeB connector

TP19

Power Switch to supply +5V from STLINK USB

IN1

IN2

ON3 GND 4

SET 5

OUT 6

OUT 7

FAULT8

U37ST890CDR

U5V_STLINK

R110 100K

R26210K

C143100nF

output current limitation : 600mA

VUSB_ST_LINK

R1842K2

1 2

LD9RedR268

1K

C145100nF

FCC and IC compliance statements UM1855

98/100 DocID027351 Rev 2

Appendix B FCC and IC compliance statements

B.1 FCC (Federal Communications Commission) compliance statement

B.1.1 Part 15.19

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

B.1.2 Part 15.105

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference's by one or more of the following measures:

Reorient or relocate the receiving antenna.

Increase the separation between the equipment and the receiver.

Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

Consult the dealer or an experienced radio/TV technician for help.

B.1.3 Part 15.21

Any changes or modifications to this equipment not expressly approved by STMicroelectronics may cause, harmful interference and void the FCC authorization to operate this equipment.

B.2 IC (Industry Canada) compliance statement

B.2.1 Industry Canada

This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions : (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation.

Le présent appareil est conforme aux CNR d’Industrie Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deux conditions suivantes : (1) l’appareil ne doit pas produire de brouillage, et (2) l’utilisateur de l’appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d’en compromettre le fonctionnement.

DocID027351 Rev 2 99/100

UM1855 Revision History

99

4 Revision History

Table 46. Document Revision History

Date Version Revision Details

22-Jul-2015 1 Initial Version

29-Jul-2015 2Added Section 2.6.2: Bootloader limitations.

Classification change from ST Restricted to Public.

UM1855

100/100 DocID027351 Rev 2

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2015 STMicroelectronics – All rights reserved

UM1855 User manual - Farnell element14 · such as USB, USART, digital microphones, A DC and DAC,...

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