Chapter 2 Introduction of IC Fabrication - Miunapachepersonal.miun.se/~gorthu/ch02.pdf · Hong...

Hong Xiao, Ph. D. www2.austin.cc.tx.us/HongXiao/Book.htm 1

Chapter 2Introduction of IC

FabricationHong Xiao, Ph. D.

[email protected]


Objectives

• Define yield and explain its importance

• Describe the basic structure of a cleanroom.

• Explain the importance of cleanroom protocols

• List four basic operations of IC processing

• Name at least six process bays in an IC fab

• Explain the purposes of chip packaging

• Describe the standard wire bonding and flip-chipbump bonding processes


Wafer Process Flow

Materials

Design

Masks

IC Fab

Test

Packaging

Final Test

ThermalProcesses

Photo-lithography

EtchPR strip

ImplantPR strip

Metallization CMPDielectricdeposition

Wafers


Fab Cost

• Fab cost is very high, > $1B for 8” fab

• Clean room

• Equipment, >$1M per tool

• Materials, high purity, ultra high purity

• Facilities

• People, training and pay


Wafer Yield

total

goodW Wafers

WafersY =


Die Yield

total

goodD Dies

DiesY =


Packaging Yield

total

goodC Chips

ChipsY =


Overall Yield

YT = YW×YD×YC

Overall Yield determines whether a fab ismaking profit or losing money


How Does Fab Make Money

• Cost:– Wafer (8”): ~$150/wafer*

– Processing: ~$200 (1$/wafer, 200 process steps)

– Packing: ~$1/chip

• Sale:– ~100 chips/wafer

– ~$50/chip (low-end microprocessor in 2000)

*Cost of wafer and price of chip are changing daily, numbersare choosing randomly based on general information.


How Does a Fab Make (Loss) Money

• 100% yield: 150+200+100 = $450/wafer

• 50% yield: 150+200+50 = $400/wafer

• 0% yield: 150+200 = $350/wafer

• 100% yield: 100××50 = $5,000/wafer

• 50% yield: 50×50 = $2,500/wafer

• 0% yield: 0×50 = $0.00/wafer

• 100% yield: 5000 - 450 = $4550/wafer

• 50% yield : 2500 - 400 = $2100/wafer

• 0% yield : 0 - 350 = − $350/wafer

Cost:

Sale:

ProfitMargin:


Throughput

• Number of wafers able to process– Fab: wafers/month (typically 10,000)

– Tool: wafers/hour (typically 60)

• At high yield, high throughput brought


Defects and Yield

nDAY

)1(

1

+∝


Yield and Die Size

Y = 28/32 = 87.5% Y = 2/6 = 33.3%

Killer Defects


Illustration of a Production Wafer

Test die

Die


Illustration of a Production Wafer

Scribe Lines

Dies

TestStructures


Clean Room

• Particles kills yield

• IC fabrication must in a clean room

• Artificial environment with low particle counts


Clean Room

• First used for surgery room to avoid bacteriacontamination

• Adopted in semiconductor industry in 1950

• Smaller device needs higher grade clean room

• Less particle, more expensive to build


Clean Room Class

• Class 10 is defined as less than 10 particleswith diameter larger than 0.5 µm per cubicfoot.

• Class 1 is defined as less than 1 such particlesper cubic foot.

• 0.18 mm device require higher than Class 1grade clean room.


Cleanroom Classes

0.1

1

10

100

1000

10000

100000

Class 100,000Class 10,000Class 1,000

Class 100

Class 10Class 1

# of

par

ticle

s /

ft3

0.1 1.0 10

Particle size in micron

Class M-1


Definition of Airborne ParticulateCleanliness Class per Fed. Std. 209E

Class

Particles/ft3

0.1 µm 0.2 µm 0.3 µm 0.5 µm 5 µm

M-1 9.8 2.12 0.865 0.28

1 35 7.5 3 1

10 350 75 30 10

100 750 300 100

1000 1000 7

10000 10000 70


Effect of Particles on Masks

Particleson Mask

Stumpon +PR

Hole on−PR

Film Film

Substrate Substrate


Effect of Particle Contamination

Partially Implanted Junctions

Particle

Ion Beam

Photoresist

Screen Oxide

Dopant in PR


Cleanroom Structure

Process Area

Equipment AreaClass 1000

Equipment AreaClass 1000

Raised Floorwith Grid Panels

Return Air

HEPA Filter

Fans

Pump, RFand etc.

ProcessTool

ProcessTool

Makeup Air Makeup Air


Gowning Area

Gown Racks

Benches

Shelf of Gloves, Hairand Shoe Covers Disposal Bins

Wash/CleanStations

Storage

Shelf ofGloves

Shelf ofGloves

Entrance

ToCleanroom


IC Fabrication Process Module

Photolithography

Thin film growth,dep. and/or CMP

Etching

PR Stripping PR Stripping

Ion Implantation

RTA or Diffusion


Illustration of Fab FloorProcess Bays

Gowning Area

Corridor

Equipment Areas

Sliding Doors

Service Area


Wet Processes

DryDryEtch, PR strip, or clean Rinse


Horizontal Furnace

Center Zone

Flat Zone

Distance

Temperature

Heating Coils

QuartzTube

Gas flow

Wafers


Vertical FurnaceProcessChamber

Wafers

Tower

Heaters


Schematic of a Track StepperIntegrated System

Hot Plates

PrepChamber

Chill Plates

Chill PlatesSpin Coater

Developer

Stepper

WaferMovement

Wafer


Cluster Tool with Etch and StripChambers

TransferChamber

PR StripChamber

Loading Station

EtchChamber

PR StripChamber

EtchChamber

Unloading Station

Robot


Cluster Tool with Dielectric CVDand Etchback Chambers

TransferChamber

Loading Station

PECVDChamber

O3-TOESChamber

Unloading Station

Robot

Ar SputteringChamber


Cluster Tool with PVD Chambers

TransferChamber

Loading Station

Ti/TiNChamber

Al⋅CuChamber

Unloading Station

Robot

Al⋅CuChamber

Ti/TiNChamber


Dry-in Dry-out CMP System

Wafer Loadingand Standby

Post-CMP Clean

Rinse

Dryer and WaferUnloading

Multi-head Polisher

PolishingPad

Clean Station

PolishingHeads


Process Bay and Equipment Areas

Process Area

Equ

ipm

ent A

rea

Equ

ipm

ent A

rea

Process Tools

Tab

les

For

PC

and

Met

rolo

gy T

ools

Service Area

Sliding Doors

Wafer Loading Doors


Test Results

Failed die


Chip-Bond Structure

Chip (Silicon)Chip BacksideMetallization

SolderSubstrateMetallization Substrate (Metal or Ceramic)

Microelectronics Devices and Circuits

Melt andCondense


Wire Bonding

Metal Wire

Formation ofmolten metal ball

Bonding Pad Bonding Pad Bonding Pad

Press to makecontact

Head retreat

Wire Clamp


Wire Bonding

LeadBonding Pad Bonding Pad Lead

Lead contact withpressure and heat

Clamp closed with heaton to break the wire


IC Chip with Bonding Pads

Bonding Pads


IC Chip Packaging

Pins

Chip

BondingPad


Chip with Bumps

Bumps


Flip Chip Packaging

Chip

Bumps

Socket Pins


Bump Contact

Chip

Bumps

Socket Pins


Heating and Bumps Melt

Chip

Bumps

Socket Pins


Flip Chip Packaging

Chip

Socket Pins


Molding Cavity for Plastic Packaging

Bonding Wires IC Chip

Lead Frame

PinsChip Bond Metallization

Top Chase

Bottom Chase

Molding Cavity


Ceramic Seal

Ceramic Cap

Bonding Wires IC Chip

Lead Frame, Layer 1

Pins

Cap SealMetallization

Chip Bond Metallization

Layer 2Layer 2


Summary

• Overall yield• Yield determines losing money or making

profit• Cleanroom and cleanroom protocols• Process bays• Process, equipment, and facility areas• Die test, wafer thinning, die separation, chip

packaging, and final test

Chapter 2 Introduction of IC Fabrication - Miunapachepersonal.miun.se/~gorthu/ch02.pdf · Hong...

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