Basic IC Fabrication 2

1

Inverter fabrication

3

2

Basic CMOS Process Flow

Starting Point: Pure silicon wafer (heavily-doped) with a lightly-doped epitaxial (epi) layer.

An epi layer is used to provide a cleaner layer for device formation and to prevent “latch-up” of CMOS transistors.

Silicon Substrate P+

~2 microns

~725 microns

Silicon Epi Layer P-

3

Basic CMOS Process Flow - Shallow Trench Formation

Grow Pad Oxide: A very thin (~200A) layer of silicon dioxide (SiO2) is grown on the surface by reacting silicon and oxygen at high temperatures. This will serve as a stress relief layer between the silicon and the subsequent nitride layer.



Pad Oxide

4


Deposit Silicon Nitride: A layer (~2500A) of silicon nitride (Si3N4) is deposited using Chemical Vapor Deposition. This will serve as a polish stop layer during trench formation.



Silicon Nitride

5


Pattern Photoresist for Definition of Trenches: One of the most critical patterning steps in the process. 0.5 - 1.0 microns of resist is spun, exposed, and developed.



Silicon Nitride

Photoresist

6


Etch Nitride and Pad Oxide: A reactive ion etch (RIE) utilizing fluorine chemistry is used.



Silicon Nitride

Photoresist

7


Etch Trenches in Silicon: A reactive ion etch (RIE) utilizing fluorine chemistry is used. Defines transistor active areas.



Silicon Nitride

Photoresist

Transistor Active Areas

Isolation Trenches

8


Remove Photoresist: An oxygen plasma is used to burn off the resist layer.



Silicon Nitride

Transistor Active Areas

Isolation Trenches

9


Fill Trenches with Oxide: A CVD oxide layer is deposited to conformally fill the trenches. The oxide will prevent “cross-talk” between the transistors in the circuit.



Silicon Nitride

Future PMOS Transistor

Silicon Dioxide

Future NMOS Transistor

No current can flow through here!

10


Polish Trench Oxide: The surface oxide is removed using a Chemical Mechanical Polish (CMP). The CMP process is designed to stop on silicon nitride.



Silicon Nitride

Future PMOS Transistor Future NMOS Transistor

No current can flow through here!

11


Remove Silicon Nitride: A wet etch in hot phosphoric acid (H3PO4) is used, completing formation of Shallow Trench Isolation (STI).




12

Basic CMOS Process Flow - Well Formation

Pattern Photoresist for N-Well Formation: A non-critical masking layer, utilizing thicker resist to block the implant.




Photoresist

13


Implant N-Well: A deep (high-energy) implant of phosphorous ions creates a localized N-type region for the PMOS transistor.



Future NMOS Transistor

Photoresist

N- Well

Phosphorous (-) Ions

14


Strip N-Well Photoresist:



Future NMOS TransistorN- Well

15

Photoresist


Pattern Photoresist for P-Well Formation: A non-critical masking layer, utilizing thicker resist to block the implant.



Future NMOS TransistorN- Well

16


Implant P-Well: A deep (high-energy) implant of boron ions creates a localized P-type region for the NMOS transistor.



Photoresist

N- Well

Boron (+) Ions

P- Well

17


Strip P-Well Photoresist:



N- Well P- Well

18


Anneal Well Implants: This step repairs damage to the silicon surface caused by the implants and electrically activates the dopants. It also drives the dopants somewhat deeper, but Rapid Thermal Processing is used to minimize dopant spreading.


Silicon Epi Layer P-P- WellN- Well

19

Basic CMOS Process Flow - Gate Formation

Grow Sacrificial Oxide: A thin (~250A) oxide layer is grown to capture defects in the silicon surface.



Sacrificial Oxide

20


Remove Sacrificial Oxide: Sac ox is immediately removed in a wet HF solution, leaving behind a clean silicon surface.



21


Grow Gate Oxide: This is the most critical step in the process! A very thin (20-100A) oxide layer is grown that will serve as the gate dielectric for both transistors. It must be extremely clean, and grown to a very precise thickness (+/- 1A).



22


Deposit Polysilicon: Polycrystalline silicon is deposited using Chemical Vapor Deposition to a thickness of 1500-3000 angstroms.



Polysilicon

23


Pattern Photoresist to Define Gate Electrodes:

This is the most critical patterning step in the process! Precise sizing of the poly gate length is a first-order determinant of transistor switching speed. The highest-technology patterning systems are used (i.e. DUV) along with thinner-than-normal photoresist due to the critical nature of the layer.



PhotoresistChannel Length

Polysilicon

24


Etch Polysilicon and Strip Resist: Reactive Ion Etching using fluorine chemistry is used. The completes the formation of the “gate stack.”



Gate Oxide

Poly Gate Electrode

25

Basic CMOS Process Flow - Gate FormationOxidize Polysilicon: A thin layer of oxide is grown on top of the polysilicon to act as a buffer between the poly and the subsequent silicon nitride layer.



Gate Oxide

Poly Gate Electrode

Poly Re-oxidation

26

Basic CMOS Process Flow - Source/Drain Formation

Pattern Photoresist for NMOS Transistor Tip Implant:



Photoresist

27

Basic CMOS Process Flow - Source/Drain FormationNMOS Transistor Tip Implant: A very shallow (low energy) and low dose implant of arsenic ions begins the formation of the NMOS transistor source and drain. The “tip” will serve to reduce hot electron effects near the gate region.



Photoresist

Arsenic (-) Ions

N Tip

28


Strip Photoresist:



N Tip

29


Pattern Photoresist for PMOS Transistor Tip Implant:



Photoresist

N Tip

30


PMOS Transistor Tip Implant: A very shallow (low energy) and low dose implant of BF2 ions begins the formation of the PMOS transistor source and drain. The “tip” will serve to reduce hot electron effects near the gate region.



Photoresist

BF2 (+) Ions

N TipP Tip

31


Strip Photoresist:



N TipP Tip

32


Deposit Silicon Nitride Layer: Using Chemical Vapor Deposition, thickness 1200-1800A.



Silicon Nitride

Thinner Here

Thicker Here

N TipP Tip

33

Basic CMOS Process Flow - Source/Drain FormationEtch Nitride to Form Spacer Sidewalls: Using a carefully controlled RIE etch, the thin nitride is removed from the horizontal surfaces, but the sidewalls remain. These sidewalls will precisely position the implants that form the transistor sources and drains.



Spacer Sidewall

N TipP Tip

34


Pattern Photoresist for NMOS Transistor Source/Drain Implant:



Photoresist

N TipP Tip

35

Basic CMOS Process Flow - Source/Drain FormationNMOS Transistor Source/Drain Implant: A shallow and high-dose implant of arsenic ions completes the formation of the heavily-doped NMOS transistor source and drain. The spacer shadows the implant near the gate region.



Photoresist

Arsenic (-) Ions

N+ Source N+ DrainP Tip

36


Strip Photoresist:



N+ Source N+ DrainP Tip

37

Basic CMOS Process Flow - Source/Drain FormationPattern Photoresist for PMOS Transistor Source/Drain Implant:



N+ Source N+ Drain

Photoresist

P Tip

38

Basic CMOS Process Flow - Source/Drain FormationPMOS Transistor Source/Drain Implant: A shallow and high-dose implant of BF2 ions completes the formation of the heavily-doped PMOS transistor source and drain. The spacer shadows the implant near the gate region.



BF2 (+) Ions

Photoresist

N+ Source N+ DrainP+ DrainP+ Source

39


Strip Photoresist and Anneal Implants: Use Rapid Thermal Annealing to virtually eliminate dopant migration in the shallow source and drains. The electronic devices are now completely formed. All that remains is to connect them together.



N+ Source N+ DrainP+ DrainP+ Source

Lightly Doped “Tips”

40

Basic CMOS Process Flow - Salicide Formation

Strip Surface Oxides: A quick dip in HF to expose bare silicon in the source, gate, and drain areas.



N+ Source N+ DrainP+ Source P+ Drain

41


Deposit Titanium: Use a sputterer to deposit a thin (200-400A) layer of titanium across the entire wafer surface.



N+ Source N+ DrainP+ Source P+ DrainTitanium

42


Titanium Silicide Formation: Rapid Thermal Processing in nitrogen at 800 Degrees C causes the titanium to react with silicon, forming titanium silicide, where the two are in contact. In other areas, the titanium is unchanged. This process perfectly aligns the silicide to the exposed silicon, and is called Self-Aligned Silicide, or Salicide.




Titanium SilicideUnreacted Titanium

43


Titanium Etch: The unreacted titanium is removed using a wet etch in NH4OH + H2O2. The titanium silicide remains. TiSi2 provides an ohmic contact between silicon and metal.




Titanium Silicide

44

Basic CMOS Process Flow - 1st Interconnect LayerDeposit BPSG: Silicon dioxide doped with small amounts of boron and phosphorous to enable film reflow and to getter contaminants. Deposited using Chemical Vapor Deposition. Approximate thickness is 1 micron. This layer will electrically insulate the devices from the 1st metal layer.




BPSG

45

Basic CMOS Process Flow - 1st Interconnect Layer

Polish BPSG: Use Chemical Mechanical Polishing to achieve a flat surface on the BPSG layer. If not removed, the bumps on the surface from the underlying topography would cause a problem for the subsequent photolithography steps and degrade metal step coverage.




BPSG

46


Pattern Photoresist to Define Contacts: Contacts are openings in the BPSG layer enabling electrical access to the devices below. This is a critical photolithography step.




BPSG

Photoresist

47


Contact Etch: A carefully designed RIE etch using fluorine chemistry to achieve vertical sidewalls.




BPSG

Photoresist

48

Strip Photoresist:




BPSG


49


Titanium Nitride Deposition: A sputterer is used to deposit TiN to a thickness of about 200A. This layer will help the subsequent tungsten layer to adhere to the oxide.




BPSG

Titanium Nitride

50

Basic CMOS Process Flow - 1st Interconnect LayerTungsten Deposition: Tungsten is chosen because it deposits conformally (via CVD) and can fill the contact holes. The thickness must be at least half of the diameter of the contact.




BPSG

Titanium Nitride

Tungsten

51


Polish Tungsten: CMP is used to remove the surface tungsten. The remaining tungsten forms “plugs”. The surface titanium nitride is also removed.




BPSG W Contact Plug

52

Deposit Metal1 Layer: Each interconnect layer is actually a sandwich of different layers. A sample is shown below. The films are deposited by sputtering.




BPSG W Contact Plug

Metal1

Ti (200A) - electromigration shuntTiN (500A) - diffusion barrier

AlCu (5000A) - main conductor

TiN (500A) - antireflective coating


53

Pattern Photoresist for Metal1 Interconnects:




BPSG W Contact Plug

Metal1

Photoresist


54

Etch Metal1: An RIE etch utilizing chlorine chemistry. Multiple etch steps are required due to the multiple different metal layers.




BPSG W Contact Plug

Metal1

Photoresist


55

Strip Photoresist: First interconnect layer is completed.




BPSG W Contact Plug

Metal1


56

Basic CMOS Process Flow - 2nd through Nth (as many as 8) Interconnect Layer

Deposit IMD1: Undoped silicon dioxide is deposited using successive CVD depositions and etches to achieve filling between metal lines. Approximate thickness is 1 micron. This layer will electrically insulate the metal layers from one another.




BPSG W Contact Plug

Metal1

IMD1

57

Basic CMOS Process Flow - 2nd through Nth interconnect Layer

Polish IMD1: Use Chemical Mechanical Polishing to achieve a flat surface on the IMD layer. If not removed, the bumps on the surface from the underlying topography would cause a problem for the subsequent photolithography steps and degrade metal step coverage.




BPSG W Contact Plug

Metal1

IMD1

58

Pattern Photoresist to Define Vias: Vias are contact openings in the IMD layers enabling electrical access between metal layers.




BPSG W Contact Plug

Metal1

IMD1

Photoresist


59

Via Etch: A carefully designed RIE etch using fluorine chemistry to achieve vertical sidewalls.




BPSG W Contact Plug

Metal1

IMD1

Photoresist


60

Strip Photoresist:




BPSG W Contact Plug

Metal1

IMD1


61

Tungsten

Deposit Titanium Nitride and Tungsten: Same as for the first interconnect layer.




BPSG W Contact Plug

Metal1

IMD1


62

Polish Tungsten:




BPSG W Contact Plug

Metal1

IMD1 W Via Plug


63

Deposit Metal2: Subsequent metal stacks will be similar to Metal1 but tend to increase in thickness and width as their runs are longer and they carry more current.




BPSG W Contact Plug

Metal1

IMD1 W Via Plug

Metal2


64

Pattern Photoresist for Metal2 Interconnects:

Adjacent metal layers are patterned perpendicular to each other to minimize inductive coupling between layers (not shown in cross-sectional diagram).




BPSG W Contact Plug

Metal1

IMD1 W Via Plug

Metal2

Photoresist


65

Etch Metal2: An RIE etch utilizing chlorine chemistry. Multiple etch steps are required due to the multiple different metal layers.




BPSG W Contact Plug

Metal1

IMD1 W Via Plug

Metal2

Photoresist


66

Strip Photoresist: 2nd interconnect layer is completed.




BPSG W Contact Plug

Metal1

IMD1 W Via Plug

Metal2


67

Basic CMOS Process Flow - PassivationDeposit Passivation Layer: There are many types of passivation (silicon nitride, silicon oxynitride, polyimide, and others). Its purpose is to protect the completed circuit from scratches, contamination, and moisture.




BPSG W Contact Plug

Metal1

IMD1 W Via Plug

Metal2

Passivation

68




BPSG W Contact Plug

Metal1

IMD1 W Via Plug

Metal2

Passivation Bond Pad

Poly Gate

Gate Oxide

Silicide Spacer

Basic CMOS Process Flow - PassivationPattern Passivation Layer: Polyimide passivation is photo-definable. Other passivation layers require a patterned photoresist layer followed by an etch step. Bond pad openings allow electrical access to the chip.

69

Basic CMOS Process Flow

Now Let’s Review!!

Basic IC Fabrication 2

Documents

Transcript of Basic IC Fabrication 2