CAE tools and technology challenges in making deep sub-micron IC designs Kostas Kloukinas CERN,...

CAE tools and technology challenges in making deep sub-micron IC designs

Kostas KloukinasCERN, PH-ESE dept.

CH1211, Geneve 23

Switzerland

ESE Group seminar 30/3/2010

Overview

Technology Challenges

Modern CAE Tools

IC design CAE tools at CERN

30/3/10 [email protected] 2

How it all got started….


10 cm process

.35 um process

…and the story continues…


CAE Tools co-evolved with process technology

What drives CAE tools Innovation


CAE tools have to coop with:

Deep Submicron effects “Black List” Numerous and Complicated Design Manufacturing Rules Leakage currents of devices Interconnect parasitics Process Variations Process Fault modes and Design For Manufacturability (DFM)

Design Challenges System On Chips (SOC) and IP Reuse Low Power Design techniques Formal Design Methodologies

Digital design flows Analog and Mixed Signal flows Hierarchical Implementation flows

Advanced Verification Techniques


Complicated Design Rules Design Manual page count:

250nm: 170 pages 130nm: 600 pages + numerous application notes

Design Rule Check deck files: 250nm: 5,300 lines 130nm: 13,500 lines 90nm: 38,400 lines 65nm: 89,300 lines

One single verification tool is not capable any more to detect all DRC violations! Foundries require design sign-off verification using independently two

verification tools from two different vendors.

Tools make use of parameterized cells (Pcells) and automated “analog routers” to assist layout work and increase design productivity.


Parameterized cell

Full Custom IC Assembly Router

Features and Benefits Device, cell, block and top-level chip

assembly routing support. Design constraint and process rule driven Interactive signal routing Multi-net/bus routing support On the fly Design Rule checking Variable Width and Spacing rules Automated signal routing Automated special net shielding

Requirements: Support from foundry PDK with

technology specific design rules andconstraints.


Tool: Cadence Virtuoso Chip Assembly Router to augment design productivity.

Leakage currents affecting Power Digital Circuit Power Dissipation

Dynamic Power dissipation Short circuit power Switching power P = C * f * V2

dd

Static Power due to leakage currents

Leakage currents in deep submicron technologies: Gate tunneling leakage (a) Sub-threshold leakage (b) Reversed biased PN junction leakage (c) Gate Induced Drain Leakage (b)

Leakage Power is a significant component of the total power dissipationin 90nm technologies and below.


Multiple VT standard cell libraries Multiple VT standard cell libraries.

High VT cells for low power

Low VT cells for high performance

Nominal VT cells for general purpose.

Logic synthesis High performance strategy

Synthesize with Low VT libraries and then optimize with High and Nominal.

Low power strategy Synthesize with High VT libraries

and then optimize with Low and Nominal.

Integrated strategy Synthesize with all libraries concurrently. State-of-the-art synthesis tools, like Synopsys “Design

Compiler” or Cadence “RTL Compiler”, support multi VT synthesis. Efficient synthesis is obtained when it is implemented at a cell level (not block level).

CAE tools have to deal with: Multiple libraries of 1,000s of cells Highly customized design flows.


Low Power Design (1/6)


Multi Voltage Libraries Different fixed supply voltages

depending performance requirements. Requires standard cell libraries

characterized at different supply voltages

Level Shifter cells Each power domain receives the voltage swing it expects.

Power Gating Power down idle blocks to reduce leakage currents. Requires special power control cells (switches) as well as isolation and state retention cells.

Dynamic Voltage and Frequency scaling. Voltage and frequency dynamically adjusted in response to changing workloads. Applicable to processors and microcontrollers.

CAE tools are required to handle: Multiple standard cell libraries characterized at different

power supply voltages. Floorplanning and special power rooting. Multi modes, Multi Voltage of operation.

High-Low Level Shifter

Low-HighLevel Shifter

Floorplanning with Level Shifters

Low Power Design (2/6) Power Switch cells

In a power gating design, sleep transistors are used as switches to shut off power supplies to parts of a design in standby mode

Power Grid floorplanning Better IR drop management & area optimization. Complexity in Physical Synthesis and Power Routing.

Ring Style floorplanning Less complex P&R especially for existing hard IP blocks For large blocks the IR drop in the center can be high.

Isolation & State Retention cells Isolation logic is typically used at the output of

a powered-down block to prevent floating, unpowered signals (represented by unknown or X in simulation) from propagating from powered-down blocks.

To speed power-up recovery, state retention power gating flops can be used to retain their state while the power is off.


Power grid distribution Ring style distribution

Low Power Design (3/6) Control of the substrate voltage

Basic Principle: Increase the back gate voltage to increase VT and thus

decrease leakage. Decrease the back gate voltage to decrease VT and thus

increase performance at the expense of leakage power consumption. (Difficult & risky approach)

Special Tap cells (fill cells) Back or forward biasing for

performance/leakage optimization N-well voltage different from VDD Substrate or P-well (triple well process) voltage different

from VSS Bias voltage routed as signal pin or special power net

Correct well/substrate voltages in case of on-chip power gating Well pins connect wells to always-on power supplies

Keep wells “alive” when island is power down VNW must connect to always-on power when using

“header” power switches. VPW must connect to always-on power when using

“footer” power switches.



Clock Gating Useful when data only loaded infrequently. No dynamic power when clock is stopped. Transformation to the 2nd implementation can be

done automatically by the CAE synthesis tool. Integrated Clock Gating cells (ICG) are special

standard cells that ensure a predictable clock gating behavior.

Controlled with tool specific settings. Can use normal standard cells but timing issues

are always a hazard.

Clock Gating: Cloning & Decloning You can even reduce the power some more by

moving the clock gating cells to higher levels in the hierarchy and combining them as much as possible.




Operand Isolation (Data Gating) Holding inputs to combinatorial blocks constant when

their outputs are not required. Reduces power by preventing switching activity

Gate level power optimizations Cell sizing Buffering Pin swapping Factoring

Implementation choices for Data Paths Multipliers Adders Bus Encoding Pipelining

Asynchronous Logic Design Extremely hard work with practically no support

from CAE tools!


Power intend description languages Universal Power Format (Synopsys) Common Power Format (Cadence)

Power aware simulation Power aware synthesis Power aware verification Power aware implementation Power aware logic equivalence check Power aware sign-off


Interconnect Parasitics Increased number of metal layers at finer pitch.

The wire interconnect dominates timing Gate delay equals to interconnect delay at 130nm.

Metal interconnects have smaller widths, taller heights, shorter intra-layer spacing. In 350nm, wire to substrate capacitance was dominant. In 90nm, wire to wire capacitance is dominant.

Increased complexity of interconnect parasitic device extraction: Copper wire distortions caused primarily due to

CMP (Chemical Mechanical Polishing) results in irregular trapezoid conductors.

Below 90nm wireline variations require (min/typ/max) extraction.


Signal Integrity issues Crosstalk in Deep Submicron

Smaller geometries increase coupling Technologies have gotten faster.

Edge rates are much higher, increasing the likelihood of crosstalk and worsen power/ground bounce.

Chips are much more complex, increasing the likelihood of long parallel wires.

Crosstalk induced Noise The aggressor net causes glitching on the victim net. If the glitches coincide with clock edges

then errors occur.

Crosstalk induced Delay Causing signal to speed up or slow down.

CAE Tools involved: Interconnect parasitic extraction engines. Static Timing Analysis engines Timing Optimization engines (buffer resizing) Place & Route engines (net reordering, wire spreading)


Evolution of Digital Libraries

More accurate Timing Libraries Above 90nm NLDM is good enough

NLDM (Non Linear Device Model) “liberty” files (.lib)

Below 90nm Current Source models in use Interconnect capacitance > cell drive impedance. Non linear switching waveforms. Input pin capacitance becomes a function slope. Current sources are more effective at tracking

non-linear switching waveforms. Timing, Noise and Power calculations. ECSM (Effective Current Source Model) by Cadence CCS (Composite Current Source model) by Synopsys

More Libraries due to: Multi-VT options Multi-voltage options Multi-corners due to process parameters:

Tox, VTh variations Interconnect variations


MMMC analysis & optimization Static Timing Analysis & Optimization

Many Modes of operation Functional modes Low Power design techniques

Process Variations Interconnect corners Device VT corners

Range of Voltage & Temperature conditions.

Traditional method Single mode/corner analysis Design for worst case conditions Still good for 90nm Overdesign or non-converging solution for < 65nm.

MMMC: Multi Mode Multi Corner “Scenario” (PVT+Mode+Parasitics) based approach. Optimization runs concurrently on all “scenarios” . Tools identify “dominant scenarios” performing

automated “scenario” reductions.


Design for Variability Process Variations

Random dopant fluctuations affecting VTH Lithography (metalization) Intra-die variations Wafer- level, wafer-to-wafer, lot-to-lot variations

Traditional Static Timing Analysis Difficult to meet timimg Too pessimistic => overdesign.

Statistical Static Timing Analysis (SSTA) RC extraction with sensitivites Uses sensitivities to find correlations among

delays. Uses these correlations when computing how to

add statistical distributions of delays. Needs libraries supporting statistical timing


Design for Reliability IR drop refers to fluctuations of the supply

voltage over the length of the supply line.

For IC design we consider both static & dynamic IR drop.

Electromigration EM problems occur when the power grid is not

sufficient to handle the current densities required by the design.

On the signal nets driven by high drive strength cells if the wires are too narrow,

On the power grid when several large current hungry cells are placed near to each other and are fed by inadequate power grid routing.

CAE Tools Synopsys: PrimeRail Cadence: VoltageStorm


Animated voltage drop maps

Automated Power Grid Design PNA: Power Network Analysis

Manual Power Planning Provides early estimation of the final sign-off

analysis. “Virtual rails” that are not simulated,

only higher metal layers are considered. “What if” analysis varying number of straps,

width of straps, placement of pads, etc. Iterations to achieve target constraints.

PNS: Power Network Synthesis Attempt to eliminate the manual work! PN constraints describe the design targets like

total IR drop, as well as provide guidelines for the layout of the grid.

PNS is quite often an iterative process. Once the IR-drop and EM maps look ok the

power plan can be committed and the physical straps and rings can actually be laid down.


Power Network Analysis

Power Network Synthesis

Flip Chip Solutions

RDL flow Wirebond pads placed at the periphery. Redistribution wiring layer to connect to ball pads.

Area Array flow Special C4 IO pads placed in designated “sites” inside the chip area. Special short signal routing. Special concerns for the placement of ESD structures


Design For Manufacturability Antenna Violations

To prevent damage caused by charge build-up on MOS gates (during plasma etch processing steps), which causes damage to the MOS gate oxides

If you fail to fix antenna violations, you will end up with plasma induced gate oxide damage.

Max Metal Width Rules To prevent large areas of metal from lifting off during

processing due to differences in thermal co-efficient (metal and substrate will expand by different amounts)

Reduces the effects of Electro-migration. Slotting/Cheesing wide wires

or Splitting wide wires into multiple smaller wires.

Pattern Density Rules To reduce dishing and erosion of the inter-level dielectrics,

requires metal lines to be at a certain minimum distance from each other (metal density). This leads to the so called metal fills (dummy metal)


The cause of many design Tape Out delays! Early consideration of pattern density rules is essential.

Layout Sign-Off Tools


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Sign-off Evolution: Growing Importance of Sign-off

Example

1X

Complexity

30-40X

complexity

180nm

130nm

90nm

65nm

Design Schedule Design Schedule Variability Due to Sign-off

Future Project – 40 32nm ?

Should be predictable

Conservative design

Analog & Mixed Signal Flows


The Concept

The use of the workflows may vary depending on the design requirements and organization of design teams.

Top-Down Functional Design Early chip level verification strategy has to be in place and validated with correct partitioning between analog and digital. As the project is proceeding toward completion, the same top-level validation is done by replacing the behavioural model with a transistor-level description (including RC parasitic if required).

Top-Down Physical Design Early floorplanning (including pad placement) even with rough estimation of block (area, aspect ratio, pin location) will enable to plan for special nets routing (buses, clocks, power network, sensitive nets ...). As the project is proceeding toward completion, the same floorplanning could be refined and adapted.

Bottom-up Block Function & Physical Design Analog and Digital block circuit level implementation (transistors & gates)

Advanced CAE tools platform. Full-Custom Analog design

Cadence Virtuoso platform “Front End design flow”

Standard-cell Digital design Cadence SOC Encounter platform “Back End design flow”

Key Technology: Open Access database A common database to save & restore designs

from Virtuoso and SOC_Encounter platforms. Significantly reduces data translations and

associated errors. Open standard. (http://openeda.org)


“Analog on Top” Design Flow


SOC_EncounterDigital block creation

SOC_EncounterDigital block creation

VirtuosoChip assembly

VirtuosoChip assembly

For big ‘A’ small ‘D’ designs.For big ‘A’ small ‘D’ designs.

BeginBegin

FinishFinish

Virtuoso Floorplanning Generate Physical Hierarchy.

Early in design phase: from soft-block (abstract) to hard-block (layout)

Helps avoid late-in-cycle block resizing, reshaping, pin-shuffling.

Cut down design cycle time with continuous and iterative floorplanning.

Accurate area estimation.

Full connectivity view (instances, connectivity, pins & prboundary)

Partial layout view generation (abstract like)


AMS Designer Simulator

Mixed-signal, mixed-language, mixed-level simulator. Verilog¨, Verilog-A, Verilog-AMS, VHDL, VHDL-AMS,

System-C, System-Verilog, SPICE, and Spectre languages

Component-level schematics, netlists, behavioral models, structural models

A single-executable simulator incorporating the fastest in digital simulation (NCSim) with a choice of analog solvers (Spectre and UltraSim¨). UltraSim provide FastSPICE simulation capability.

Built on the INCA (Interleaved Native Compiled Architecture) platform.

High performance Fewer interfaces between tools Small, efficient memory footprint

Unified Debugging environment


Constraint driven Analog design


“Digital on Top” Design Flow


SOC_EncounterChip Design

SOC_EncounterChip Design

VirtuosoAnalog Block Creation

VirtuosoAnalog Block Creation

For big ‘D’ small ‘A’ designs.For big ‘D’ small ‘A’ designs.

RTL synthesis

Floorplanning& power routing

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

SignoffRC extraction

Timing analysis

DRC

DFM

LVS

Logical Equivalence

CheckingClock tree synthesis

Routing

Timing optimization

Timing optimization

Tape-out

Automated taskUser task

Objectives At present, Support for two advanced technology nodes:

Development of: “CMOS8RF Mixed Signal Design Kit” “Analog & Mixed Signal Methodologies (Workflows)”

Provide: Maintenance Training Support


CMOS 8RF-LM

Low cost technology forLarge Digital designs

CMOS 8RF-LM

Low cost technology forLarge Digital designs

CMOS 8RF-DM

Low cost technology for Analog & RF designs

CMOS 8RF-DM

Low cost technology for Analog & RF designs

BiCMOS 8WL

Cost effective technology for Low Power RF designs

BiCMOS 8WL

Cost effective technology for Low Power RF designs

BiCMOS 8HP

High Performance technology for demanding RF designs

BiCMOS 8HP

High Performance technology for demanding RF designs

CMOS 9SF LP/RF

High performance technology for dense designs

CMOS 9SF LP/RF

High performance technology for dense designs

130nm CMOS130nm CMOS 90nm CMOS90nm CMOS

CAE Tools & Technology support


FoundryFoundry Physical IPvendors

Physical IPvendors

CAE Toolsvendors

CAE Toolsvendors

CERN CAE tools &

technology support

CERN CAE tools &

technology support

Cadence VCAD

design services

Cadence VCAD

design services

CERN designersCERN designers External designersExternal designers

CMOS8RF Mixed Signal design kit

30/3/10 [email protected]

IBM Standard

cell libraries

IBM Standard

cell libraries

IBM PDKIBM PDK

Mixed Signal Design

Kit

Mixed Signal Design

Kit

CAE Tool

s

CAE Tool

s

Key Features: IBM PDK V1.6 IBM Standard cell and IO pad libraries

Physical Layout views available. Access to standard cell libraries is legally

covered by already established IBM CDAs

New versions of CAE Tools Open Access database support.

Interoperability of Virtuoso and SOC-Encounter platforms.

Compatible with the “Europractice” distributions.

Support for LINUX Platform (qualified on RHEL4)

Two design kits available: CMOS8RF-DM (3-2-3 BEOL) CMOS8RF-LM (6-2 BEOL)

38

CMOS8RF Mixed Signal Workflows


Analog & Mixed Signal (AMS) Workflows. Formalize the design work by employing

standardized and validated Design Workflows. Formalize the design work

across design teams in common projects. Provide a repository with reference design examples.

Development work subcontracted to Cadence, VCAD design services.

Close collaboration of CERN - VCAD - IBM VCAD brought in their invaluable expertise on the CAE tools IBM provided the physical IP blocks and important technical assistance CERN assisted the development and validated the design kit functionality.

39

Analog & Mixed Signal Workflows



Prepared bySandro BonaciniCERN PH/[email protected]

“I2C slave” serial interface IP block employing Triple Module Redundancyfor enhanced SEU protection.


RTL synthesis

Floorplanning& power routing

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization


Timing analysis

DRC

DFM

LVS

Logical Equivalence

CheckingClock tree synthesis

Routing

Timing optimization

Timing optimization

Tape-out

Automated task

User task

Digital Design Flow

Synthesis


RTL compilerscript [.tcl]

Abstract layoutDefinition [.lef]

Capacitancetables [.CapTbl]

Max timingLiberty libraries

[.lib]

RTL synthesis

RTL description[.v] / [.vhd]

Timingconstraints

[.sdc]

Mapped netlist[.v]

Conformal script[.lec]

Synthesis,mapping andtiming reports

[email protected]

Logic Equivalent Checking (LEC)


Tool: Conformal

Logical Equivalence

Checking

Max timingLiberty libraries

[.lib]

Mapped netlist[.v]

Conformal script[.lec]

RTL description[.v] / [.vhd]

LECreport

[email protected]

Floorplanning & Power Routing


Define Chip/core size target area utilization I/O placement module placement in

case of TMR or other special constraints

Power planning/routing Core/block rings and

stripes

[email protected]

Placement


Encounter command file

Placement

Scan-chain reorder

Open AccessFloorplannedDesign [.oa]

Connect cells power/ground

Add tap cells

Open AccessPlaced

Design [.oa]

Reports

[email protected]

Placement

30/3/10 [email protected] 47Sandro Bonacini - PH/ESE - [email protected]

Power/ground connections

Tap cellsStandard cells

[email protected]

Congestion analysis


Use Encounter Trialroute to estimate congested areas

Manually add placement partial blockage

Change position of I/Os or blocks

…or increase number of routing metals

Open AccessPlaced

Design [.oa]

Congestion analysis

Placement optimization

Open AccessPlaced

Design [.oa]

[email protected]

Clock tree synthesis & signal routing


[email protected]

Design For Manufacturing



Cells & metal fill

Open AccessRouted

Design [.oa]

Antenna fix

Via optimization

Timing analysis

Open AccessFinal

Design [.oa]

Signoff timingreport

Delay file[.sdf]

Final netlist[.v]

Signal integrity analysis

[email protected]

Antenna fix


Re-routes long nets Inserts tie-down diodes

[email protected]

Via optimization


[email protected]

Filler cells and metal fill


[email protected]

Back to Virtuoso !


OA design is present in Virtuoso Easily included in a

mixed-signal chip

[email protected]

Training: AMS Workshops

Workshop Targets: Present the IBM CMOS8RF (130nm) Mixed Signal Kit. Present Workflows for Analog, Digital and Mixed Signal designs. Introduce the new Platform of Cadence CAE Tools.

This is NOT: A course on analog or digital designing. An advanced course targeted to a specific Cadence Tool.


Example Design

The workshop modules are based on a realistic Mixed Signal ASIC: Analog IP block: DAC Digital IP block: SRAM Digital block: I2C slave

synthesizable RTL code Triple Module Redundancy

Digital Flow Scripts

Top level Behavioral Modeling

Design verification

Final chip Physical verification


AMS Workshop Contents Day 1 (Lead by Maxime Barbe)

- Introduction to AMS kit Workshop - Functional Verification : Digital Simulation Flow - Functional Verification : AMS Simulation from command-line - Functional Verification : AMS Simulation from DFII

Day 2 (Lead by Maxime Barbe)- Analog IP Characterization : ADEXL - Overview of IC6.13 (ADEXL and VSE) - Analog Block Creation: Constraints

Day 3 (Lead by Vincent Cao Van Phu) - Hierarchical Floorplaning (Virtuoso based) - CDB IP Import to OA database for IC61 Methodology

Day 4 (Lead by Vincent Cao Van Phu)- Digital Block Implementation- Block IP Characterization Back End- Digital IP Characterization Front-End

Day 5 (Lead by Vincent Cao Van Phu)- Constraint Driven Analog Block Creation Back-End- DRC (Calibre + Assura workflows)- LVS (Callibre + Assura workflows)- Extraction- Round table discussion and workshop evaluation (30min).


Analog &

Mixed Signal

Digital

Physical Verification

AMS Workshops Workshop sessions

1st session: 26/10 – 30/10, 2009 (CERN internal engineers, “pilot” run) 2nd session: 16/11 – 20/11, 2009 (CERN, open to external engineers) 3rd session: 30/11 – 4/12, 2009 (IPHC, Strasbourg, France) 4th session: 1/2 – 5/2, 2010 (CERN, with fees) 5th session: 15/2 – 19/2, 2010 (CERN, with fees) 6th session: 1/3 – 5/3, 2010 (CERN, with fees) 7th session: 12/4 – 16/4, 2010 (CERN, with fees)

Statistics 10 engineers/session. 70 engineers in total.

Support Technical: Bert Van Koningsveld Secretarial: Evelyne Dho


Future Plans

Extend the functionalities of the CMOS8RF (130nm) kit. Next PDK release scheduled for 3Q 2010

Integrates PDK V1.7.0 Implements bug fixes as reported by users.

Development of a Design Kit for the CMOS9LP/RF (90nm) Standard cell libraries. Design Workflows similar to those in the CMOS8RF Design Kit.

IP Block Packaging Solution


IP packaging solution (VCAD)


DECM tool in use at CERN Design Environment Configuration Management

Workflow management tool Design environment configuration

(environment variables, startup files, tool paths, etc) CAE tools rely heavily on UNIX environment variables for their

configuration.

Centralized management: Customized design environment for each project Consistency of setup within the design team Stability Project versioning

Flexibility Easy Graphical User Interface for the users and administrators. Different GUIs for different user roles Multiple sessions with different design environment configurations Built in project access control mechanism

VCAD Productivity IP solution.

Administrator: Bert Van Koningsveld


PDKs &LibrariesPDKs &Libraries

EDA ToolsEDA Tools ProjectsProjectsWorkflowsWorkflows

Admin editorAdmin editor Project editorProject editor Project usersProject users

DECM serverDECM server

RAID ServerRAID ServerCAE Server #1CAE Server #1

Users Workstations (LINUX PCs)

lnxmic2SUNC. Paillard

lnxmic3SUNK. Kloukinas

lnxmic4SUNS. Marchioro

lnxmic5SUNA. Rivetti

lnxmic6CogestraL. Pierobon

lnxmic7CogestraW. Bialas

lnxmics1DELL1 TB RAID 1 Disc Storage

lnxmic8Cogestra P. Aspell

Tivoli serverTivoli serverCERN ITCERN ESE

lnxmic9SUNP. MoreiraS. Bonacini

lnxmic10SUNW. Snoeys

DAS serverDELL7 TB RAID 6 Disc Storage

LINUX CAE platform for IC design STATUS: Feb. 15, 2010


lnxmic11CogestraM. Marra

lnxmic12SUNG. Venturini

lnxmic13SUNJ. Kaplon

lnxmic14SUNK. Poltorak

lnxmic15SUNF. Faccio

lnxmic16SUNS. Michelis

lnxmic17SUNS. Orlandi

lnxmic18SUNF. Anghinolfi

lnxmic19SUNW. Snoeys

lnxmic20CogestraR. De Oliveira

lnxmic21HP L. Perktold

lnxmic22SUNX. Llopart

lnxmicjbSUNT.S. Poikela

File Backup serverAdministrators: Bert Van Koningsveld Wojciech Bialas

The CERN ASIC support website


http://cern.ch/asic-support

Download Design Kits and access technical documents(restricted access)

Information about MPW runs and foundry access services.

Communicate news and User support feedback formsand access request forms.

This website replaces our ‘afs’ based download facility.

Wrap Up

A message to Industry


A message to industry:“ The present situation of IC design, which has high levels of flexibility in implementation is not sustainable by small and medium scale design groupsand a highly structured design flow and methodologies will need to be established”

Foundry Foundry

130 nm

90 nm

65 nm

45 nm

Third party IP vendorsThird party IP vendors

MethodologiesMethodologies

CAE VendorsCAE Vendors


Acknowledgements• IDESA training EU 7th Framework Program (http://www.idesa-training.org/) for material presented in slides.• Cadence & VCAD services group in Paris for material presented in slides.• IBM for technology data presented in slides.• Sandro [email protected], for his work on the customized digital design flow.• [email protected], [email protected], for their efforts in the CAE tools support services.

Sign-Off Formal Equivalence

Verify that the final netlist is functionally equivalent to the original RTL code.

Using formal methods to compare logic. Two representations:

Reference (Golden) RTL code, the “correct” reference design Implementation (unknown) the design being verified.

Give a pass/fail result with information to help diagnosis.


CAE tools and technology challenges in making deep sub-micron IC designs Kostas Kloukinas CERN,...

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