Assembly and Test Houses: Checklist for Discrete ... · PDF fileChecklist for Discrete...

DLR-RF-PS-STD-010

Issue 1

April 2010

Assembly and Test Houses:

Checklist for Discrete Semiconductor Components

Manufacturer and Line Survey

Basic Specification No.2025200

Issue 1

Deutsches Zentrum German für Luft- und Raumfahrt e.V. Aerospace Center


Checklist for Discrete Semiconductor Components Manufacturer and Line Survey Basic Specification No.2025200 Draft: DLR-RF-PS-STD-010

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Copyright © 2005 German Aerospace Center - DLR. All rights reserved. Copyright © in this document is owned by German Aerospace Center - DLR. Any person is hereby authorized to view, copy, print, and distribute this document subject to the following conditions:

The document may be used for informational purposes only. The document may only be used for non-commercial, non-profit purposes. Any copy of this document thereof must include this Copyright notice.

This document is provided "as is", and copyright holders make no warranties, including, but not limited to, warranties of merchantability, fitness for a particular purpose, non.infringement; that the contents of the document are suitable for any purpose; nor that the implementation of such contents will not infringe any third party patents, copyrights, trademarks or other rights. Copyright holders will not be liable for any direct, indirect, special or consequential damages arising out of any use of the document or the performance or implementation of the contents thereof. For permission requests, questions, or further information, please contact Dr. Andreas Jain - DLR - Quality and Product Assurance, +49 (2203) 601 - 2954.


Checklist for Discrete Semiconductor Components Manufacturer and Line Survey Basic Specification No.2025200 Draft: DLR-RF-PS-STD-010

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Table of Contents

1. PURPOSE 5

2. APPLICABLE DOCUMENTS 5

3. TERMS AND DEFINITIONS 6

4. INTRODUCTION 7

4.1 General 7 4.2 Capability Program Variants 7

5. ACCESS AND PROPRIETARY INFORMATION 7

6. REQUIREMENTS 8

6.1 Requirements for an ATH 8 6.2 Requirements for a Semiconductor Manufacturer 8

7. EVALUATION PROCEDURE 9

7.1 Audit Team 9 7.2 Audit Preparation 9 7.3 Audit Conduct 10 7.4 Audit Reporting 12 7.5 Corrective Actions 12 7.6 Audit Records 13

8. ATH QUESTIONNAIRE 14

8.1 General 14 8.2 Survey checklist 15 APPENDIX A Guideline for a Questionnaire for Audit by the ATH at the Chip Manufacturer 54

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Change Record

Issue Details of Change

A Initial Issue

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1. PURPOSE

The purpose of this specification is to define the requirements of ESCC 20200 Component Manufacturer Evaluation as part of the Evaluation Phase of an DLR Capability Approval of Assembly and Test House ( ATH ) with ATH Product Capability Approval or ATH Capability Approval both in accordance with Basic Specification No 2435200. The specification provides an audit- and checklist which enables the party interested in procurement of the subject components to assess the ability of the ATH concerned to successfully execute a contract for the supply of high reliability semiconductors.

2. APPLICABLE DOCUMENTS

The following documents form part of, and shall be read in conjunction with, this specification. The relevant issues shall be those in effect on date of starting evaluation.

DLR-Documents

- DLR No. 5200, Discrete Semiconductor Components ; Assembly and Test Houses; Generic Specification.

- DLR No. 2265200, Evaluation Test Program for Discrete Semiconductor Technologies; Assembly and Test Houses; Basic Specification - DLR No. 2435200, Requirements for Capability Approval of Discrete Semiconductor Technologies; Assembly and Test Houses: Basic Specification

ESCC-Documents

- ESCC No. 20200, Component Manufacturer Evaluation. - ESCC No. 20600, Preservation Packaging and Despatch of ESCC Electronic

Components. - ESCC No. 21500, Calibration System Requirements. - ESCC No. 21300 Terms, Definitions, Abbreviations, Symbols and Units. - ESCC No. 20900, Radiographic Inspection of Electronic Components. - ESCC No. 22700, Requirements and Guidelines for the Process Identification

Document ( PID ) - ESCC No. 23800, Electrostatic Discharge Sensitivity Test Method.

- ESCC No. 24600, Minimum Quality System Requirements.

Other (Reference) Documents

- MIL-STD-202, Test Methods for Electronic and Electrical Component Parts. - MIL-STD-750, Test Methods for Semiconductor Devices - MIL-STD-883, Test Methods and Procedures for Microelectronics. - ISO Publication No.8402, Quality Management and Quality Assurance- Vocabulary - ISO Publication No.9000, Quality Management Systems: Fundamentals and Vocabulary

- ISO Publication No.10011-1, Guidelines for Auditing Quality Systems- Part 1: Auditing - ISO Publication No.10011-2,Guidelines for Auditing Quality Systems- Part 2: Qualification

Criteria for Quality Systems Auditors

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3. TERMS AND DEFINITIONS

The general terms, definitions, abbreviations, symbols and units specified in ESCC 21300, ESCC 20200 and ISO Publication No. 8402 shall apply. In addition the following shall apply: Abbreviations ATH Assembly and Test House DLR Deutsches Zentrum für Luft- und Raumfahrt ESCC European Space Component Coordination PID Process Identification Document SM Semiconductor Manufacturer Definitions Assembly and Test House A company which procures the Discrete Semiconductor Chips from the semiconductor manufacturer in the needed quality and at agreed standards, assembles these chips into packages and performs all relevant and required inspections, testing and measurements at chip and package level.

Semiconductor Manufacturer A company which designs the Discrete Semiconductor Chips,

develops the processes for the Chip Fabrication and performs the Chips Production in the required characteristic and quality.

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4. INTRODUCTION

4.1 GENERAL

The purpose of the evaluation of an ATH is to assess the capability and the adequacy of the organisation, plant and facilities and to ascertain the ATH's ability to supply Semiconductor components to the appropriate ESCC and DLR specifications.

The ATH evaluation is managed by the DLR. The main assessment comprises one or more formal audits conducted by an DLR audit team appointed by managing agency.

4.2 CAPABILITY PROGRAM VARIANTS

As subsequent described this specification defines for Assembly and Test Houses (ATH) two variants of capability programs. ATH Product Capability Approval The ATH Product Capability Approval of a component technology demands that all requirements for a component technology including the semiconductor chip technology are successfully met. This requires in addition to the activities for the assembly and testing of the components at the ATH a very close cooperation with and control by the ATH of the semiconductor manufacturer and the willingness of the semiconductor manufacturer to perform all specified activities within this specification and in the specification ESCC 24300. After successful completion of the evaluation and capability approval program components within the specified capability domain are considered as qualified components. ATH Capability Approval The ATH Capability Approval requires the successful performance of all activities by the ATH for the assembly and testing of the components as specified within this specification and in the specification ESCC 24300. The ATH has to procure the semiconductor chips to the highest available quality level and has to demonstrate the compatibility of the semiconductor chips with the package and the applied assembly and testing processes. But the semiconductor manufacturer with his product is not part of the capability program.

However, components delivered by an ATH with an ATH Capability Approval can not be considered as a qualified component. As long as these components are within the specified capability domain only the assembly and the testing of such components can be considered as qualified.

5. ACCESS AND PROPRIETARY INFORMATION

For an ATH Product Capability Program the ATH shall allow the DLR audit team to have access to all appropriate working areas and provide access to personnel and facilities sufficient for the accomplishment of the evaluation. The semiconductor manufacturer shall allow the ATH team to have access to all appropriate working areas and provide access to personnel and facilities sufficient for the accomplishment of the evaluation. For an ATH Capability Program the ATH shall allow the DLR audit team to have access to all appropriate working areas and provide access to personnel and facilities sufficient for the accomplishment of the evaluation. The DLR respectively the ATH is responsible for ensuring that all proprietary information obtained in the course of the evaluation is not disclosed to any other party without the expressive written permission of the ATH respectively the semiconductor manufacturer. Reports arising from the evaluation shall be treated as strictly confidential between the ATH, the semiconductor manufacturer and the DLR.

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6. REQUIREMENTS

6.1 REQUIREMENTS FOR AN ATH

For a successful evaluation of the ATH it is required to be able to demonstrate conformance to the DLR requirements: For a quality system in the case the of an ATH Product Capability Program or an ATH

Capability Program the ATH must meet the requirements of ESCC 24600 and the specifications referenced herein.

For the manufacturing line in the case of an ATH Product Capability Program and of a ATH

Capability Program the ATH must apply the appropriate quality system requirements to the line and be able to demonstrate a systematic ability to manufacture the required DLR components in accordance with an approved PID to the requirements of the applicable DLR or ESCC Generic and Detail Specifications.

For the survey and control of the semiconductor manufacturer in the case of an ATH

Product Capability Program, the ATH must have a quality management system in place which allows a survey and control for the wafer / chips manufacturing at the semiconductor manufacturer. For this purpose the ATH shall establish a questionnaire for the semiconductor manufacturer. Guidelines for such a questionnaire are provided in Appendix A to this specification.

The ATH must achieve conformance within the evaluation phase of a DLR qualification or capability approval. At the outset of an evaluation, the ATH is required to make a self assessment of the degree of existing conformance and to initiate appropriate measures to achieve total conformance.

6.2 REQUIREMENTS ON A SEMICONDUCTOR MANUFACTURER

For a successful evaluation the semiconductor manufacturer is required to be able to demonstrate conformance to the DLR requirements: in the case of an ATH Product Capability Program to fulfil the requirements for the survey

and control regarding wafer and chip manufacturing conducted by the ATH. The guideline for the requirements can be find in Appendix A to this specification.

in the case of an ATH Capability Program to fulfil the ATH purchase order requirements. At the outset of an evaluation, the ATH is required to make a self assessment of the degree of existing conformance of the semiconductor manufacturer and to initiate appropriate measures to achieve total conformance.

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7. EVALUATION PROCEDURE

The evaluation procedure is illustrated in the flow chart given in Figure 1. It comprises the gathering of background information, the establishment of a degree of readiness and the performance of one or more audits of the quality system and manufacturing line of the ATH.

In the case of an ATH Product Capability Program also the survey and control of the semiconductor manufacturer is illustrated

In addition to the procedural details defined herein, an audit shall be performed generally in accordance with the guidelines of ISO Publication No.10011-1.

7.1 AUDIT TEAM

In the case of an ATH Capability Program an audit team will be established by DLR with an audit team leader ( Lead Auditor ) responsible for the planning, executing, reporting and close out of the audit at the ATH. Additionally in the case of an ATH Product Capability Program the ATH itself shall establish an audit team with an audit team leader ( Lead Auditor ) responsible for the planning, executing, reporting and close out of the audit at the semiconductor manufacturer. Roles and responsibilities of auditors shall comply with sub-clause 4.2.1 of ISO Publication No. 10011-1 and auditors shall be selected with due regard to the recommendations of ISO Publication 10011-2.

7.2 AUDIT PREPARATION

The Lead Auditor shall plan the audit with the ATH, additionally in the case of an ATH Product Capability Program the ATH shall plan the audit with the semiconductor manufacturer by appropriate communications and meetings to achieve the following objectives: an agreed audit plan with audit dates. The plan is to include kick-off and close-out meetings, a

schedule indicating the main topics to be audited and the assignment of auditors to audit tasks. The plan shall also define the working language for the performance of the audit.

Completion of the audit questionnaires of Para.8 by the ATH and of Appendix A by the

semiconductor manufacturer and their review by the auditors prior to the audit. Review by the auditors of appropriate ATH and / or semiconductor manufacturer documentation (

e.g. Quality manual, PID, wafer fabrication etc. ) prior to the audit. Submission by the ATH and / or the semiconductor manufacturer of the statement of readiness of

Appendix B of ESCC 20200 prior to the audit. Acceptance of the Lead Auditor, or in the case of an ATH Product Capability Program the

ATH of any declared shortcomings or non-conformances from the ATH and / or the semiconductor manufacturer prior to the audit in so far as they affect the utility and timing of the audit. ( An audit shall be postponed when known shortcomings are too numerous or of a critical nature. )

Identification of the ATH and / or semiconductor manufacturer key personnel to host the audit. Acceptance by the ATH of the DLR audit team personnel. Acceptance by the semiconductor manufacturer in the case of an ATH Product Capability

Program of the ATH's audit team personnel.

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The ATH and / or the semiconductor manufacturer shall plan appropriately for the audit so as to ensure that: A review by the DLR respectively by the ATH in the case of an ATH Product Capability

Program requirements has been completed and any significant known areas of non-conformance are identified in conjunction with the submission of the Statement of Readiness of Appendix B of ESCC 20200.

The facilities and areas to be audited will be appropriately operational with normal complement of

personnel and accessible by the auditors against agreed audit schedule. An appropriate meeting room is available to the audit team for the opening and closing meetings

as well as for review of documents and for any closed audit team discussions. The chief inspector or other designated management personnel are available for the closing

meeting to receive the summary of the audit results.

7.3 AUDIT CONDUCT

The audit, whether a quality system, a manufacturing line audit or the survey and control of the semiconductor manufacturer in the case of an ATH Product Capability Program , shall be conducted in the following manner: An kick-off meeting to introduce the audit team and audit hosts, to outline the purpose and scope

of the audit and to agree any changes to the audit schedule or other practical details. Performance of the audit with the aid of the appropriate DLR Checklist, respectively the ATH

Checklist in the case of the survey and control of the semiconductor manufacturer in the case of an ATH Product Capability Program by review of documentation and records, observations of work and inspection practices and by the questioning of appropriate personnel. All concerns, whether findings or observations, shall be communicated verbally at the time to the audit host and / or the the supervisory staff for the function concerned.

On completion of the audit activities the audit team shall meet in closed session to prepare an

executive summary of the audit results. This summary shall identify the major areas of concern arising from the audit.

A close-out meeting to present the executive summary of the audit results.

Figure I Evaluation Procedure is shown here after.

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FIGURE I: EVALUATION PROCEDURE

ATH assesses

compliance

Conducted by DLR Conducted by ATH

Semiconductor Manufacturer ( SM )

assesses compliance

ATH completes

questionnaire

Semiconductor Manufacturer

completes questionnaire

ATH provides statement

of readiness

Semiconductor Manufacturer

provides statement of readiness

Perform

Audit

Audit

Report

ATH / Semiconductor Manufacturer

Corrective Action Plan

Close Out of

Corrective Actions

Completion of Evaluation Phase

ATH appoints

audit team

DLR appoints

audit team

Audit Planning

( meeting with ATH if

required )

Audit Planning

( meeting with SM if

required )

Commence Evaluation

Phase

Component

Evaluation ( DLR No. 2265200 )

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7.4 AUDIT REPORTING

The Lead Auditor is responsible for the preparation and distribution of an audit report in English reflecting the results obtained by the audit team. The report shall include inter alia:

A statement of confidentiality generally in accordance with model given in Appendix C of

ESCC20200 A distribution list, agreed with the ATH and / or the semiconductor manufacturer, to include the

audit team members, the DLR's and the ATH's Chief Inspector or other designated person, and the responsible DLR and / or ATH personnel managing the controlling activity.

The purpose and scope of the audit. The definitions of finding, observation, and comment. An executive summary giving the main concerns and whether the audit was satisfactory or

unsatisfactory. In general and finding equates to an unsatisfactory audit and initiates a corresponding requirement for corrective action.

A recommendation, with reference to the purpose of the audit, as to whether the audit results may

affect the ATH's or the semiconductor manufacturer's ability to properly continue the overall activity, e.g. the evaluation phase, until appropriate corrective actions are completed.

A sequential listing of all findings, observations and comments. Where applicable precise objective

evidence shall be recorded together with references to the relevant requirements document. When necessary, a request for a corrective action plan addressing findings and observation. Acknowledgements. Appendices to include relevant details of the audit planning / execution, personnel involved and

the statement of readiness. Where useful, a completed Checklist shall also be appended. The audit report shall be submitted within a period agreed between the ATH and / or the semiconductor manufacturer and the lead auditor.

7.5 CORRECTIVE ACTIONS

When requested to do so, the ATH and / or the semiconductor manufacturer shall prepare and submit a corrective action plan within an agreed period from receipt of the audit report. The plan shall address each finding with one or more corrective actions and shall discuss each observation with corrective actions where appropriate. The plan shall identify responsible personnel and due dates against each action.

The lead auditor shall review the corrective action plan and accept it when it is considered to adequately address the audit results. The lead auditor is responsible for the monitoring of the close out of the corrective actions. Verification may appropriately be achieved by communications, review of revised documents, specific meetings or by a re-audit. On successful completion of the corrective action plan the lead auditor shall provide the ATH and / or the semiconductor manufacturer with a notification of the audit close out.

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7.6 AUDIT RECORDS

The lead auditor is responsible for the delivery of an audit file on close out of the audit to DLR . The audit file is to contain, as a minimum: The audit report the corrective action plan Evidence of close out of the individual actions Copies of appropriate correspondence The formal notification of audit close out provided to the ATH and / or the semiconductor

manufacturer.

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8. ATH QUESTIONNAIRE

8.1 GENERAL

This questionnaire is designed for use during initial survey of an ATH's ability to produce high quality articles, its management organisation, production facilities, test facilities and technical know-how. When completed, this Checklist should enable the party interested in procurement of the subject components to assess the ability of the ATH concerned to successfully execute a contract for the supply of high reliability space hardware. The questionnaire content should be used by the ATH as a reference when completing the statement of readiness given in Appendix C of ESCC20200. Completed questionnaires together with supporting documents ( company quality manual, company and product brochures, draft PID etc. ) should be submitted to the lead auditor in accordance with Para 7.2.

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8.2 SURVEY CHECKLIST

8.2.1

ATH AND SURVEY TEAM INFORMATION

a) ATH Name : Address : Telephone : web-site :

b)

Survey requested by : Survey Team Leader : Team Members :

c)

Key personnel of ATH interviewed: Name Function Contact 1. 2. 3. 4. 5. 6.

d)

Type of Company ( Private company, limited company, etc. )

e)

Affiliated with any other company? If so, which:

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f)

No. of employees: - total number : - Production : - Quality Assurance : - Q.A Inspection : - Prod.Engineering : - Design Engineering : -Reliability Control : -Other :

g)

Number of shifts :

Para Topic Yes No N/A Comments

h)

General Production line : (1) Device types manufactured:

(2) Will flow diagrams of steps to

produce discrete semiconductors

be available to survey team?

i)

Are specifications, if any,

referenced in the flow diagram

j)

Principal Government and

industrial customers:

1.

2.

3.

k)

Is the ATH's semiconductor production

1. Continuous 2. Pilot Production 3. Advanced R&D, limited

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f)

No. of employees: - total number : - Production : - Quality Assurance : - Q.A Inspection : - Prod.Engineering : - Design Engineering : -Reliability Control : -Other :

Para Topic Yes No N/A Comments

8.2.2 MANAGEMENT ORGANISATION

a) Is the management organisation and responsibilities defined in official ATH documentation?

b) Has the quality policy been

documented by management, and is it known and followed at all levels of the organisation?

d) Which level of management

participates actively in orientating policy towards space component production?

e) Is the management

representative for quality management reporting on the performance of the quality system to the ATH's management?

Does this system lead to ( corrective ) actions being taken in respect of the production line?

f) Is the executive management

reviewing the quality system at defined intervals to ensure its continuing suitability and effectiveness in satisfying ISO9001 and ESCC No.24600?

g) Do current and future business

plans include the continuing supply of space components and where is this stated and by

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Para Topic Yes No N/A Comments whom?

h) Is there a policy declaration

concerning proprietary rights and confidentiality concerning manufacturing processes and will this inhibit the audit?

i) What is management commitment to supplying space components, developing further space business and increasing the semiconductor technological scope in respect of space components?

j) Is space component business /

production integrated with other business sectors or is it segregated by the use of special space production / flow lines?

k) Do senior management

understand special needs of space component business and space requirements and is this disseminated to key areas of the organisation?

l) Has the 'reliability' department

the same authority from management as the 'engineering' and 'production' departments? Does this mean direct responsibility for reliability of products in the line?

m) How would contract for space

components be organised?

n) How can original requirements

from Orderer ( DLR, Space Agency or end-user ) be assumed to be correctly translated into internal instructions?

o) How can information necessary

to the Orderer ( corrective actions, deviations, notification of inspection, and / or problem areas ) be assumed to be issued and channelled to the Orderer?

8.2.3 QUALITY ASSURANCE SYSTEM AND ORGANISATION

a) Does the ATH have an existing and maintained quality assurance system and organisation?

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Para Topic Yes No N/A Comments Is this system in compliance with ESCC24600 Is this system in compliance with other quality system standards In case of YES, which standards are this?

b)

Is there an appointed quality representative / quality manager / chief inspector And to whom does (s)he report?

c) Does the ATH have a quality

manual?

d) Is this manual; as a whole or

relevant sections; available to designated departmental organisation holders? Is this document kept updated

e) Is there a description in the

quality manual of quality policy, quality organisation, and supporting quality documentation system, procedures and work instructions?

f)

Has the quality assurance group sufficient authority in relation to its position within the company's organisation ( see organigramm )?

g) Are areas of responsibility within

the quality assurance group clearly defined?

h) Are quality plans developed to

meet the project requirements of specific market sectors?

Is such a quality plan available for space grade semiconductor components?

i) Are corrective actions to which

Q.A management is committed delegated to responsible staff or does Q.A management have

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Para Topic Yes No N/A Comments direct authority regarding the line?

j) Is there a periodic quality data reporting system covering all operational and manufacturing operations?

k)

What is the relationship between the quality organisation and the reliability organisation

l) Is a Q.A. Manual or equivalent

document supplied to all levels of appropriate supervisory personnel?

Is such document updated

m) Are written procedure available

for identification, segregation, control and disposal of accepted / rejected materials?

n)

Is there an inspection system in place and is it performed by quality assurance personnel and / or other departmental personnel?

o) Is this inspection system used throughout the ATH's organisation and specially in the following areas: - Incoming Inspection - In-process Inspection - Manufacturing Process - Final Inspection and testing - Packaging and delivery

p) Does Q.A maintain a system of written procedures for statistic controls ( control chart, lot plot, etc. ) in any of the following areas: - In-process inspection - Manufacturing process

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Para Topic Yes No N/A Comments - Final inspection

q) Is Q.A responsible for

determination of need for, and the conducting of, quality training?

r) Are training programmes in

place for all quality and reliability critical processes and are personnel attending these training programmes tested for competency at: - the conclusion of training courses - Periodically

s) Are work instructions available

to inspection and production personnel and are visual aids provided to personnel where necessary?

t) Is there an internal quality audit

policy established and does it maintain an internal quality audit system and define the responsibilities for conducting internal audits?

u) Is the internal quality audit

system fully documented and are there associated planned programmes and procedures?

v) Are internal quality audits

performed in association with : - ESCC requirement - ISO 9000 requirements

w)

Are the findings and reports of internal quality audits reviewed and analysed. And are these findings and reports followed up in terms of corrective and preventive measures? And is there evidence of this influencing quality policy and management attitude to quality?

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Para Topic Yes No N/A Comments x)

Is there an established procedure defining identification, collection, indexing,access, filling, storage, maintenance and disposition of quality records?

Are records maintained for a minimum of 5 years?

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Para Topic Yes No

N/A

Comments

8.2.4 MEASURING, TEST EQUIPMENT AND CALIBRATION

a) Does the ATH maintain a

documented measuring equipment, standards and software control and calibration system and a time schedule for measurement frequency?

b) Is calibration of equipment and

facilities subcontracted If so, from whom? What is the name and status of this facilities and is the organisation certified / accredited to International / European / National standard systems and which?

And is the subcontracted calibration system fully documented? If not, is the internal calibration system fully documented and described?

c) Is the internal calibration

system using standards traceable to International / European / National standards?

d) Are calibration procedures

adhered to and up-to date?

e) Who is responsible for the

management of the calibration system and which department maintains the system and takes custody of measuring equipment and calibration standards?

f) Are decals used for equipment

identification to show that the units have been calibrated; when next calibration date is due and calibrator identification?

Are decals up-to-date?

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Para Topic Yes No

N/A

Comments

Para Topic Yes

No

N/A

Comments

g) Does the calibration system

include training of personnel engaged in calibration duties?

h) Have calibrating personnel up-

to-date certification records reflecting date, traceability to NBS and identification of calibrator

i) Does the calibration system

embodies methods of introducing new equipment and facilities into the calibration system and determine calibration status?

j) Does the calibration system

include methods of re-introduction and re-calibration of repaired or modified equipment and facilities?

k) Do the calibration procedures

provide measures for removal of any equipment not maintained or calibrated according to established schedules?

l) Are there measures available

for making calibrated equipment tamper-proof and for the detection of tampering?

m) Is measuring equipment stored,

handled and transported under controlled conditions?

n) Is the calibration status of the

measuring equipment compatible with record held?

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Para Topic Yes No

N/A

Comments

8.2.5 CONFIGURATION OF DOCUMENTS AND DRAWINGS

a)

Has the ATH adequate written procedures for configuration control of specifications, documents, drawings and contract changes?

b) Does the configuration control

system provide for documented change control guaranteeing availability of required drawing at relevant manufacturing or inspection step?

Do flow documents show current revisions

c) Does the system cater for the

provision of a master list and matters of configuration controlled documents and drawings?

d) Are all ESCC, European /

International / National standards and specification used by the ATH up to-date and of the correct and latest issue?

e) Does Q.A review all drawings

and changes therein prior to their becoming effective?

f) Has the ATH established a

procedure for involvement of material suppliers and customers in the configuration control process?

g) Are current specification

revisions shown on prints of drawings?

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Para Topic Yes No

N/A

Comments

8.2.6 RELIABILITY

a) Does the ATH have an

established reliability system and is it defined in formal documentation

b) Does the ATH have a separate

reliability organisation or in absence of this is their personnel designated with responsibilities for operating a documented reliability system?

c) Does staff operating the

reliability system have same authority as quality, production and engineering management?

d) Is there a direct feed-back of

information between Reliability, Design Engineering and Q.A groups to ensure timely notification of all relevant data?

e) Does the reliability system

respond promptly and efficiently to unexpected and / or newly detected failures?

f) Are line failures ( type and

causes ) analysed and reported to those responsible for corrective actions?

g) Are corrective actions resulting

from failure analysis agreed with the Q.A group involved or Reliability if parts or process changes must be made? Q.A Group :

Reliability :

h) Has Reliability right to approve

test specifications, data tabulation, parts or process changes?

i) Is there a system for :

In-process failure analysis:

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Para Topic Yes No

N/A

Comments

End -item failure analysis:

Para Topic Yes

No

N/A

Comments

j) Are following items submitted to

failure analysis as a matter of routine?

- Production line rejects?:

- Lots with high rejection rate:

Define: - ( e.g. out of family )

- Items returned by Orderer :

- Items returned by Orderer with special request for failure analysis:

k) Has the ATH a failure analysis

laboratory for an equivalent facility?

l) Is failure analysis equipment:

- Available :

- In use:

- Adequate:

m) Are there trained personnel

dedicated for failure analysis?

n) Are failure analysis procedures:

- Available:

- In Use:

o) Are failure analysis reports:

- Available:

- Adequate:

p) Does rating system provide for

effectiveness of written corrective actions received from Suppliers?

q) Do data sheets reflect the

results of failure analysis reports?

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Para Topic Yes No

N/A

Comments

r) Give examples of problems investigated by failure analysis department?

s) Has the ATH an evaluation

laboratory for determination of product characteristics?

Para Topic Yes

No

N/A

Comments

8.2.6.1 Additional Questions for an ATH with ATH Product Capability Program

a) Does the ATH reliability

system extend to the procurement of discrete semiconductor wafer / dice and is there evidence of its effective operation?

b) Does the ATH reliability

system provide for access to all pertinent development and production data of the discrete semiconductor wafer / dice?

c ) Are reliability data available in

respect of discrete semiconductor wafers / dice processed from the ATH's manufacturing line which are to be Product Capability approved?

d) Does the ATH reliability

system provide for the liaison with the customer concerning reliability expectations for the discrete semiconductor wafers / dice?

e) Does the ATH reliability

system responses to customer requests for reliability requirements and data for the discrete semiconductor wafers / dice?

8.2.7 DESIGN OF COMPONENT

a) Does the ATH have a

programme plan available to ensure the reliability of the

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Para Topic Yes No

N/A

Comments

Discrete Semiconductor Component's design prior to full scale production, release and delivery?

b) Have procedures been

established and responsibilities assigned for the control of development and verification activities at the product design stage, and are they maintained and fulfilled?

Para Topic Yes

No

N/A

Comments

c ) Does the ATH maintain

procedures for the control of information flow between parts of the internal and external organisation involved in the design process?

d) Does the ATH identify,

document, review, design changes and modifications and are they approved by authorised personnel before implementation?

e) Are design input requirements

identified, documented and is their adequacy against customer and regularity requirements reviewed?

f) Are design output

requirements documented in such a way that they can be verified and validated against design input requirements ?

g) Is a block diagram of the

design process and the selection of materials used?

h) Are methods for the

configuration control of designs available?

i) Does the ATH design

procedure include a description of the interface

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Para Topic Yes No

N/A

Comments

between design planning and customer component specification review?

j) Does the ATH have a system

for presentation of the design to the customer, formal agreement of the design, amendment of the design and freezing of the final design?

k) Does the ATH have a system

for assessment of the impact of design changes?

Para Topic Yes No

N/A

Comments

l)

Does the ATH have a system for identification of personnel authorised to make changes in the design?


a) Has The ATH a description of

the physical design layout rule set which specifies the topology of all physical structures, including those for alignment and test purposes in terms of:

Function ( e.g. Diffusion, conductor, contact, dielectric )

Size ( e.g. min./max. width / length / depth )

Positioning ( e.g. Spacing between structures of equal or different nature )

The vertical dimensions of all layers ( e.g. Depth of diffusion, trenches, thickness of polysilicon, metallisation )

b) Has the ATH a description of

the electrical rule and parameter set in terms of:

31

Para Topic Yes No

N/A

Comments

Sheet resistivities

Current carrying capability

Sheet and edge capacitances

dielectric breakdown voltages

Transistor parameters and associated simulation models

Other relevant parameters or restrictions not covered in the previous points like suitability to implement special circuit design techniques

Para Topic Yes

No

N/A

Comments

c ) Has the ATH acquired or

established traceability to information and data describing the design system employed by the wafer / die fabrication source in respect of:

A general description of the design system including block diagrams representing: - the software structure of the system

the implementation of a configuration control system guaranteeing the traceability of all software and data forming part of the system

The application of a quality assurance system addressing at least documentation procedures, acceptance testing prior to system release and the organisation of error

32

Para Topic Yes No

N/A

Comments

reporting and corrective action procedure

A description of hardware platform ( e.g. Work stations )

The library of cells, including pad cells, shall be described at least in terms of: - the circuit symbol characterised by its name and pad connections with associated function -the functional diagram - electrical and timing parameters including guard ring functions and static and dynamic power consumption - the detailed circuit schematic including effective transistor size

Software and associated data described in terms of: - the origin and version of the programme - A comprehensive description of its functional scope - The programming language and the amount of code - All software serving simulation type purposes that requires a detailed description of the underlying models and their parametric capabilities

A description of the design configuration control system

A description of the design quality assurance system

d) Has the ATH acquired or

33

Para Topic Yes No

N/A

Comments

established traceability to design proving data arised from test structures that include:

Transistors and capacitors for measurement of oxide charge density and threshold voltage shifts

Diodes and transistors for the measurement of leakage currents

Resistors for the measurement of current carrying capabilities and electromigration

Measurement of dielectric breakdown voltages for each dielectric layer

evaluation of other known failure modes or parametric degradations affecting the technology when subjected to radiation

Test data for each wafer / die technology

e) Does the ATH have the

necessary arrangements and documented procedures with the wafer / die source that demonstrates:

The necessary design configuration control agreements and assurances

That wafer / dice come from fabrication lots of space proven designs

That procured wafer / dice is accompanied with supporting performance data

The ATH is advised in a timely manner of changes to proven designs together with any necessary new design proving measures, test results and performance

34

Para Topic Yes No

N/A

Comments

data

That, in the case of design changes, the ATH's procurement specifications reflect the appropriate issue status to proven design

f) Has the ATH acquired or

established traceability to verification data relevant to all materials, process and device parameters as there are:

Sheet resistance for each non dielectric layer ( e.g. polysilicon metal )

Contact resistance

Dielectric isolation ( breakdown voltage )

Transistor parameters

Leakage currents

Junction alignment

Para Topic Yes

No

N/A

Comments

8.2.8 Compatibility between Chip and Assembly Methods and Materials

a) Does the ATH define and

document the compatibility between discrete semiconductor design and manufacturing?

b) Does the ATH verify and how

is it verified that the discrete semiconductor component has been designed exclusively with approved materials, wafers / dice and processes?

c ) Does the ATH verify and how

is it verified that the discrete semiconductor component has been designed in compliance with all the stated technology related electrical, mechanical, environmental / climatic

35

Para Topic Yes No

N/A

Comments

rules?

d) Does the ATH co-operate with

the customer regarding drawing reviews and agreement for proceed with manufacturing?


a) Does the ATH maintain a

system providing for an audit of the manufacturer of the discrete semiconductor component ?

b) Does the ATH describe details

of the manufacturer of the discrete semiconductor component?

c) Does the ATH describe the co-

ordination of interaction between the discrete semiconductor manufacturer in regard of:

resolving problems during wafer / die manufacturing

production yield

proving of design's suitability in foreseen application

Implementation of the requirements of ESCC 24300 and ESCC 2435200 during wafer / die manufacturing

the implementation of configuration control in respect of proven design?

Warranty for the discrete semiconductor in regard of functionality, quality and materials used

8.2.9 Procurement of Wafer / Die and other Materials

a) Does the ATH identify all

wafer / die sources used in the assembly, packaging and test of components intended for space applications including:

36

Para Topic Yes No

N/A

Comments

the type of source ( e.g. Fabrication plant authorised distributor )

their location

points of contact?

b) Does the ATH identify the

procured wafer / dice technologies and are there contractually binding agreements with the wafer / dice manufacturer in respect of:

used technologies and materials

type of substrate, orientation, epitaxy, backside

c) Does the ATH describe the

space qualification status of the procured wafer / dice ( e.g. RHA designator, MIL class, )

Para Topic Yes

No

N/A

Comments

d) Does the ATH have a system,

procedures and descriptions of:

Form and content of procurement specification

The methods how to ensure that space proven wafer / die designs are specified together with the appropriate status

Content of procurement specification as e.g.: maximum ratings, specification of electrical, mechanical and environmental performance

37

Para Topic Yes No

N/A

Comments

Identification of procured material

How the procurement specification is reviewed internally, with the customer and the wafer / die source and the effect of this for the final specification

How information is handled when specification changes require modifications of current purchase order.

How “incoming inspection” is informed of changes in purchase order.

e) Does the ATH have a vendor

rating system?

f) Does the ATH have an

agreement / dialogue with the wafer / die source concerning intended use, assembly, packaging and test methods

Para Topic Yes

No

N/A

Comments


38

Para Topic Yes No

N/A

Comments

a) Does the ATH have contracts

/ agreements with the wafer / die source for:

Formalised authority / agreements concerning the distribution, marketing of the wafer / dice and the assembly and packaging of the die.

Acquisition of reliability and process data

Liability related to failures during assembly, packaging and testing

Liability related to “in service” failures due to failure of the procured wafer / dice

Notification of changes during fabrication process and semiconductor design

Notification of problems and fabrication deficiencies found after wafer / die deliveries

8.2.10 Incoming Inspection of Wafer / Die and other Materials

a) Are the ATH written standard

inspection procedures adequate for control of incoming materials and services received? Do inspectors know how and when to apply these procedures?

b) Are wafer / dice and materials

received in a controlled area from which removal prior to inspection is impossible and which guaranties segregation of non-conforming material?

c) Are wafer / dice and materials

properly handled and protected during incoming inspection?

39

Para Topic Yes No

N/A

Comments

d) Does Incoming Inspection use

drawings and purchase orders assuring lot traceability and homogeneity with proven designs?

If so, do these documents show Quality Control review and are they up-to-date?

e) Are test reports / data

documentation from suppliers being reviewed?

f) Does Incoming Inspection

have appropriate facilities, visual aids and measuring equipment?

g) Does Incoming Inspection

have provisions for handling, storage and protection of wafer / dice and other type of material?

h) Does the Incoming Inspection

system provide for feedback and corrective actions with the source concerning non-conforming material?

i) Does the Incoming Inspection

System provide for inspection, handling, storage of wafer / dice ?

j) Does the Incoming Inspection

system provide for 100% wafer probing, recording of probe data and the marking of non-conforming die?

k) Does Incoming inspection

perform 100% visual inspection of accepted probed wafer?

l) Does Incoming Inspection

perform SEM inspection on sample basis of accepted wafer / dice?

40

Para Topic Yes No

N/A

Comments

m) Does Incoming Inspection

include scribing / breaking of accepted wafer?

If so, is a 100% visual inspection performed afterwards?

n) Does Incoming Inspection

include bondability test, die shear test and lot acceptance test?

o) Are shelf life and cure date

materials properly identified and controlled?

p) Are suitable inspections and

tests, including physical and chemical tests, performed on raw materials?

q) Are Incoming Inspection tests

subcontracted and which are these and to whom?


a) Does Incoming inspection system include:

revision of delivered production data ( e.g. design rules, fabrication process materials, backside processing, parameter monitor and sample plans ) for wafer / dice

revision of production yield during wafer / die manufacturing

revision of wafer acceptance criteria and lot formation

41

Para Topic Yes

No

N/A

Comments

8.2.11 Evaluation of Discrete Semiconductor Wafer / Die / Dice


established policy concerning the evaluation of procured wafer / dice to space / customer requirements?

b) Does the evaluation

programme include:

electrical performance characterisation

review of accompanying data package related to: - quality and reliability, - lot homogeneity - traceability - wafer / lot acceptance test

review of wafer / die fabrication process related to: - workmanship, - materials used, - metallisation, - current density, - final passivation

construction and destructive physical analysis

8.2.12 Assembly and Packaging Line

a) Are discrete semiconductor

components intended for space use manufactured on:

the standard manufacturing line

a special line

a part standard / part special line

b) Are cleanrooms and / or clean

workstations used?

c) Are all manufacturing

operations to be performed in house or are some subcontracted and if so, what

42

Para Topic Yes No

N/A

Comments

steps and to whom?

Para Topic Yes

No

N/A

Comments

d) Are subcontractors for outside

processing and testing evaluated and assessed?

e) Does the ATH have

specialised jigs, fixtures and facilities to manufacture space semiconductor components?

f) Does the ATH identify specific

personnel for the manufacture, inspection and test of space components and is this personnel included in a dedicated training programme?

Are records maintained of training and competence of operators for key wafer / die processing, assembly, packaging and testing?

g) Does the ATH maintain a

system of wafer / die and material traceability and is this fulfilled by the use of travellers?

h) What recent manufacturing

line audits ( internal or external ) have been performed and with what results?

i) Does Q.A. have written in-

process procedures to control acceptance of products?

j) Are requests for corrective

actions issued in writing?

Are such requests answered?

Does corrective actions result in corrective measures being implemented?

k) Does Q.A. Organisation

maintain any statistical

43

Para Topic Yes No

N/A

Comments

controls ( X&R, etc. ) in manufacturing and processing and are these controls up-to-date and at individual process stations?

Para Topic Yes

No

N/A

Comments

l) Are calibrations evidenced

and up-to-date?

m) Are records maintained of

training and competence of operators for key wafer / die processing, assembly, packaging and test?

n) Are certified operators

identifiable by means of a card or badge on their clothing?

o) Are there specific standards

for handling, cleanliness and care of materials, parts and equipment available?

p) Does the ATH maintain an

established system that provides for the selection and approval of materials used regarding:

incoming inspection

procurement specifications

procedures for and control of limited shelf life time

appropriate storage facilities handling and transportation instructions

q) Does the assembly and

packaging line provide for and maintain the following:

cleanliness of manufacturing conditions and environment

44

Para Topic Yes No

N/A

Comments

Clean room conditions and to what processes do the apply: - Production control and Screening tests - Internal Visual Inspection - Cleaning - Sealing

Definition of and documentation how often: - air filters checked and changed - the contamination level of the 10 000 count environment is checked - the contamination level of the 100 count environment is checked

Is authority granted to cease production when contamination level is exceeded?

Ensure that personnel in a clean room environment are provided with adequate protective clothing and which?

Provide clean room procedures and discipline in respect of clothing, access food consumption, allowable materials, cosmetics, etc.?

System for cleaning of components and tools ?

Temporary storage space are suitably protected to maintain the cleanliness level?

8.2.13 Production Control and Screening

a) Does the ATH maintain an

established system that provides for description of the basic technologies used for the assembly, packaging, testing and screening of discrete semiconductor components dedicated for

45

Para Topic Yes No

N/A

Comments

space use?

b) Does the ATH have an

established product control and screening system and is it defined in a process identification document ( PID )

Para Topic Yes

No

N/A

Comments

c) Are the following controls

documented and maintained on the die mounting process:

Temperature

Time

Pressure

Ultrasonic power

Cleanliness

Ambient conditions

Documentation of die shear test results

d) Are the following controls

documented on the lead bonding process:

Type of lead bonding

Temperature

Pressure

Time

Condition of capillary or electrode control

Ultrasonic power

Ambient conditions

Documentation of bond strength test

e) Are devices cleaned prior to

sealing?

Is 100% inspection performed on clean?

46

Para Topic Yes No

N/A

Comments

f) Are devices stored and

transported in protective carriers following cleaning operation?

g) Do inspectors have adequate

visual aids to establish reject criteria prior to encapsulation?

Para Topic Yes

No

N/A

Comments

h) What type of internal visual

inspection is performed and are rejected parts:

stored in containers for rejected parts

identified as rejected parts and how

disposed of and how

i) What type of package sealing

is used?

j) Are the following controls

documented on the sealing operation?

Pre-seal bake ( time temperature, ambient )

Heat ( or power ) used

Humidity during sealing ( moisture content in ppm )

Flow rate of gases

Welding controls ( pressure, power, time )

k) Does the ATH maintain and

document their in-process inspection and test system?

l) Does the ATH use inspection

and / or operation travellers sequential to performance

47

Para Topic Yes No

N/A

Comments

and control of all operations and processes?

m) Do travellers:

refer to inspection procedures and are inspectors trained to use them and when to use them

refer to controlled specifications and do specifications issue show current revision status

Para Topic Yes

No

N/A

Comments

n) Are there documents

describing in-process manufacturing procedures and controls and are inspectors trained in when and how to use them?

o) Do in-process Q.A.

Inspectors:

summarise quality experience on the basis of specific process stages?

issue quality reports on a regular basis?

do these reports result in appropriate remedial actions or improvements in the relevant processes?

p) Is wafer identification

maintained throughout processing?

q) Are masks checked prior to

use?

r) Are wafers / dice stored and

transported in protective carriers?

48

Para Topic Yes No

N/A

Comments

s) Are dice inspected for

physical damage following scribing?

t) Has Q.A authority to stop

production flow in case of out-of-control conditions?

u) Does the ATH provide regular

summary inspection and test reports to the Q.A management ( lot acceptance, percentage of defects, types of failures )?

Do these summary reports result in actions to decrease problem areas?

Para Topic Yes

No

N/A

Comments

v) Is a testing laboratory or

equivalent facility available for Q.A purposes?

Which of the following tests are performed in this laboratory or facility:

Electrical Tests - is there automatic test equipment available and are tests performed on Go-no-go or recorded basis - are D.C and A.C tests performed

Mechanical tests

Chemical tests

w) Is an environmental test

facility available in-house?

If not, state where:

Are the following tests performed at this facility:

Temperature

Shock ( mechanical,

49

Para Topic Yes No

N/A

Comments

thermal )

Acceleration

Vibration

Moisture Resistance

Altitude

Radiographic

Hermeticity ( Gross and fine leak )

Lead Fatigue

Life Tests, Burn-Ins - how many positions are available - does Burn-In , Life test require soldering of leads - what precautions are taken to maintain solderability of leads after burn-in

Are charts provided for the monitoring of environmental test equipment?

x) Is final visual inspection

performed on 100%?

y) State how failed components

are:

separated and segregated from processed lots and how it is ensured that these components are prevented from being unintentionally reinserted with accepted components

stored for failure analysis and other investigations

8.2.14 Inspection and Test Facilities

a) Are environmental test

facilities maintained in - house or are they subcontracted to a Test House or other organisation?

b) Are in-house test facilities and

measuring equipment

50

Para Topic Yes No

N/A

Comments

identified, documented and brought under calibration control?

c) Are subcontracted test

facilities fully identified together with their accreditation status or other recognised approval?

d) Are the following tests

performed in-house:

Temperature

Shock ( mechanical, thermal )

Acceleration

Vibration

Moisture Resistance

Altitude

Radiographic

Hermeticity ( Gross and fine leak )

Lead Fatigue

Life Tests, Burn-Ins

e) How many burn-in positions

are available?

f) Does burn-In require

soldering of leads?

What precautions are taken to maintain solderability of leads after burn-in

g) Are charts provided for the

monitoring of environmental test equipment?

h) Is in-house test equipment

and facilities exclusively for inspection, test and screening purposes or is it also used and / or located in other departments and if so, which departments?

i) Is the test facility suitably:

Illuminated

51

Para Topic Yes No

N/A

Comments

Ventilated

temperature and humidity controlled

Dust-controlled

j) Is availability of relevant

inspection and test procedures at working level in the following areas ensured:

Incoming inspections

In-process inspections

Pre-cap inspections

Production control

Screening tests

Burn-in and electrical testing

Lot acceptance testing

Visual Inspections

Para Topic Yes

No

N/A

Comments

8.2.15 Non Conforming and Corrective Action

a) Have provisions been made

for:

the identification of non-conforming product

the documentation of non-conformities

the segregation of non-conforming products

the notification of relevant functions

b) Are responsibility and

authority for the disposition of non-conforming product specified, documented and maintained?

c) Are non-conforming products

re-processed or reworked and

52

Para Topic Yes No

N/A

Comments

is there a clearly defined re-process and rework policy?

d) Are quality records, such as

non-conformance reports, used to actively determine where corrective actions may be necessary?

e) Has the ATH established an

appropriate failure analysis capability?

f) Is a failure analysis procedure

available and maintained?

g) Is there a maintained

procedure for implementing corrective and preventive actions?

8.2.15.1 Additional Questions for an ATH with Product Capability Approval

a) Are service reports and other customer feedback e.g. reports from discrete semiconductor wafer / die manufacturer, such as non-conformance reports, used to actively determine where corrective actions may be necessary?

8.2.16 Traceability


established system for ensuring identification and traceability for identification of materials, wafer/ dice, parts processed, test structures from drawings, specifications, purchase orders, travellers and documents during all stages of production and delivery?

8.2.16.1 Additional Questions for an ATH with Product Capability Approval


established system for traceability for identification of materials, processes, specifications, test structures, travellers and documentation

53

Para Topic Yes No

N/A

Comments

of wafer / die manufacturing at the discrete semiconductor manufacturer?

8.2.17 Handling, Storage, Packaging and Delivery

a) Do written procedures exist

for handling, storage, packaging and delivery?

b) Are they maintaining the

quality of the product, materials, wafer / dice?

c) Do Q.A personnel perform

audits of outgoing lots?

d) Do shipment documents

reflect inspection status or evidence of inspection, identification and similar shipping requirements?

e) Are devices and invoices

verified against the purchase order?

f) Are special packaging

methods applied for components dedicated for space use?

If so, which are these?

8.2.18 Training of Personnel

a) Are procedures maintained for

identifying training needs and provide for the training of all personnel performing activities affecting quality?

b) Are personnel assigned to

manufacture, test and inspection of dedicated space parts qualified and assessed on the basis of appropriate education, training and experience as required?

8.2.18.1 Additional Question for an ATH with Product Capability Approval

a) Does the ATH's experience

with manufacturing of components dedicated for

54

Para Topic Yes No

N/A

Comments

space use result in education and / or training of relevant personnel at the discrete semiconductor manufacturer?

55

APPENDIX A Guideline for a Questionnaire for Audit by the ATH at the Chip Manufacturer

The minimum requirements for such a questionnaire are defined on the following pages. In the case that chapters' contents, range and questions are similar to paragraphs of the Survey Checklist herein, only the reference to the applicable paragraph of the Survey Checklist is given. The audit can then be conducted along the applicable questions of the Survey Checklist herein. The general range and intent is described in each case within the first line. Where necessary more details are defined or can be defined in the following lines of the relevant chapter. It may become necessary to attach additional sheets by completing this questionnaire.

1.

CHIP MANUFACTURER AND SURVEY TEAM INFORMATION

a) Chip Manufacturer Name : Address : Telephone : web-site :

b)

Survey requested by :

Survey Team Leader : Team Members :

c)

Key personnel of Chip Manufacturer interviewed: Name Function Contact 1. 2. 3. 4.

d)

Type of Company ( Private company, limited company, etc. )

e) Wafer / Chip Type to be procured:

56

Para Topic Yes No

N/A

Comments

2. MANAGEMENT ORGANISATION AND RESPONSIBILITIES

See Survey Checklist para 8.2.2 herein. The structure of the Manufacturer's management organisation and responsibilities shall be determined. Particular emphasis shall be placed on the Manufacturer's management commitment to supplying space grade wafer / dice. The status and support given to the Manufacturer's Quality and Reliability Organisation shall also be determined.

3. QUALITY ASSURANCE SYSTEM AND ORGANISATION

See Survey Checklist para 8.2.3 herein.

The effectiveness and functionality of the Manufacturer's Quality Assurance System and Organisation shall be determined.

Specific quality system requirements are given in ESCC 24600.

4. MEASURING, TEST EQUIPMENT, CALIBRATION


The maintenance by the Manufacturer of a functioning and effective control and calibration system for measuring equipment, standards and test software shall be determined.

Specific ESCC calibration requirements are given in ESCC 21500.

57

Para Topic Yes No

N/A

Comments

5. CONFIGURATION OF DOCUMENTS AND DRAWINGS

See Survey Checklist para 8.2.5 herein. The measures established by the Manufacturer to identify documents and drawings used in the specification, contract, design, manufacture, inspection, test, packaging and release for delivery of space grade components shall be determined.

6. RELIABILITY

See Survey Checklist para 8.2.6 and 8.2.6.1 herein.

It shall be determined if the Manufacturer has a functioning reliability system with the necessary independence and authority to monitor reliability, investigate component reliability problems and impose necessary corrective actions. In addition the aspects of the cooperation between the Manufacturer and the ATH has to be determined.

7. DESIGN OF COMPONENT


The physical design of a discrete semiconductor component is defined by a set of technology specific rules and parameters. The acquisition of data or the traceability to data verifying the geometrical layout rule set and allowing the electrical or optical evaluation of discrete semiconductor wafer / die shall ensure that the procured wafer / die is suitable

58

Para Topic Yes No

N/A

Comments

for space use.

8. COMPATIBILITY BETWEEN CHIP AND ASSEMBLY METHODS AND MATERIALS


The involvement of the Manufacturer in methods, materials and tests for assurance of compatibility between the chip and the assembly methods and materials used by the ATH shall be considered. In addition the involvement of the Manufacturer related to warranty aspects shall be determined.

9. PROCUREMENT OF WAFER / DICE

See Survey Checklist para 8.2.9 8.2.9.1 herein. The relationship between the Manufacturer and the ATH shall be determined. The association established between the ATH and the Manufacturer is the key determinant ensuring that procured wafer / die is reliable and demonstrated as suitable for space use and that lot traceability and homogeneity is maintained.

10. MANUFACTURING LINE

See Survey Checklist para 8.2.10 and 8.2.10.1, and paras 8.2.12. (1) to 8.2.14.( 1) herein.

The Manufacturer's established manufacturing, processing, testing, inspection, wafer cutting ( if applicable ) shall be determined. Additionally the

59

Para Topic Yes No

N/A

Comments

specifics for the procured wafer / dice shall be defined. See below

a) Fabrication process sequence

and limits

b)

Fabrication process materials and their specifications

c) Quality control and incoming

inspection of piece parts and materials used for manufacture procured wafer / dice

d)

Photoresistive materials and their specifications

e) Method of mask making and

identification

f) Doping material source,

concentration and process technique

g) Cross section diffusion profile

h)

Passivation or glassivation material and their specifications, thickness and technique of deposition; process temperature and time

i)

Oxide composition and thickness, temperature and time for oxidation

j)

Metallisation system ( pattern, material,deposition, etching technique, line width and thickness )

k) Junction formation process,

material and technique

l)

Conductor and dielectric materials;

Ohmic contact formation

m)

Backside process including wafer thinning and backside metallisation

n)

Process Parameter monitoring and how are they documented

60

Para Topic Yes No

N/A

Comments

o)

Sample plans for wafer / lot acceptance including quantity and acceptance criteria and applied test sequence

p) Radiation hardness assurance (

if applicable )

q)

Current carrying capability of conductive layers

Dielectric breakdown voltage(s)

r)

Electrical parameters and simulation models

s) Production yield figure

t) Wafer / die size

u)

Manufacturer recommendation for die bonding and die attach methods including time and pressure

11. NONCONFORMING AND CORRECTIVE ACTION


The Manufacturer's established system for identification, documentation, review, segregation, disposition and notification of relevant functions for non-conforming products and

61

Para Topic Yes No

N/A

Comments

processes shall be determined.

12. TRACEABILITY


The Manufacturer's established measures taken to ensure traceability to wafer / die lot, test structures, processes, travellers and identification of associated paperwork and records shall be determined.

13. HANDLING, STORAGE, PACKAGING, DELIVERY


The Manufacturer's established system ensuring adequate handling, storage, packaging and delivery of wafer / dice for space use shall be determined.

14. TRAINING OF PERSONNEL


The Manufacturer's established system for training of personnel shall be determined. The interaction of personnel training at the ATH and the manufacturer shall be defined.

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