A non-linear Electro-thermal scalable Model for High Power RF LDMOS Transistor
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A Nonlinear Electro- Thermal Scalable Model for High-Power RF LDMOS Transistor Author: John Wood, Fellow, IEEE, Peter H. Aaen, Member, IEEE, Daren Bridges, Member, IEEE, Michael Guyonnet, Daniel S. Chan, Member, IEEE, and Nelsy Monsauret Source: IEEE transaction on microwave theory and techniques, Vol:57, No:2 February 2009 Presenter Md. Nur Kutubul Alam Roll: 0703028 EEE Khulna University of Engineering and Technology Bangladesh
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RF LDMOS Transistor
Transcript of A non-linear Electro-thermal scalable Model for High Power RF LDMOS Transistor
MM20 vs HVEKVLDMOS Model DC Only Evaluation
A Nonlinear Electro-Thermal Scalable Model for High-Power RF
LDMOS Transistor
Author: John Wood, Fellow, IEEE, Peter H. Aaen, Member, IEEE, Daren Bridges, Member, IEEE, Michael Guyonnet, Daniel S. Chan, Member, IEEE, and Nelsy MonsauretSource: IEEE transaction on microwave theory and techniques, Vol:57, No:2 February 2009
Presenter Md. Nur Kutubul AlamRoll: 0703028EEEKhulna University of Engineering and TechnologyBangladesh
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Outline
• Why LDMOS Transistors
• About Models of transistor
• New proposed model in above
mentioned paper
• Validation of proposed model
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Why LDMOS Transistors
Laterally diffused MOS is
• Field effect transistor• High power transistor• Performance & cost• RF frequency
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What is Model
• A way to read elements easily• Is the process of
generating abstract• conceptual analysis
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NLDMOS Structure with Scalable Ldrift
Figure 2. HV-EKV model structure with built in Rdrift.
Scalable Ldrift0.8[um]~4.8[um]
Figure 1. MM20 model structure with Rdrift VerilogA code.
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The proposed Model
Fig 3: Block representation of the transistor model
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Equivalent Electrical Network
Fig 4: New extrinsic network with the cold-FET intrinsic circuit for a transistor with total gate periphery of 4.8 mm
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Nonlinear Intrinsic Model
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S-parameters from Measurement vs Model
Fig 5: Comparison between measured and modeled s-parameters
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Load line under mismatched condition
Fig 6: Load line for a Transistor operating under mismatched conditions supper-imposed upon the drain current (under pulsed operation)
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ANNs for Function Approximation and Extrapolation
Fig 7: Illustration of the various regions of the drain current. The measured characterization data is indicated by region I, while regions II and III represent the extrapolation and breakdown regions.
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Prediction of device behaviour using ANNs
Fig 8: Surface plot of the drain current as predicted by the full drain current model. The thick line indicates the range of voltages over which the drain current was measured.
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Behaviour of Charge state function
Fig 9: Plot of Qg versus Vds and Vgs. Outside the measured region indicated by the thick line, the charge surface predicted by the neural network is smooth and very well behaved, even at extremely high voltages, which would never experienced in practice, but may be used by the simulator during convergence.
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Modeled and Measured Drain current and input power at different temperature
Fig 10: Modeled and measured drain current is plotted at 25, 75 and 125 degree celsious as a function of applied gate voltage.
Fig 11: Measured and modeled output power versus input power for bias current equal to 6 and 9 mA/mm
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Validation of Model
This EM Model -• Is Nonlinear• Is Temperature sensitive• Has Optimized parameter• Is in good agreement with experimental data
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Conclusion
• New model is proposed
• Model is optimized from experimental data
• More perfect simulation is possible
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References
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References
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References
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THANK YOU ALL
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