A Dual-Pulse-Clock Double Edge Triggered Flip-Flop for Low Voltage and High Speed Application

Kuo-Hsing Cheng and Yung-Hsiang Lin

Department of Electrical Engineering Tamkang University

Taiwan, R.0.C Email: cheng@ee.t!a.edu.tw

ABSTRACT In this paper, a low voltage dual-pulse-clock double

edge triggered D'flip-flop (DPDET) is proposed. The DPDET flip-flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. The total transistors count is reduced to improve speed and power dissipation in flip-flop. The number of transistors is reduced by 40% to 70% compared to other double edge triggered flip-flops. Based on 0.35um single- poly quad-metal' CMOS technology, the HSPICE simulation results show that the operating speed of the DPDET flip-flop is 2.7 GHz at a 3.3V supply voltage. The operating speed of the DPDET flip-flop is increased about 41% and 49% in compared with others for 3.3V and 2.5V supply voltage, respectively. The power dissipation is reduced about 36% and 29% in compared with others for 3.3V and 2.5V supply voltage, respectively. Moreover, the DPDET flip-flop can be used in a 0.9V supply voltage with 224 MHz operating speed. Therefore the proposed DPDET flip-flop is suitable for low supply voltage and high speed CMOS applications.

1. INTRODUCTION

In recent years there has been an increasing demand for high-speed digital circuits at low power consumption. Double edge triggered (DET) flip-flop, which can maintain the same data rate at half clock frequency in compare with conventional single edge triggered (SET) flip-flop. As a result, the half clock frequency significantly reduces the power dissipation. True single phase clocking (TSPC) [1][2] has been demonstrated to be an efficient methodology to achieve very high-speed digital VLSI design. Double edge triggered flip-flop based on the TSPC technique will he suitable design for high-speed and low power VLSI applications.

In this paper, a new dual-pulse-clock double edge triggered D-flip-flop (DPDET) is proposed. The total transistors count is lower than previously published DET

flip-flops. The dual-pulse train generation circuit is extemal to the flip-flop and therefore can be used to feed multiple double edge triggered flip-flop. It can achieve the reduction of total capacitances. The operating speed of the proposed DPDET flip-flop is faster than conventional DET flip-flops [3][4]. Moreover, the important advantage of the DPDET flip-flop is that it can operate correctly under very low supply voltage, 0.9 volt, and the previously proposed DET flip-flops can not operate correctly under the same supply voltage.

The HSPICE simulations, based on 0.3Sum single-poly quad-metal CMOS technology, are made to determine speed and power dissipation with various supply voltage.

This paper is constructed as follows. In Section 2, four well-known double edge triggered flip-flops are presented. In Section 3, the operation of the proposed flip-flop is given. In Section 4, simulations of the flip-flop are performed and the comparison of the proposed DPDET flip-flop with the existing structures. Finally, a conclusion is given in Section 5.

2. CONVENTIONAL DET FLIP-FLOP In this paragraph, four well-known DET flip-flops

[3][4][5] will be briefly presented. Figure 1 shows two double edge triggered flip-flops proposed by M. Afghahi and I. Yuan [3]. which use twenty transistors to implement two complementary latches in parallel. The main difference of the two flip-flops is the merging structure. In Fig.l(b), the merging structure uses a NAND gate to reduce the number of clocked transistors. The third type DET flip-flop proposed by J. S. Wang [4] is shown in Fig.2, which has eighteen transistors with fewer clock capacitive loading. In Figures 1 and 2, those three flip- flops have the same character, using two complementary latches in parallel. One latch must react to the positive edge of the clock pulse and the other must react to the negative edge. Then a merging circuit is used to merge the outputs of two latches into a single output.

Another scheme for double edge triggered flip-flop design without merging circuit is shown in Fig.3. The PDET flip-flop proposed by B. Pontikakis and M. Nekili

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[SI does not use a merging circuit. As shown in Fig.3(a) and (h), the PDET flip-flop consists two parts, the double edge triggered pulsed clock generator and pulse-clock PDET flip-flop. The PDET flip-flop has fewer MOS transistors as compare with previous work. However, the operation of the PDET flip-flop has some serious problem as following. When pulse is high and D-in is low, nodes A and B are charged to high, MN3 is turned on, then node C is low and output is high. When pulse changes from high to low, the output keeps its previous state. If the pulse keeps low and D-in changes from low to high, MPI turns off and MN2 tuns on. Because the node C is low, MP2 is turned on. Then the voltage of node A i s dropped to turn on MP3, through MP2 and MN2. Then node C is charged to high and output changes high to low. As a result, at the hold time of the PDET, it cannot keep the previous data at the flip-flop output. It will make a mistaken output data.

Q

(a) (b)

Fig. 1 Conventional DET Flip-Flop (a)M. Afghahi9la, (b)M. Afghahi9lb [3]

Q

- -

Fig2 The DET Flip-Flop, J. S. Wang97 [4]

"dd

T

* (b) Fig.3 The pulse-clocked DET flip-flop [5 ]

(a) Pulse-Clock Generator, (b)PDET Flip-Flop

3. THE PROPOSED DPDET FLIP-FLOP DESIGN

As shown in Fig.4(a) and (h), the proposed DPDET flip-flop circuit includes two parts, dual-pulse-clock generator and split DPDET latch, respectively. The design of the dual-pulse-clock generator is based on the pass- transistor logic design scheme. Therefore, the proposed new XOR / XNOR gate for dual-pulse-clock generator has low power and high speed properties. The proposed split DPDET latch uses a PMOS transmission gate to connect nodes A and B. However, this makes the new circuit has higher operating speed and can he operated in low voltage applications. The detail operations of those circuits are described as follows.

As shown in Figures 4 and 5 , the new dual-pulse-clock generator uses a dual rails XOR / XNOR gate to generate clkgulse and clkhgulse, respectively, on the positive and negative edge of the input clock signal. When the input clock signal clk is low, as a result, clkb is high, clkd is low. Therefore, MNI and MPI are tumed on, and MN2, MN3, MN4, MP2 are turned off. Then the output c lk ju lse is low and clkbqulse is high. On the rising edge of clk, MN1 still turns on for a short duration of inverter gate delay. On this short time duration, clkqulse generates a positive narrow pulse to sample input data value. On the same rising edge, MN4 is tumed on and clkd still keeps at low for a short duration of inverter gate delay, clkhgulse generates a negative narrow pulse to sample input data value. Comparatively, on the falling edge of clk, clkgulse and clkhgulse have the same previous results,

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respectively. Because the generator circuit uses four NMOS transistors as pass-transistors, clkgulse and clkbgulse are weak high. In order to improve this drawback, adding two PMOS transistors, MP1 and MP2, driven by clkgulse and clkbgulse, respectively. Therefore, the proposed circuit can be used for low supply voltage.

clk clkb

I - I

elkgulse clkbgulse

Vdd

T Vdd

T

Fig.4 The Proposed PDPET Flip-Flop (a)Dual-Pulse-Clock generator, (b)Split DPDET latch

clk

clkb

clkd

clkgulse n n n clkbgulse U U

Fig.5 Pulse waveforms of the Dual-Pulse-Clock generator

As the previous mention, the four DET flip-flops have the same disadvantage. They are not suitable for low supply voltage. The proposed new circuit can improve this drawback. Another advantage of the proposed circuit is that it uses only six transistors. The number count of transistors is reduced by 70% in compared with twenty transistors used in Fig. 1, 67% reduction in compared with Fig.2, and 25% reduction in compared with the split- output latch in Fig.3, respectively. The dual-pulse train generation circuit is extemal to the flip-flop, and therefore, can be used to feed multiple double edge triggered flip- flop. It can achieve the reduction of total capacitances and the power dissipation. The operating speed of our proposed circuit is faster than conventional DET flip-flop.

4. SIMULATION AND COMPARISON RESULTS

The simulation of various conventional DET flip-flops and new proposed DPDET flip-flop are based on 0.35 um single-poly quad-metal CMOS process with an output load capacitor of O.lpF. Because the previous proposed flip- flop [5] which is shown in Fig.3, causes some problems described in Section 3. The simulation of the new proposed DPDET flip-flop only compares with three previous proposed DET flip-flops in [3][4]. Analyzing the lowest supply voltage for the flip-flops, the supply voltage is gradually decreased down from 3.3V to a point where the flip-flop fails to operate. The lowest operating voltage is 1.3V, 1.3V, 1.7V and 0.9V for Fig.l(a), Fig.l@), Fig.2, and the new DPDET flip-flop, respectively. As shown in Fig.6, in order to measure the speed for all flip-flops, the Q output !?om the DET flip-flop is fed to an odd nunher of inverter chains and connected back to the flip-flip input in a ring oscillator formed [3]. Then, to measure the operating frequency of the flip-flop, the frequency of the input clock is gradually increased up to a point where the oscillator fails to operate. However, the inverter chains delay must be subtracted from the clock period for the calculation of the maximum operating frequency of the flip-flips.

c l k d I Fig.6 Schematic diagram of the simulation for operating speed

The maximum operating frequency of conventional and proposed flip-flops are shown in Fig.7 for various supply voltage. It is clear that the operating speed of the new proposed DPDET flip-flop is increased by 35% to 41%

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and 27% to 49% in compared with others for 3.3V and 2.5V supply voltage, respectively. The operating speed of the DPDET flip-flop can achieve 2.7 GHz at 3.3V supply voltage and 224 MHz at 0.9V supply voltage. The power dissipation of various DET flip-flop is shown in Fig.8. The power dissipation of the new proposed DPDET flip-flop is reduced by 21% to 36% and 18% to 29% in compared with others for 3.3V and 2.5V supply voltage, respectively. Because the dual-pulse trains generation circuit is external to the flip-flop and therefore can he used to feed multiple double edge triggered flip-flop, we need only considering the power dissipation of the OUT proposed split DPDET latch in Figd(b).

Fig.7 The comparison of the operating speed

160 140 I 20 iw 80 60 40

UW

Supply voltage

Fig.8 The comparison of the power dissipation

Comparisons of simulation results for the four flip-flops indicate significantly that OUT proposed DPDET flip-flop offers advantages in terms of supply voltage, speed, power and transistors count.

5. CONCLUSION

triggered flip-flops, the DPDET flip-flop uses only six transistors, operated correctly under the low supply voltage. The total transistors count is reduced to improve speed and power dissipation. The number of transistors is reduced by 40% to 70% compared to other double edge triggered flip-flops. The operating speed of the DPDET flip-flop is 2.7 GHz at 3.3V supply voltage. The operating speed is increased by 35% to 41% and 27% to 49% in compared with others for 3.3V and 2.5V supply voltage, respectively. Moreover, the DPDET flip-flop can he used in a 0.9V supply voltage with 224 MHz operating speed. The power dissipation is reduced by 21% to 36% and 18% to 29% in compared with others for 3.3V and 2 . W supply voltage, respectively. Simulations are performed using HSPICE in 0.35um single-poly quad-metal CMOS technology. The proposed circuit is suitable for low supply voltage, 0.9 volt, and high speed CMOS applications.

REFERENCES [ l ] J. Yuan and C. Svensson, “High-speed CMOS Circuit

Technique,” IEEE J. Solid-Slats Circuits, vo1.24, no. I , pp.62-71, Feb. 1989.

[Z] M. Afghahi and C. Svensson, “A Unified Single- Phase Clocking Scheme for VLSI Systems,” IEEE J. Solid-Sluts Circuits, vol.SC-25, no.1, pp.225-233, Feb. 1990.

[3] M. Afghahi and I. Yuan, “Double Edge-Triggered D- Flip-Flop for High-speed CMOS Circuits,’’ IEEE J. Solid-Stuts Circuits, vol. SC-26, no.8, pp.1168-1170, Aug. 1991.

[4] Jinn-Shyan Wang, “A New True-Single-phase- Clocked Double-Edge-Triggered Flip-Flop for Low - Power VLSI Designs,” IEEE Infernufionu/ Symposium on Circuits and Systems, Hong Kong, pp.1896-1899, June 9-12, 1997.

[ 5 ] B. Pontikakis and M. Nekili, “A Novel Double Edge- Triggered Pulse-Clocked TSPC D Flip-Flop for High- Performance and Low-Power VLSI Design Applications,” IEEE International Symposium on Circuit andSystems, Arizona, vo1.5, pp.101-104, May 26-29,2002.

In this paper, a low voltage dual-pulse-clock double edge triggered D-flip-flop is proposed. The DPDET flip- flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge

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