ECE 223 Synchronous Logic - University of Waterloomsachdev/ECE223/Overhead Slides/ECE...
Transcript of ECE 223 Synchronous Logic - University of Waterloomsachdev/ECE223/Overhead Slides/ECE...
1
1
Synchronous Logic
M. Sachdev Dept. of Electrical & Computer EngineeringUniversity of Waterloo
ECE 223Digital Circuits and Systems
2
Sequential CircuitsCombinational circuits
Output = f (present inputs)
Sequential circuitsOutput = f (present inputs and past inputs)Circuit remembers past history Must contain memory
inputs k n outputs
present state next state
combinationalcircuit
memorym m
state
2
3
Synchronous Sequential Circuits
A synchronizing, periodic signal, Clock, facilitates the transition from present state to next state
Memory is provided by flip-flops
4
SR (Set Reset) LatchesNOR LatchSR = 11 is avoided
Outputs are not complementaryInput transition from 11 00 may cause circuit to: (i) fall into either state, or become meta-stable
3
5
SR (Set Reset) LatchesNAND LatchSR = 00 is avoided
Outputs are not complementaryInput transition from 00 11 may cause circuit to: (i) fall into either state, or become meta-stable
6
SR Latch with control InputC = 0
Latch retains its stateC = 1Allows propagation of SR inputs
4
7
Data (D) LatchData latch eliminate, the need for complementary inputs
Outputs are also complementary
8
Flip-flopLatch Is level sensitive to the control signal
Multiple data transition may cause problem while C =1Flip-flop is edge triggered
Flip-flop samples the data on Clock transition
5
9
Edge Triggered Flip-flopEfficient implementation
Multiple data transitions do not affect the output
10
J-K Flip-flopVersatile flip-flop
Can be Set, Reset, or Complement (toggle) its output
6
11
J-K Flip-flopQn+1 = JQn’ + K’Qn = D
JK Qn
00 01 11 10
0 1 1
1 1 1
Qn+1
J K Qn Qn+1
0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0
12
Asynchronous InputsAbility to Reset (or Set) irrespective of Clock state
Often needed in computation
7
13
Analysis of Clocked Sequential CircuitsProcedure
Determine state equations(tranistion equations) Determine the state table(transition table)Determine state diagram
Example – Analysis with D flip-flop
A(t+1) = A(t)x(t) + B(t)x(t)B(t+1) = A’(t)x(t)OrA(t+1) = Ax + BxB(t+1) = A’xSimilarly, y = (A+B)x’
14
State Table
11110000A
Present State
10000001101000100111
01111
OutputNext StateInput
000A
010B
100y
100B
010x
8
15
State Table, State Diagram
1110y
x =0 x =1x =1x =0
11100100AB
Present State
01000
OutputNext State
000000AB
101101AB
000y
16
Analysis with JK Flip-flop
JA = B, KA = Bx’JB = x’ KB = A’x + Ax’ = A⊕x
9
17
State Table
11001100
JA
01000100
KA
01010101
JB
11110000A
Present State
11100001101000101111
10111
Flip-flop InputsNext StateInput
100A
101B
010
KB
100B
010x
A(t+1) = JA’ + K’AB(t+1) = JB’ + K’B
18
State Diagram
10
19
Analysis with Toggle Flip-flopThe Characteristic Equation
Q(t+1) = T⊕Q = T’Q + TQ’
20
Analysis with Toggle Flip-flop
01100110B
11000000y
Output
01111000A
Next State
11110000A
Present State
00100111
11
Input
100B
010x
11
21
Mealy and Moore Models (Machine)Most general model of a sequential circuit has inputs, outputs, and internal states
Two different models – (i) Mealy model, (ii) Moore Model
Difference is how output is generatedMealy Model – Output is a function of present state & inputMoore Model – Output is only a function of present state
22
Mealy Machine
Observation Output can change asynchronous to the clockThe output delay with respect to clock is unpredictableDifficult to do the timing analysis
12
23
Moore Machine
Observation Output changes synchronously to the clockThe output delay with respect to clock is predictableEasier timing analysis
inputsoutputs
combinatorialcircuit
flip-flops
currentstate
clock
next statefunction
combinatorialcircuit
24
State ReductionSequential circuit analysis
Circuit diagram state table (or state diagram)
Sequential circuit design State diagram (state table) circuit diagram
Redundant state may exist in a state diagram (or table)By eliminating them reduce the # of logic gates and flip-flops
“Two states are equivalent if for each member of the set of inputs, they give exactly same state or an equivalent stateWhen two states are equivalent, one of them can be removed
13
25
State Reduction - Example
BDAEC
X=1
00101
Output
CBDAD
X=0
Next State
EDCBA
Present State
A/1 C/1 P/1
D/0 D/0
Q/0E/0B/0
0
0 0
0
0
0
0 0
1
1
1
1
1
1
1
1
0QPQ (B,E)
0DQD
P
X=1
1
Output
D
X=0
Next State
P (A,C)
Present State
26
State Reduction – Home Work
Reduced the shown state diagram
(Page 199 in the text book)
14
27
State Assignment
States must be assigned coded binary values
In order to realize with physical components
00000
X=0
ddddb
X=1
11000
X=1
Output
aeaca
X=0
Next State
edcba
Present State
edcba
State
100011010001000
Assignment 1Binary
110010011001000
Assignment 2Gray code
1000001000001000001000001
Assignment 3One-hot
28
Sequential Circuits – Design ProcedureProcedure
1. Words or timing diagram 2. Draw state transition diagram3. Make state table4. Reduced state table (if possible)5. Assign binary values to states 6. Choose flip-flop type7. Derive simplified flip-flop input equations and output equations8. Draw the logic diagram
15
29
Synthesis using D Flip-flopsGiven the state diagram, design the circuit using D flip-flops
10100010B
11000000y
Output
10101000A
Next State
11110000A
Present State
00100111
11
Input
100B
010x
30
Synthesis using D Flip-flops
DA = Ax + Bx DB = Ax + B’x y = AB
16
31
Synthesis using D Flip-flops
32
Synthesis using JK Flip-flopGiven the state table, design the circuit using JK flip-flops
XXXX0100JA
1000XXXXKA
XX10XX10JB
01101010B
10XX01XXKB
Flip-flop Inputs
01110100A
Next State
11110000A
Present State
00100111
11
Input
100B
010x
17
33
Synthesis using JK Flip-flop
34
Synthesis using JK Flip-flop
18
35
Book Sections – Sequential CircuitsMaterial is covered in Sections 5.1 – 5.4, 5.6 – 5.7