Sequential Circuits: Latches &...

Sequential Circuits:Latches & Flip-Flops

Sequential Circuits

• Combinational Logic:– Output depends only on current input– Able to perform useful operations

(add/subtract/multiply/encode/decode/select[mux]/etc…)

– Require cascading of many structures– Costly and inflexible

Chapter 4: Sequential Circuits (4.1 -- 4.3)

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Sequential Circuits (cont.)

• Sequential Logic:– Output depends not only on current input but

also on past input values– Store information between operations– Need some type of memory (Register) to

remember the past input values. (Commonly use D type Flip Flops as Registers)


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Define Schematic Terminology


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I/Ps O/Ps4 4

5

D(3:0)

Dout(3:0)

P(P,Dout(3:0))

D(3)

D(2)

D(1)

D(0)

D(3:0)

Not a short circuit!Signals merge into a

Bus or Vector

Sequential Circuits (cont.)


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Information StoringCircuits – Registers(Flip Flops)

Timed “States”Probably more than 1 bit if >2 states

Sequential Logic: Concept

• Sequential Logic circuits remember past inputs and past circuit state.

• Outputs from the system are“fed back” as new inputs.

• The storage elements are circuits that are capable of storing binary information: memory.


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Synchronous vs. Asynchronous machines

There are two types of sequential circuits:• Synchronous sequential circuit: the behavior

can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock.

• Asynchronous (fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless).


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Clock Signal


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Different duty cycles

Clock generator: Periodic train of clock pulses

Rising Clock Edge

Falling Clock Edge

Circuits:Flip flops as state

memory


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The flipThe flip--flops receive their inputs from the flops receive their inputs from the combinational circuit and also from a clock signal combinational circuit and also from a clock signal with edges (rising or falling) that occur at fixed with edges (rising or falling) that occur at fixed intervals of time, as shown in the timing diagram.intervals of time, as shown in the timing diagram.


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Buffers

Inverters

Storing Elements

Can’t change the stored value!

SR latch (NOR version)


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---- SR: “setSR: “set--reset”, bistable element with two extra reset”, bistable element with two extra inputs; note the “undefined” output for S=R=1. inputs; note the “undefined” output for S=R=1.

---- Reading the logic:Reading the logic:

Q = (R+Q’)’; P = (S+Q)’Q = (R+Q’)’; P = (S+Q)’Illegal state

R=S=1 ??

• Illegal output, because– When S=R=1, both outputs go to zero.– If both inputs now go to 0, the state of the SR

flip flop is depends on which input remains a 1 longer before making transition to 0.

– Hence, “undefined” state. MUST be avoided.


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S’R’ Latch (NAND version)


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S’

R’

Q

Q’

0 00 11 01 1

S’ R’ Q Q’0

1

1

0

1 0 Set

0 0 10 1 11 0 11 1 0

X Y NAND



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S’

R’

Q

Q’

0 00 11 01 1

S’ R’ Q Q’1

1

1

0 1 0 Hold

0 0 10 1 11 0 11 1 0

X Y NAND

1 0 Set



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S’

R’

Q

Q’

0 00 11 01 1

S’ R’ Q Q’1

0

0

1

0 0 10 1 11 0 11 1 0

X Y NAND

1 0 Hold

1 0 Set0 1 Reset



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S’

R’

Q

Q’

0 00 11 01 1

S’ R’ Q Q’1

1

0

1

0 0 10 1 11 0 11 1 0

X Y NAND

0 1 Hold

1 0 Set0 1 Reset1 0 Hold



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S’

R’

Q

Q’

0 00 11 01 1

S’ R’ Q Q’0

0

1

1

0 0 10 1 11 0 11 1 0

X Y NAND

0 1 Hold

1 0 Set0 1 Reset1 0 Hold

1 1 Disallowed


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SR Latches


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SR Latch Simulation (Timing Diagram)


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SR Latch with Clock signal

Latch is sensitive to input changes ONLY when C=1Latch is sensitive to input changes ONLY when C=1

CLK

CLK

SR Latch with Clock signal (cont.)


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S’

R’

Q

Q’

S

R

CLK

S R CLK S’ R’ Q Q’0 0 1 1 1 Q0 Q0’ Store 0 1 1 1 0 0 1 Reset1 0 1 0 1 1 0 Set1 1 1 0 0 1 1 DisallowedX X 0 1 1 Q0 Q0’ Store

D Latch

• One way to eliminate the undesirable indeterminate state in the RS flip flop is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch:


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CLK

D Latch (cont.)


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D

S R CLK Q Q’0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 Q0’ Store

0 1 0 11 1 1 0X 0 Q0 Q0’

D CLK Q Q’

S’

R’

Q

Q’

S

R

CLK

Latches: Behaviour & Issues

• Level triggered• Latches are “transparent” (= any change on the

inputs is seen at the outputs immediately).• This causes synchronization problems! (not

recommended for use in synchronous designs)• Solution: use latches to create flip-flops that can

respond (update) ONLY on SPECIFIC times (instead of ANY time).


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Alternatives in FF choice

• Edge triggered (rising or falling edge of clk) used in synchronous design

• Various types exist:– RS– D– JK


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SR Flip Flop


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–– Enables edgeEnables edge--triggered behaviortriggered behavior

––This is This is NOTNOT a latch (even though it is a latch (even though it is built from latchesbuilt from latches

Master Slave

CLK CLK

CLK

CLK


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S R CLK Q Q’

0 0 Q0 Q0’ Store 0 1 0 1 Reset1 0 1 0 Set1 1 1 1 DisallowedX X 0 Q0 Q0’ Store

•When C=1, master is enabled andstores new data, slave stores olddata.•When C=0, master’s state passesto enabled slave (Q=Y), master notsensitive to new data (disabled).

SR Flip Flop (contd.)SR Flip Flop (contd.)

CLK CLK CLK


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Master-Slave J-K Flip-Flop

CLK CLK CLK

CLK

Positive Edge-triggered D Flip-Flops

• Attach level-triggered D latch to level-triggered SR latch, using complemented clocks.

• D-Type Positive Edge-Triggered Flip-Flop:

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29Chapter 4: Sequential Circuits (4.1 -- 4.3)

CLK CLK

CLK


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Positive Edge-Triggered J-K Flip-Flop

CLK

CLK

CLK

Sequential Circuits: Latches &...

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