3D low-profile Silicon interposer using Passive...

3D low-profile Silicon interposer

using Passive Integration (PICS)

and Advanced Packaging Solutions

Stéphane Bellenger, IPDiA

EUFANET Toulouse conferences, November 28 th-29th, 2011

Application requirements examples: implications for electronics modules

Which solutions? IPDiA proposal general overview

Passive Integrated Platform : 2D & 3D silicon usage- Deep trench capacitor : how to integrate more- Inductance : enhanced Q-factor highway

PICS Silicon-Interposer. Generals

2D Interposer Platform : external components & inte rconnect- External Components : Chip-to-Wafer usage- 2D Connective Substrate : technical challenges & benefits- Module on Board / Flip Chip Module usages

3D Interposer Platform : how to create 3D interconn ect- Via technology / Two-sides routing :- Flip Chip Module usage

Conclusions

3D Advanced Integration trends

From long time being, most of the following key cha racteristics has driven the aerospace applications development, with more i ntensity since last years linked to sensors & captor development and in tegration using advanced MEMS technologies:

• Higher integration level and miniaturization (Increasing the functionality

combination and the complexity within a single package)

• More memory, more sensor, more calculation, more RF communication

• Outisde components localization, meanings,

• Extended temperature ranges (From -65°C up to 150°C )

• Rapid temperature changes during system wake-up

• Resistance to external aggressions (Particles, Humidity) – Hermiticity

• Packaging and product reliability (Vibration, Thermal cycling, extreme

conditions,…)

• Low energy consumption

Aerospace application requirements

All of these previous requirements are based on the following reasons (Why), and application domains (Where):

Why?• To design equipment as small as, as light as possible (Weight & space saving)• To combine a maximum of electronics into well integrated boxes• To better support high levels of vibrations• Huge thermal variations during flight, orbiting.• Having the sensors closest to the hottest areas for efficient monitoring• Improved operations when batteries or solar cells are used. Smaller energy

sources are also the lighter ones.

Where?• Satellite � sensors, communication systems and mission control electronics,

power control• Launchers � flight control and communication systems• Avionic and space � mechanical constraint sensors & analysers

Aerospace application requirements

Medical application requirements

From last 5-7 years huge development activities for medical application, we recognize key factors highlighted by the main players, especi ally for nomad or implantable applications such as pacemaker, defibrillator, card iac rhythm management, hearing aid (Cochlear implant, external behind-the-ear, in-the- ear, invisible canal,…), blood pressure control, glaucoma control, electronic lens, motion control, and more.

- To increase the life time of the module (More impor tant requirement for implantable modules compared to ext ernal nomad modules). As an example, to increase from 8-10 years to 15-20 years implantable defibrillator module life time

- To increase the range and the quality of the functi onalities within the same volume for the module: more computi ng, more memory footprint, more RF communication (WiFi, Bluetooth, etc…), more sensors for diagnostic, etc… As an example, to put autofocus capability for presbyopia dynamic recovering within bionic contact lens

- To improve the comfort of the patient (End user). As an example, to replace behind-the-ear by in-the-ear or implantable hearing aid modules in order to decrease the equipment weight decreasing and improve the discretion

Implications for electronic modules

As the main differentiators in most of the medical applications, the key electronic components as well as the general electronic archit ecture are directly managed by the application owner. Others components including pass ives, discretes, substrate and general packaging solution is also a big part of th e application roadmap in order to address the following main application requirements :

– To decrease the power consumptions during stand-by modes (Leakage currents) and operating mode (Global power consumption)

• Reduce the component power consumption� Active components � this is addressed by the Medical Module Makers with their

external suppliers and their internal chip development within the IC roadmap� Passives components � this addressed by the Medical Module makers with their

external suppliers with more limitation. Passive Integration is a more interesting solution (Developed later on)

• Reduce the power consumption linked to the substrat e (Tracks width, length)� Standard PCB roadmap (Limitation)� Standard ceramic roadmap (Limitation)� Silicon Interposer is an improved alternative solution (Wafer fab design rules)

• Reduce the power consumption linked to external com ponent interconnections� Passive Integration on silicon (Reduce line width and length between passive)� Silicon interposer as a platform to receive external components (3D packaging)

Implications for electronic modules

As the main differentiators in most for the applica tions described, the key electronic components as well as the general electronic archit ecture are directly managed by the application owner. Others components including pass ives, discrete, substrate and general packaging solution is also a big part of th e module manufacturers roadmap in order to address the following main application req uirements:

– Vertical integration in z axis in order to remain w ith the smallest footprint as possible for the module of the module (Advanced 3D packaging ). This roadmap is facing some important and existing challenges or limitations

• Most of the components need to be accessible at the die level. Some time, it is not possible to get sales contract. When is accessible, the wafer requires to be supplied in order to generate the die thickness and pads (Bumps) we want� Wafer back-end technology access: wafer bumping, thinning and sawing

• Most of the external components have an “unchanged” footprint and technology (Components on the shelf for passives, switches, Receivers, etc…) � no “easy way” for a vertical integration solution with a standard stack technology� 3D stacking solution with dimensional component mismatch?� Interconnection strategy linked to various pad termination (Pads and the nature of

the end metal, bumps and the nature of the materials)?� Process development and industrial strategy linked to mixed technologies: SMD

soldering, chip gluing and wire-bonding, flip-chipping, glob-top, underfill, etc…• Material mismatch between most of the external comp onents (Silicon) and

laminated, organic or ceramic substrates �� reliability limitation







Conclusions


Which solutions? IPDiA proposals

Thanks to the 3 roadmap focuses to be worked out wi th external electronic suppliers, IPDiA technology and products is a-well adapted solution:

– Replacing discrete Passive by Integrated passive co mponent• Leakage current reduction during stand-by modes• Better form factor for capacitors and inductors• Components integration capabilities thanks to RF domain• Reliability enhancement

– Using silicon substrate instead of PCB/Ceramic subs trate• Smallest track length between passives, and between components• Higher routing density (Factor 10 reduction)• Smallest footprint capability

– 2D and 3D Interposer platform• More compatible for IC integration on top of (CoB or flip/chip)• Better thermo-mechanical compatibility• Optimized vertical integration and size at optimum footprint

IPDIA overview

Company located in Caen, Normandy, FranceMore than 50 years of success in semi-conductors including 8 years in 3D silicon passive devices Dedicated campus covering 7 hectares, including• IPDiA’s headquarters• Sales and Marketing organization• Strong R&D Team• 6” wafer fab with integrated passives capacity

of 150k wafers/year

, a new company based on a

unique technology

IPDIA’s “PICS” passive integration (IPD) technology is a highly efficient way to integrate 10’s to 100’s of passive components such as resistors, capacitors, inductors , PIN Diodes and Zener Diodes in a single Silicon die.

• 3D Silicon Submounts / Interposers– 2D and 3D interposer products for hih tech industrial and Medical– Submount for HB LED Packaging + ESD Protection– TVS (transient voltage suppressor) for HB LED

• 3D Silicon RF– A range a standard products such as filter, balun, coupler…– Customized component network (Application Specific Integrated

Passives) for RF applications.

• 3D Silicon Capacitors– A range a standard products

• High stability for “demanding application” • Low Profile for ”height constraint application “ • Wire bonding for near decoupling in IC packaging

– Customized component network ASIP (Application Specific Integrated Passives) for advanced decoupling applications.

Product range







Conclusions


• High or Low Ohmic Silicon substrate

• High Quality Factor Inductors and superior self-resonance frequency

Q>80 @ 10GHz

• Polysilicon Resistors up to 100kOhms with excellent matching capabilities (<0.1%)

• Very High Density Capacitors up to 10µF and MIM Capacitors up to 100pF both with ultra low ESR

• Zener Diodes for ESD protection BV>10V and ESD Capability 15KV Air discharge(IEC 6100-4-2, level4)

• PIN diodes for RF switch applicationsIsolation > -21dB @0.5GHz

e

SC S ⋅

=εε 0

e

SC S ⋅

=εε 0

Passive Integration technology platform

PICS1 PICS2 PICS3Density

(nF/mm²)20 80 250

Depth 17µm 30µm > 45µm

PICS High Density Capacitors

e

SC S ⋅

=εε 0

e

SC S ⋅

=εε 0

Trench capacitor technology

PICS3

250 nF/mm², 12 BV

PICS5

1000 nF/mm², 12 BV

PICS4

400 nF/mm², 12 BV Production

R&D

2010 2011 2012 2013

Capacitance technology roadmapCapacitance technology roadmap

PICS3 « HV »

250 nF/mm², 30 BV

PICS4 « HV »

400 nF/mm², 30 BV

Comparison based on a 4 nH coil

Qexceed Copper

PCS1 Aluminum

RFCMOS45n

Aluminum

Qexceed+8Qexceed+8Qexceed+8Qexceed+8 Qexceed+4Qexceed+4Qexceed+4Qexceed+4

Q-factor : RFCMOS, PICS1, Qexceed & Qexceed+

PICS Inductances : Q factors

PICS Inductances: Q factors

Maximum Quality factor

Inductance

(nH) Qexceed Qexceed+8 Qmax

0.8 80@18GHz 100@18GHz >

2,4 [email protected] [email protected] >

4,2 [email protected] [email protected] >

6 33@2GHz 55@2GHz >







Conclusions


PICS Silicon-Interposer, generals

• Integration of passive component (Wafer processing)– To build /adapt a full system module (adding Passives and Diodes)– To miniaturize the system thanks to PICS form factor & performances

• A platform to receive external components (Chip-to- Wafer processing)– External IC’s in picked & placed or flipped technologies– SMD’s or discrete packages in surface mount technology

• To interconnect integrated passives & external comp onents (2D-interposer)– Interconnection factor prepared from packages to advanced IC’s– Interconnection dimensions thanks to wafer processing– Optimized performances thanks to small interconnection dimension

• To interconnect top and bottom sides (3D-interposer )– Conductive vias (Wafer processing)– Double-side patterning process (Various metal finishing options)

Substrate Printed Circuit Board (PCB)

Thick/thin flex Ceramic SiliconInterposer

Line width / Spacing

90µm down to 65µm for advanced PCB

technologies

75µm down to 50µm for advanced thin flex

technologies

75 µm to 50µm for advanced LTCC

technologies

5µm

Accuracy around 25µm

Accuracy around 15µm

Accuracy around 15µm or less for

LTCC

Below 1µm

Metal layers for signal and routing management

One metal layer in-between 2 thick laminated layer

Two layers for advanced flex

technology

One layer No limitation(2 to 3 layer)

Via diameter 200µm or below for advanced PCB

150µm for the best in class

120µm for advanced LTCC

75µm or below

Comparison on main dimensions aspects

Advantages of Si-Interposer for Advanced Packaging solutions for Medical modules

Substrate Printed Circuit Board

(PCB)

Thick flex Ceramic SiliconInterposer

CTE1 ~ 20 ppm/°K ~ 20 ppm/°K ~ 10 ppm/°K ~ 2 ppm/°C

Big CTE mismatch with DSP and

memories die set

Big CTE mismatch with DSP and

memories die set

Slight CTE mismatch with DSP and

memories die set

No CTE mismatch with DSP and

memories die set

Temperature Limited to 250°C with warpage

Lower than 200°C with polymer degradation

Higher than 400°C Higher than 400°C

Process compatibility

Very good with SMD

Intermediate with SMD

Good with SMD Good with SMD

Critical with silicon die set

Intermediate with silicon die set

Good with silicon die set

Perfectly adjusted for silicon die set

Comparison on main thermal, thermo-mechanical and m aterial aspects

Advantages of Si-Interposer for Advanced Packaging solutions for Medical modules

General 2D-Interposer PlatformGeneral 2D-Interposer Platform

InterposerInterposers

only

PICS IPD

Interposer +

passive devices

Die 1

Die 2Die 1

Interposers

with IPD

Die 2

Page 8

InterposerInterposers

only

Die 2 Die 1

Interposers

with IPD

Die 1

PICS IPD

Interposer +

passive devices

Die 1

Die 1

General 3D-Interposer PlatformGeneral 3D-Interposer Platform

Page 9







Conclusions


2D-PICS Interposer Platform

• Active components to be mounted onto the PICS inter poser– Silicon die (Digital IC’s, Analog IC’s, low power discrete)– Small packages (Passive SMD, Oscillators, Diodes, Transistors, etc…)

• Interconnection processes : Wafer level package C2W– Vertical die : die pick & place, wire-bond, dam&fill– Planar die : flip-chip and underfill– packages pick & place : solder print, pick&place, reflow

• Silicon die to be reported : main characteristics– Die size : 250µm x 250µm up to 15mmx15mm– Die thickness : 80µm min– Pad size / pitch min : 40µm / 60µm– Aluminum based end-metal

Die 1Die 2

Passive Integrated Die (PICS)


• Stacked die design : Necessary for vertical die tech nologies

• Specific die-pad design onto interposer (Adhesion / reliability)

• Thermal dissipation requirement as an optiono Conductive glue : Raw Silicon or metalized back-sideo Solder material : Back-side metalized die

• Conductive/non conductive glue characteristics• Low stress, lower CTE as possible• Low bleeding effect (Jetting technology is preferred)• Thickness control for reliability (Thermal cycling)

• Gold ball bonding (20µm diameter min, ball size 45µm)• Reverse ball stitch on ball (rbsob) for low profile modules• Aluminum based metal on die pad and interposer patterns

• Protection required with glob-top or dam & fill (Better definition)


• Flip-Chip design : Space saving

• Bumping and thinning processeso Thinning down to 80µm thicknesso 30µm bump diameter (Min), 50µm bump pitcho [5µm;80µm] bump height (Gold, SAC Solder, Gold-Tin, CuSn)

� Stencil printing (Solder bumps) � Pitch > 150µm� Gold stud bumping � Opening pad > 50µm� Galvanic growing (Solder / Gold) � Pitch min 40µm

• Flip-chip processeso Flux dipping + reflow + flux cleaning (Solder bumps)o Thermo-compression (Gold-Gold Interco, ACF, NCF)

• Underfilling processo Adapted material (Low stress, lower CTE as possible)o Controlled volume and bleeding effect (Jetting technology)

2D-PICS Interposer PlatformConstraints to anticipate:

• Mixed technologies (Chip-on wafer / Flip-chip on wafer)– Interposer end metal suitable for

o Die pad (vertical technologies) : ENiG (Low cost)o Gold ball bonding metallization : Aluminumo Solder bump flip-chip : ENiG (Low cost)o Gold bump, gold stud bump : Aluminum / Gold

Low cost : ENiG maskable process for both wire bond (Al) and solder flip-chip (NiAu)

Medium cost : TiW/Au full metallization for wire bond and thermocompression

• Mixed glue/solder pick & place and flip-chip processing– Operational flow to manage

o Solder print on wafero Package pick & place, then vertical die pick & placeo Reflow soldering and flux cleaningo Flip-chip : thermo-compression / Flux dipping-reflowo Wire bonding, then dam & fill (vertical die)

Thermal process influences on material and components

Market Application : Cellular in HVQFN package

� IPD RF module (with 73 SMD embedded) for W-CDMA & GSM RF transceiver

� 850-950MHz & 1.7-1.9GHz

� RF Silicon carrier flip chipped on lead frame (SIP)

� Components: RF capacitors, RF inductors, RF baluns, loop filters, decoupling capacitors and RF ESD protections.

5 mm x 5 mm

Active die flip-chipped on the IPD

� Market Application: AC/DC converter in CSP package

� Frequency range: 100 MHz

� Components: Resistors, capacitors, Inductor, Interconnects

PICS die

CMOS dieCout

Cin

L

Active die flip-chipped on the IPDModule architecture

2D-PICS Interposer Examples

Sensor

µCTRL

TX

3 Active dies flip-chipped on the IPD

7.00 mm x 7.00 mm2nd interconnect bumps on IPD Double flip-chip on foil

IPD


Medical (In-vivo T ° monitoring)

� 3 die flipped over PICS Interposer

� Gold stud bumps on actives die

� Capacitors, Resistor and PIN Diode on PICS, interconnection

� External solder balls (WLCSP)

� Module flipped over flex substrate

Digital TV (Dual TV Tuner)

� 2 tuners flipped over PICS Interposer

� SnAg galvanic bumps on actives die

� Capacitors, Resistor on PICS, interconnection

� External Aluminum pads

� Module picked and place over laminated substrate (LGA package)

3 Active dies flip-chipped on the IPD 7.00 mm x 7.00 mm


Defibrillator (RF Module demonstrator)

� Shown during MiNaPAD Grenoble 2011 by SORIN

� PRIIM Project (French government subsidies)

� SORIN, CEA-LETI, IPDiA Partnership

� PICS Technology in 2D-interposer Platform

2D architecture exemple for hearing aids

All compoents are reported to the upper interposer side

Pad distrib ution suitbale for wire bonding technology to interconnect the module to the external applicative substrate

Passive Integartion technology for R, L and C

Interposer size depend on the number of external SMD, the Passive Integration scenario (Passive component values) and the external die set dimension

DSPEEPROM

Interposer

EEPROM

EEPROM DS

P







Conclusions


3D-PICS Interposer with Via +/-PICS

- Reduced RC delays

- Low resistivity

- Smallest area

- High routing density

- Low power consumption

- Short connection

- High density

- Good heat dissipation

Dielectric 2 – Nitride

Finition 1 - Ni-Au

dielectric in vias - OxideSilicon

metal 1 - Aluminium

metal 0 - Copper

dielectric 1 - Oxide


Passivation 1 – Organic passivation layer

metal 2 - Copper

Passivation 0 – Organic passivation Layer

Via – Copper filling

Finition 0 - Ni-Au

Dielectric 2 – Nitride

Finition 1 - Ni-Au


metal 1 - Aluminium

metal 0 - Copper




metal 2 - Copper



Finition 0 - Ni-Au

Finition 1 - Ni-Au


metal 1 - Aluminium

metal 0 - Copper




metal 2 - Copper



Finition 0 - Ni-Au

Via structure on Integrated Passive (PICS2 Cu generation)

PICS Interposer : Via structure3D-PICS Interposer : Via structure

3D-PICS Interposer : Vias

3D interposer main characteristics

Integrated Passive (PICS2 Cu generation)

Electrical

performances

Series resistors of vias versus frequency

Results on through silicon vias with a 75µm diameter and a 300µm depth

3D-PICS Interposer : Vias

Parasitic Inductors of vias versus frequency

Interposer for lighting platform

Interposer with TSV and Cu

routing on the wafer backside

3D-PICS Interposer : Examples

- PICS2 Cu (Passive Integration generation)- Top side with one µ-controller flipped + underfill (Jetting)- Bottom side with one RF-die flipped + underfill (J etting)- WL-CSP Module with end 300µm Leadfree solder balls

Top side

3D-PICS Interposer : Examples

Bottom sideCross section

All SMD components and EEPROM are reported to the upper interposer sideDSP is reported to the bottom side

Solder ball diameter & pitches could be 100µm / 300µm depending on DSP die thickness

Vias technologie to redistribute the solder ball at the interposer bottom side

DSP

Interposer

DSP

EEPROM

EEPROM

EEPROM

3D architecture exemple for hearing aids

Interposer size depend on the number of external SM D, the Passive Integration scenario (Passive component values) and the externa l die set dimension

EEPROM

DSP

0,80mm

3D architecture exemple for higher integration requirements (PoP)

EEPROM

EEPROM

DSP

1,20mm

EEPROM

Interposer

DSP

Interposer

DSP

InterposerDSP

Interposer

+

+

+

+…..Interposer size depend on the number of

external SMD, the Passive Integration scenario (Passive component values) and the external die set dimension







Conclusions


Passive integration technologies coupled with 2D/3D-interposers bring differentiations and

miniaturization

3D Silicon and IPD platforms are now fully visible in Medical applications

Main driver is the packaging integration density, the number of passive components

and external IC integration

Lower vias diameter and pitches, as well as thinner interposer platforms will is achievable

ConclusionsConclusions

Thanks for your attention

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