1

KGD and 2.5D & 3D IC Assembly -

Building a Path to Success Rich Rice ASE Group Nov 15th, 2012

Presented by

Agenda

  Business models   Roles   What is practiced today   Requirements for tomorrow   Gaps to address

2

2.5D / 3D Business Models

3

4

3D IC Ecosystem Models

Logic IC Fab with via formation MEOL CoC

Assembly

Memory

Final Test

•  Foundry w/via OSAT MEOL + backend

•  Foundry w/via + MEOL OSAT backend •  IDM / Foundry Captive Turnkey

•  ALL 3 FLOWS WILL LIKELY DEPLOY

Memory supplied by product owner

5

MEOL CoW / CoC Assembly

Memory

Final Test

•  Foundry IC Interposer foundry OSAT MEOL

•  Foundry IC Interposer foundry OSAT ASSY •  Foundry IC + Interposer OSAT MEOL

•  Foundry IC + Interposer w/MEOL OSAT ASSY •  IDM / Foundry Captive Turnkey

•  MOST OR ALL FLOWS WILL LIKELY DEPLOY

All components supplied by product owner

Chip 1 Chip 2

Analog

Sensors

Logic IC

2.5D IC Ecosystem Models

Interposer Fab with via formation

© 2012 TechSearch International, Inc.

Effect of Interposers on 3D-IC Forecast

Source: TechSearch International, Inc.

Logic, Memory & Analog Enjoy The Wave

7

  Logic 3D SoC/SiP including interposer chips, APU, GPU, CPU, MCU, FPGA, and covering integration with wide IO memory

Roles

8

Typical Roles  System Integrator / Product Owner

  Procures all silicon components   Designs package, or co-designs with assembly provider   Provides test program and initial hardware - responsible for test coverage

and overall product functionality   Procures final manufactured module

  IC Foundry / Interposer Foundry   Receives IC design from product owner   Delivers sorted die, KGD, or interposer to product owner / assembly

provider   Reliability level is known, FA is done at die level for returns

 Assembly / Test provider   Receives all die, package config info, testing programs from product owner   Deploys assembly and test manufacturing infrastructure with suitable

technologies, interconnect yields and reliability   Delivers finished goods to product owner

9

Responsibilities of OSAT

 Design   Provides package design rules with necessary technology solutions

aligned to manufacturing   Executes package co-design with customer   Consults on applicable test flow and hardware requirements

 Manufacturing   Provides appropriate technology solution and manufacturing capacity

infrastructure at bump, assembly and test   Procures necessary manufacturing materials   Inspects consigned materials (die) to agreed upon specifications

 Yield and Reliability   Maximizes interconnect yields through assembly and test   Reports all yield information to customer (product owner)   Ensures interconnect reliability to meet the customer requirements   Conducts package level FA, reports results to product owner

10

"   NPI / Pilot Run Analysis

"   Product Maintenance

"   Yield Management

"   Test SW & HW Management

"   Auto Data Collection System (ADC) "   Yield Management System (YMS I & II) "   Test Program Management (Auto-Down Loaded) "   Consigned Key Server & Remote Login Management

Test Engineering Product Engineering

System Management

Product & Test Engineering Services

"   Test Program Development

"   Test Program Conversion

"   Test Program Optimization

"   Multi-Site Creation

"   Flexible Reporting "   Test Time Reduction

What is practiced today?

12

13

Multi-Dice Loading Trend   Data covers WB and Flip Chip products

14

Yield Status

  Incoming Die   Standard inspections, same as single die   Probed before assembly

 Assembly   2 Dice : >= 99.9%   > 2 Dice : >= 99.5%   Wirebond, Flip Chip, and combination of both   “Mature” subordinate die are commonplace

 Final Test   Most customers are doing FT with BIST   Typical Yields : > 98.5%   Very few customers do full functional testing on memory after assembly

2D & 2.5/3D Packaging Technology

1995

SOP QFP

Laminate Substrate in BGAs

Stacked Die

QFN Side-by-side WB Chips

3D IC

Leadframe

2000 2014

Side-by-side Flip Chips

Build-up Substrate in FCBGAs

FC + WB

2.5D IC

2D

3D

Chip Pkg

PoP

15

Requirements for 2.5D / 3D Die

16

17

Product Type Criteria 200 mm Wafer Readiness 300 mm Wafer Readiness

Y2009 Y2012 Y2009 Y2012

Wafer Thinning / Grinding 50 µm

Via Last

Via Etching 20 ~ 50 µm, AR 10

Via Isolation 20 ~ 50 µm, AR 10

Via Seedlayer 20 ~ 50 µm, AR 10

Via First

Via Etching 5 ~ 10 µm, AR 10

Via Isolation 5 ~ 10 µm, AR 10 Via Seedlayer 5 ~ 10 µm, AR 10

Thin Wafer Handling 50 µm With Carrier With Carrier

Via Surface Finish No Cu Dishing

Re-distribution (Double Sides) -

Micro-bumping 30 µm Pitch

TSV Wafer Probing & Testing 30 µm Pitch 50 um Now 50 um Now

Wafer Singulation -

D2W/W2W Bonding Solder / Micro Bump

Assembly -

Final Test -

Ready for Mass Production Ready for Qualification No Solution Yet

Ready for Prototyping

Source: 2009 Data from ASE’s Ho Ming Tong in SEMICON Taiwan

Industry 2.5D / 3D IC Production Tooling Readiness

Gaps to address

18

Yield Estimation

19

  Application:   2/4 memories + 1 Logic

  Thickness:   Package: 2.xx mm   Interposer: 100 um

  Size:   Package: 40X40 mm2 ~ 60X60 mm2

  Current issues:   HBM (memory) has high cost ($40 ~80 USD).

  Yield estimation:   85% : KGD, interposer: 90%, assembly (GPU bonding): 95%, assembly

(memory bonding): 99%   94% : KGD, known good interposer, assembly (GPU bonding): 95%, assembly

(memory bonding): 99%

  To improve yield   Interposer test (currently with inspection only)   Logic(+interposer) test prior to memory bond   More experience with handling memory cubes

3D IC Test Challenges   Wafer Probing

  Thinned wafer handling »  Grinding before/after test »  Assembly flow vs. Test

  TSV test »  TSV defect »  Double-sided wafer probing?

  Die/wafer contact interface material »  Bond pads/ micro bumps/

TSV »  Cu pillars

  Contact force of high I/O number vs wafer thickness

»  Probe Force »  Probe material

  Fine Pitch »  Area array pitch < 50um »  > 1000 contacts

  Package Test

  Heterogeneous cores Logic + analog + memory Embedded passive Embedded die Assembly and test process

flow integration

  Test Methodologies KGD fault coverage New fault types DFT System Level test

  Cost of test One insertion/multi insertions ATE or Customized Bench

Joint Development among IC Design/ Foundry/ Assembly & Test companies

Fundamental Study Capability Is Required for Assembly and Test Subcontractors

Processor

Memory

Micro Bump or pillar bump( Pitch<50um)

Memory Cube Micro Bump (Pitch: < 50um)

Solder Ball (Pitch: 400~500um) Substrate

Processor

Assembly In-process Test

Test Challenges  Micro bump damage of processor  Memory cube test  Micro bump pitch < 50um  Assembly warpage control for test

22

22

Probe Card Technology Gap

Density

Multi-layer Cantilever

MEMS/Membrane

Array pitch : 50 um

Contactless

2014

Vertical

•  Assembly & test companies see a gap of probe technology for array pitch under 50 um

•  Fundamental study of probe impact on wafer contact material is required (micro bumps/ TSVs/ Cu pillars)

Summary  Multi die packages are prevalent today  Roles are generally known for 2.5D and 3D IC,

but different business models will be deployed  OSAT perspective on gaps related to KGD

  Fine pitch probe technology   Silicon interposer yields / overall product yields   Memory stack handling and testing experience   Overall product assembly / test flow

23

24

Survival of the Fittest

“Market” Always Give “Fair Test” to Select The One to Survive!

I would like to acknowledge

Calvin Cheung – ASE US CP Hung – ASE CRD

Roland Yao – ASE KH LSI Roger Hwang – ASE KH Test

for their tremendous support and contributions to this presentation.

25

Thank you

www.aseglobal.com