picture.iczhiku.com...STANFORD UNIVERSITY Department of Electrical Engineering Prof. Boris Murmann...

STANFORD UNIVERSITY Department of Electrical Engineering

Prof. Boris Murmann

EE214: Analog Integrated Circuit Design - Autumn 2006/07 -

http://eeclass.stanford.edu/ee214/

Table of Contents

Introduction 3Lecture 1 Long Channel MOS Model 10Lecture 2 Common Source Amplifier 19Lecture 3 Figures of Merit for Transistors 31Lecture 4 Subthreshold Operation, Short Channel Effects 41Lecture 5 fT and Intrinsic Gain, gm/ID-based Design 53Lecture 6 Extrinsic Capacitances 67Lecture 7 Miller Effect, Zero Value Time Constant Analysis 78Lecture 8 Electronic Noise 90Lecture 9 Electronic Noise (Continued) 103Lecture 10 Body Effect, Common Gate Stage 112Lecture 11 Common Drain Stage 124Lecture 12 Differential Pair 135Lecture 13 Offset Voltage, Current Mirrors 146Lecture 14 Process Variations, Feedback 159Lecture 15 Fully Differential Amplifiers 169Lecture 16 Stability, Feedback Circuit Analysis 178Lecture 17 Loop Gain Simulation 189Lecture 18 Two-Stage OTA 201Lecture 19 Compensation, Noise in Feedback OTAs 210Lecture 20 OTA Design Considerations 221Lecture 21 Step Response 226Lecture 22 Slewing 236Lecture 23 Feedback and Port Impedances, OTA Variants, CMFB

Implementation 246

Lecture 24 Single Ended OTAs, Output Stages 259Lecture 25 Supply Insensitive Biasing 268Lecture 26 Bandgap Reference 278Lecture 27 Bandgap Reference (Continued) 284Lecture 28 Technology Scaling 293Lecture 29 Class Summary 309

1

EE 214 IntroductionB. Murmann 1

EE214Analog Integrated Circuit Design

Boris MurmannStanford University

[email protected]

Copyright © 2006 by Boris Murmann


A Few Words About Your Instructor

• Assistant Professor in EE since 2004

• PhD, UC Berkeley 2003

– Digitally assisted A/D conversion

– Use sloppy analog circuits (low power, fast)

– Correct errors using digital post-processor

• ~ 4 years work experience in IC industry

– Mixed signal IC design, low power, high voltage

• Current research direction

– Digital correction techniques for data converters

– Sensor interfaces

– Circuit design in new technologies• Post-CMOS devices, organic devices

3


EE214 Basics (1)

• Teaching assistants

– Mohammad Hekmat, Alireza Dastgheib, Abhishek Kamath

– Review Session: Fri 2:15-3:05 PM, Skilling 193 (Live on E4)

• Administrative support

– Ann Guerra, CIS 207

• Lectures are televised

– But please come to class to keep the discussion interactive!

• Web page: http://eeclass.stanford.edu/ee214

– Check regularly, especially FAQ section

– Register for online access to grades and solutions• Only students enrolled can register; we manually control the

access list based on Axess data


EE214 Basics (2)

• Required text

– Analysis and Design of Analog Integrated Circuits, 4th Edition, Gray, Hurst, Lewis and Meyer, Wiley, 2001. (On reserve in Engineering Library)

• Useful reference

– The Designer’s Guide to Spice and Spectre, Ken Kundert, Kluwer Academic Publishers, 1995. (On reserve in Engineering Library)

• Course prerequisites

– EE101B or equivalent

– Basic device physics and models (PN junctions, MOSFETs, BJTs), basic linear systems (poles, zeros)

– Some exposure to a circuit simulator, basic Unix commands

– May consider concurrent enrollment in EE114X to brush up on the above (primarily for undergraduates)

4


Assignments

• Homework (20%)

– Handed out on Mondays, due following Monday in class

– Late policy• Score drops 0.5 dB per hour after deadline

– Policy for off-campus students: Fax/email to SCPD before deadline stated on handout

• Midterm Exam (30%)

• Project (20%)

– Design of an amplifier using HSpice (no layout)

– Work in teams of two• OK to discuss with other teams, but no file exchange!

• Final Exam (30%)


Honor Code

• Please remember you are bound by the honor code

– I will trust you not to cheat

– I will try not to tempt you

• But if you are found cheating it is very serious

– There is a formal hearing

– You can be thrown out of Stanford

• Save yourself and me a huge hassle and be honest

• For more info

– http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/honorcode.pdf

5


Be Reasonable When Asking TAs

• The TAs will not give you "the answer times two"…

• They will also NOT debug your HSpice deck

– Figuring out what's wrong with your circuit is an essential component of this class


Circuit Simulation

• Primary tools: HSpice/AWaves

– You can use other tools at "own risk"

– Tutorial docs and example simulation decks for HSpice are provided on course web site

• Great alternative to AWaves: Plot HSpice results using Matlab– Download "Hspice Toolbox" at:

http://www-mtl.mit.edu/research/perrottgroup/tools.html#hspice

– This toolbox is installed in course directory (see tutorial for path)

• EE214 Technology

– 0.35µm CMOS

– BSIM3v3 models provided on web site

• First review session (this week) will focus on simulation basics

6


The Spice Monkey Problem (1)

• What most people know

– Even a very large number of monkeys randomly arranging characters will never manage to write an interesting book

• What some people tend to forget

– Even a very large number of "Spice Monkeys" randomly tweaking circuits will never manage to design a robust, optimized IC

[Courtesy Isaac Martinez]


The Spice Monkey Problem (2)

• Simply put

– Spice is nothing but a "calculator" that lets you evaluate and test your ideas

– There is no need to simulate anything unless you already know the (approximate) answer!

– Must always be aware of modeling limitations

• Especially in the integrated circuits arena, uneducated, purely simulator driven design can be costly

– Mask sets cost up to $2 Million (90 nm production)

– Turnaround time is on the order of months

– If your chip doesn't work, you cannot simply send the customer a "patch"…

7


Analysis versus Design

• Unlike common perception, analog circuit analysis and design is not "black magic"

• Circuit analysis

– The art of decomposing a circuit into manageable pieces

– Based on the simplest, but sufficiently accurate models

– One circuit ⇒ one solution

• Circuit design

– The art of synthesizing circuits based on experience from extensive analysis

– One set of specifications ⇒ Many solutions

– Design skills are best acquired through "learning by doing"• This is why we'll have a design project…


Course Topics

• CMOS technology and device models

• Electronic noise

• Single-stage amplifiers

• Current mirrors, active loads

• Differential pairs

• Operational and transconductance amplifiers

• Feedback, stability and compensation

• Temperature and supply independent biasing

8


Learning Goals

• Develop deeper understanding of MOS device behavior relevant to analog design

• Develop a feel for limits and tradeoffs in analog circuits (speed, noise, power dissipation)

• Learn to bridge the gap between complex device models/behavior and basic hand calculations

– Design using look-up tables, "gm/ID methodology"

• Develop a systematic, non-spice-monkey design style

• Solidify the above aspects in a hands-on design project

– Design and optimization of a high performance feedback amplifier used in many industrial circuits/applications

9

EE 214 Lecture 1B. Murmann 1

Lecture 1CMOS Technology

Long Channel MOS Model


[email protected]



Overview

• Reading– 2.8 (MOS fabrication), 2.9 (Active MOS devices)– 2.10.1 (Resistors), 2.10.2 (Capacitors)– 1.1, 1.5.0, 1.5.1, 1.5.2, 1.5.3 (Large signal MOS model)

• Introduction– In this first lecture, we will cover some of the background

that positions EE214 as an introductory course on circuit design using CMOS technology. In the lectures to come, we will focus on the problem of amplifier design as a vehicle to establish a set of considerations that apply to more complex circuits and also other technologies. At first, we will review the ‘long channel model’ of a MOS transistor. Driven by circuit examples, we will later augment this simple model to include additional effects that are relevant in practice.

10


The Big Picture

• Most modern electronic information processing systems rely on amplification of "small" physical signals– E.g. signal from RF antenna, disk drive head, microphone, …

• EE214 uses amplifiers as a vehicle to teach you the basics of analog integrated circuit analysis and design– Material forms basis for other and/or more complicated circuits


Technological Progress

Vacuum Tube1906

ModernCMOS

Transistor1947

Modern DiscreteTransistors

Integrated Circuit1958

11


Economics

[European Nanotechnology

Roadmap]


Future Applications

12


Discrete vs. Integrated Circuits

• Minimize transistor count

• Devices usually don't match

• Arbitrary resistor values

• Capacitors 1pF…10mF

• "Unlimited" number of transistors

• Devices match well

• Keep resistors < 10…100k

• Keep capacitors < 10…50pF

Discrete Audio Amplifier Integrated CMOS Audio Amplifier


Modern Integrated Circuit Technologies

• Why use CMOS for analog integrated circuits?

– Low cost, driven by high volume digital ICs

– Integration with high density digital circuits• BiCMOS tends to be expensive

Parameter CMOS Si BJT SiGe BJT

Device Speed High High High

Noise Poor Good Good

Transconductance Poor Good Good

Intrinsic gain Poor Better Best

13


Basic MOS Operation (1)

• With zero voltage at the gate, device is "off"

– Back to back reverse biased pn junctions

0V VD (>0V)0V

0V


Basic MOS Operation (2)

• With a positive gate bias applied, electrons are pulled toward the positive gate electrode

• Given a large enough bias, the electrons start to "invert" the surface (p→n type), a conductive channel forms

– Magic "threshold voltage" Vt (more later)

>0

14


Basic Operation (3)

• If we now apply a positive drain voltage, current will flow

• How can we calculate this current as a function of VGS, VDS?

>0

VDS>0

ID=?


Assumptions

1) Current is controlled by the mobile charge in the channel. This is a very good approximation.

2) "Gradual Channel Assumption" - The vertical field sets channel charge, so we can approximate the available mobile charge through the voltage difference between the gate and the channel

3) The last and worst assumption (we will fix it later) is that the carrier velocity is proportional to lateral field (ν = µE). This is equivalent to Ohm's law: velocity (current) is proportional to E-field (voltage)

>0

VDS>0

15


First Order IV Characteristics (1)

• What we know:

[ ]tGSoxn VyVVCyQ −−= )()(

WvQI nD ⋅⋅=

Ev ⋅= µ

[ ] WEVyVVCI tGSoxD ⋅⋅⋅−−=∴ µ)(


First Order IV Characteristics (2)

dyydVE )(=[ ] WEVyVVCI tGSoxD ⋅⋅⋅−−= µ)(

[ ] dVVyVVCWdyI tGSoxD ⋅−−= )(µ

[ ]∫ ⋅−−=∫DSV

tGSox

L

D dVVyVVCWdyI00

)(µ

( ) DSDS

tGSoxD VV

VVLWCI ⋅

⎥⎥⎦

⎤

⎢⎢⎣

⎡−−=

2µ

• For VDS/2 << VGS-Vt, this looks a lot like a linear resistor: I=1/R × V

• Lets plot this IV relationship...

16


Plot of First Order IV Curves

• Something is wrong here...

– Current should never decrease with increasing VDS

• What happens when VDS>VGS-Vt?

– VGD = VGS-VDS becomes less than Vt, i.e. no more channel or "pinch off"

VDSID

VGS-Vt


Pinch-Off

• Effective voltage across channel is VGS - Vt

– After channel charge goes to 0, there is a high lateral field that ‘sweeps’ the carriers to the drain, and drops the extra voltage (this is a depletion region of the drain junction)

• To first order, current becomes independent of VDS

N N

– V G S +

+ V DS –

y

y = 0 y = L

Q ( y ) , V ( y ) n

Voltage at the end of channelIs fixed at VGS-Vt

17


Modified Plot and Equations

VDS

IDVGS-Vt

Triode Region

Forward Active Region

( ) DSDS

tGSoxD VV

VVLWCI ⋅

⎥⎥⎦

⎤

⎢⎢⎣

⎡−−=

2µTriode Region:

Forward Active: ( ) 2)(21)(

2)(

tGSoxtGStGS

tGSoxD VVLWCVVVVVV

LWCI −=−⋅⎥⎦

⎤⎢⎣⎡ −−−= µµ


Model Accuracy

• The above equations constitute the most basic MOS IV model

– "Long channel model", "Quadratic model", "Low field model"

• Unfortunately it doesn't describe modern CMOS devices accurately

– Pushing towards extremely small geometries has resulted in very high electric fields

• Some of the assumptions on slide 12 become invalid

• Other second order dependencies arise

• Nevertheless, we will use this simple model in the first few lectures to develop some basic circuit intuition

– Will fix and refine as we go…

18


Lecture 2Common Source Amplifier

Small-Signal Model


[email protected]



Overview

• Reading– 3.0 (Amplifier basics), 3.1 (Model selection)

– 3.3.2 (Common source amplifer)

– 1.6.0 - 1.6.5 (Small signal MOS model)

• Introduction

– In this lecture, we will use the simple long channel MOS model to construct our first amplifier - a common source stage. Looking at its transfer function, we'll find that treating signals as "small" with respect to the bias conditions allows us to linearize the circuit. Next, we generalize this approach and develop a more universal "small signal model" for MOS devices that are biased in the forward active region.

19


First-Order MOS Model Summary

( )221

tGSoxD VVL

WCI −≅ µ

Sub-Threshold

(more la

ter...)

Vt VGS

VDS

VGS-Vt

FORWARD ACTIVE

TRIODE

( ) DSDS

tGSoxD VVVVL

WCI ⋅⎥⎦⎤

⎢⎣⎡ −−≅

2µ

≅

≅

"VCCS"


One Way to Amplify

• Convert input voltage to current using voltage controlled current source (VCCS)

• Convert back to voltage using a resistor (R)

• "Voltage gain" = ∆Vout/∆Vin

– Product of the V-I and I-V conversion factors

20


Common Source Amplifier

• MOS device acts as VCCS

( )221

tioxD VVL

WCI −= µ ( ) RVVL

WCVV tioxDDo ⋅−−= 221 µ


Biasing

• Need some sort of "battery" that brings input voltage into useful operating region

• Define VOV=VI-Vt, "quiescent point gate overdrive"– VOV=VGS-Vt with no input signal applied

"Bias"

"Signal"

VI

∆Vo

∆Vi

VO

VOV

21


Relationship Between Incremental Voltages

• What is ∆Vo as a function of ∆Vi?

( )

( )[ ][ ]

⎥⎦

⎤⎢⎣

⎡ ∆+∆⋅⋅−=

∆+∆⋅−=

−∆+⋅−=∆

⋅∆+−=∆+

OV

ii

OV

D

iiOVox

OViOVoxo

iOVoxDDoO

VVVR

VI

VVVRL

WC

VVVRL

WCV

RVVL

WCVVV

212

22121

21

2

22

2

µ

µ

µ

• As expected, this is a nonlinear relationship

• Nobody likes nonlinear equations, we need a simpler model

– Fortunately, a linear approximation to the above expression is sufficient for 90% of all analog circuit analysis


Small Signal Approximation (1)

• Assuming ∆Vi << 2VOV, we have

⎥⎦

⎤⎢⎣

⎡ ∆+∆⋅⋅−=∆OV

ii

OV

Do V

VVRV

IV2

12

iOV

Do VR

VIV ∆⋅⋅−≅∆ 2

• If we further pretend that the input voltage increment is infinitely small, we can find this result directly by taking the derivative of the large signal transfer function at the "operating point" VI

RV

IdVdV

OV

D

VVi

o

Ii

⋅−==

2

22


Small Signal Approximation (2)

• Graphical illustration:

VI

VO

VOV

dVo/dVi

• The slope of the above tangent is the so called "small signal gain" of our amplifier


Small Signal MOS Model

• Fortunately we don't have to repeat this analysis for every single circuit we build

• Instead, we derive a linearized circuit model for the MOS transistor and plug it into arbitrary circuits

23


Transconductance

• The parameter that relates small signal gate voltage to drain current is called transconductance (gm), or y21 in two-port nomenclature

• The transconductance is found by differentiating the large signal I-V characteristic of the transistor in its operating point

( )221

tGSoxD VVL

WCI −= µ

( ) OVoxtGSoxGS

D

gs

dm V

LWCVV

LWC

VI

vig µµ =−=

∂∂==

OV

Dm V

Ig 2=


Additional Model Components

• Now that we've decided to move on using "small signal" approximations, it also becomes easier to refine our model and make it more realistic

• Let's first take a look at "intrinsic gate capacitance"– Intrinsic means that these capacitances are unavoidable and

required for the operation of the device– Note that there are plenty of extrinsic, technology related

capacitances• We'll talk about some of those later

• When talking about gate capacitance, we must distinguish several operating regions– Transistor on

• Triode and forward active regions

– Transistor "off"• Subthreshold operation

24


Transistor in Triode Region

• Gate terminal and conductive channel form a parallel plate capacitor across gate oxide CGC= WLεox/tox= WLCox

– We can approximately model this using lumped capacitors of size ½ CGC each from gate-source and gate-drain

• Changing either voltage will change the channel charge

• The depletion capacitance CCB adds extra capacitance from drain and source to substrate

– Usually negligible

L

S D W

G

C GC

C CB


Transistor in Forward Active Region

• Assuming a long channel model, if we change the the source voltage in the forward active region

– The voltage difference between the gate and channel at the drain end remains at Vt, but the voltage at the source end changes

– This means that the "bottom plate" of the capacitor does not change uniformly

• Detailed analysis shows that in this case Cgs=2/3WLCox

– See text, section1.6.2

• In the long channel model for forward active operation, the drain voltage does not affect the channel charge

– This means Cgd=0 in the forward active region!• Neglecting second order effects and extrinsic caps, of course

25


Transistor Off

• There is no conductive channel

– Gate sees a capacitor to substrate, equivalent to the series combination of the gate oxide capacitor and the depletion capacitance

• If the gate voltage is taken negative, the depletion region shrinks, and the gate-substrate capacitance grows

– With large negative bias, the capacitance approaches CGC

L

S D W

G

C GC

C CB


Intrinsic MOS Capacitor Summary

Subthreshold TriodeForward Active

Cgs 0 ½ WLCox2/3 WLCox

Cgd 0 ½ WLCox 0

Cgb 0 01

11−

⎟⎟⎠

⎞⎜⎜⎝

⎛+

oxCB WLCC

WLx

Cd

SiCB

ε=

26


Dependence of ID on VDS

• Admittedly, our simple first order MOS I-V equation for the forward active region looks pretty unrealistic

– Ideal current source!

• In reality, the drain current has a weak dependence on VDS

VDS

ID

VGS-Vt

Triode Region

Forward Active Region

Finite dID/dVDS


Channel Length Modulation

• "Channel length modulation" is outdated nomenclature for a combination of several physical effects that cause finite dID/dVDS

• The precise dependence of ID on VDS is very hard to model

– You can convince yourself by looking at the BSIM3 manual

• One simple modeling approach was to assume that the large signal current ID increases linearly with VDS ("fudge factor" λ)

)1()(21 2

DStGSoxD VVVL

WCI λµ +−=

• Unfortunately, this simple modified equation has become too inaccurate to predict large signal behavior

– Must rely on simulation for the "final tweak"

– As we will see, this is actually not a big issue…

27


Small Signal Output Resistance

• Yet, we must somehow take the finite dID/dVDS into account, since it quantifies how much our forward active device deviates form an ideal current source

• Again, this becomes somewhat easier by limiting ourselves to "small signals"

• Define "small signal output resistance" ro

DS

D

o dVdI

r=1

VDS

ID

Operating Point

Slope = 1/ro


Dependence of ro on VDS

• In the above example, it seemed like ro is independent of the VDS operating point (as long as the device is forward active)

• Unfortunately, modern MOS I-V curves can look like this

VDS

ID

OP1

Slope = 1/ro1OP2

Slope = 1/ro2

• Only experimental data or simulation will help us in practice totake VDS dependence into account

28


Another ro Caveat

• Is vds really a "small signal"?

• The small signal approximation for ro becomes somewhat inappropriate when the vds swing spans a large fraction of a nonlinear ID-VDS characteristic

• Luckily, in most practical situations, other (well understood) sources of nonlinearity dominate (e.g. transconductance)

OP1

VDS

IDOP


Output Resistance - Summary

• The above conclusions on output resistance seem pretty devastating

– Don't really know how to calculate ro, have to trust technology data

– ro depends on operating point, which also means that there is an additional source of nonlinearity

• In practice this has only mild implications

– We'll never design a circuit that relies on a precise value or particular dependence of ro

– In order to be able to reason about the impact of ro in the circuit design process, we will work with typical values and lower bounds from Spice simulations

29


1st Order Small Signal Model (Forward Active)

entsn/measurem simulatiofrom followsr

WLC32C

VI2g

o

oxgs

OV

Dm

−

=

=

30


Lecture 3Common Source Amplifier Performance

Figures of Merit for Transistors


[email protected]



Overview

• Reading

– 1.6.8 (Transit Frequency)

• Introduction

– Having established some basic modeling tools, we will now look at the achievable performance of our common source stage. We'll derive first order expressions for the amplifier's bandwidth and power dissipation. As we will see, these metrics are proportionally related to more fundamental performance measures of the MOS device itself: Transit Frequency and Transconductor Efficiency.

31


Common Source Amplifier Revisited

• Consider a common source stage driven by a "transducer"

• Ideally, what we want to achieve is

– A certain voltage gain

– Large bandwidth, low power dissipation


Transfer Function

gsiLom

i

oCsR

RrgsvsvsH

+⋅==1

1)||()()()(

• For simplicity, let's assume that RL is fixed, and RL<< ro

• The desired DC gain (ADC) then dictates our choice for gm

DC gain FrequencyDependence

OVmD

OV

Dm

VgI

VIg

21

2

=

=• Now recall that

L

DCm R

Ag =

32


Power Dissipation

• Substituting ID and gm using the expressions on the previous slide yields

OVDCL

DD VAR

VP ⋅⋅=21

• Clearly, minimizing VOV will also minimize power dissipation

– Actually, how about making VOV ≅ 0?• More later…

• Let's now look at the bandwidth of this circuit

• Power dissipation is given by

DDD IVP ⋅=


Bandwidth

• The –3dB bandwidth of our circuit is

oxgsgsi

dB WLCCCR 3

2:with13 ==−ω

OVm VLWCoxg µ=

• In order to make this expression more insightful, we can eliminate Cox using

OVDCi

LdB V

LARR ⋅⋅⋅=− 23

123 µω

• It then follows that

33


Discussion

• With the assumed fixed design specifications, and a given technology (µ, Lmin) , both power and bandwidth of our circuit are completely determined by the choice of VOV

• Bad news: Making VOV small to save power also means that we lose bandwidth

– This makes intuitive sense since

OVDCL

DD VAR

VP ⋅⋅=21

OVDCi

LdB V

LARR ⋅⋅⋅=− 23

123 µω

OVox

mVC

gLW

µ=

• With gm and L fixed, smaller VOV translates into a bigger (wider) device, and thus larger Cgs


Generalization (1)

• What we really want from our MOS transistor

– Lots of gm without investing much current

– Lots of gm without having large Cgs

• To quantify how good of a job our transistor does, we can therefore define the following "figures of merit"

gs

m

D

mCg

Ig and

• Using long channel MOS equations, we find

223and2

LV

Cg

VIg OV

gs

m

OVD

m µ==

• As expected, these equations reflect the same tradeoff that we've observed in the above circuit example

34


Generalization (2)

• Part of your job as a designer is to choose VOV such that– You get sufficient bandwidth– And use as little power as possible to accomplish this

• Even though we've come to this graph using a very simple example, the observed tradeoff tends to hold in general– Of course, second order considerations will factor in as you

learn more about circuit design…

VOV

gm/ID

gm/Cgs


Product

• In cases where we want to get the "best of both worlds", it is interesting to look at the product of our two figures of merit

VOV

gm/ID

gm/Cgs

gm/ID*gm/Cgs

23LC

gIg

gs

m

D

m µ=⋅

• While this result looks boring, it shows that using smaller channel lengths improves circuit performance

– Either or both speed and power efficiency

35


Scaling Impact

• Thanks to "Moore's Law" feature sizes and thus the available minimum channel lengths have been shrinking continuously

– Lmin decreases roughly 2x every 5 years

– Lmin=10µm in 1970, Lmin=90nm in 2004

• From the above discussion, it is clear that we can exploit technology scaling in different ways

– Build faster circuits (gm/Cgs), while keeping power efficiency constant (gm/ID)

• E.g. A/D converter for a disk drive - want to maximize bandwidth/throughput

– Build more power efficient circuits (gm/ID), while keeping the bandwidth constant (gm/Cgs)

• E.g. A/D converter for video signals - bandwidth fixed by a certain standard


Transit Frequency (ωT)

• The transit frequency of a transistor is defined as the frequency where the magnitude of the common source current gain (|io/ii|) falls to unity

• Ignoring extrinsic capacitance, it follows that

223

LV

Cg OV

gs

mT

µω ==

• Incidentally, this metric is identical to the figure of merit weconsidered earlier in the context of a CS amplifier…

• Note that we can also express transit frequency in units of Hz

πω2

TTf =

36


Transit Frequency Interpretation

• The transit frequency is only useful as a figure of merit in thesense that it quantifies gm/Cgs

• It does not accurately predict up to which frequency you can usethe device

– At high frequencies, many assumptions in our "lumped" transistor model become invalid

– Rule of thumb: Lumped model is good up to about ωT/10

• At higher frequencies, device modeling becomes more challenging and many effects depend on how exactly you layout and connect the device

– These effects are covered in more detail in EE314

– In EE214, we will assume that we operate below ωT/10


ωmax

• Can show that

gdgate

TCr

ωω21

max =

• A step into the right direction for quantifying the high frequency capability of a MOSFET is to look at its power gain with gate sheet resistance effects included

– The quantity ωmax is defined as the frequency at which the magnitude of the common source power gain falls to unity

– Also known as "maximum frequency of oscillation"

37


Gain

• Let's now return to our common source amplifier example to gain some insight into another performance metric of interest: Small signal DC voltage gain

gsiLom

i

oCsR

RrgsvsvsH

+⋅==1

1)||()()()(



Case 1: RL<< ro

• In this case, the DC gain is

OV

LDLmDC V

RIRgA 2==

• For operation in the forward active region, we definitely need

DDLD VRI <

• Therefore, we have

OV

DDDC V

VA 2<

• Note that the above expression is an upper bound, and cannot quite be achieved in practice

– Nevertheless, this is a useful equation for back of the envelope limit considerations

38


Case 2: RL>> ro

• This corresponds to the case where RL is essentially replaced by a current source

• Now we have two biasing problems– Must precisely adjust both VI and ID to set quiescent point of Vo

– We'll solve these kinds of problems when looking at more practical biasing approaches, later in this course….


Intrinsic Gain

• With RL→∞, the basic common source stage achieves its maximum possible voltage gain or "intrinsic gain"

omDC rgA =

• As mentioned before, it is nearly impossible to develop a simpleequation that yields ro as a function of the device's bias point in modern technologies

• For the remainder of this course, we therefore regard the combined quantity "gm·ro" as a technology dependent parameter

– Must be characterized through measurements/simulations

• Interestingly, it will turn out that the gain of other, more complicated circuits is fundamentally linked to the intrinsic device gain "gm·ro"

39


Figure of Merit Summary

• Transit Frequency

gs

mT C

g=ω

• Transconductor Efficiency

D

mIg

• Intrinsic Gain

omrg

• Note that we can characterize any technology (MOS, BJT, …) with respect to these quantities

– Next lecture we'll look at our "EE214 technology" (0.35µm CMOS)


+ Width Independence

• These figures of merit are (to first order) independent of transistor width

– Simplifies technology characterization and enables design in a "normalized space"

WW

Cg

gs

m ∝WW

I

IdV

d

Ig

d

dgs

D

m ∝= W1Wrg om ⋅∝

40


Lecture 4EE214 Technology: gm/IDSubthreshold OperationShort Channel Effects


[email protected]



Overview

• Reading

– 1.8 (Weak Inversion)

– 1.7 (Short Channel Effects)

• Introduction

– Last lecture, we found that one important figure of merit for transistors is the transconductor efficiency, gm/ID. Today we'll look at gm/ID in our EE214 0.35µm technology. We will find that additional modeling is needed to explain the behavior of this parameter below and around Vt, and also the deviation from the long channel model in strong inversion. This leads us to an analysis of subthreshold current and an introduction to short channel effects.

41


gm/ID Simulation

$ gm/id vs. gate overdrive

$ Boris Murmann, September 2006

.param gs=1

vds d 0 dc 1.5Vvgs g 0 dc 'gs'mn1 d g 0 0 nch214 L=0.35um W=10um

.op

.dc gs 0.4V 1.2V 10mV

.probe ov = par('gs-vth(mn1)')

.probe gm_id = par('gmo(mn1)/i(mn1)')

.options post brief

.lib './ee214_hspice.txt' nominal

.end


Result

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

25

30

35

40

VOV

[V]

gm

/ID

[1/V

]

EE214 technology2/V

OVBJT (q/kT)

42


Observations

• Our long channel predication is fairly close for VOV > 150mV

• Unfortunately gm/ID does not approach infinity for VOV → 0

• It also seems that we cannot do better than a BJT, even though the long channel equation would predict that for 0 < VOV < 2kT/q ≅ 52mV at room temperature

• For further analysis, it helps to identify three distinct operating regions

– Strong inversion: VOV > 150mV• Deviations due to short channel effects

– Weak Inversion: VOV < 0 • Behavior similar to a BJT, gm/ID nearly constant

– Moderate Inversion: 0 < VOV < 150mV• Transition region, an interesting mix of the above


Weak Inversion

• Questions:

– What determines the current when VOV< 0, i.e. VGS< Vt?

– What is the definition of Vt?

• A closer look at the device current in our previous simulation:

-0.5 0 0.5 10

0.2

0.4

0.6

0.8

1

V [V]

I D [m

A]

-0.5 0 0.5 110

-5

10-4

10-3

10-2

10-1

100

V [V]

I D [m

A]

43


Definition of Vt

• Vt is defined as the VGS at which the number of electrons pulled to the surface equals the number of doping atoms

• Seems somewhat arbitrary, but makes sense in terms of surface charge control


Mobile Charge versus VOV

• Around Vt, the relationship between mobile charge in the channel and gate voltage becomes linear (Qn ~ Cox[VGS-Vt])

– Exactly what we assumed to derive the long channel model

0.E+00

1.E-07

2.E-07

3.E-07

4.E-07

5.E-07

6.E-07

-1.0 -0.5 0.0 0.5 1.0

VOV [V]

Ch

arg

e [

C]

Fixed Charge

Mobile Charge

Total Charge

44


Mobile Charge on a Log Scale

• On a log scale, we see that there are mobile charges before we reach the threshold voltage

– Fundamental result of solid-state physics, not short channels

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

-1.00 -0.50 0.00 0.50 1.00

VOV [V]

Mo

bil

e C

har

ge

[C]


BJT Similarity

• We have– An NPN sandwich, mobile minority carriers in the P region

• This is a BJT!– Except that the base potential is here controlled through a

capacitive divider, and not directly an electrode

45


Subthreshold Current

• We know that for a BJT

)//( qkTVSC

BEeII ⋅≅

• In our case we have

)//()(0

qnkTVVD

tGSeII −⋅≅

• n is given by the capacitive divider

ox

js

ox

oxjs

C

C

C

CCn +=

+= 1

where Cjs is the depletion layer capacitance

• In our technology n ≅ 1.5


Subthreshold Transconductance

• Similar to BJT, but unfortunately n (≅1.5) times lower

kT

qI

ndV

dIg D

GS

Dm

⋅== 1kT

q

ndV

dI

I

g

GS

D

D

m 1==

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

25

30

35

40

VOV

[V]

gm

/ID

[1/V

]

EE214 technology2/V

OVBJT (q/kT)1.5x

46


Moderate Inversion

• In the transition region between weak and strong inversion, we have two different current mechanisms

dxdn

qkT

dxdnD - (BJT)Diffusion

E - (MOS)Drift

µν

µν

==

=

• Both current components are always present

– Neither one clearly dominates around Vt

• Can show that ratio of drift/diffusion current ~(VGS-Vt)/(kT/q)

– MOS equation becomes dominant at several kT/q

• One way to close the gap between the two regimes is to work with a mathematical fit

– Sometimes useful for computer optimization, not so great for hand analysis…


A Curve Fitting Attempt

⎪⎪

⎩

⎪⎪

⎨

⎧

∞→

→

≅

⎟⎠⎞

⎜⎝⎛ ⋅++

=

OVOV

OV

OVD

m

VV

VkT

q

m

mkTqVkT

q

mI

g

;2

0;1

11

122

0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

25

30

35

40

VOV

[V]

gm

/ID

[1/V

]

EE214 technology2/V

OVFitted Equation (m=1.7)

47


A Closer Look at Strong Inversion

• Long channel model overestimates gm/ID by roughly 10…20%

– Something worth looking into…

0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

5

10

15

VOV

[V]

gm

/ID

[1/V

]

EE214 technology2/V

OV


Short Channel Effects

• Velocity saturation due to high lateral field

• Mobility degradation due to high vertical field

• Vt dependence on channel length and width

• ro = f(VDS)

• …

• We will limit the discussion in EE214 to the first two aspects of the above list

– Focus on qualitative understanding, since we will not factor these effects into our hand calculations

48


Velocity Saturation (1)

• In lecture 1, we assumed that the carrier velocity is proportional to the lateral E-field, v=µE

• Unfortunately, the speed of carriers in silicon is limited

– At very high fields (high voltage drop across the conductive channel), the carrier velocity saturates

Approximation:

EE

1

µE ν

c+

=


Velocity Saturation (2)

• It is important to distinguish various regions in the above plot

– Low field, the long channel equations still hold

– Moderate field, the long channel equations become somewhat inaccurate

– Very high field across the conducting channel – the velocity saturates completely and becomes essentially constant (vscl)

• To get some feel for latter two cases, let's first estimate the E field using simple long channel physics

• In the forward active region, at pinch-off, the lateral field across the channel would be

m

V.

m.

mVe.g.

L

V E OV 610570

350200 ⋅==

µ

49


Field Estimates

• In our 0.35µm technology, we have for an NMOS device

m

V.

Vsm

.

sm

101.73

v E

5

sclc

62 1026

0280⋅=

⋅==

µ

• The above example shows that an 0.35µm NMOS device at VOV=200mV does not operate anywhere near Ec

• How about 0.13µm?

m

V.

m.

mV E 61051

130200 ⋅==

µ

• Still not too bad…


Short Channel Equation

• Bottom line is that most existing and future MOS analog circuitsare impaired, but not completely limited by velocity saturation

– The digital folks will tell you a different story• Why?

• A simple equation that captures the moderate deviation from the long channel forward active drain current is (see text)

( )OVc

OVcOVox

c

OVOVoxD

VLE

VLEV

L

WC

LEV

VL

WCI

+⋅⋅≅

⎟⎟⎠

⎞⎜⎜⎝

⎛ +⋅≅

µ

µ

21

1

121 2

"Parallel Combination"

50


Typical Values for EcL

• As long as VOV is "much less" than these voltages, the above simplified equation holds with reasonable accuracy

• We can use these numbers to check our earlier simulation data for gm/ID. With the correction factor, we have

NMOS PMOS

0.35µm 2 V 8V

0.13µm 0.6V 2.4V

902

2201

12

1

12.

V.V.g.e

LEVVI

g

OVOV

c

OVOVD

m ⋅≅⎟⎠⎞

⎜⎝⎛ +⋅

⎟⎟⎠

⎞⎜⎜⎝

⎛ +⋅≅

• Reasonable agreement with simulation data on slide 15

(Note that this expression is found by using 1.223 and 1.233 in the text, and not from the approximate ID expression on the previous slide)


Mobility Degradation due to Vertical Field

• In short channel MOSFETS, the oxide thickness has been continuously scaled down with feature sizes

– 6.5nm in 0.35µm, 2.2nm in 0.13µm technology

• As a result, there is a large vertical electric field that tries to pull the carriers closer to the "dirty" silicon surface

– Imperfections impede movement and thus mobility

• This effect can be included by replacing the mobility term with an "effective mobility"

( ) V.....

VOVeff

140101

=+

≅ θθµµ

• Yet another "fudge factor"

– Possible to lump with EcL parameter

51


Summary

• The long channel model does not predict gm/ID with reasonable accuracy in any operating regime

– Accuracy also tends to get worse in newer technology

• Once again, we'll find a way to deal with this in practice

• Simple trick: Change of design variables

– Instead of "thinking", in terms of VOV, we will use gm/ID as a design variable, and not as an unknown that is determined from our choice of VOV

• "gm/ID design methodology" - more later…

• Next lecture, we will first familiarize ourselves with the achievable ft and intrinsic gain in our EE214 technology

52


Lecture 5EE214 Technology: fT and Intrinsic Gain

gm/ID-Based Design


[email protected]



Overview

• References

– F. Silveira et. al. "A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA," IEEE Journal of Solid-State Circuits, Sept. 1996, pp. 1314-1319.

– D. Foty, M. Bucher, D. Binkley, "Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id," Proc. Int. Conf. on Electronics, Circuits and Systems, pp. 1179-1182, Sept. 2002.

– Denis Flandre's Notes: "Méthodologie gm/ID: un chaînon entre l'analyse symbolique et la synthèse de circuits analogiques basse puissance," available athttp://www.comelec.enst.fr/taisa/Presentations/DenisFlandre.pps

53


Overview

• Introduction

– Today, we'll continue to characterize the EE214 technology. The two remaining figures of merit that are of interest to us as circuit designers are fT and intrinsic device gain. In conclusion, we find that VOV is not "directly" related to either performance metric we care about. Hence, we switch towards a strategy called "gm/ID-based design", in which gm/ID, rather than VOV, is used as a central design variable.


Performance Metrics of Interest


gs

mT C

g=ω


D

mIg

• Intrinsic Gain

omrg

54


fT Simulation

$ ft vs. gate overdrive


.param gs=1

vds d 0 dc 1.5Vvgs g 0 dc 'gs'mn1 d g 0 0 nch214 L=0.35um W=10um

.op

.dc gs 0.4V 1.2V 10mV

.probe ov = par('gs-vth(mn1)')

.probe ft = par('1/2/3.142*gmo(mn1)/(-cgsbo(mn1))')

.options post brief dccap


.end


Result

223

21

LVf OV

Tµ

π=Long Channel:

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

25

30NMOS W/L=10/0.35

VOV

[V]

f T [G

Hz]

EE214 technologyLong Channel Fit

55


Observations - fT

• Again, a simple long channel model doesn't do a very good job

– Large fT discrepancy in weak inversion and in strong inversion, at large VOV

• The reasons for these discrepancies are exactly the same as the ones we came across when looking at gm/ID– Bipolar action in weak and moderate inversion

– Short channel effects at large VOV

• Less gm, hence lower gm/Cgs

• Same conclusion, we won't be able to make good predictions with a simple long channel relationship


Another Look at gm/ID·fT

2

321

Lf

Ig

TD

m µπ

=⋅Long Channel:

-0.1 0 0.1 0.2 0.3 0.4 0.50

20

40

60

80

100

120

140

160

NMOS W/L=10/0.35

VOV

[V]

gm

/ID

*fT [G

Hz/

V]

EE214 technologyLong Channel

Short channel effects

Sweet spot (?)

Long channel predicts too much gm/ID

56


Intrinsic Gain Simulation

$ gm*ro vs. vds$ Boris Murmann, September 2006

$ vt measured using .op run.param vt1=580m.param vt2=600m

mn1 d g1 0 0 nch214 L=0.35um W=10ummn2 d g2 0 0 nch214 L=0.40um W=10umvg1 g1 0 dc 'vt1+0.2' vg2 g2 0 dc 'vt2+0.2' vd d 0 dc 1

.op

.dc vd 0 3.3V 10mV

.probe av1 = par('gmo(mn1)/gdso(mn1)')

.probe av2 = par('gmo(mn2)/gdso(mn2)')

.options post brief


.end


Intrinsic Gain Plot (VOV=200mV)

0 1 2 30

20

40

60

80

100

120NMOS W=10um

VDS

[V]

gm

*ro

0 0.2 0.4 0.60

20

40

60

80

100

120NMOS W=10um

VDS

[V]

gm

*ro

L=0.35umL=0.4um

L=0.35umL=0.4um

Long Channelgmro=const.

57


Observations – Intrinsic Gain

• The gm·ro product shows a strong dependence on VDS bias– Mostly due to varying ro, (see lecture 2, slide 20)

• Also, there is a very smooth transition from triode to somethingclose to forward active behavior– Long channel model would have predicted an abrupt change

to large intrinsic gain at VDS = VOV

– From the plots, we see that we need VDS > 1.5…3 VOV to get appreciable gain

• At high VDS, ro and thus gm·ro decrease due to SCBE (substrate current induced body-effect)– Highly technology dependent, and usually not present in

PMOS devices– If you are interested in more details, please refer to EE316

or a similar course


Why care about VOV?

• By now, it should be clear that VOV is not a very useful design variable

– There is no simple expression that accurately links either gm/ID, ft or gm·ro to VOV

– VOV does not even clearly define the onset of forward active operation ("Vdsat")

• The primary variables we care about from a design and performance perspective are gm/ID, ft and gm·ro

– So why not work exclusively with these?

– In case we need a rough estimate for "Vdsat", we can always use Vdsat ≅ 2/(gm/ID)

• E.g. gm/ID=10V-1 ⇒ Vdsat ≅ 200mV

• Let's go back to a design example using a simple CS stage

58


Design Example 1

• Given specifications

– DC gain=-2, ID ≤ 2mA, f-3dB=100MHz, CL=10pF

– Make transistor as small as possible


Hand Calculations (1)

mS.gRgA

pFMHzR

CRf

mLmDC

LLL

dB

612159

22

15910100

1211

21

3

=Ω

=⇒−=−=

Ω=⋅

=⇒=− ππ

• If we use all the available current, we have

V.

mAmS.

Ig

D

m 1362

612 ==

• We know that in our technology gm·ro ~> 40, even for minimum channel length. Hence, for a small signal gain of 2, the output impedance of the amplifier will be dominated by RL

– OK to use L=Lmin=0.35µm

• We can now find RL and gm simply as

59


Hand Calculations (2)

• How about using less current?

• Recall that for fixed transconductance W ~ 1/VOV ~ gm/ID– Using less current means larger gm/ID and thus larger device

• But specifications said to minimize device size

• As a last step, we need to determine the actual device width

– For design implementation and verification with Spice

• Using long channel equations will be very inaccurate

• Solution: Sizing chart

– Plot of ID/W as a function of the design variable gm/ID– Can generate this chart once for several channel lengths

and use it throughout the design process


Current Density Chart

0 5 10 15 20 250

10

20

30

40

50

60

70

80

90NMOS L=0.35um

gm

/ID

[1/V]

I D/W

[uA

/um

]

(VDS=1.5V)

60


3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2010

0

101

NMOS L=0.35um

gm

/ID

[1/V]

I D/W

[uA

/um

]

A Better Current Density Chart

23µA/µm

6.3 1/V

(VDS=1.5V)


Does VDS matter?

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2010

0

101

NMOS L=0.35um

gm

/ID

[1/V]

I D/W

[uA

/um

]

VDS

=0.5V

VDS

=1.5V

VDS

=2.5VAt gm/ID = 6.3 1/V:

ID/W = 21.8 A/m (VDS=0.5V)

ID/W = 23.3 A/m (VDS=1.5V)

ID/W = 23.6 A/m (VDS=2.5V)

∴ Insignificant dependence on VDS; OK to use a single chart for design (e.g. VDS=1.5V)

61


Spice Verification

• So, the device width is

• How to determine VB?

• Adjust VB in Spice until gm/ID=6.3V-1

• Good initial guess– VB ≅ Vt+2/(gm/ID) ≅ 600mV+317mV

• Fortunately, we'll find a way to build circuits without VB

– No need to iterate in practice…

mm

WI

IWD

D µµ 8723

2000 ===


DC Operating Point

**** mosfetssubckt element 0:mn1 model 0:nch214 region Saturationid 2.0147mibs 0. ibd 0. vgs 845.0000mvds 1.6797 vbs 0. vth 569.7473mvdsat 201.1145m

beta 60.5664mgam eff 894.1238mgm 12.7994mgds 223.6427u

gmb 2.7928mcdtot 112.7289fcgtot 154.6957fcstot 294.9323f

cbtot 300.7032fcgs 107.6797fcgd 19.7903f

V.

mA.mS.

Ig

D

m 1376012812 ==

62


AC Response

100

101

102

0

1

2

3

4

5

6

7

f [MHz]

|vo

/vi|

[dB

]

5.87dB=1.97


Observations and Remarks (1)

• The design is essentially "dead on" target!– No need for any Spice tweaking

• We accomplished this by focusing on a performance related parameter (gm/ID) in the design process– Note that strictly speaking, device width is not a design

parameter, since it does not directly relate to any of the specs that we were given!

63


Observations and Remarks (2)

• The key advantage of gm/ID based design is that it allows you to transition from hand analysis to Spice without much of the "usual" modeling uncertainties

– Simply because we are incorporating relevant simulation data into the design process

– "Closed loop" design

– Enables you to optimize your circuit without even running a Spice simulation!

• To see why this is good, let's compare with some popular alternatives, as seen in many labs and cubicles around the country…


Design Methodology 1 (Worst)

• Have an existing design that somehow works for a different process, different specs, …

• Port this design over and tweak all 137 transistor geometries until I meet the specs…

• 500 Spice runs later, I am approaching the deadline with a design that somehow works, god knows how/why

64


Design Methodology 2 (Better)

• Remember the square law transistor model from class

• Go through the pain of estimating µCox, and do some hand calculations

• Plug my design into Spice and realize that everything is about 20…80% off

• Throw away my hand analysis and revert back to the "Spice Monkey" design flow from here


Design Methodology 3 (Much Better)

• Spend some time to characterize your technology using Spice– Current density as a function of gm/ID (Sizing Chart)– gm/ID vs. fT for different L– Intrinsic gain for different L– Junction capacitance estimate ("self loading")

• Do hand calculations using the generated technology data– Use MathCAD or Excel script– Can quickly iterate through tens of different designs, if

necessary

• Implement and verify in Spice– Only minor tweaking necessary (if any)– Done!

• More later…

65


gm/ID Considerations

• In case there is no "hard constraint" on gm/ID, e.g. via ωT or swing, a good starting point is to bias the device around the "technology hot spot" (highest gm/ID·fT)

0 5 10 15 20 25

20

40

60

80

100

120

140NMOS L=0.35µm

gm

/ID

[1/V]

gm

/ID

*fT [G

Hz/

V]

66


Lecture 6Design Example 2

Extrinsic Capacitance


[email protected]



Overview

• Reading

– 1.6.7 (Parasitic Elements)

• Introduction

– In today's lecture, we'll look at another CS amplifier design example – this time with a more realistic input source that has finite resistance. Through this example, we find that we need more modeling to accurately predict the resulting pole at the gate node. Our discussion leads to a discussion of parasitic extrinsic capacitors around the MOSFET - overlap and junction capacitance.

67


Design Example 2

• Given specifications

– DC gain=-4, ID ≤ 0.5mA

– RL=1k, Ri=10k

– Maximize and estimate bandwidth

gsiLom

i

oCsR1

1)R||r(g)s(v)s(v)s(H

+⋅−==



Hand Calculation

• Just as in the previous design example, we know thatgm·ro >> ADC. Hence we simply find

mSk

g

RgA

m

LmDC

41

44

=Ω

=

−=−=

• In order to maximize bandwidth, we need Cgs as small as possible. Again, this is the case for using up all the availablecurrent, i.e. minimum gm/ID

VmA.mS

Ig

D

m 1850

4 ==

• In order to estimate the achieved bandwidth, we can now find Cgs using

?mS

fgC

T

mgs

421

21

ππ==

68


Transit Frequency Chart

0 5 10 15 20 250

5

10

15

20

25

30NMOS L=0.35um

gm

/ID

[1/V]

f T [G

Hz] 16GHz


Bandwidth

• Using the transit frequency chart, we find

fFGHzmS

fgC

T

mgs 40

164

21

21 ===

ππ

MHzfFkCR

fgsi

dB 39840101

211

21

3 =⋅

==− ππ

• As a last step, we'll now verify the design using Spice

– Use current density chart to find W

69


3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2010

0

101

NMOS L=0.35um

gm

/ID

[1/V]

I D/W

[uA

/um

]

Current Density Chart

15.5µA/µm


Spice Verification

• Device width

• Simulation circuit

m.

WI

IWD

D µ32515

500 ===

70


DC Operating Point

**** mosfetssubckt element 0:mn1 model 0:nch214 region Saturationid 507.0226uibs 0. ibd 0. vgs 795.0000mvds 1.4930 vbs 0. vth 572.5882mvdsat 172.3503m

beta 22.1349mgam eff 894.1238mgm 4.0656mgds 70.2071u

gmb 897.2679ucdtot 42.9622fcgtot 56.5567fcstot 108.8000f

cbtot 112.7236fcgs 39.3251fcgd 7.2419f

V.

AmS.

Ig

D

m 10285070664 ==

µfF.Cgs 339= Good Agreement.


Frequency Response

• Simulation result: f-3dB=180MHz. Hand analysis: f-3dB=398MHz !

– Time to take a look at extrinsic capacitance…

100

101

102

0

2

4

6

8

10

12

14

f [MHz]

|vo

/vi|

[dB

]

3dB

11.6dB=3.8

71


Extrinsic Capacitance

• Overlap capacitance– Gate to source and gate to drain

• Junction capacitance– Source to bulk and drain to bulk


Overlap Capacitance

• Two components

– Direct overlap ~ CoxWLoverlap

– Additional component due to fringing fields• Non-negligible in modern technology (poly thickness large

compared to other feature sizes)

• EE214 technology parameters

– NMOS: Col= 0.23fF/µm

– PMOS: Col= 0.48fF/µm

72


Junction Capacitance

• Two components

– Area (AS, AD) and Perimeter (PS, PD)

mjswDB

jswmj

DB

jjdb

PBV1

CPS

PBV1

CASC

⎟⎠⎞

⎜⎝⎛ +

⋅+

⎟⎠⎞

⎜⎝⎛ +

⋅=

EE214 Technology

Cj Cjsw mj, mjsw PB

NMOS 0.85 fF/µm2 0.49 fF/µm 0.39 0.51V

PMOS 1.11 fF/µm2 0.48 fF/µm 0.48 0.93V

• Tedious to hand-calculate– In practice, we'll work with estimates and leave accurate

calculations for the final Spice tweak

• HSpice automatically calculates junction capacitance based on W and a geometry factor

– LTSpice does not (must specify AS, AD, PS, PD)


Layout Dependence

73


MOS Capacitor Summary

Subthreshold TriodeForward Active

Cgs Col ½ WLCox+ Col2/3 WLCox + Col

Cgd Col ½ WLCox+Col Col

Cgb ≅ small* ≅ small*

Csb Cjsb Cjsb+ CCB/2 Cjsb+ 2/3CCB

Cdb Cjdb Cjdb+ CCB/2 Cjdb

111

−

⎟⎟⎠

⎞⎜⎜⎝

⎛+

oxCB WLCC

* Channel is not a perfect "shield," hence there is some finite Cgb


Capacitance Simulation

• Gradual transition from weak inversion to forward active, and forward active to triode!

0 0.5 1 1.5 2 2.5 3 3.50

2

4

6

8

10

12

14

NMOS W/L=10/0.35, VDS

=0.5V

VGS

[V]

Ca

pa

cita

nce

[fF

]

Cgs

Cgd

Cgb

74


Does Junction Capacitance Matter?

• Let's plug in some numbers…– Using the data on slide 13, W=10µm and VDB=1.5V we find

• Cjdb,nmos = 11.3fF• Cjdb,pmos = 13.7fF

• How does this compare to Cgs?– In our technology, Cox=5.3aF/µm2, with W= 10µm and

L=0.35µm, we find• Cgs,nmos = 15fF• Cgs,pmos = 17fF

• Rule of thumb– Junction capacitance is comparable to Cgs!

• Cj ~ 0.8 Cgs (for minimum L at 1.5V bias)

• Unfortunately, this means that junction capacitance will be significant in many circuits…


PMOS Well Capacitance

• In the EE214 (N-well) technology, the PMOS transistor is a 5 terminal device!– G, D, S, B, Substrate

• N-well forms a PN junction with Substrate– Often "AC shorted" when N-well=VDD, Substrate=GND– Not shorted when we connect N-well to source!

• Resulting capacitance ~ 0.1fF/µm2

• Not modeled in Spice! Must add extra diode manually in this case

75


Complete Small Signal Model (Forward Active)


HSpice .OP Output Variables

cdtot 42.9622f

cgtot 56.5567f

cstot 108.8000f

cbtot 112.7236f

cgs 39.3251f

cgd 7.2419f

cdtot ≡ Cgd + Cdb

cgtot ≡ Cgs + Cgd + Cgb

cstot ≡ Cgs + Csb

cbtot ≡ Cgb + Csb+ Cdb

cgs ≡ Cgs

cgd ≡ Cgd

HSpice (.OP) Corresponding Small SignalModel Elements

76


+ A Note on Transcapacitance

• It turns out that this complicated model still doesn't describe the parasitics with 100% accuracy

– Since MOSFETS are 4-terminal devices, we are really dealing with a "4-terminal capacitor" and not with a network of simple two-terminal capacitors

• In practice, such "transcapacitance" effects are rarely relevantfor design & hand analysis

– Model based on two-terminal capacitors is usually good to within a few percent

– We'll simply ignore transcapacitance and use Spice as a final check to see if this was OK…

• In case you are curious about more details, please refer to section "Introducing Transcapacitance" in the HSpice manual

77


Lecture 7Design Example 2 (Continued)

Zero-Value Time Constant Analysis


[email protected]



Overview

• Reading– 7.1, 7.2.0, 7.2.1 (Miller Effect in CS Stage, only pp. 488-493)– 7.3.0, 7.3.1 7.3.2 (Zero-Value Time Constant Analysis)– 7.3.3 (Cascade Amplifier Frequency Response) – Supplementary document "Bandwidth estimation techniques," by

Tom Lee (optional, see website).

• Introduction– Last lecture, we found that using a simple circuit model based on

only intrinsic capacitance is not sufficient for accurate bandwidth prediction in our CS stage. Having learned about the involved extrinsic capacitances, we are now in a position to improve our hand analysis and match the Spice result with good precision. Tosimplify the analysis, we will utilize the so-called "Miller Approximation". Next, we will take at look at the the "Zero-Value Time Constant Analysis" as an alternative method, which is useful for a much broader class of circuits, beyond simple common source stages.

78


Design Example 2 Revisited

?)s(H =


Bandwidth Estimation (1)

• To simplify the problem, let's first neglect ro and Cdb

– We'll need to check later is the latter assumption was OK

• Next, we cut the circuit as shown below and calculate the equivalent admittance seen looking into the right side of the cut

)s(v)s(i)s(Y

gs

=

79


Bandwidth Estimation (2)

( ) ( ) 0=⋅−++⋅−= gdgsoL

ogsmgdogs sCvv

RvvgsCvvi

( )⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

+

−−=⋅−==∴

gdL

m

gd

Lmvgdvgs CsR

gC

sRg)s(AwithsC)s(A

)s(v)s(i)s(Y

1

11


Miller Approximation

• Assuming that the poles and zeros in Av(s) occur at much higher frequencies than the bandwidth we are trying to estimate, it is OK to replace Av(s) with its DC value

– This is known as the "Miller approximation"

– It is always a good idea to check (later) if the approximation was indeed valid!

• With the Miller approximation, we have

( ) gdLm sCRg)s(Y ⋅+≅ 1

• This is the same as a capacitor to GND with a value of (1+gmRL) times Cgd

– "Amplified capacitance"

80


Generalization

• Interesting cases

– Av=0 ⇒ Zin=Z (no surprise…)

– Av=1 ⇒ Zin=∞• "Bootstrapping"

– Av>1, e.g. Av=2 ⇒ Zin=-Z (negative!)

– Av<0, ⇒ Zin=Z/(1+|Av|)• Impedance reduction

( )vin

vtestvtest

test

test

testin

AYY

AZ

ZvAv

vivZ

−=

−=−==

1

1


Modified Input Network

• Very simple!

– At least much simpler than using exact expressions• See e.g. equation 7.19 in the text

• Next, we'll verify if the involved assumptions hold in our example circuit, and also see how accurately we can match Spice

– Need estimates of Cgd and Cgb

( )[ ]gdLmgbgsidB CRgCCR

f⋅+++

≅− 11

21

3 π

81


Extrinsic Capacitance Estimates

• Estimating Cgd is simple:fF.fF.

mfF.WCgd 4723032230 =⋅=⋅=µ

• How about Cgb?

• We can include Cgb by using a modified transit frequency chart

• Previously, we used

gs

mT C

gfπ21=

• Taking extrinsic capacitances into account, we can redefine

gg

m

gdgbgs

mT C

gCCC

gfππ 21

21 =

++=

• The chart on the following slide was generated with the Spice deck shown on slide 5, lecture 5, with the following modified line – .probe ft = par('1/2/3.142*gmo(mn1)/(-cggbo(mn1))')


Modified Transit Frequency Chart

80 5 10 15 20 250

5

10

15

20

25

30NMOS L=0.35um

gm

/ID

[1/V]

f T [G

Hz]

Improved estimate using Cgg

Previous estimate

11.25

82


Improved Bandwidth Estimate

• Using the transit frequency chart, we find

fFGHz.

mSfgC

T

mgg 57

25114

21

21 ===

ππ

( )[ ]

[ ]

[ ] MHzfF.fFk

CRgCR

CRgCCRf

gdLmggi

gdLmgbgsidB

1844745710

121

121

11

21

3

=⋅+Ω

=

+=

+++≅−

π

π

π

• Our simulation result from last lecture was

MHzf Spice,dB 1803 =−

• Pretty good! (2% error)


Assumption Check (1)

• It is interesting (and necessary in general) to check how good the Miller assumption was in this analysis

• We assumed that

LmgdL

m

gd

Lmv RgCsRgC

sRg)s(A −≅

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

+

−−=

1

1

up to the frequency of interest (~180MHz)

• Let's check this by calculating the magnitudes of the pole and zero in Av(s)

GHzfF.

mSCg

GHz.fF.kCR

gd

m

gdL

8647

421

21

521471

1211

21

==

=⋅Ω

=

ππ

ππ

83



• We had also assumed that the impact of Cdb is negligible

– How can we make sure this is OK?

• One possible solution: Re-derive Av(s) with Cdb present

Cgs+Cgbgmvgs

+vgs-

+vo-

RL

Ri

vi

Cgd

Y(s)i(s)

Cdb

( ) 00 =⋅+⋅−++ dbgdgsoL

ogsm sCvsCvv

Rvvg

)s(v)s(v)s(A

gs

ov =



• Zero is unchanged, but pole frequency is lowered. From our Spice output, we know that Cdb=35.8fF, and hence

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

++

−−==∴

)CC(sRgC

sRg

)s(v)s(v)s(A

dbgdL

m

gd

Lmgs

ov 1

1

GHz.)fF.fF.(k)CC(R dbgdL

73835471

1211

21 =

+⋅Ω=

+ ππ

• Still not too bad, since 3.7GHz >> 180MHz

– But what if we now add some load capacitance at the output of the amplifier?

• Will appear in parallel with Cdb

84


Effect of Output Loading (1)

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

+++

−−==

)CCC(sRgC

sRg

)s(v)s(v)s(A

LdbgdL

m

gd

Lmgs

ov 1

1

• Suppose CL=10pF, then

! MHzMHzpFk)CCC(R LdbgdL

180161011

211

21 <<=

⋅Ω≅

++ ππ


Effect of Output Loading (2)

• Obviously, with the added CL=10pF, the Miller approximation does not hold any more

• So what is going on in this modified circuit, with large CL?– Cgd is "amplified" only at low frequencies, before CL

"destroys" the gain from vgs to vo

– The pole caused by Cgd no longer impairs the 3-dB bandwidth of the circuit

– Intuitively, the bandwidth must now be somehow set by CL

• After all, it destroys the gain from vgs to vo, which implies that the gain from vi to vo must also roll off

• With very large CL, it is intuitively clear what the approximate bandwidth of the circuit should be– But how about other cases and circuits that don't have a

straightforward Miller approximation?

85


Zero-Value Time Constant Analysis

• Fortunately, there is a more general method that allows us to estimate the bandwidth of arbitrary circuits (within limits)

– Without going though the pain of deriving the complete s-domain transfer function

• "ZVTC Analysis," or "Open Circuit Time Constant Analysis"

• Here's how it works

– Remove all but one capacitor. Short independent voltage sources, remove independent current sources

– Calculate resistance seen by capacitor and compute τj=RjoCj

– Repeat for all capacitors in the circuit

– Sum all time constants and calculate bandwidth estimate

∑≅−

jdB τ

ω 13


Example (1)

• Step 1:

11 CRi=τ

86


Example (2)

iLmLitest

testitestmLitest

test

testgsmLgs

test

testo RRgRR

i)iRig(RRi

i)ivg(Rv

ivR ++=++=

++==2

• Step 2:

• Step 3:

33 CRL=τ

22 C)RRgRR( iLmLi ++=τ

Lo RR =3


Bandwidth Estimate Based on ZVTC

• Reality check using numbers from design example 2

3213213

1211

21

CRC)RRgRR(CRf

LiLmLiidB ++++

=++

≅∴ − πτττπ

fF.CCfF.CC

fF.CCC

db

gd

gbgs

835

47

649

3

2

1

==

==

=+=

psfF.kpsfF.)kk(

psfF.k

368351377471105

49664910

3

2

1

=⋅Ω==⋅Ω+Ω⋅=

=⋅Ω=

τττ

MHzf dB 175121

3213 =

++≅∴ − τττπ

• Not bad!

– Spice simulation gave 180MHz

– Miller approximation result was 184MHz

87


Inclusion of CL

• What happens if again, we consider adding a large load capacitance (CL)?

pFCCCfF.CC

fF.CCC

Ldb

gd

gbgs

10

47

649

3

2

1

≅+=

==

=+=

ps,pFkpsfF.)kk(

psfF.k

00010101377471105

49664910

3

2

1

=⋅Ω==⋅Ω+Ω⋅=

=⋅Ω=

τττ

MHz.f dB 614121

3213 =

++≅∴ − τττπ

• Now the third time constant dominates and significantly reduces our bandwidth estimate

• Looks like this is a powerful method

– Miller effect is taken care of, output loading effect is included

• Most importantly though, the method provides us with insight about the limiting elements in our circuit!


How ZVTCs Work

• Intuition

– Each time constant relates to the bandwidth that we would get if no other capacitors were present

• "Local bandwidth bottleneck"

– For simplicity, the ZVTC method linearly combines the local bottlenecks to estimate the overall bandwidth

• Mathematically, the ZVTC method is based on the approximation

11 111

1 +≅

++++= −

− sbK

sb...sbsbK)s(H n

nn

n• Can show that

– b1 corresponds to the sum of all time constants in the circuit

– This approximation is OK unless there are "undamped" complex poles, or several limiting poles with comparable magnitude

88


A Simple Example

• Roughly -22% error

• ZVTC estimates tend to be conservative

– Actual bandwidth will almost always be at least as high as estimate

RC.

RC.

RC dBdB506440121

33 ==−⋅= −− ωω

Exact bandwidth: ZVTC Method:


ZVTC Accuracy and Other Caveats

• Accuracy tends to be OK when there is a single dominant pole– Not surprising, since the "approximation" shown on slide 22

makes no error for a single pole system– Fortunately, many practical circuits indeed have a somewhat

dominant pole

• Some elements, like AC coupling caps, must be eliminated before applying the ZVTC method– These caps are meant to be shorts at high frequencies, and

do not degrade the signal bandwidth– Can use method of "short circuit time constants" to

determine coupling cap sizes• See supplementary document by Tom Lee

• The ZVTC method tells us nothing about zeros in the transfer function!

89


Lecture 8Electronic Noise


[email protected]



Overview

• Reading

– 11.1 (Noise Introduction)

– 11.2.2 (Thermal Noise)

– 11.3.3 (MOS Transistor Noise)

– Supplementary Handout: "Introduction to Noise," by Daniel Cooley

• Introduction

– Electronic noise is a significant and fundamental issue in the design of high performance analog circuits. The noise level of a circuit affects the "fidelity" or accuracy of the signals that are beingprocessed. As we shall see, minimizing electronic noise is costly; there exists a steep tradeoff with power dissipation and bandwidth. Today's lecture will provide an introduction to electronic noise at the component level (resistors and MOSFETs). We will use these results in the remainder of the course to analyze the impact of noise in various circuits.

90


Types of Noise

• "Man made noise", interference noise

– Signal coupling

– Substrate coupling

– Finite power supply rejection

– Solutions• Fully differential circuits

• Layout techniques

• "Electronic noise" or "device noise" (focus of this lecture)

– Fundamental• E.g. "thermal noise" caused by random motion of carriers

– Technology related• "Flicker noise" caused by material defects and "roughness"


Significance of Electronic Noise (1)

"Signal" "Noise"

noise

2signal

noise

signal

P

V

P

PSNR ∝=

Signal-to-Noise Ratio

91



• Example: Noisy image

http://www.soe.ucsc.edu/~htakeda/kernelreg/kernelreg.htm



• The "fidelity" of electronic systems of often determined by their SNR

– Examples• Audio systems

• Imagers, cameras

• Wireless and wireline transceivers

• Electronic noise directly trades with power dissipation and speed

– In most circuits, low noise dictates large capacitors (and/or small R, large gm), which means high power dissipation

• Noise has become increasingly important in modern technologies with reduced supply voltages

– SNR ~ Vsignal2/Pnoise ~ VDD

2/Pnoise

• Designing a low power, high performance circuit requires good understanding of electronic noise!

92


Topics/Questions

• How to model noise of circuit components

• How to calculate/simulate noise performance of a complete circuit (e.g. SNR)

• Do we need to worry about electronic noise in all circuits?

– The answer must be no; digital folks never talk about this…

– Need to get a feel for situations where noise matters


Ideal Resistor

• Constant current, independent of time

• Non-physical

– In a physical resistor, carriers "randomly" collide with latticeatoms, giving rise to small current variations over time

i(t)

1V/1kΩ

93


Physical Resistor

• "Thermal Noise" or "Johnson Noise"– J.B. Johnson, "Thermal Agitation of Electricity in Conductors,"

Phys. Rev., pp. 97-109, July 1928.

• Can model random current component e.g. using a noise current source in(t)

i(t)

1V/1kΩ


Properties of Thermal Noise

• Present in any conductor

• Independent of DC current flow

• Instantaneous noise value is unpredictable since it is a result of a large number of random, superimposed collisions with relaxation time constants of τ ≅ 0.17ps

– Consequences:• Gaussian amplitude distribution

• Knowing in(t) does not help predict in(t+∆t), unless ∆t is on the order of 0.17ps (cannot sample signals this fast)

• The power generated by thermal noise is spread up to very high frequencies (1/τ ≅ 6,000Grad/s)

• The only predictable property of thermal noise is its average power!

94


Average Power

• For a deterministic current signal with period T, the average power is given by

( )∫−

⋅⋅=2/T

2/T

2av dtRti

T

1P

• This definition can be extended to capture non-deterministic random signals

– Assuming a real, stationary and ergodic random process

( )∫−

∞→⋅⋅=

2/T

2/T

2n

Tn dtRti

T

1limP

• For notational convenience, we typically drop R in the above expression and work with "mean square" current (or voltages)

( )∫−

∞→⋅=

2/T

2/T

2n

T

2n dtti

T

1limi


Thermal Noise Spectrum

• The so-called power spectral density (PSD) shows how much power a signal caries at a particular frequency

• In the case of thermal noise, the power is spread uniformly up to very high frequencies (about 10% drop at 2,000GHz)

PSD(f)

f

n0

• The total average noise power Pn in a particular frequency band can be found by integrating the PSD

( )∫ ⋅=2

1

f

f

n dffPSDP

95


Thermal Noise Power

• Nyquist showed that the noise PSD of a resistor is

( ) kT4nfPSD 0 ⋅==

• k is the Boltzmann constant and T is the absolute temperature

– 4kT = 1.66·10-20 Joules at room temperature

• The total average noise power of a resistor in a certain frequency band is therefore

( ) fkT4ffkT4dfkT4P 12

f

f

n

2

1

∆⋅=−⋅=⋅= ∫


Equivalent Noise Generators

• Can model the noise using either an equivalent voltage or current generator

fR

1kT4

R

Pi n2n ∆⋅⋅==fRkT4RPv n

2n ∆⋅⋅=⋅=

V4vMHz1f

Hz/nV4f

v

Hz

V1016

f

v

:1kΩR For

2n

2n

218

2n

µ∆

∆

∆

=⇒=

=

⋅=

=

−

nA4iMHz1f

Hz/pA4f

i

Hz

A1016

f

i

:1kΩR For

2n

2n

224

2n

=⇒=

=

⋅=

=

−

∆

∆

∆

96


Two Resistors in Series

( ) fRRkT4vvv 2122n

21n

2n ∆⋅+⋅⋅=+=

• Always remember to add independent noise sources using mean squared quantities

– Never add RMS values!

( ) 2n1n22n

21n

2

2n1n2n vv2vvvvv ⋅⋅−+=−=

• Since vn1(t) and vn2(t) are statistically independent, we have


MOSFET Thermal Noise (1)

• As one would expect, the noise of a MOSFET operating in the triode region is equal to that of a resistor

• In the forward active region, the thermal noise of a MOSFET can be modeled using a drain current source with spectral density

fgkT4i m2d ∆γ ⋅⋅⋅=

• For a long channel MOSFET γ=2/3

• For the past ten years, researchers have been debating over the value of γ in short channels

– Preliminary (wrong) results had suggested that in short channels γ can be as high as 2…5 due to hot carrier effects

97


MOSFET Thermal Noise (2)

• Fortunately, these discussions have come to an end with the conclusion that short channels have γ ≅ 1– A.J. Scholten et al., "Noise modeling for RF CMOS circuit

simulation," IEEE Trans. Electron Devices, pp. 618-632, March 2003.


Spice Simulation (1)

$ EE214 MOS device noise simulation


vd dd 0 1.5vm dd d 0

vg g 0 dc 0.8 ac 1mn1 d g 0 0 nch214 L=0.35u W=10uh1 c 0 ccvs vm 1

.op

.ac dec 100 10k 1gig

.noise v(c) vg

.options post brief


.end

dd1.5V

d

0V c

CCVS1V/A

98


10-2

10-1

100

101

102

103

10-24

10-23

10-22

f [MHz]

avg

(i d 2)/

df

[A2 /H

z]

HSpice ("outnoise")4kT*2/3*g

m

Spice Simulation (2)

???

(gm=1.28mS)


1/f Noise

• Also called "flicker noise" or "pink noise"

• Caused by traps near Si/SiO2 interface that randomly capture and release carriers

• Occurs in virtually any device, but is most pronounced in MOSFETS

• One (empirical) way to model flicker noise:– Known as "NLEV=2" HSpice model

• For other models, see HSpice manual or– D. Xie et al, "SPICE Models for Flicker Noise in n-MOSFETs from

Subthreshold to Strong Inversion," IEEE Trans. CAD, pp. 1293-1303, Nov. 2000

• Kf is strongly dependent on technology; numbers for EE214 0.35µm CMOS technology:– Kf,NMOS = 0.5·10-25 V2F– Kf,PMOS = 0.25·10-25 V2F

f

f

LW

g

C

Ki

2m

ox

f2f/1

∆⋅

=

99


1/f Noise Corner

• By definition, the frequency at which the flicker noise density equals the thermal noise density

fgkT4f

f

LW

g

C

Km

co

2m

ox

f ∆γ∆ ⋅⋅=⋅

⎟⎠

⎞⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛=

⋅=⇒

W

I

I

g

L

1

C

1

kT4

K

LW

g

C

1

kT4

Kf

D

D

m

ox

f

m

ox

fco

γ

γ

• Example: NMOS, L=0.35µm, gm/ID=10V-1 → ID/W=10A/m

⇒ fco = 244kHz

• In more recent technologies, 1/f corner frequencies can be on the order of 10MHz


1/f Noise Contribution (1)

• Just as with white noise, the total 1/f noise contribution is found by integrating its spectral density

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

=⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

=

⋅= ∫

1

2m

ox

f

1

2m

ox

f

f

f

m

ox

f2tot,f/1

f

flog3.2

LW

g

C

1

kT4

K

f

fln

LW

g

C

1

kT4

K

f

f

LW

g

C

1

kT4

Ki

2

1

γγ

∆γ

• Total flicker noise depends on number of frequency decades

– Same flicker noise power in 1…10 Hz as in 1…10 GHz

– RMS noise proportional to sqrt(# of frequency decades)

• So, does flicker noise matter?

– Look at noise integral to see its relative contribution to totaldrain current noise

100


1/f Noise Contribution (2)

• For circuits with "high bandwidth", flicker noise is often insignificant

– Beware of exceptions…

102

104

106

108

10-23

10-22

10-21

10-20

f [Hz]

Sp

ect

rum

[A2 /H

z]

102

104

106

108

0

50

100

f [Hz]

Sq

rt(I

nte

gra

l) [n

A]


Lower Integration Limit

• Does the flicker noise PSD go to infinity for f→0?

– For a fun discussion, seeE. Milotti, "1/f noise: a pedagogical review," available at http://arxiv.org/abs/physics/0204033

• Even if the PSD goes to infinity, do we care?

– Let's say we are sensing a signal for a very long time (down to a very low frequency), e.g.

• 1 year ≅ 32 Msec, 1/year ≅ 0.03 µHz

– Number of frequency decades in 1/year to 100Hz ≅ 10• Means instead of 7 decades, we'd now have 17 in the previous

example

• sqrt(17/7) = 1.56 → Only 56% more flicker noise!

101


MOS Model with Noise Generator

Noiseless!

f

f

LW

g

C

KfgkT4i

2m

ox

fm

2d

∆∆γ⋅

+⋅⋅⋅=


Other MOSFET Noise Sources

• Gate noise

– "Shot noise" from gate leakage current

– Noise from to finite resistance of gate material

– Noise due to randomly changing potential/capacitance between channel and bulk

• Relevant only at very high frequencies

• Bulk noise

• Source barrier noise in very short channels (Navid & Dutton)

– Shot noise from carriers injected across source barrier

• More in EE314…

102


Lecture 9Electronic Noise (Continued)


[email protected]



Overview

• Reading

– 11.4 (Circuit Noise Calculations)

– 11.5 (Equivalent Input Noise Generators)

– 11.9 (Noise Bandwidth)

• Introduction

– Having established the basic noise mechanisms in MOSFETS, today's lecture looks at noise in circuits. We will learn how to calculate the signal to noise ratio in a basic RC circuit and a common source amplifier. These examples are useful prerequisites for analyzing more complicated circuits (e.g. OTAs, later in this class). Furthermore, we will use these simple to develop a basic feel for the relevance of noise and associated tradeoffs.

103


Noise in Circuits (1)

• Most interesting circuits have more than one relevant noise source

• In order to quantify the net effect of all noise sources, we must refer the noise sources to a single "interesting" node pair of the circuit

– Usually output or input


Noise in Circuits (2)

• Output referred noise– Refer noise to output via

individual noise transfer functions

– Physical concept, exactly what one would measure in the lab

• Input referred noise– Represent total noise via a

fictitious input source that captures all circuit-internal noise sources

– Useful primarily for "fair" comparisons

• E.g. independent of circuit gain

104


Datasheet Example


Circuit Example 1

• Let's calculate

– Output referred noise

– Input referred noise

– Signal-to-noise ratio at output

105


Output Referred Noise

( )2

222

out,nns1f2j1

1nV4sRC11RkT4

fv

⋅+=

+⋅⋅=

π∆

• Short input voltage, add noise source

• Calculate transfer function from noise source to output

• Multiply noise PSD with squared transfer function to get output PSD


Input Referred Noise

RVout

1k

C

1pF

v2

( )22

in,n nV4RkT4f

v=⋅=

∆

• Simply equal to noise PSD of resistor (in this example)

106


+ A Note on Equivalent Input Noise Generators

• In general, input referred noise must be modeled by an equivalent voltage and current source

– See section 11.5 in the text (optional)

• Modeling the noise with a voltage alone I sufficient when the circuit is indeed driven by an ideal voltage source (always an approximation)

• Or, when the input impedance of the circuit is large

– This is the case in MOS circuits at low to moderate frequencies

– Different story at RF frequencies• You'll learn more about this in EE314


Spice Simulation

$ EE214 RC circuit noise


vin in 0 ac 1r1 in out 1k

c1 out 0 1pF

.ac dec 100 100 1gig

.noise v(out) vin

.options post brief


.end

104

106

108

10-18

10-17

10-16

f [Hz]

No

ise

[V

2 /Hz]

outnoiseinnoise

107


Signal-to-Noise Ratio

• Over which bandwidth should we integrate the noise?

• Two interesting cases

– The output is measured or observed by a system with finite bandwidth (e.g. human ear)

• Use frequency range of that system as integration limits

• Applies on a case by case basis

– "Total integrated noise"

∫ ⋅

==2

1

f

f

2out,n

2peak,out

noise

signal

dff

v

V21

PP

SNR

∆


Total Integrated Noise (1)

• Interesting result

– Total noise at the output depends only on C (even though R is generating the noise)

CkTdf

RCf2j11RkT4v

0

22

tot,out,n =⋅+

⋅⋅= ∫∞

π

• Simply the integral over all frequencies (zero to infinity)

• Relevant metric when output is observed without (significant) band limiting– Or when the output is sampled (e.g. switched capacitor

circuits)

• Most suitable for getting a general feel about noise and to establish basic quantitative arguments

108


Total Integrated Noise (2)

• Increasing R increases the noise power spectral density, but also decreases the bandwidth

– R drops out in the end result

102

104

106

108

1010

10-22

10-20

10-18

10-16

10-14

f [Hz]

Sp

ect

rum

[V2 /H

z]

102

104

106

108

1010

0

20

40

60

f [Hz]

Sq

rt(I

nte

gra

l) [ µ

V]

R=1kR=100k

R=1kR=100k


SNR (1)

( ) dB8110122log10 6 =⋅

• Back to our example; plugging in numbers

( )6

2

222peak,out

noise

signal 10122V64V5.0

pF1kTV5.0

CkT

V21

PP

SNR ⋅=====µ

• SNR in dB

• Is this "good"?

• Typical system requirements

– Audio: SNR ≅ 100dB

– Video: SNR ≅ 60dB

– Gigabit Ethernet Transceiver: SNR ≅ 35dB

109


SNR (2)

• Assuming Vout,peak = 1V

SNR [dB] C [pF]20 0.0000008340 0.00008360 0.008380 0.83

100 83120 8300140 830000

Hard to make such small capacitors…

Designer will definitely be concerned about thermal noise, capacitor sizes set by SNR

"Hardcore" thermal noise battle…

• General rules of thumb

– Up to SNR ~ 40dB, integrated circuits are usually not limited by thermal noise

– Achieving SNR >100dB is extremely difficult• Must usually rely on external components or "tricks" (such as

oversampling, see EE315)


MDS and DR

• Minimum detectable signal (MDS)

– A somewhat arbitrary definition

– Quantifies the signal level in a circuit that yields SNR=1; i.e.noise power = signal power

• Dynamic range (DR)

MDSP

DR max,signal=

• If the noise level in the circuit is independent of the signal level (not always the case), it follows that the DR is equal to the "peak SNR", i.e. the SNR with the maximum signal applied

110


Circuit Example 2: Common Source Amplifier

( )

( )

( )

α

γ

γ

πγ

πγ

⋅=

+=

+=

⋅+⋅⎟⎠⎞

⎜⎝⎛ +=

⋅+⋅⎟⎠⎞

⎜⎝⎛ +=

∫∞

CkT

A1CkT

Rg1CkT

dfRCf2j1

RgR1kT4v

RCf2j1Rg

R1kT4

dffv

v

m

0

2

m2

tot,o

2

m

2o

[Ignoring 1/f noise for simplicity]


CS Stage Noise/Power Tradeoff

• Assuming that we're already using the maximum available signal swing, improving the SNR by 6dB means

– Increase C by 4x

– Decrease R by 4x to maintain bandwidth

– Increase gm by 4x to preserve gain

• Assuming that we can keep gm/ID constant, this means that we must increase ID by 4x

• Bottom line

– Improving the SNR in a noise limited circuit by 6dB ("1bit") QUADRUPLES power dissipation !

111


Lecture 10Body Effect

Common Gate Stage


[email protected]



Overview

• Reading– 1.6.6 (Body Transconductance)– 3.3.4, 7.2.4.2 (Common Gate Stage)– 3.4.2.2, 7.3.4 (up to p. 526) (Cascode Stage)

• Introduction– Having completed our discussion of simple common source

amplifiers, we now continue by exploring alternative ways of forming and using single transistor stages. First, we will look at the common gate stage, followed by a discussion of the common drain stage in future lectures. While CS stages can usually be configured with source and substrate nodes tied together, this is often not the case in the CG and CD configurations. Hence, we'll first need to take a look at the socalled "body effect," which becomes significant in this context.

Somewhat tedious to read…

112


The "Atoms" of Analog Circuit Design

• As we've seen from the discussion so far, a common source stage is sufficient for building a simple amplifier

– How about the other two possible configurations?

• We'll find that common gate and drain stages can be incorporated as valuable add-ons, for building "better" amplifiers

• Interestingly, many analog circuits can be decomposed into a combination of the above three fundamental building blocks


Body Connection

• In the EE214 (N-well) technology, only the PMOS device has an isolated body connection

• Newer technologies (e.g. 0.13µm CMOS) also tend to have NMOS devices with isolated body ("twin-well" process)

113


Body Connection Scenarios


Body Effect (1)

• With positive VSB, depletion region around source grows

• Increasing amount of negative fixed charge in depletion region tends to "repel" electrons coming from source

– Need larger VGS to compensate for this effect

VSB>0

114


Body Effect (2)

• This effect is usually factored in as an effective increase in Vt

• Detailed analysis shows

( )fSBftt VVV φφγ 220 −++=

• A change in Vt also means a change in drain current

– Define small signal body transconductance

SB

D

BS

Dmb V

IVIg

∂∂−=

∂∂=

fSBSB

t

D

GS

t

D

SB

t

m

mb

VVV

IV

VI

VV

gg

φγ

22 +=

∂∂=

∂∂

∂∂

∂∂−=

-1


gmb Simulation

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 210

12

14

16

18

20

22

24

NMOS W/L=10/0.35um, VGS

-Vt=0.2V

VBS

[V]

gm

b/gm

[%]

SpiceFit using 2φ

f=0.6V, γ=0.36V-1

VSB

115


Modified Small Signal Model


Common Gate Stage

RS

RL

Vo

-(gm+gmb)vi

+vi-

ii Cgs+Csb

Cgd+Cdb

ro

mbmmsbgsS gg'gCCC +=+=Define:

116


CG Current Transfer

11

1 >>+

≅ Sm

m

Si

o R'gfor

'gCsi

i

Sm

SSSm

Sm

SSm

m

i

o

R'gCRsR'g

R'gR

sC'g

'gii

++

⋅+

≅

++≅

11

11

1


CG Input Impedance (1)

testgs vv −=

( )

SoL

om

test

testin

o

o

o

testtestmtesttest

testoLmo

testmo

test

o

o

L

oo

sCrRr'g

viY

rv

rvv'gi:v@KCL

vr||R'gv

v'gr

vrv

Rv:v@KCL

++

≅=⇒

−+=

≅⇒

−−+=0

117


CG Input Impedance (2)

• At low frequencies

( )⎟⎟⎠

⎞⎜⎜⎝

⎛ +++

≅om

oLS

oL

omin r'g

rRsCrRr'gY 1

⎟⎟⎠

⎞⎜⎜⎝

⎛+≅=

o

L

minin r

R'gY

R 111


– RL<<ro:

– RL>>ro:

min 'g

R 1≅

om

Lin r'g

RR ≅

(well known)

(not so well known…)


CG Output Impedance

Stestgs

gsmo

gs

o

testtest

Riv

v'grv

rvi

−=

++=

( )Smotest

testout R'gr

ivR +≅= 1

(Very high if g'mRS>>1 !)

118


CG Summary

• Current gain is unity up to very high frequencies

– Our "simple," ignorant device model predicts up to roughly fT

• Input impedance is very low

– At least when the output is also terminated with some reasonable impedance

• Can achieve very high output resistance

• In summary, a common gate stage is ideal for turning a decent current source into a much better one

– Seems like this is something we can use to improve our common source stage

• Which is indeed nothing but a decent (voltage controlled) current source


Cascode Stage

• Invented ~1920, in the context of vacuum tube circuits

– http://web.mit.edu/klund/www/cascode.html

( )12210

1 1 omoomi

mm r'grRgiigG +≅≅⋅=

( ) ( )222111221 1 omomomomomom rg~r'grgr'grgRG ⋅≅+=

119


High Frequency Benefits

• Very close to 1, for moderate values of RL

– Mitigates Miller effect

– Even if RL is large, there is often a load capacitance that provides a low impedance termination to help maintain this feature

• Additional benefit

– Cascode mitigates direct forward coupling from Vi to Vo at high frequencies

⎟⎟⎠

⎞⎜⎜⎝

⎛+≅=

22

11 1

o

L

m

mxm

i

x

rR

'ggZg

vv


High Frequency Issues

• Cascode causes pole around fT– Usually non-dominant

– Can be a headache for stability/phase margin in circuits with feedback

• More later…

m

sbgsi

o

'gCC

sii

++

≅1

1

120


Design Example 2 (Lecture 6) Revisited

• What we expect to see in Spice after adding the cascode device

– Gain should be closer to gm1·RL

– Bandwidth should increase (reduction of Miller effect)

– Non-dominant pole around some fraction of fT of cascode device

M2

M1


Frequency Response (1)

• Bandwidth increased from 180MHz to 250MHz

100

101

102

0

5

10

15

f [MHz]

|vo

/vi|

[dB

]

Without cascodeWith cascode

121


Frequency Response (2)

10-3

10-2

10-1

100

101

102

-100

-80

-60

-40

-20

0

20

f [GHz]

|vo

/vi|

[dB

]

Without cascodeWith cascode


Non-Dominant Pole Estimate

subckt element 0:m2 0:m1 model 0:nch214 0:nch214 region Saturati Saturatiid 514.6895u 514.6895uvgs 918.7732m 815.0000mvds 904.0836m 581.2268mvbs -581.2268m 0. vth 705.0212m 587.7659mvdsat 178.3723m 175.2946mbeta 22.3498m 22.1558mgam eff 926.5549m 894.1238mgm 4.0936m 3.9871mgds 94.1732u 108.6333ugmb 676.0386u 898.3368ucdtot 43.0143f 52.2437fcgtot 56.0163f 56.5703fcstot 91.3803f 108.9679fcbtot 93.8478f 121.9629fcgs 40.2737f 39.5319fcgd 7.1355f 7.2417f

( ) ( )fF2.7fF52fF40fF4.91fF40mS68.0mS4

21

CCC'g

21f

1db2sb2gs

m2p

−+−++≅

++≅

π

π

GHz2.5f 2p ≅

GHz4.11fF56

mS421f 2T

≅

≅π

For comparison:

122


Supply Headroom Issue

• Even if we adjust VB such that VDS1 is small, adding a cascode reduces the available signal swing

• This can be a big issue when designing circuits with VDD≅1V

– Typically need each VDS>~0.2V

– A severe dynamic range penalty


Cascode Noise

• It is typically argued that cascodes no not add a significant amount of noise

• A closer look reveals that cascodes can contribute significant noise at high frequencies

– Noise current A no longer compensates B at high frequencies

• We'll take a more quantitative look at this later in this course

VB

Vi

Vo

RL

VDD

i2n1

i2n2

VB

Vi

Vo

RL

VDD

i2n1

A

B

123


Lecture 11Common Drain Stage

(Source Follower)


[email protected]



Overview

• Reading

– 3.3.7 (Common Drain Stage)

– 7.2.2 (Frequency Response of Voltage Buffers)

– 5.3 (Source Follower as an Output Stage, optional)

• Introduction

– Last lecture, we have seen that a common gate stage has a fairly low input impedance, and high output impedance. The common drain stage that we'll analyze today exhibits the exact opposite features: High input impedance and low output impedance. After an analysis of relevant port characteristics, we will discuss some potential applications and also drawbacks of this circuit.

124


Common Drain Stage


CD Voltage Transfer (1)

LtotLtotgsm

gsm

i

o

RsCsCg

sCgvv

1+++

+=

( ) 01 =−−−⎟⎟⎠

⎞⎜⎜⎝

⎛++ oimgsi

LtotgsLtoto vvgsCv

RsCsCv

( )

Ltotm

Ltotgs

m

gs

Ltotm

m

i

o

Rg

CCsg

sC

Rg

gvv

11

1

1

+

++

+⋅

+=

omb

LLtotsbLLtot r||g

||RRCCC 1=+=

125


Low Frequency Gain

• Interesting cases

– RL→∞, ro→∞, gmb=0• PMOS, source tied to body, ideal current source

Ltotm

mv

Rg

ga 10

+= o

mbLLtot r||

g||RR 1=

10 =va

mbm

mv gg

ga+

=0– RL→∞, ro→∞, gmb≠0• NMOS, ideal current source)

(typically ≅ 0.8)

– ro→∞, gmb=0, RL finite• PMOS, source tied to body, load resistor

Lm

mv

Rg

ga 10

+=


High Frequency Gain

• Three scenarios

( )pszs

avvsa v

i

ov

−

−⋅==1

10

gs

m

Cgz −=

Ltotgs

Ltotm

CCR

gp

+

+−=

1

(infinite bandwidth !?)

|z|<|p| |z|>|p| |z|=|p|

126


CD Input Impedance

• By inspection

( ) ( ))s(asCCCsY vgsgbgdin −++= 1

• Gain term av(s) is real and close to unity up to fairly high frequencies

• Hence, up to moderate frequencies, we see a capacitor looking into the input

– A fairly small one, Cgd + Cgb, plus a fraction of Cgs


PMOS Stage with Body-Source Tie

• Gate-body capacitance is in parallel with Cgs

• gmb generator inactive

– Low frequency gain very close to unity

• Very small input capacitance

( )( )gdin

vgbgsgdin

sCY)s(aCCssCY

≅

−++= 1

127


Bootstrapped PMOS Stage

• "Extremely" small input capacitance

( ))s(a)s(asCY vNvPgdin −≅ 1


CD Output Impedance (1)

• Let's first look at an analytically simple case

– Input driven by ideal voltage source

• By inspection

( )sbgsmbmout CCsgg

Z++

= 11

• Low output impedance

– Resistive up to very high frequencies

128



• Now include finite source resistance

( )( )( )gsm

o

go

gsmgox

sCgvv

v

sCgvvi

+⎟⎟⎠

⎞⎜⎜⎝

⎛−=

+−=

1x

ox i

vZ =

igs

i

o

g

RsC

Rvv

+= 1




( )

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+≅

m

gs

gsi

mx

gsC

CsRg

Z1

11

Ri > 1/gmRi < 1/gm

Inductive behavior!

129


Equivalent Circuit for Ri > 1/gm

• This circuit is prone to ringing!

– L forms an LC tank with any capacitance at the output

1

1

22

21

−=

=

=

im

gsi

i

m

RgCR

L

RRg

R||R


Inclusion of Parasitic Input Capacitance

( )( )ii

m

gs

igsi

mx

CsRg

sCCCsR

gZ

+⎟⎟⎠

⎞⎜⎜⎝

⎛+

++=

11

11

• What happens to this result if we don’t neglect Ci=Cgd+Cgb?

gs

m

iiigsi Cg

CRCCR<<

+11

iigs

m

igsi CRCg

CCR11 <<

+

130


Application 1: Level Shifter

• Output quiescent point is roughly Vt+Vov lower than input quiescent point


Application 2: Buffer

• Low frequency voltage gain of the above circuit is ~gmRbig

– Would be ~gm(Rsmall||Rbig) without CD buffer stage

131


Issues

• Several sources of nonlinearity

– Vt is a function of Vo (NMOS, without S to B connection)

– ID and thus Vov changes with Vo

• Gets worse with small RL

• Reduced input and output voltage swing

– Consider e.g. VDD=1V, Vt=0.3V, VOV=0.2V• CD buffer stage consumes 50% of supply headroom!

– In low VDD applications that require large output swing, using a CD buffer is often not possible

– CD buffers are more frequently used when the required swing is small

• E.g. pre-amplifiers or LNAs that turn µV into mV at the output


Application 3: Load Device

• Advantages compared to resistor load

– "Ratiometric"• Gain depends on ratio of similar

parameters

• Reduced process and temperature variations

– First order cancellation of nonlinearities

• Disadvantage

– Reduced swing

22

10

mbm

mv gg

ga+

=

132


Summary – Elementary Transistor Stages

• Common source

– VCCS, makes a good voltage amplifier when terminated with a high impedance

• Common gate

– Typically low input impedance, high output impedance

– Can be used to improve the intrinsic voltage gain of a common source stage

• "Cascode" stage

• Common drain

– Typically high input impedance, low output impedance

– Great for shifting the DC operating point of signals

– Useful as a voltage buffer when swing and nonlinearity are not an issue


Biasing Issue

• Something we haven't talked about

– How to build VB?

• Especially when gain is large, output quiescent voltage is very sensitive to changes in VB

VDD

Vo

vi

VB

133


A Possible Solution

• VGS of M1 and M1' are equal, which implies that their drain currents are (approximately) equal

• gm1 is set by a current (IB), rather than a voltage– Independent of Vt

• Great!

• Problem: Cbig and Rbig

– High pass filter– Large area for low corner

frequency– Typically, this approach is

practical only in some RF circuits


Better Solution: Differential Amplifier

• Bias point of Vop and Vom set by IB– Independent of quiescent

value of Vip and Vim

• Differential output (Vop-Vom) depends only on differential input (Vip-Vim)

• More next lecture…

134


Lecture 12Differential Pair


[email protected]



Overview

• Reading

– 3.5.0, 3.5.3, 3.5.5 (Differential Pair)

• Introduction

– The differential pair is the most widely used two-transistor sub-circuit in analog ICs. As we have already seen last time, using a differential pair as a replacement for a simple common source stage eliminates the need for a precise gate bias voltage (VB). In addition, its differential input and output voltages are more immune to parasitic signal coupling. Today we will analyze some properties of differential pairs and introduce the notion of common- and differential-mode signal components.

135


Differential Pair

• When Vip=Vim, and both transistors are identical, we must have Id1=Id2=ITAIL/2

• How about Vip=Vim=1V versus Vip=Vim=2V?

– Makes no difference!

• From a signal perspective, we care only about the difference of the applied voltages

– Makes sense to introduce a new variable

• Vid=(Vip-Vim)

ITAIL

Id1

Vip

Id2

Vim


Differential and Common Mode (1)

• We now still need a second variable that describes the potential of nodes Vip and Vim

with respect to GND

– Could choose either Vip or Vim

• More elegant solution

– Cut Vid in half and define a new independent variable

– "Common mode" voltage Vic

ITAIL

Id1

+Vip-

Id2

Vid

+Vim-

136


Differential and Common Mode (2)

ITAIL

Id1

+Vip-

Id2

Vid/2+

Vim-

Vid/2

Vic

imipid VVV −=

2

2id

icim

idicip

VVV

VVV

−=

+=

2imip

ic

VVV

+=⇒


Coupling Noise Immunity

• Using differential pairs/signals not only solves the biasing issue, but also mitigates coupling noise issues

Single Ended Signaling Differential Signaling

137


Large Signal Transfer Function (1)

• Let's first do a simple analysis using long channel equations

ITAIL

Id1

M1

+Vip-

Id2

Vid/2+

Vim-

Vid/2

Vic

M2

LWC

IVV

LWC

IVV

IIIVVVV

ox

dtgs

ox

dtgs

TAILdd

gsimgsip

µµ2

21

1

21

21

22 +=+=

=+

−=−

2id

ox

TAILidox2d1dod V

LWC

I4VL

WC21III −=−=⇒

µµ


Large Signal Transfer Function (2)

2

21

21 ⎟⎟

⎠

⎞⎜⎜⎝

⎛−=−=⇒

OV

id

OV

id

TAIL

dd

TAIL

od

VV

VV

III

II

• We can turn this into a more elegant expression by using

2

21

2 OVoxTAIL V

LWCI µ=

where VOV is the quiescent point gate overdrive with Vid=0

• This equation predicts

– Iod/ITAIL = 0 when Vid=0, as expected

– Complete current steering (Iod/ITAIL=±1) takes place when Vid= ±VOV√2

138


Large Signal Plot

• Note that the equation on previous slide is only valid in the center of this transfer function (between saturation points)– Why?

Iod/ITAIL

⎝

2 1 0 1 2

1

0

1Slope = ITAIL/VOV

Vid/VOV-√2 √2


Observations

• Looks like something we have seen before

– A transfer function that is somewhat linear as long as Vid<<VOV

• For small signal analysis, we can find an equivalent transconductance by differentiation at the operating point

OV

TAIL

Vid

odm V

IdVdIG

id

===0

• Note that the transconductance of M1 and M2 is given by

OV

TAIL

OV

TAIL

OV

D,m V

IV

I

VIg === 2

2221

139


Does the Tail Node Move?

• Can show that

ITAIL

Id1

+Vip-

Id2

Vid/2+

Vim-

Vid/2

Vic

Vx

2

411 ⎟⎟

⎠

⎞⎜⎜⎝

⎛−−−=

OV

idOVticx V

VVVVV

• From this expression, we see that from a small signal perspective the tail node is pinned at Vic-Vt-VOV

– "AC ground"


Small Signal Equivalent

• Sufficient to work with half circuit!

– Can directly apply everything we've learned about single transistor stage

• Half circuit caveats

– Can not analyze nonlinearity using half circuits

– Assumes that M1 and M2 are identical

id1 id2

gmvid/2 Vx

-gmvid/2

iod/2

gmvid/2

iod

gmvid

idmddod vgiii =−= 21

140


Differential Voltage Amplifier Example


Short Channel Effects

• Can model short channel effects using long channels with source degeneration

ITAIL

Id1 Id2

Rsx Rsx

LWC

IVV

LWC

IVV

IIIRIVVRIVV

ox

dtgs

ox

dtgs

TAILdd

sxdgsimsxdgsip

µµ2

21

1

21

2211

22 +=+=

=+

−−=−−

mess... big⇒LV

gR

c

OV

msx ε

1=

141


Nonlinearity Comparison (1)

• Can look at this using Taylor expansions

• Without Rsx (long channel), we can show that

...VV

VV

II

OV

id

OV

id

TAIL

od −⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟⎠

⎞⎜⎜⎝

⎛≅

3

81

• With Rsx (short channel) this becomes

( ) ( ) ...VRg

VRgVRg

VII

OVsxm

id

sxmOVsxm

id

TAIL

od −⎟⎟⎠

⎞⎜⎜⎝

⎛⋅+⎟⎟

⎠

⎞⎜⎜⎝

⎛+

−⎟⎟⎠

⎞⎜⎜⎝

⎛⋅+

≅3

111

81

1

• Short channel differential pair is "more linear"

– But also has less gm at a given current

• For fairness, let's compare nonlinearity at same gm/ID


Nonlinearity Comparison (2)

• Recall that

OVsxmD

m

VRgIg 2

11

+≅

• Plugging this into the equations on the previous slide yields

...VIgV

Ig

II

idD

mid

D

m

TAIL

od −⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟⎠

⎞⎜⎜⎝

⎛≅

3

21

81

21

...VIg

RgV

Ig

II

idD

m

sxmid

D

m

TAIL

od −⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛+

−⎟⎟⎠

⎞⎜⎜⎝

⎛≅

3

21

11

81

21

Long Channel

Short Channel

• Minor win for short channel in terms of linearity

– In practice, this may be overshadowed by additional effects that are not captured in the simple degeneration model

142


"Linear Region" of Transfer Function

• In the long channel case, we found that for good linearity we need Vid<<VOV

• As we have seen from the derivation above, this requirement can be generalized to capture both long and short channel cases simultaneously

• A few approximate rules of thumb

⎟⎟⎠

⎞⎜⎜⎝

⎛<<

D

mid

Ig

V 2

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅<

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅<

D

mid

D

mid

Ig

.V

Ig

.V 220250

For ~1.5% nonlinearity error: For ~0.1% nonlinearity error:


Voltage Amplifier Transfer Functions

• In a differential amplifier, we primarily want to have large gain that links only the two differential variables

id

oddm v

vA =

• Unfortunately, circuit nonidealities will also cause nonzero "parasitic" gain terms

ic

occm v

vA =id

occmdm v

vA =−ic

oddmcm v

vA =−

See text 3.5.6.9

143


Common Mode Gain

• Ideally zero (RTAIL=∞)

• With finite RTAIL:

ic

occm v

vA =

[ ]( )TAILmoTAILm

mcm RgrR

RggA 21

21⋅+⋅

⋅+−=


Common Mode Rejection Ratio

• Figure of merit that quantifies ratio desired/undesired gain

– Ideally infinite

cm

dm

AACMRR =

• For our simple resistively loaded differential pair, this becomes (assuming R<<ro and ignoring body effect)

TAILm

TAILm

mm R2g1

RR2g1

gRgCMRR ⋅+=

⋅⋅+

⋅≅

• Other important figures of merit

dmcm

dm

AA

− cmdm

dm

AA

−

144


Power Supply Rejection Ratio

• In practice, "noise" on the supplies will also propagate to the output

– In a differential system usually due to (half-) circuit imbalance

• Define

dd

od

vvA =+

ss

od

vvA =−

++ = A

APSRR dm

−− = A

APSRR dm


Input Referred Interpretation

• E.g. 1mV input signal, 100mV supply noise

– Need PSRR >> 100 (40dB)

• PSRR can be a very critical issue in highly integrated, complex integrated circuits

– Lots of potential supply noise sources• E.g. cross-talk between analog and digital sections

Amplifier

VDD

vi or vidvo or vod

+PSRRvdd

−PSRRvss

145


Lecture 13Offset Voltage

Current Mirrors


[email protected]



Overview

• Reading

– 3.5.6.6, 3.5.6.7 (Input Offset Voltage)

– 4.1, 4.2 (Current Mirrors)

• References– M. Pelgrom et al., "Matching properties of MOS transistors," IEEE J. Solid-

State Circuits, Oct. 1989.

– P.G. Drennan et al., "Understanding MOSFET mismatch for analog design," IEEE J. Solid-State Circuits, March 2003.

• Introduction

– So far, we have worked with perfectly balanced differential pairs. In practice, there is always some imbalance due to matching errors between circuit elements. In this lecture, we will consider the input referred offset of a differential pair as an example. Following this discussion, we will take a closer look at practical implementations of current mirrors with emphasis on high swing biasing techniques.

146


Offset Voltage

• Defined as the input voltage one needs to apply to make the differential output of an amplifier equal to zero

• There is no offset in a perfectly balanced differential amplifier

• Two fundamentally different sources of offset

– Systematic• Due to an "imbalance by design"

• See e.g. lecture 22, OTA with single ended output

– Random• Due to mismatch between nominally identical devices


Resistor Mismatch

• Want large gm/ID to mitigate this error (low VOV)

⎟⎠⎞

⎜⎝⎛ ∆+⋅=

RRRIRI dd 121

D

d

D

d

D

d

d

d

II

II

II

II

RR ∆+≅∆−

∆+==∆+ 1

211

211

12

1

RRV

Ig

II

osD

m

D

d ∆≅≅∆

RR

IgV

D

mos

∆⎟⎟⎠

⎞⎜⎜⎝

⎛≅

−1

147


Current Factor Mismatch

LWCoxµβ =

( ) 22

21 ovov VV βββ ∆+=

ββ∆+=12

2

21

ov

ov

VV

ββ∆+≅+≅

2111

2

1

OV

os

ov

ov

VV

VV

ββ∆

⎟⎟⎠

⎞⎜⎜⎝

⎛≅

−1

D

mos I

gV


Threshold Mismatch

tttos VVVV ∆=−= 21

148


Complete Expression

• Experimental data shows that it is reasonable to model the errorterms as uncorrelated random variables

– Need to add up variances

⎥⎦

⎤⎢⎣

⎡ ∆+∆⎟⎟⎠

⎞⎜⎜⎝

⎛+∆≅

−

RR

IgVV

D

mtos β

β1

⎥⎥⎦

⎤

⎢⎢⎣

⎡+⎟⎟

⎠

⎞⎜⎜⎝

⎛+≅ ∆∆

−

∆22

22

RR

D

mVV I

gtos

σσσσββ

• The error standard deviations depend on device geometries

– Usually larger area means smaller offset


Pelgrom Coefficients

• In 0.35µm technology: AVt ≅ 7mV-µm, Aβ ≅ 1%-µm

– AVt tends to scale down with technology, roughly proportional to gate oxide thickness

– Aβ has remained roughly constant with scaling

• Example: W=50µm, L=0.35µm, gm/ID=10V-1, ∆R=0

WLA

WLA

t

t

VV

β

ββσσ == ∆∆

( ) ( ) ( ) ( ) mV.mV.mV..

%V.

mVosV 681240671

350501

101

350507 22

2

2

2

=+=⋅

+⋅

=σ

• Vt mismatch usually dominates Vos, especially in moderate and weak inversion (large gm/ID)

149


Current Mirror Bias

• Objectives

– Want accurate mirror ratio ITAIL/IREF

– Want large RTAIL (and small CTAIL) for good CMRR

– Want small Vmin to maximize common mode input range


Basic Sizing Considerations

• Always use L1=L2

• Make W1/W2 or W2/W1 integer

– Use unit devices connected in parallel

– "m-factor" in Spice• E.g. M1 d g s b W=10u L=0.35u m=5

150


Inaccuracy due to Offset

• Want small gm/ID ("large VOV") to mitigate errors due to random and systematic offset in VGS

– Unfortunately this means large Vmin

( )2121 ososm VVgIII +≅−=∆

( )21 ososD

m VVIg

II +≅∆


Inaccuracy due to ∆VDS

• Two options

– Use device with large ro (Large L)

– Make V1 as close as possible to V2

oo rV

rVVIII ∆=−≅−=∆ 21

21

VDS

ID

∆V

∆Islope=1/ro

151


Output Resistance

0 0.5 1 1.5 2 2.5 3 3.50

500

1000

1500

2000

2500

NMOS W/L=10, VGS

=800mV, L=0.35µm...0.7µm

VDS

[V]

r o [k Ω

]


Output Resistance Zoom

0 0.1 0.2 0.3 0.4 0.5 0.6 0.70

100

200

300

400

500

600

700

NMOS W/L=10, VGS

=800mV, L=0.35µm...0.7µm

VDS

[V]

r o [k Ω

]

≅2/(gm/ID) ≅ 4/(gm/ID)

152


Higher Rout

• A cascode can help create a higher output resistance, e.g. to improve CMRR in a differential pair

• Even though the impedance is now high at the current mirror output, we still need V1=V2 to minimize systematic errors in the current ratio I2/I1

2omout rgR ≅


Solution 1

• Works, but VOUTmin is very large

– Using long channel algebra, we have

( ) OVttOVtminOUT VVVVVV 22 +=−+≅

• Note that using long channel equations tends to be OK for current mirrors

– Usually operated in strong inversion

– Channel length often not minimum

153


Solution 2

• Use some kind of "magic battery" that sets the cascode gate potential such that VOUTmin = 2VOV (minimum possible)

• "High swing" bias


Magic Battery 1

• Gate overdrive of ¼ device is twice as large as VOV of all other devices

– Vcas=Vt+2VOV

– VOUTmin = 2VOV

• Sensitive to body effect

154


Magic Battery 2

• Less sensitive to body effect

• Stacked device mimics transistor with length 4L

– May not match characteristics of devices with length L all that well


Magic Battery 3

• Insensitive to body effect

• (1/3) triode device will not exactly produce VOV

– Typically make device ~1/5 of W, to allow for safety margins and improved Rout

[ ] OVxxx

ttOVxoxOVox VVVVVVVVLWCV

LWCI =⇒⋅⎟

⎠⎞

⎜⎝⎛ −−++=≅

231

21 2

1 µµ

155


Magic Battery 4

• No extra current branch

• Needs lots of headroom on input side

• Sensitive to body effect


Magic Battery 5

• The previous circuits assumed that Lmirror=Lcascode

– Sometimes want Lmirror≠Lcascode

• The above circuit makes Vcas =Vt2 + VOV2 + VOV1

– VOUTmin becomes VOV2 + VOV1, as desired

I2I1

W1/L1 W1/L1

VcasW2/L2

W2/L2

I1

(2/3)*W1/L1

W1/L1

Vx

I1

W2/L2

156


Design Considerations

• In all of the above-discussed circuits, care must be taken to keep the devices forward active with sufficient safety margin, and not to "waste" too much ro

– Typically use ~1/6 in 1/4 size device approach (slide 18)

– Typically use ~1/5 in 1/3 triode device approach (slides 20-22)

• Work with integer ratios and unit devices as much as possible

– Using a 1/5 device really means that we work with a unit device of size 1, and use 5 of them elsewhere

• Keep mirror ratio (I2/I1) reasonably small

– Typically no larger than 10…20


Capacitive Coupling

• Can use decoupling capacitors to reduce the amplitude of noise coupling into bias nodes

• If noise is "deterministic" and occurs at the right point in time, you might be better off not decoupling, but making the bias node"fast" so it can recover quickly!

Vx

Low cap:fast recovery

High cap:slow recovery

big bounce

small bounce

t

t

Vx

157


Current Distribution

• Typically, we'll only have one single reference current generator on a chip

• Can generate/distribute currents across chip in two different ways

– Distribute gate voltage• Can cause big problems due to IR drop

• Usually limited to local distribution

– Distribute currents• Have one global bias cell close to reference that sends currents

into local biasing sub-circuits

• Disadvantage: Consumes additional current

158


Lecture 14Process Variations

Feedback


[email protected]



Overview

• Reading

– 8.0, 8.1, 8.2, 8.3 (Feedback)

– 9.2 (Relation Between Gain and Bandwidth)

– Supplementary Handout "Feedback Systems" by Tom Lee (see web, optional)

• Introduction

– In today's lecture we will first take a look at typical component variations in CMOS technology. In light of these numbers, we then consider negative feedback as a tool for building amplifiers with precisely defined gain. As we shall see, using a forward amplifier with "high", but arbitrary gain, combined with a ratiometric, passive feedback network allows us to build drift and process insensitive precision gain stages.

159


PVT

• So far, we've assumed that our Spice model accurately predicts the performance of every single chip we make

• We have also assumed that all our circuits run at room temperature, and VDD is precisely fixed

• In practice, it is the circuit designer's job to ensure that thecircuit works in presence of large variations

– PROCESS: Variations among production lots• "Slow, Nominal and Fast" corners• Sometimes there are even significant variations across wafers

and individual chips

– VOLTAGE: VDD is usually specified only within ±10%• E.g. VDD= 2.7…3.3V in our technology

– TEMPERATURE: Ambient temperature variations• 0…70°C (or -40…125°C)


Graphical Interpretation

[Razavi, p. 599]

160


Typical Variations

Parameter Lot-to-LotTemperature Coefficient

Device Matching (Area Dependent)

Vt ±100mV -2mV/°C ~1…10mV

µCox ±20% -0.33%/°C ±0.2%

Rpoly2 (50Ω/square) ±20% 0.2%/°C ±0.1%

Rnwell (1k Ω /square) ±40% 1%/°C ±1%

Cpoly-poly2 ±15% -30ppm/°C ±0.1%


Consequences

• Performance metrics that depend on absolute component values will show large variations

• Sometimes this is OK

– E.g. bandwidth of a circuit• Can overdesign, and make sure to have minimum required

bandwidth in presence of worst case variations

• Sometimes this is not OK

– E.g. need a precise gain of two in an A/D converter• gmRL or gmro will never be accurate enough

• Solution: Use negative feedback to desensitize the circuit to gmRL or gmro variations

161


Negative Feedback

• Harold S. Black, 1927

( )outinout fvvav −=

afa

vv

in

out

+=

1

• Interesting case:

fvvaf

in

out 11 ≅⇒>>


Interpretation

• As long as we have "large" gain in the forward path a, the overall gain will depend only on f

• Since vout/vin ~1/f, we often make f ≤ 1

– E.g. for a "closed loop" gain of two, we need f=0.5

• f ≤ 1 is easy to implement, and ratiometric!

– A "wire" (f=1) or resistive or capacitive voltage divider

1≅in

out

vv

1

21

RRR

vv

in

out +≅

162


Example

• Case 2: a=1000

5021 .fRR =⇒=

• Case 1: a=100

.....f

avv

in

out 96078150

1001

11

1 =+

=+

=

.....f

avv

in

out 996007150

10001

11

1 =+

=+

=

• 10x variation in forward gain, and only about 1.8% change in closed loop gain!


Gain Sensitivity

• Defineaf

aA+

=1

• Can show that

Taa

afaa

AA

+

∆

=+

∆

=∆11

• Fractional change in gain is reduced by product of a and f, which can be made arbitrarily large (conceptually)

– Loop gain T

• We will find that loop gain is a very meaningful parameter that will also appear in bandwidth and impedance calculations

– More later…

163


Effect of Negative Feedback on Nonlinearity

• Substitute (2) into (1), then compare coefficients to get

( ) ( ) ( )( ) 3

31

331

2

1

inin

!

out

outinoutinout

vbvbv

fvvafvvav

+=

−+−=

( )41

33

1

11 11 fa

abfa

ab+

=+

=

• Linear term as expected, reduced by (1+T)

• Cubic term reduced by (1+T)4!


Negative Feedback and Bandwidth

• Closed loop transfer function:

1

0

1ps

a)s(a.g.E−

=

fapsfa

af)s(a

)s(a)s(A

01

0

0

111

111

+−

⋅+

=+

=

• Bandwidth increases by (1+T)!

– But gain is reduced by (1+T)

• Product of gain and bandwidth remains constant

164


Bode Plot Illustration


Early Obstacles

• Today we are taking the concept of negative feedback for granted

• At the time of his "invention," Harold Black had a hard time convincing his colleagues that negative feedback was indeed something useful

– It was very hard to make a "high gain" forward amplifier using vacuum tubes

– Why have large gain and then throw it away by applying negative feedback?

• Long before negative feedback had been deemed useful, positive feedback was routinely applied to increase the gain of amplifiers

165


Positive Feedback

• Edwin H. Armstrong, 1915

( )outinout fvvav +=

afa

vv

in

out

−=

1

• Examplea

.a

vv.af

in

out 10901

90 =−

=⇒=

• Tenfold increase in gain!


Feedback Using Ideal OpAmp

21

1

RRRf+

=

( )−+ −⋅= vvgvout

1

21

21

111 RRR

RRRg

gaf

avv

in

out +≅

++

=+

=

ga =

166


Inverting Configuration

• Circuit does not map directly into generic block diagram

– Cannot directly identify a and f

– a ≠ g

?f =

( )−+ −⋅= vvgvout

?a =


Superposition

a⇒

af−⇒

167


Inverting Configuration

gRR

Ra ⋅+

−=21

2

gRR

Raf ⋅+

−=−21

1


Result

2

1

21

2

21

1

RR

gRR

R

gRR

R

aaff −=

⋅+

−

⋅+==g

RRRa ⋅+

−=21

2

1

2

1 RR

afa

vv

in

out −≅+

=

• It can be quite tedious to try and morph arbitrary circuits into a generic "af" block diagram

– Especially when impedances come into play

• Elegant alternative: "Return Ratio Analysis"

– More later…

168


Lecture 15Fully Differential OpAmps and OTAs


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Overview

• Reading

– 6.0, 6.1.1, 6.1.2, 6.1.2 (Basic Feedback Concepts)

– 12.1, 12.2, 12.3, 12.4 (Fully Differential OpAmps)

– 6.1.7 (Internal Amplifiers)

• Introduction

– Having discussed the basic properties of ideal feedback loops, we will now take steps toward a practical implementation of feedback amplifiers in CMOS technology. The first amplifier we consider uses a very crude gain stage, composed of a simple differential pair and an active current mirror load. For the time being, we will use this crude topology as a vehicle to gain insight into terminology, analysis and design tradeoffs, before moving to more complicated circuits in future lectures.

169


A Crude "High-Gain" Amplifier

• Output common mode not well defined

– Depends on mismatch in currents between top and bottom current mirror


Common Mode Feedback

• Feedback loop forces Voc=Voc,desired by adjusting tail current

170


Fully Differential vs. Single Ended (1)

• Symmetrical

– Helps mitigate parasitic coupling

– Good PSRR

– Easy to analyze

• Twice as much output swing compared to single ended

• Lower complexity

– No CMFB

– Fewer feedback components

• Can build non-inverting unity gain buffer without using any feedback components


Fully Differential vs. Single Ended (2)

• Most precision analog integrated circuits are based on fully differential stages

– Data converters, filters, etc.

• In contrast, printed circuit board circuits tend to be single ended

– Want minimum complexity and component count

• In EE214, we will study mostly fully differential circuits

– More to come in EE315

• In all of the upcoming assignments, we will use a very simple, ideal common mode feedback circuit to avoid distraction from the main design task

– Practical CMFB implementation examples will follow later in this course

171


Differential Mode Small Signal Half Circuit


Load Considerations

• Low load resistance will destroy the gain of our amplifier

– RL may may be an explicit load or due to parasitic loading from feedback network

• Need large gain in feedback loop for good precision

172


Solution 1: Buffer

• Can be very difficult to build

• Can cost lots of headroom

• Additional area, power


Solution 2: Capacitive Feedback

• Loads amplifier only at high frequencies, DC gain unaffected

• Issue: Charge initialization on caps

– Sometimes possible to use large resistors in parallel

173


Switched Capacitor Circuits (1)

During φ1 During φ2


Switched Capacitor Circuits (2)

• In switched capacitor (SC) circuits, the charge initialization problem is taken care of

– One phase for charge initialization, a second phase for amplification

• Predominant approach for precision signal processing in CMOS integrated circuits

• SC circuits tend to look very complicated, but always boil down to same design problem

– Build a good amplifier with capacitive feedback network

• More applications in EE315, in EE214 we'll just design the circuit during φ2, without worrying about the switches

174


OpAmps versus OTAs (1)

Operational Amplifier Operational Transconductance Amplifier


OpAmps versus OTAs (2)

OpAmp

• "General Purpose"

• Ideally a voltage controlled voltage source

• Low output impedance

• Can drive resistive and capacitive loads

• Essentially OTA + buffer

• Buffer increases complexity and power dissipation

OTA

• Most on-chip amplifiers are OTAs

• Ideally a voltage controlled current source

• High output impedance

• Cannot drive resistive loads

• Use capacitive (switched capacitor) feedback

175


OTA Gain Bandwidth Product

• GBW is independent of Ro

• Note that CLtot is the sum of all capacitors seen by the output– Including junction caps, etc.

Ltotoom

id

od

CsRRG

vv

+−=

11

Ltot

m

Loom C

GCR

RGGBWππ 211

21 =⋅=


OTA Unity Gain Frequency (1)

( )

1

0

11ps

aCsRRG

vvsa

Ltoto

om

id

od

−=

+−==

1pff

( )sa

0a

11

1

0!

p

u

ffj

a =−

uf

1101 =⇒>>

u

ppu f

faff

Ltot

mpu C

GGBWfafπ21

10 ==≅⇒

176


OTA Unity Gain Frequency (2)

• The above result holds to good precision when

– There is no second pole before or close to fu– |ao| is large, which implies fu>>fp1

• Important consequence

– No need to include large resistors (such as Ro) for analysis of circuit behavior around fu

1pff

( )sa

0a

uf

∞=oR With

177


Lecture 16

StabilityAnalysis of Feedback Circuits


[email protected]



Overview

• Reading

– 9.3 (Stability)

– 8.8 (Return Ratio Analysis)

– Supplementary Handout "Feedback Systems" by Tom Lee (see web, optional)

• Introduction

– This lecture covers basics on the analysis of feedback amplifiers. Using a simple OTA with capacitive feedback as an example, we will study the so called "Return Ratio" method as a tool to assess stability and calculate the bandwidth of feedback amplifiers. Interestingly, most relevant performance metrics follow directly from the "return ratio" or loop gain of the circuit, which highlights the significance of this parameter in feedback system design.

178


Stability

• Most general criterion: BIBO

– Bounded input – bounded output

– Applies to any system

• A continuous time linear system is BIBO stable if all its poles are in the left half of the s-plane

– Can calculate roots of 1+T(s) to check stability• Tedious and hard to do in general

)s(T)s(a

)s(f)s(a)s(a

vv)s(A

i

o

+=

+==

11


Methods for Checking Stability

• Nyquist Criterion

– Based on evaluating T(s) in a polar plot

– Works for arbitrary T(s)• Even if T(s) itself is unstable

– See books on control theory for details

• Bode Criterion

– A subset of the general Nyquist criterion that can be applied when T(s) itself is stable

• Safe to use in most electronic circuits

• Beware of exceptions

– System is unstable when |T(jω)| > 1 at the frequency where Phase(T(jω)) = -180°

– Can use simple bode plot to check for stability

179


Stability Measures

ωc

ω180

ωc

ω180

|T(jω)|

Phase[T(jω)]

( )[ ] cjTPhasePM ωωω =−°=180

( )180

1

ωωω

=

=jT

GM

Typically want GM ≥ 3…5

Typically want PM ≥ 60…70°


Closed Loop Peaking

ω/ωc

[Text, p.632]

Closed-loop gain, normalized to 1/f

180


OTA with Capacitive Feedback

• Important questions

– Is this circuit stable? What is its phase margin?

– What is the low frequency closed loop gain?

– What is the closed loop bandwidth?


Example: Simple Single Stage OTA

• Issues– Feedback network loads amplifier– Amplifier loads feedback network– At high frequencies, there exists a (capacitive) feedforward

path that overrides the amplifier• Cannot be modeled using the above generic feedback block

diagram

?

181


Solutions

• If all we needed was the closed loop transfer function, we couldsimply do a KCL/KVL based analysis

– Can be quite tedious, especially for more complex circuits

– Hard to assess stability and stability margin

• Two port feedback analysis

– "Shunt-series, shunt-shunt, series-shunt, series-series" feedback configurations

• See text, sections 8.4, 8.5, 8.6

– Attempts to identify amplifier (a) and feedback network (f) with loading effects included

– Some feedback circuits cannot be modeled using two-ports• E.g. bias circuits that use feedback tend to have only one port


Return Ratio Analysis (1)

• Does not attempt to identify forward gain and feedback network transfer functions separately

• Analysis entirely based on looking at gain around feedback loop

– Return ratio, loop gain, a·f, loop transmission• Different terminology for the same thing

• From the loop gain of a circuit, we can determine

– Stability, closed loop gain characteristics, node impedances

• Analysis can be applied to arbitrary feedback circuits, independent of topology, port structure, etc.

• We will first look at the complete framework of this technique

– Then identify a way to partition the analysis for our needs and reduce its algebraic overhead

182


Return Ratio Analysis (2)

1. Set all independent sources to zero

2. Break the feedback loop by disconnecting a controlled source in the feedback loop

• E.g. VCCS, VCVS, …

3. Inject a test signal st at the breakpoint

• Current or voltage, depending on type of removed source

4. Find the return signal sr generated by the dependent source that was disconnected from the circuit in step 2.

5. The return ratio (loop gain) of the circuit is given by T=–sr/st

• The text uses the symbol R , we will use T for simplicity and to acknowledge that this quantity is the same as T=af in the ideal feedback block diagram


Example

ox vv ⋅= β

xsf

f

CCCC

++=β

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅−=

tott sC

Riv 100

( ) fLtot CCC β−+= 1

( ) ( )[ ]fLom

totm

t

r

CCsRRG

sCRG

iisT

βββ

−++⋅⋅=⎟⎟

⎠

⎞⎜⎜⎝

⎛⋅⋅=−=

1111

00

183


Return Factor

• In literature, β is often called "feedback factor"

– We will call it "return factor" to avoid confusion with f of thegeneric feedback block diagram

( ) ( )[ ]fLom CCsR

RGsTβ

β−++

⋅⋅=11

10

Feedback loadingCapacitive feedback divider, includes amplifier input

capacitance Cx

xsf

f

CCCC

++=β


Phase Margin

pωω

( )ωjT

0T

cω

omRGT ⋅= β0

( )[ ]fLop CCR β

ω−+

=11

( ) fL

mc CC

Gβ

βω−+

≅1

1>>≅ omp

c RGβωω( )[ ]ωjTPhase

°0

°− 45

°−90

ωpω

( )[ ] °−≅⎟⎟⎠

⎞⎜⎜⎝

⎛−= −

=901

p

cc

tanjTPhaseωωω ωω

°≅°−°≅ 9090180PM

184


Closed Loop Bandwidth

• From lecture 14, we know that the bandwidth of the closed loop amplifier is given by

( ) 003 1 TT ppdB ωωω ≅+=−

( )[ ]fLo

omdB CCR

RGβ

βω−+

≅− 13

( )[ ] cfL

mdB CC

G ωβ

βω ≅−+

≅− 13

• Closed loop bandwidth is equal to the unity gain (crossover) frequency of |T(jω)|


Remaining Questions

• What is the low frequency closed loop gain of the amplifier?

• How does capacitive feedforward at high frequencies affect the closed loop transfer function?

• Both of these questions could be answered by deriving the closed loop transfer function from first principles (KVL/KCL)

• Alternatively, it is possible to calculate the complete closed loop transfer function based on T(s)

( ))s(T

d)s(T

)s(TAvvsA

i

o

++

+== ∞ 11

• A∞ is the closed loop gain with ideal feedback (Gm→∞)

• d is the direct signal feedthrough with the controlled source removed (Gm→0)

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=af

aff

A :y similaritNote1

1

185


Comparison

• Two-Port Analysis

• a, f

• 1/f

• Return Ratio Analysis

• T

• A∞

T1d

T1TAA

++

+= ∞af1

aff1A

+=

(feedforward effects are not modeled)


Finding A∞

• With infinite Gm, vx must be zero, and there is no current though Cx

fosi sCvsCv +=0

f

s

CCA −=∞

186


Finding d

• Writing a general expression for d will be quite messy

• Better to distinguish the two cases of interest

– Low frequency (Ro<<|1/jωC|)

– High Frequency (Ro>>|1/jωC|)


High Frequency Result

• Pole as expected

• Zero at Gm/Cf, typically a very high frequency

– Far beyond ω-3dB if CL is large

• In most cases, calculating feedforward zeros is easier using simple KCL analysis, with large resistors removed

)s(Td

)s(T)s(TA)s(A

++

+= ∞ 11

( ) ( )[ ]m

fL

m

f

f

s

GCCs

GsC

CCsA

ββ−+

+

−−= 1

1

1

187


Low Frequency Result

• No feedforward, capacitors are open circuits

• Define static gain error

0

0

0

00 11 T

dT

TAA+

++

= ∞

0

000 1

0T

TCCAd

f

s

+−=⇒=

∞

∞ −=A

AA 0ε ⎟⎟⎠

⎞⎜⎜⎝

⎛−−≅

+−=

+−=−=

∞ 0

0

0

00 11111

111

11T

TT

TAAε

0

1T

≅ε


Summary – OTA with Capacitive Feedback

• To find the static gain error– Write an expression for the low frequency loop gain, neglect

all impedances due to capacitors– Note that capacitive voltage dividers still work at low

frequency!

• To find the closed loop bandwidth– Write an expression for the high frequency loop gain, neglect

finite output resistance of all devices– The 3-dB bandwidth of the closed loop circuit is

(approximately) equal to the unity gain frequency of T(jω)

• To assess stability and phase margin– Determine phase of (high-frequency) T(jω) at its unity gain

frequency• Boring for single pole systems, more interesting if two or more

poles are involved…

188


Lecture 17Loop Gain Simulation


[email protected]



Overview

• Introduction

– Last lecture, we've seen that return ratio analysis is a useful tool for characterizing feedback amplifiers in terms of stability, bandwidth and static precision. Since we are always interested in verifying our hand analysis results using simulations, it is desirable to have an equivalent method available in Spice. In this lecture, we will discuss the so called Middlebrook method for loop gain simulation. This particular approach helps overcome the issue that ideal loop breakpoints, e.g. at controlled sources, are not directly accessible in Spice.

189


References

• H.W. Bode, Network Analysis and Feedback Amplifier Design, Van Nostrand, New York, 1945.

• R.D. Middlebrook, "Measurement of Loop Gain in Feedback Systems," Int. J. Electronics, Vol. 38, No.4, .pp. 485-512, 1975.

• S. Rosenstark, "Loop Gain Measurement in Feedback Amplifiers," Int. J. Electronics, Vol. 57, No.3., pp. 415-421, 1984.

• P.J. Hurst, "Exact Simulation of Feedback Circuit Parameters," Trans. on Circuits and Systems, pp.1382-1389, Nov. 1991.

• P.J. Hurst, S.H. Lewis, "Simulation of Return Ratio in Fully Differential Feedback Circuits," Proc. CICC 1994, pp.29-32.

• Ken Kundert, "A Test Bench for Differential Circuits," Online: http://www.designers-guide.com/Analysis/diff.pdf


Circuit Example 1

• What is the loop gain in this circuit?

190


Return Ratio Analysis

• As we've seen last lecture, such a hand calculation is pretty straightforward

• How can we simulate T(jω) in Spice?– Using "real" transistor models

( )t

r

iisT −=


Spice MOSFET AC Simulation Model

• Nodes of ideal controlled source are not accesible!

– Cannot break loop at gm generator

191


Popular Simulation Approach

• Inaccurate

• Hard to estimate mock load

• May get different results for different breakpoints

• Ideally, we'd like to avoid all of the above issues

• Solution: Middlebrook method

( )t

r

vvjT −≅ω


Problem Generalization

• Middlebrook argued that any single single loop feedback circuit can be partitioned as shown below

• Hence, there is always some "nonideal" breakpoint between impedances– How can we use this breakpoint to find the loop gain?

available breakpoint

21

21

ZZZZg)s(T m +⋅=

192


Double Injection Trick

• No “DC“ break in the loop, all loading effects included!

• Measure Tv and Ti separately, then calculate actual T

1

22 Z

ZZgTvv

mvx

y +⋅=≡−

2

11 Z

ZZgTii

mix

y +⋅=≡

21

21

ZZZZgT m +

⋅=True Loop Gain:

Solving yields:

21++−=iv

iv

TTTTT

iv T11

T11

T11

++

+=

+


Simulation Example

• Two options

– Run two copies of the same circuit simultaneously, or

– Run two simulations with different stimuli

x

yv v

vT −=

x

yi i

iT =

193


Spice Code

.param ai=1 av=0

m1 vo x 0 0 nch214 L=0.35u W=10u

i1 0 vo 100u

cf vo y 200f

rf vo y 100gig

cs y 0 400f

xt x y looptest ai='ai' av='av'

.op

.ac dec 10 1e3 10e9

.options post brief


.include utils.sp

.alter

.param ai=0 av=1

.end

* utils.sp

.subckt looptest x y ai=0 av=0

vx middle x dc 0

vy middle y ac 'av'

it 0 middle ac 'ai'

.ends looptest


Matlab Postprocessing

% load signals from first run and calculate Ti

m = loadsig('middlebrook1.ac0');

ti = evalsig(m, 'I_xt_vy')./evalsig(m, 'I_xt_vx')

% load signals from second run and calculate Tv

m = loadsig('middlebrook1.ac1');

tv = -evalsig(m, 'y')./evalsig(m, 'x')

f = 1e-6*evalsig(m, 'HERTZ');

% calculate loop gain

t = (tv.*ti-1)./(2+tv+ti)

% calculate magnitude, phase and plot

% ...

194


Simulation Result

10-2

10-1

100

101

102

103

104

-40

-20

0

20

40

f [MHz]

Ma

gn

itud

e [d

B]

10-2

10-1

100

101

102

103

104

-100

-50

0

f [MHz]

Ph

ase

[de

gre

es]

TvTiT

TvTiT


How to do this in Awaves?

• Generally much more tedious, but some shortcuts make it possible to do this

– Remember that 1/(1+T) = 1/(1+Tv) + 1/(1+Ti)

– Plugging in voltages & currents for Tv and Ti, this becomes 1/(1+T) = vx/(vx-vy) + ix/(ix+iy)

– With unity test voltage and current, this simplifies to1/(1+T) = vx/1V + ix/1A

– Probe real and imaginary parts of vx and ix in HSpice using• .probe ac vxreal = par('vr(x)')

• .probe ac vximag = par('vi(x)')

• .probe ac ixreal = par('ir(xt.vx)')

• .probe ac iximag = par('ii(xt.vx)')

• Can now create expressions for phase and magnitude of T and plot using real and imaginary components of vx and ix

195


Circuit Example 2

Cs

+vid-

+vod-

Cs

Cf

Cf

CL

CL


Fully Differential Testbench

xmxp

ymypv vv

vvT

−−

−=xmxp

ymypi ii

iiT

−−

=

196


Differential Looptest Circuit

.subckt difflooptest xp xm yp ym ai=0 av=0

vxp middlep xp dc 0

vyp middlep yp ac 'av'

vxm middlem xm ac 'av'

vym middlem ym dc 0

it middlem middlep ac 'ai'

.ends difflooptest


Simulation Result

10-2

10-1

100

101

102

103

104

-40

-20

0

20

40

f [MHz]

Ma

gn

itud

e [d

B]

10-2

10-1

100

101

102

103

104

-100

-50

0

f [MHz]

Ph

ase

[de

gre

es]

TvTiT

TvTiT

197


Alternative Approach

• Use baluns to convert differential signals into CM/DM components and use simple single ended loop test circuit

• The above setup is particularly for use with Spectre simulator– Spectre has built-in Middlebrook analysis, called "stb"– Simply replace looptest block with "iprobe" element– Spectre automatically finds and plots T, no post-processing

needed


xfmr

xfmr

Ideal Balun

• Useful for separating CM and DM signal components

• Bi-directional, preserves port impedance

• Uses ideal, inductorless transformers that work down to DC

• Not available in all simulators (e.g. not available in LTSpice)

= .subckt balun vdm vcm vp vm

e1 vp vcm transformer vdm 0 2

e2 vcm vm transformer vdm 0 2

.ends balun

198


+ New Middlebrook Method

• Recently, Middlebrook came up with an alternative way of looking at feedback circuits

– A more "design oriented analysis"

• He titled this approach "The General Feedback Theorem – A final solution for feedback systems"

• If you are curious about this new method, please refer to

– http://rdmiddlebrook.com

– http://ardem.com/free_downloads.asp


Multi Loop Considerations

• Any practical feedback circuit has multiple feedback loops

– Fully differential circuits have CM/DM loops

– Local device feedback through Cgd, Rsource

– ...

• Solutions

– Decompose fully differential circuit into CM/DM loops

– If a local feedback loop can be modeled as a combination of a stable controlled source and passive impedances, the multi-loop circuit reduces to a single loop [Hurst 94]

– If there is a common breakpoint that breaks all feedback loops simultaneosly, stability can be checked by finding the return ratio at the single breakpoint [Hurst 94]

199


Last Resort: General Nyquist Criterion

[Bode 45]:

“If a circuit is stable when all its tubes have their nominal gains, the total number of clockwise and counterclockwise encirclements of the critical point must be equal to each other in the series of Nyquist diagrams for the individual tubes obtained by beginning with all tubes dead and restoring the tubes successively in any order to their nominal gains“

[You may want to take a controls class if you are interested in this...]


[Bode 45]:

“... thus the circuit may sing when the tubes begin to lose their gain because of age, and it may also sing, instead of behaving as it should, when the gain increases from zero as power is supplied to the circuit...“

Another Useful Quote

Always run one or more transient analyses for a "true" stability check!

200


Lecture 18Differential Mode Voltage Range

Two-Stage OTA


[email protected]



Overview

• Reading

– 6.3 (Basic Two-Stage MOS Amplifiers)

– 12.6.1 (Fully Differential Two-Stage-Amplifier)

– 12.6.5 (Neutralization)

• Introduction

– As we will see in today's lecture, the available output swing and open-loop gain of our simple single stage OTA are fairly limited. Hence, we will begin to consider a two-stage OTA architecture as an alternative. Unfortunately, with the addition of a second stage, we also introduce a second pole, which makes it difficult to achieve reasonable phase margin. The compensation techniques discussed in the following lecture will provide solutions to this problem.

201


Output Swing of Simple OTA

• Available output swing depends on input and output common mode levels

• May be limited by headroom for differential pair device (Vminn) or active load (Vminp)


Maximum Available Swing

• Input and output common mode adjusted such that all devices operate at "edge" of forward active region

– Well defined using long channel model, very gradual transition in short channels

• Unfortunately, the choice of Vic and Voc are often dictated by the circuits that interface with the amplifier

– E.g. Vic=Voc=1.5V( )tminnminpminDDmax,odpp VVVVV −−−= 2

202


Example Vic=Voc=VDD/2

• Assuming that we are limited by Vminn, and Vminn~VOV, the available differential peak-to-peak swing is ~4Vt

• Since the transition to triode is smooth, which criterion shouldwe use find the "exact" output range of an amplifier?


Gain vs. Output Swing DC Simulation

• In EE214, we arbitrarily define output range as the peak-to-peak swing that causes no more than 30% drop in Vod/Vid

-1.5 -1 -0.5 0 0.5 1 1.540

50

60

70

80

90

Vod

[V]

Vod

/Vid

[V/V

]

-30%

Vodpp,max

203


How Much Gain Can We Get?

• Small signal gain (around Vid=Vod=0):

vop

von

mn

mpvon

op

onvon

opon

oponmnvo

aa

gga

rra

rrrr

ga+

=+

=+⋅

⋅=1

1

1

1

( )( ) vop

von

nDm

pDmvonvo

aa

I/gI/gaa

+=

1

1

vonvonvo a||aa = ( ) ( )nDmpDm I/gI/g for =

• E.g. avon=avop=50, (gm/ID)n= (gm/ID)p ⇒ avo=25

• Static gain error ~1/To ~1/avo ~1/25=4%

– Not precise enough for many applications


Two-Stage Amplifier

• More output swing, more gain ~(gmro/2)2

• Output range no longer depends on input common mode

204



• Same as for single stage OTA!

• Common mode of first stage output is set via VGS of common source device in second stage


Simplified AC Half Circuit with Feedback

( ) ( ) ( ) ( )sasasa

ps

ps

RgRgsT mm ⋅=⋅=

⎟⎟⎠

⎞⎜⎜⎝

⎛−⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛−

⋅= βββ 21

21

2211

11 111

1CR

p −=22

21CR

p −=

205


How About Miller Effect?

• Two ways to deal with Miller amplification of Cgd in first stage– Use cascodes

• Often needed for high gain, anyways

– Use "neutralization caps"• See text, section 12.6.5


Bode Plot of Loop Gain

• If ωp1 and ωp2 are close to each other, the loop will essentially have no phase margin!

ω

1pω

°0

°−90

°−180 ω

2pω

( )ωjMag

( )ωjPhase

( )sa1

( )sa⋅β

( )sa2

( )sa⋅β

206


Introducing a Dominant Pole

• The problem is solved if we somehow manage to make ωp1<< ωp2

– Or ωp2<< ωp1

• Loop behaves close first order system around crossover frequency

ω

1pω

°0

°−90

°−180 ω

2pω

( )ωjMag

( )[ ]ωjTPhase

( )sa1

( )sa⋅β

( )sa2

cω


Phase Margin

• At the crossover frequency, the dominant pole has shifted the phase by about -90°

• The non-dominant pole's phase at ωc is given by -tan-1(ωc/ωp2)

⎟⎟⎠

⎞⎜⎜⎝

⎛−°−°≅ −

2

190180p

ctanPMωω

⎟⎟⎠

⎞⎜⎜⎝

⎛≅ −

c

ptanPMωω 21

ωp2/ωc PM

1 45°2 63°3 72°4 76°5 79°

207


Creating a Dominant Pole

• Numerical example:

mSGG mm 121 == Ω== kRR 10021 pFC 12 =

MHz.CR

f p 612

1

222 ==

π

°= 72PM

kHzf

f pc 530

32 == Hz

RGRGff

mm

cp 106

22111 =

⋅⋅=β

50.=β

nFRf

Cp

152

1

111 =

⋅⋅=

π

• Two issues

– Very low fc, which means low closed loop bandwidth

– Huge capacitor• Get roughly 1fF/µm2 in CMOS technology

• C1 would occupy about 4mm x 4mm !


Utilizing the Miller Effect

• Purposely connect an additional capacitor between gate and drain of M2 (Cc = "Compensation capacitor")

• Two interesting things happen

– Low frequency input capacitance of second stage becomes large – exactly what we need for low ωp1

– At high frequencies, Cc turns M2 into a diode connected device – low impedance, i.e. large ωp2 !

208


Pole Splitting

• More analysis next lecture…

c

209


Lecture 19Compensation

Noise in Feedback OTAs


[email protected]



Overview

• Reading

– 9.4.1, 9.4.2, 9.4.3 (Compensation)

• Introduction

– In this lecture, we will continue to look at pole splitting as amethod for achieving sufficient phase margin in a two-stage amplifier. While using a Miller capacitance for compensation helps move the non-dominant pole to higher frequency, it also introduces an undesired zero in the transfer function. Today, we'll discuss several options on how to cope with this artifact.

– In addition, we will derive useful expressions for the total integrated noise in OTAs.

210


Two-Stage OTA with Cc

• Detailed analysis shows:

( ) ( ) ( )[ ] ( )1c2c21212

c122m1c12c2

2m

c22m11m

i

o

CCCCCCRRsCRRgRCCRCCs1gCs1RgRg

vvsa

++++++++

⎟⎟⎠

⎞⎜⎜⎝

⎛−⋅⋅

==

• Very messy…


Dominant Pole Approximation

• We can write the denominator as

( )21

2

2121

11111pp

spp

sps

pssD +⎟⎟

⎠

⎞⎜⎜⎝

⎛+−=⎟⎟

⎠

⎞⎜⎜⎝

⎛−⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛−=

• Since in a practical design outcome we'll have |p1|<<|p2|, we can approximate

( )21

2

1

11pp

sp

ssD +⎟⎟⎠

⎞⎜⎜⎝

⎛−≅

• With this simplification, we can now easily identify p1 and p2 by comparing the coefficients with the expression from the previousslide

211


Final Result

• Questions

– How can we design an amplifier with these complex expressions?

– What will the zero in the transfer function do to us?

( )⎟⎟⎠

⎞⎜⎜⎝

⎛−⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛−

⎟⎠⎞

⎜⎝⎛ −

⋅≅

21

0

11

1

ps

ps

zs

asa v

c

m

Cgz 2+=

( ) ( ) cmcmcc CRRgCRRgCCRCCRp

12212222111

11 −≅++++

−≅

2121

22

CCCCC

gp

c

m

++−≅


RHP vs. LHP Zero

Phase

°0

°− 45

°−90

ωzω

zω zω−

Phase

°0

°+ 45

°+ 90ωzω

212


OTA Transfer Function with RHP Zero

• RHP zero will reduce phase margin

– Unless gm2 >> βgm1

c

mc C

g 1βω ≅

c

mz C

g 2=ω

1

21

m

m

c

z

gg

βωω =

ωz

(assuming zero is beyond crossover)


Mitigating the Impact of RHP Zero

• Create unilateral feedback through Cc

– Source follower

– Cascode compensation• Ahuja, IEEE J. Solid-State Ckts., 12/1983

• Ribner, IEEE J. Solid-State Ckts., 12/1984

• "Nulling resistor"

– Push zero to infinity

– Push zero into LHP and cancel nondominant pole (!)

213


Source Follower

• Mitigates feedforward path issue

• Problems: Reduced output swing, additional power dissipation


Cascode Compensation (1)

• Cc sees low impedance, output of first stage sees high impedance looking into cascode device

– Reduced feedforward

214


Cascode Compensation (2)

• Benefits

– Tends to push ωp2 to higher frequencies, when load capacitor is large (see text)

• Can use smaller Cc, less power in first stage

• Issues

– Additional power dissipation

– Bias current mismatches cause input referred offset

• The above two issues can be addressed by feeding back to cascode device embedded in first stage (Ribner, JSSC 12/1984)

– New issue: Complex design problem (3rd order system)


Nulling Resistor (1)

• New transfer function becomes

( )⎟⎟⎠

⎞⎜⎜⎝

⎛−⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛−⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛−

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⋅≅

321

20

111

11

ps

ps

ps

Rg

sCasa

zm

c

v

• p1 and p2 unchanged, new pole p3, and a knob to tune the zero

215



• Rz=1/gm2 pushes the zero to +∞– Can use a transistor in triode region to implement resistor

• Helps track process variations



• Rz=(1+C2/Cc)/gm places zero on top of ωp2!– Cancels p2

– Good in theory, may be troublesome in practice– If the pole and zero don't fall exactly on top of each other, we

get a so-called pole-zero doublet• Can cause very slow settling tails in transient response• See supplementary handout "Effect of Doublet on Amplifier

Settling Time" (optional)

• Third pole

1

2

13

1Cg

CRm

zp ≅≅ω

11

11

23 >>= typically CC

gg c

m

m

c

p

βωω

216


Other Compensation Methods

• Nested Miller compensation

– >2 gain stages

– Higher order response presents design challenge

– Not (yet?) used much

– Ref: R. G. H. Eschauzier and J. H. Huijsing. Frequency Compensation Techniques for Low-Power Operational Amplifiers. Kluwer, 1995.

• Lag/lead compensation

– See handout "Feedback Systems" on website

– An attempt to improve bandwidth/phase margin by adding additional zeros to T(s)

– May introduce doublets and worsen noise performance


Noise in Feedback OTAs

• Single stage amplifier

• Single stage amplifier with cascode

• Two stage amplifier

217


Single Stage Amplifier

CL+vi-

+vo-

M1

M2VB

Cf

Cs

⎟⎟⎠

⎞⎜⎜⎝

⎛+⎟

⎟⎠

⎞⎜⎜⎝

⎛++=

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

∞1m

2m

f

1gg

1m

2m2tot,o

gg1

CC

A1CkT

gg1

CkTv

γ

βγ

• Make gm2 as small as possible, i.e. use small gm/ID for current source device

– Issue: Smaller gm/ID means less available swing

• Small Cgg1, i.e. high fT helps reduce noise

( )β−++= 1CCCC fjunctionL


Useful Integrals

218


Single-Stage Amplifier with Cascode

• Analysis shows

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

1m

2m

2p

c

1m

2m2tot,o

gg

k111

CkT

gg11

CkTv

β

ωω

β

• Make gm2 as small as possible, i.e. use small gm/ID for cascode device

– Reduces gm2/gm1 and Cx

– Issue: Smaller gm/ID means less available swing

Ltot

1mc C

gβω =

x

2m2p C

g=ω

( )β−++= 1CCCC fjunctionLc

2pkωω

=


Two-Stage Amplifier

• Analysis shows

– See supplementary handout "Noise in a Two-Stage Amplifier"

• Need large Cc for low noise

• Noise from second stage can be significant if CL is small and β is large

Noise from second stage

≅ 1

219


SNR in Differential Circuits

• In fully differential circuits, the effective output swing is doubled

– But there are two half circuits that contribute noise

• Signal power increases by 4x, noise power increases by 2x

– 3dB win in terms of SNR

– At the cost of twice the power consumption (no free lunch…)

CkTVSNR

2o∝

220


Lecture 20OTA Design Considerations


[email protected]



Overview

• Reading

– Supplementary handout "OTA Design Example"

• Introduction

– Today, we will review a possible design strategy for two-stage OTAs. Since there exist many degrees of freedom in this topology, a thorough hand analysis is essential, and can help minimize, if not completely eliminate, the time needed for a large number of Spice iterations.

221


Two-stage OTA Design Strategy

• The design equations for a two-stage OTA are fairly complex, and involve several capacitances that may not be known a priori

• Solution: Iterative hand analysis/design– Most efficiently done using e.g. Excel, Matlab or MathCAD

• Possible design flow1. Pick Cc based on noise spec, and Cgg1, Cgg2 based on

heuristics (see following slides) 2. Use initial guesses for junction capacitances

– Conservative starting point: Cjunction≈Cgs≈Cgg

3. Find gm, fT, gm/ID4. Iterate, using different choices in step 15. Find W for Spice verification6. Resolve potential discrepancies

– E.g. refine Cjunction estimates if necessary


A Note on Discrepancies

• Discrepancies between design script and Spice are usually on the order of 10%

– Mostly due to• Bias point dependence (VDS); charts generated for VDS=VGS

• Inaccuracy in Cjunction estimate

• First order nature of design equations

• Good news

– It is always possible to track discrepancies down if needed• Look at gm/ID , CGG, Cjunction in the bias point output

• Big difference to square law design using µCox, VOV, …

– These quantities simply don’t exist in your circuit…

222


Component Identification

1junction2gg1 CCC +=

( ) 2junctionfL2 CC1CC +−+= β 1ggsf

f

CCCC++

=β

• For algebraic convenience, we'll neglect the junction caps in the following discussion…

– Straightforward to add back in in your spreadsheet


Closed-Loop Bandwidth

• Small Cgg1 helps, but there is diminishing return if becomes small compared to Cs, Cf

• Typically a good starting point: Cgg1 ≈ Cs

– Sometimes optimum

1ggsf

f

CCCC++

=β

c

mmm

cmcdB C

gRgRgCRRg

12211

1223

1 ββωω =⋅⋅≅≅−

223


Nondominant Pole

• Heuristic: Can try to make Cgg2 ≅ CLtot

– Choosing Cgg2 much smaller may mean that we need large gm2/Cgg2=ωT2 and therefore get small gm/ID

– Choosing Cgg2 much larger may cost too much power with diminishing returns

Ltotggc

ggLtot

mp

CCCCC

g

++≅

22

22

ω ( ) fLLtot CCC β−+≅ 1

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛+

+⎟⎟⎠

⎞⎜⎜⎝

⎛+≅

c

Ltot2gg

2ggLtot

2m

Ltot

2m

2gg

2p CCC

CC

1gC

gC1

ω


Outcome

• Interesting to look at Cgg2=CLtot (not necessarily optimum) to get further qualitative insight

– With this choice, we have

⎟⎟⎠

⎞⎜⎜⎝

⎛+≅

c

Ltot

2T2p C2C121

ωω

c

mcdB C

g 13 βωω ≅≅−

• Cc large means that we can use lower ωT2, i.e. save power in the second stage

– But larger Cc also means more gm and thus more power in the first stage

• Seems like there may be an optimum value for Cc

– But Cc may ultimately be constrained by noise requirements…

224


225


Lecture 21Step Response


[email protected]



Overview

• Reading

– 7.5 (Relation Between Frequency and Time Response)

• Reference

– H.C. Yang and D.J. Allstot, "Considerations for fast settling operational amplifiers," IEEE Trans. Ckts. and Syst., March 1990, pp. 326 – 334.

• Introduction

– OTAs with capacitive feedback are primarily used in switched capacitor circuits, where fast settling to voltage steps at the input is critical. In today's lecture we will look at first and second order behavior in the step response of feedback OTAs.

226


Motivation

• In switched capacitor circuits, the amplifiers have to respond to voltage steps

• How fast of a switched capacitor circuit can we build?


Analysis

• Assuming a single pole system, we have

( )

c

0

0

f

s

in

out

s1

1T1

TCC

)s(V)s(VsA

ω+

⋅+

−=≅

Ltot

mc C

G⋅≅ βω

insf

f

CCCC

++=β

omRGT ⋅= β0

( ) fLLtot CCC ⋅−+= β1

227


Step Response

)s(V)s(A)s(V inout ⋅=

)s(V)s(AL)t(V in1

out ⋅= −

( )τ/t

0

0step

f

sstep1out e1

T1TV

CC

sV

)s(AL)t(V −− −⋅+

⋅⋅−=⎭⎬⎫

⎩⎨⎧

⋅=c

1ω

τ =

Ideal Response

Static Error

Dynamic Error

0ε⇒ dε⇒


Graphical Illustration

0 2 4 6 8 100

0.2

0.4

0.6

0.8

1

t/τ

Vou

t/Vou

t,ide

al

Dynamic Error

Static Error

228


Design Considerations (1)

• Need large DC loop gain for small static error

– |ε0| ~ 1/T0

– E.g. need T0>1000 for better than 0.1% precision

• Need small τ (large bandwidth) for fast settling

• Can define settling time ts based on tolerable dynamic error

τε /ttol,d

se−−=−

( )tol,ds lnt ετ ⋅−=

( )tol,dc

s ln1t εω

⋅−=



• Going from 1% dynamic precision to 10-6 necessitates only ~3x increase in settling time

εd,tol ts/τ

1% 4.6

0.1% 6.9

0.01% 9.2

10-6 13.8

229



ε fc/fCLK

1% 1.5

0.1% 2.2

0.01% 2.9

10-6 4.4

• A switched capacitor circuit operates in two clock phases

• Fitting the required number of time constants within ½ period lets us relate fCLK to a minimum bandwidth requirement

( )CLK

max,dc

s f1

21ln

f21t <⋅⋅

−= επ

( )max,dCLK

c ln1ff ε

π−>


How Fast Can We Go?

• fc cannot be larger than about 1/3 of the nondominant amplifier pole frequency (stability)

– In a cascoded amplifier, the nondominant pole occurs at a frequency around fT/3

• Assuming that two junction caps equal to Cgg are present

– At a reasonable bias, the NMOS transit frequency in our technology is roughly 8GHz (nominal process and temperature)

• Putting all of this together, and assuming that we'll need to settle to within 0.01% (~9 time constants), we have

MHz26630f

9f

9.21f TT

max,CLK =≅⋅=

230


Practical Aspects

• In practice, it is hard to achieve fCLK> fT/50

– Amplifier topology restriction• E.g. sometimes forced to use PMOS in signal path

– Restrictions on power dissipation• Near the technology limits, power tends to grow out of bounds

– Timing overhead to produce non-overlapping clocks• Have somewhat less than half clock cycle to settle

– Other transient effects• We'll look at some of those next…


Impact of Non-Dominant Pole

[Yang, IEEE TCAS 3/1990]

231


Simulation Example

• Using simple single stage (single pole) OTA

• Parameters– Cs=Cf=500fF, CL=10pF, β=0.48, Gm=1mS, GmRo=85, Vidstep=-10mV


Result

( )ns21

GC1C1

m

fL =−+

=β

βτ mV76.9

RG1RGVV

0m

0midstepfinal,od =

⋅+⋅−=β

β

0 50 100 150 200 250 3000

2

4

6

8

10

Time [ns]

Vo

ltag

e [m

V]

Vid

Vod

(simulation)V

od (theory)

232


Another Run

• Changed CL from 10pF to 300fF

• What's this ?

5 10 15 20 25-5

0

5

10

Time [ns]

Vo

ltag

e [m

V] V

idV

od (simulation)

Vod

(theory?)


Capacitive Feedforward

• In the first instant after the input step has been applied, the output is completely determined by capacitive voltage division

• Half circuit during initial transient:

Lf

f

Lf

Lfins

s

idstep

odstep

CCC

CCCC

CC

CVV

+⋅

+++

=

233


Analysis

• Can analyze this effect in two (equivalent) ways

– Using capacitive divider to find new starting point of exponential

– Using inverse Laplace transform of A(s) with feedforward zero included

• Recall from lecture 14, that A(s) is more precisely given by

( )0

0

f

sT1

T

ps1zs1

CCsA

+⋅

−

−−= f

m

CGz =

( ) fL

m

C1CGpβ

β−+

−=


New Result

• For our example:

⎟⎟⎠

⎞⎜⎜⎝

⎛⎥⎦⎤

⎢⎣⎡ −−⋅

+⋅⋅−=

⎭⎬⎫

⎩⎨⎧

⋅= −− τ/t

0

0idstep

f

sstep1od e

zp11

T1TV

CC

sV

)s(AL)t(V

New

( )( ) ( )

Lf

ffL

fL

fL

ffL

CCC

1

1C1C

CCC1C

CC1Czp1

+−

=−++

=−+

+−+=−

βββββ

( ) mV44.11mV10)0t(V4.1

fF300fF500fF50048.01

1od −=−≅=⇒=

+−

• Good agreement with simulation

234


New Settling Time

• Settling time for given precision increases due to feedforward, since the settling range is artificially enlarged

• E.g. in our simulation example, the time to settle within 0.1% dynamic error increases from 6.9τ to 7.3τ– Not extremely significant, especially when β is low and CL is

at least comparable to Cf

⎟⎟⎠

⎞⎜⎜⎝

⎛

⎥⎥⎦

⎤

⎢⎢⎣

⎡

+⋅−⋅−=

Lf

ftol,d

cs CC

C1ln1t βε

ω

<1

235


Lecture 22Slewing


[email protected]



Overview

• Reading

– 9.6.1, 9.6.2, 9.6.5 (Slew Rate)

• Introduction

– Today we'll complete our discussion of transient behavior in OTA circuits with capacitive feedback. Aside from the feedforward artifact we've discovered last time, there exists another effect called "slewing". Whenever the differential input pair is driven outside its "linear range", the differential output current is limited by the available tail bias. In typicalswitched capacitor circuits, slewing can cause a significant speed reduction, and is therefore an important effect to consider.

236


Simulation Example from Last Lecture

• Using simple single stage OTA (See lecture 15, slide 3)

• Parameters– Cs=Cf=500fF, CL=10pF, β=0.48, Gm=1mS, GmRo=85


Another Simulation

• Set Vidstep=-1V (CL=10pF ⇒ insignificant feedforward to output)

• What causes this discrepancy ?

0 50 100 150 200

0

200

400

600

800

1000

Time [ns]

Vo

ltag

e [m

V]

-Vid

Vod

(simulation)V

od (theory?)

237


Capacitive Divider at OTA Input

• Half circuit during initial transient:

mV480fF500fF40fF500

fF500V1

CCCC

CC

CVV

Lf

Lfins

sidstepxdstep −=

++−≅

+++

=

• Initially -480mV across differential pair input!


Differential Pair Characteristics

• Differential output current begins to saturate ~|Vid| > 1.4·2/(gm/ID)

• Beyond this point, current will be much less than that predictedby linear model (slope at origin)

Iod/ITAIL

⎝

2 1 0 1 2

1

0

1Slope = Gm

Vid/(2/[gm/ID])-√2 √2

238


0 50 100 150

-500

-400

-300

-200

-100

0

Time [ns]

Vxd

[mV

]

0 50 100 150-300

-200

-100

0

Time [ns]

Diff

. pa

ir I od

[ µA

]

Differential Pair Input Voltage vs. Output Current

-1.4·2/gm/ID)

"Slewing" "Linear Settling"


Slewing

• During "slewing", the amplifier drives its output with a constant current (equal to tail bias)

• The slewing behavior ends when |Vid| has become smaller than about 1.4·(2/gm/ID)

– This is the point when the differential pair re-enters its "linear region"

– Hence, the remaining portion of the settling is often called "linear settling"

• Even though the output voltage really settles with a (1-et/τ) relationship

• The total settling time of the amplifier in presence of slewing can be calculated as shown in the following derivation

239


Slew Rate

• In order to find the time it takes to complete slewing, we can first calculate the "ramp speed" at which the output changes

– This quantity is called "Slew Rate" (SR)

( ) fL

TAIL

Ltot

TAILod

C1CI

CI

dtdVSR

β−+===


Slewing Time

• The input of the differential pair changes at a rate equal to β·SR, where β is given by the usual capacitive feedback divider

• Hence, the time it takes to complete slewing is given by

( )SR

I/g/8.2Vt Dmxstepslew ⋅

−=

β

• In our example, we have

sV20

pF10A200

CISR

Ltot

TAIL

µµ =≅=

ns21

sV2048.0

mV280mV480tslew =⋅

−=

µ

240


Subsequent Linear Settling

• Once slewing is completed, the differential output voltage is

mV420SRtV slewslew,od =⋅=

• The final settling value in our example is roughly 1V

– Almost half way there after slewing

• This means that the dynamic error budget for the remaining settling portion has increased

– E.g. if we wanted to settle within 0.1% of the final value (~1V), we only need to complete the remaining transient to within 0.1%·1V/0.58V=0.17%

– Not a very big win, usually a negligible change in the number of required time constants

• 0.1%→6.9τ, 0.17% → 6.4τ


Complete Expression for Settling Time

• Note that circuits with large closed loop gain tend to slew less

– Since Vidstep cannot be larger than Voutputswing/Gain

– E.g. Voutputswing=2V, Gain =8 ⇒ Vxdstep < Vidstep < 250mV• Won’t slew at all if gm/ID < 2.8/250mV= 11.2V-1

( ) ( )tol,dDmxstep

linslews lnSR

I/g/8.2Vttt ετ

β−

⋅−

≅+=

( ) fL

TAIL

Ltot

TAIL

C1CI

CISR

β−+==

fins

sidstep

Lf

Lfins

sidstepxdstep CCC

CV

CCCC

CC

CVV++

≅

+++

=

insf

f

CCCC

++=β

<1

241


Slewing in a Two-Stage OTA (1)

• Nodes V1p and V1m stay roughly constant

– These nodes move at a rate equal to the slew rate Vop, Vom

divided by ~ intrinsic gain of second stage

– Second stage acts as "integrator"



• Must design circuit such that slew rate is limited by ITAIL

– IB2 limitation would cause asymmetric slewing• One branch slew limited by IB2, other slew limited by ITAIL

– Asymmetric slewing causes CM shift• Causes slow transients due to slow CMFB

242



• The maximum slew rate at which output Vom can move down

( )⎭⎬⎫

⎩⎨⎧

+=

−=−

Ltotc

2B

c

TAILp1omMAX, CC

2/I,C

2/Imindt

VVdSR

• The maximum slew rate at which output Vop can move up

c

TAILm1opMAX, C

2/Idt

)VV(dSR =

−=+

• To make slew rates equal, we need

Ltotc

2B

c

TAILCC

IC

I+

≤


Slewing in "Continuous Time" Circuits

• Slewing is not only an issue in switched capacitor circuits, it can also limit the large signal performance of continuous time circuits

• Example:

CL

iout

VoutVin

( ) ( )tVtv oo ωsinˆ=

( )dtdvCti o

Lout =

oLout VCi ⋅⋅= ω

• At large frequency and/or amplitude, the peak output current needed can exceed the maximum current available from the amplifier

( )tVC oL ωω cosˆ⋅⋅=

243


Resulting Waveform



• When slewing is an issue, it can be mitigated by biasing the relevant transistors at lower gm/ID– Increase ID, keep gm constant

– Slewing performance improves, because of larger ID and also because the differential pair input range increases (2.8/[gm/ID])

– Small signal performance remains virtually unchanged or improves if fT is a limiting factor (since fT increases)

– Issue: Lower gm/ID means higher power consumption

244


How to Incorporate Slewing in Design Flow

• Set up a spreadsheet for small signal design as usual– Settling time requirement translates into minimum "linear"

bandwidth spec (based on linear analysis, without slewing)

• Introduce a bandwidth spec scale factor K≥1 in your design script– If the circuit slews, we will need more bandwidth than

predicted from linear analysis

• Perform design optimization as usual, begin with K=1

• Calculate slewing time, add to linear settling time– Done if tslew=0

• Increase K until design meets settling time spec– In the process, you may consider to optimize gm/ID values to

minimize power in presence of slewing

245


Lecture 23Feedback and Port Impedances

OTA Variants, CMFB Implementation


[email protected]



Overview

• Reading– 8.8.2 (Closed-Loop Impedance Formula using Return Ratio)– 6.7 (MOS Active-Cascode Amplifiers)– 12.5 (CMFB Circuits)– 12.6 (Fully Differential Amplifiers)– 9.4.4 (Compensation of Single Stage CMOS OTAs)

• Reference– K. Bult, G.J.G.M. Geelen, "A fast-settling CMOS op-amp for SC circuits with

90-dB DC gain," IEEE J. Solid-State Circuits, Dec. 1990, pp. 1379 – 1384.

• Introduction– In order to complete our framework for feedback circuit analysis, we will

study the effect of feedback on port impedances in today's lecture. A useful analytical tool for quick calculations is Blackman's Impedance Formula, which allows us to find port impedances based on a superposition of simple sub-analyses.

– Next, we survey common OTA architectures and associated implementation aspects. Most OTAs used in practice are derivatives of the basic single- or two-stage topology, with add-ons such as simple cascodes or gain boosted cascodes. The survey concludes with a brief analysis of the most commonly used common mode feedback implementations.

246


Using Feedback to Modify Port Impedances

• Our initial motivation for using feedback was to build precise gain elements that are insensitive to gmR variations

• In addition, feedback can be used to increase/decrease port impedances

– In fact, we have already seen one example of such behavior• Closed loop bandwidth of OTA feedback amplifier was (1+T)

higher than open loop bandwidth

• This means the impedance seen by the load capacitor must have dropped in presence of feedback

• We can calculate the port impedances of arbitrary feedback circuits using "Blackman's Impedance Formula"

– Based on loop gain calculations

– Extremely useful and easy to use


Blackman's Impedance Formula

1. First, find port impedance with feedback loop broken

– E.g. set gm=0

2. Calculate loop gain in circuit with port under consideration shorted

3. Calculate loop gain in circuit with port under consideration open

• In many cases, either the "shorted" or "open" loop gain is zero

( ) ( )( )open portT

shortedportTkZZ portport ++⋅==1

10

247


Example 1

( ) ( )m

voutout gaRkR 100 ====

( ) 0= shortedportT

( ) vaopen portT =

vmout ag

R+

=1

11


Example 2: Shunt-Shunt Stage

( ) oFmin rRgR +== 0

( ) 0= shortedinputT

( ) omrgopen inputT =

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛+≅

++=

o

F

momoFin r

Rgrg

rRR 111

1

( ) omout rgR == 0

( ) 0= shortedoutputT

( ) omrgopen outputT =

momoout grg

rR 11

1 ≅+

=

248


Example 3: Active Cascode

• Also referred to as "Regulated Cascode" or "Gain Boosting" technique

( ) 22010 omvout rgraR ⋅≅=

( ) vmbm

mv a

ggga shortedportT ≅+

≅22

2

( ) 0=open portT

( )vom

vomout

argrargrR

⋅⋅≅+⋅⋅≅

2201

2201 1


Basic Implementation

• Can use simple CS stage as auxiliary amplifier

– Issue: Costs headroom

• See literature for more advanced implementations

– E.g. using fully differential folded cascode amplifier as an auxiliary amplifier

332201 omomout rgrgrR ⋅⋅≅

249


Properties

• Must compensate local feedback loop such that its crossover frequency ωc occurs before non-dominant pole at source of M2.

• Consideration of the total impedance at the output node (including CL) shows that gain boosting introduces a pole zero doublet around ωc

– Can result in slow step response, if not designed carefully

– See Bult, JSSC 12/1990 for design considerations

• In typical designs, "gain boosting" adds about 20-30% to the total power dissipation of an OTA


OTA Variants: Telescopic OTA

• Approximately same gain as two stage amplifier, with only two current legs

– Maximum power efficiency

• Issue: Low swing

– Especially if input and output common mode cannot be chosen freely

250


Biasing

• Typically use at least 20% of tail current in auxiliary biasing branch

– Must avoid slow recovery of this node during transients

• Can use several device in series to implement MB1

– "1/3rd or 1/5th" device

– Helps avoid extremely small width for MB1


Folded Cascode OTA

• Large input common mode rage

• Slightly improved output range

• Folding adds power dissipation

251


Compensation

• Nondominant pole ωp2=gm1a/Cp

– Cp=Cgs1a+Cj1a+Cj1

• Easy to compensate

– Make k·β·gm1/CL < ωp2

– k=3 for 72° phase margin

AC Half Circuit for Telescopic OTA AC Half Circuit for Folded Cascode OTA


Current Mirror OTA

• Gm=k·gm1,2, ωp2 ~ ωT/(1+k)

• Large swing

• Good for low speed, low power applications– See e.g. Yao, JSSC 11/2004

k 1 1 k

252


All NMOS Signal Path (1)

• Capacitive level shift allows NMOS in second stage

[Feldman et al., JSSC 10/1998]


All NMOS Signal Path (2)

• Differential pair and separate common mode feedback in second stage

[Yang et al., JSSC 12/2001]

253


Gain Boosted Gain Boosters

• Gain ~ gmro6, design achieved av0=130dB in 0.18µm technology

[Chiu et al., ISSC 2004]



• Implementation aspects

– How to sense

– How to compare to desired value

– How to provide a "knob" for adjusting Voc

254


Knob

• Typically generate ~80% of tail current with fixed bias, leave remaining 20% as tuning range for CMFB loop


Comparison Circuit

• Low frequency loop gain T0 ≅ 0.25·gmx·rop1 · gmp2/gmx

– Loop will control Voc more accurately if Mp1 is cascoded

255


Sensing

• Using a resistive divider may destroy differential gain

• Solutions

– Use source followers to drive divider (headroom issue)

– Purely capacitive sensing


CMFB Implementation Example

[Feldman et al., JSSC 10/1998]

• Circuit uses switched capacitors (CM) to set the voltage across sensing capacitors (CCM)

256


"Passive" CMFB (1)

• During φ1: Initialize voltage across Ccmfb to Voc,desired - VB

• During φ2: Activate feedback loop

– If Voc>Voc,desired, Vcntrl becomes >VB and lowers Voc


"Passive" CMFB (2)

• OTA cannot be used during φ1, because the common mode feedback mechanism is inactive

– Often not a problem in switched capacitor circuits, where the OTA is active only during one half-cycle

• Can use switched capacitor scheme shown on slide 22 to enable uninterrupted common mode feedback

• Unfortunately, this simple circuit cannot be used if an additional inversion is needed in the common mode feedback loop

– E.g. won't work for a two-stage OTA that uses a single common mode feedback loop (see e.g. slide 9, lecture 18)

– Will work for the two-stage OTA with separate CMFB loops as shown on slide 16

257


Common Mode Half Circuit

• Low frequency loop gain:

2CC

Cr

2gT

xcmfb

cmfbop

mx0

+⋅≅

• Loop crossover frequency

xcmfb

xcmfbL

mxc

C5.0CC5.0C

C

g21

+⋅

+≅ω

• Nondominant pole

y

mn2p C

g≅ω



• The required bandwidth of the common mode loop strongly depends on the amount of expected imbalance, common mode transients or ac components

– In an ideal world, the common mode is not affected by the signal and hence stays constant

• In this case, the bandwidth of the CMFB loop is unimportant

• For robustness in practical implementations, the bandwidth of the common mode loop is often chosen to be about 30% of the differential signal path bandwidth

– In a typical switched capacitor circuit with 10 time constants differential settling, this means that the common mode has about 3 time constants to settle

• Enough time to remove 95% of common mode disturbance

258


Lecture 24OTAs with Single Ended Outputs

Output Stage Examples


[email protected]



Overview

• Reading

– 4.3.5 (Differential Pair with Current Mirror Load)

– 6.3.3 (Systematic Offset in Two-Stage Amplifier)

– Chapter 5 (Output Stages)

• Introduction

– This lecture concludes our discussion of amplifier implementations by looking at a number of missing bits and pieces. First, we will discuss subtleties of OTA implementations that use a single ended output. While rarely used in the signal path of high performanceintegrated circuits, OTAs with single ended outputs can be useful as auxiliary amplifiers in biasing circuits. Finally, we will take brief look at output stages that are suitable for driving resistive loads. While most on-chip loads tend to be capacitive in nature, low impedance drivers are often needed when interfacing to off-chip components and wire lines.

259


Single Ended OTA

• Current mirror performs "differential to single-ended conversion"


Mirror Doublet

• Half of the output current comes directly from the differential pair, the other half goes through a current mirror with finite bandwidth

– Result: Pole-zero doublet

ps1

p2s1

vg

ps1

121

21vgi

idm

idmo

−

−=

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

−+=

• In the circuit on the previous slide p ≅ -ωTp/2 (neglecting junctions)

260


Unity Gain Buffer

• Closed loop gain ≅ 1

• Output impedance ≅ 1/gm

• Output range equal to common mode input range

– Advantageous to use a folded cascode OTA architecture


Inverting Amplifier

• Cx = ?, T(s) = ?

– Big mess…

261


Two-Stage OTA with Single Ended Output


Systematic Offset

• No offset if VGS6=VGS3

balances the current in the output branch

• Input referred systematic offset is (VGS6,balance-VGS3)/av1, where av1 is the gain of the first stage

262


Output Stages

• Needed to drive resistive loads (low R)

– Integrated continuous time RC-filters

– Off-chip resistive loads

– Line drivers• E.g. twisted pair (Ethernet, ISDN, ADSL)

• Solutions

– Use OTA + source follower output stage• Swing issue

– Use OTA + "low gain" common source stage• E.g. make gm·RL~1

• E.g. 20mS·50Ω =1, IBIAS=20mS·10V-1 = 2mA

– "Sophisticated" output stages• Examples on following slides


Output Stage Nomenclature (1)

• Class-A

– Output devices conduct for entire cycle of output sine wave

– E.g. source follower with constant current source bias

• Class-B

– Output devices conduct for ≅50% of sine wave cycle

– E.g. back-to back PMOS/NMOS source followers• NMOS and PMOS each conduct for about one half cycle

• No quiescent current during zero crossing of sine wave

• Class-AB

– Output devices conduct for >50%, but <100% of cycle

– E.g. a simple inverter• Problem: How to set quiescent current around zero crossing

• Needs local or global feedback to mitigate nonlinearity

263


Output Stage Nomenclature (2)

Class-A Class-B

Class-AB Class-C


Selected References on Output Stages

• D. M. Monticelli, "A quad CMOS single-supply op amp with rail-to-rail output swing," IEEE J. Solid-State Ckts., pp. 1026-1034, Dec. 1986.

• R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, "A compact power efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries," IEEE J. Solid-State Ckts., pp. 1505 - 1513, Dec. 1994.

• G. Palmisano, G. Palumbo, and R. Salerno, "CMOS Output Stages for Low-Voltage Power Supplies," IEEE Trans. Ckts. and Syst. II, pp. 96-104, Feb. 2000.

264


Class-AB Output Stage

[Hogervorst]


Output Current (Vo=0)

• Output transistors never turn off

• Quiescent current set by transistor ratios

• Large drive capability

ID(M25)

ID(M26)Iout

Iin1=Iin2 [A]

Cur

rent

[A

]

265


Complete OpAmp

[Hogervorst]


Low Voltage Variant

[Palmisano]

<Vtn+|Vtp|

266


Complete OpAmp

[Palmisano]

<Vtn+|Vtp|


A Note on General Purpose OpAmps

• Issue: Compensation

– The designer of a general purpose OpAmp does not know anything about the feedback network of the particular application

– General purpose OpAmps are typically compensated for the "worst case", i.e. unity feedback configuration

• Tends to be wasteful, since much less compensation is needed for smaller return factors

– Some general purpose OpAmps provide an external pin to let the user decide on the required compensation capacitor

267


Lecture 25Supply Insensitive Biasing


[email protected]



Overview

• Reading

– 4.4.2 (Supply Insensitive Biasing)

• Introduction

– Throughout this course, we have ignored the question on how to generate the reference bias currents used in most of our circuits. Today, we will examine a variety of current reference implementations, with primary focus on supply independence.

268


Poor Man's Bias

• Issue: Current is essentially proportional to VDD

– E.g. if VDD, varies by X%, bias current will roughly vary by the same amount

RVVVII OVtDD

INOUT−−=≅


"Vt" Referenced Bias

• By using a sufficiently large device, we can make VOV << Vt, and achieve

2

ox

INt

2

OVt

2

1GSOUT R

LWC

I2V

RVV

RVI

µ+

≅+≅=

2

tOUT R

VI ≅

• Question: By how much will IOUT

change given some variation in VDD?

269


Sensitivity

• The sensitivity of a parameter y to a change in parameter x can be approximately found using

yx

!S

xy

yx

x/xy/y

x/xy/y =

∂∂=

∂∂≅

∆∆

• In our case, we are looking for

%1.7V1.0V6.0

V1.021.g.e

VVV

21

II

II1

SSS

1OVt

1OV

IN

OUT

OUT

IN

II

IV

IV

OUT

IN

IN

DD

OUT

DD

=++

≅

∂∂⋅⋅≅

⋅=

• Not bad, but also not all that great…


BJT Version

⎟⎟⎠

⎞⎜⎜⎝

⎛==

S

IN

22

1BEOUT I

Ilnq

kTR1

RVI

%7.3mV700mV26.g.e

Vq

kT

SBE

IV

OUT

DD==

270


Stability

( )

2p1p

22m

22m11m s1

1s1

1Rg1

RgRgsT

ωω+

⋅+

⋅+

⋅≅

• Loop gain greater 1 at low frequencies, two poles

– Means that we must make one of the poles dominant to guarantee sufficient phase margin

• E.g. use large capacitance to ground at drain of T1


Self Biasing

• In the above discussed bias generator circuits, the supply sensitivity is still fairly high, because IIN is essentially directly proportional to VDD

• Idea: Mirror output current back to input instead of using supply dependent input current!

271


Start-Up Circuit

• Unfortunately, self-biasing comes with a built in "chicken and egg problem"

– There exists a stable operating point with all currents =0

– Can use a simple start-up circuit to solve this problem

(WEAK)


VBE Reference

• Utilizes "parasitic" substrate PNP transistor available in any CMOS technology

RV

I 1BEOUT =

272


Temperature Dependence (1)

• Similar to the sensitivity to supply variations, we can establish an expression for temperature variations

– Fractional temperature coefficient

OUT

OUT

F IT

I

TC ∂∂

=

• For the circuit on the previous slide we have

RVI 1BE

OUT =⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂−

∂∂=

∂∂−

∂∂=

∂∂

TR

R1

TV

V1I

TR

RV

TV

R1

TI

1BE

1BEOUT

21BE1BEOUT


Temperature Dependence (2)

• Final result

• Temperature dependence is usually quite high

TR

R1

TV

V1TC 1BE

1BEF ∂

∂−∂∂=

K/%33.0mV600

K/mV2T

VV

1 1BE

1BE

−=−≅∂∂

resistor)(poly K/%2.0TR

R1 +≅∂∂

• E.g. ∆T=100K ⇒ ∆I=-53% (!)

K/%53.0TCF −=

273


∆VBE Reference

( )nlnq

kTII

IIln

qkT

IIln

qkT

IIln

qkT

VVRI

IN

2S

1S

IN

2S

OUT

1S

IN

2BE1BEOUT

=

⎟⎟⎠

⎞⎜⎜⎝

⎛=

⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟⎠

⎞⎜⎜⎝

⎛=

−=⋅

( )nlnq

kTR1IOUT =


TC of ∆VBE Reference

( )

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂−

∂∂=

∂∂−

∂∂

=∂∂

TR

R1

TV

V1

RVnln

RTRV

TVR

nlnT

I

T

T2

T

2

TT

OUT

TR

R1

T1

TR

R1

TV

V1TC T

TF ∂

∂−=∂∂−

∂∂=

qkTVT =

• ExampleK/%13.0K/%2.0

K3001TCF =−=

• TC of resistor and kT/q partially cancel!

274


∆VGS Reference (1)

• Strange result, why is this useful?

2

1OV

REF

1OV

2OV1OV

2GS1GS2REF

Rm11V

I

m11V

VVVVRI

⎟⎠⎞

⎜⎝⎛ −

≅

⎟⎠

⎞⎜⎝

⎛ −≅

−=−=⋅

[Lee, 2nd ed. p.326]

m1


∆VGS Reference (2)

• The transconductance of M1 is approximately

21OV

1REF

1OV

1D1m R

m112

VI2

VI2g

⎟⎠

⎞⎜⎝

⎛ −⋅===

• Transconductance of M1 and other devices biased using this circuit depend only on m and R2!

– This is why this bias circuit is more appropriately called "constant gm reference"

• Design aspects

– Can use off-chip resistor to set gm precisely

– Large VOV helps reduce mismatch errors

– Small I⋅R2 makes circuit less sensitive to body effect

275


Constant Settling Time Bias (1)

• Reference

– I. E. Opris, L. D. Lewicki, "Bias optimization for switched capacitor amplifiers,"IEEE TCAS II, pp. 985-989, Dec. 1997.

Settling time with constant bias current



• Settling time of amplifier is given by

m

slew,olinslews g

CNI

CVttt

⋅+

⋅≅+=

β

• Constant gm bias helps, but is not optimum for minimizing process variations

• Really want a bias circuit that keeps ts constant

276



• Can make setting time "constant" by choosing

RVII 0

∆+=

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

+≅⇒

⋅+

⋅≅

mslew,o

s

m

slew,os

gINV

tCI

gCN

ICV

t

β

β

CNk

11t2R

tCV

Is

s

slew,o0 ⋅

⎟⎠

⎞⎜⎝

⎛ −⋅⋅⋅≅

⋅≅

β



277


Lecture 26Bandgap Reference


[email protected]



Overview

• Reading

– 4.4.3 (Temperature Insensitive Biasing)

• Introduction

– In this lecture we will introduce the basic idea behind the frequently used "bandgap" voltage reference. Conceptually, a bandgap reference simply combines two quantities with opposite temperature behavior to generate a voltage with (approximately) zero TC.

278


Key Idea

• kT/q has a positive temperature coefficient

– "PTAT" proportional to absolute temperature

• VBE of a BJT decreases with temperature

– "CTAT" complementary to absolute temperature

• Can combine PTAT + CTAT to yield an approximately zero TC voltage reference

– Useful in circuits that require a stable reference voltage• E.g. A/D converters


Conceptual Block Diagram

279


A Closer Look at VBE

• Even though kT/q increases with temperature, VBE decreases because IS itself strongly depends on temperature

⎟⎟⎠

⎞⎜⎜⎝

⎛=

S

CBE I

Ilnq

kTV

⎟⎟⎠

⎞⎜⎜⎝

⎛−≅

⎟⎟⎠

⎞⎜⎜⎝

⎛≅

C

00G

)q/kT/(V

0

CBE

IIln

qkTV

eIIln

qkTV 0G

• I0 is a device parameter, which is (unfortunately) not completely independent of temperature– We'll ignore this for now

• VG0 is the bandgap voltage of silicon "extrapolated to 0°K"


Extrapolated Bandgap

1.205eV

V205.1q

eV205.1V 0G ==

[Pierret, Advanced Semiconductor

Fundamentals, p.85]

280


Temperature Coefficient of VBE

• Assuming that both I0 and IC are constant over temperature

TVV

IIln

qk

dtdV 0GBE

C

0BE −=⎟⎟⎠

⎞⎜⎜⎝

⎛−≅

• Example

⎟⎟⎠

⎞⎜⎜⎝

⎛−≅

C

00GBE I

Ilnq

kTVV

KmV02.2

K300V205.1V6.0

dtdVBE −=−≅


CTAT + PTAT

• Returning our initial idea, we can now find the condition that gives us a temperature independent voltage

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−+≅

+⎟⎟⎠

⎞⎜⎜⎝

⎛−≅+

C

00G

C

00GBE

IIlnM

qkTV

qkTM

IIln

qkTV

qkTMV

• Combining VBE and an appropriately scaled version of kT/q produces a temperature independent voltage, equal to VG0

281


Simple CMOS Realization

( )

( )nlnq

kTRRVV

nlnq

kTR1

RV

II

1

21BEout

11

BE21

+=

===∆


Choice of n

• Usually make n=integer2-1, e.g. n=8

• Layout:

282


Design Example

• From measurement data, we know that |VBE| of a unit device is 700mV at room temperature and I=50µA

• Decided to use n=8

( ) ( )

( ) ( ) ΩΩ

Ωµ

k34.98lnmV26

V7.0V205.1k08.1nln

qkT

VVRR

k08.18lnmV26A50

1nlnq

kTI1R

1BEGO12

21

=−=−

=

===


Nonidealities

• "Curvature"

– Temperature dependence of I0

• Offset voltages and TC of offset voltages

• Resistor mismatch and TC

• Finite β and β mismatch

• More next lecture…

283


Lecture 27Bandgap Reference

(Continued)


[email protected]



Overview

• Reading

– 4.4.3 (Temperature Insensitive Biasing)

• Introduction

– Today's lecture will cover several important details that we've left out in our previous analysis of bandgap references. We will discuss nonidealities such as "curvature" and the impact of offset voltages. Finally, we will take a brieflook at state-of-the art implementations and performance.

284


Selected References (1)

• R. J. Widlar, "New developments in IC voltage regulators," IEEE J. Solid-State Circuits, pp. 2-7, Feb. 1971.– First report, LM309 5V regulator

• A. P. Brokaw, "A simple three-terminal IC bandgap reference,"IEEE J. Solid-State Circuits, pp. 388-393, Dec. 1974.– A classic implementation

• C. Palmer and R. Dobkin, "A curvature corrected micropower voltage reference," IEEE Int. Solid-State Conference, pp. 58-59, Feb. 1981.

• G. Nicollini et al., "A CMOS bandgap reference for differential signal processing," IEEE J. Solid-State Circuits, pp. 41-50, Jan. 1991.– Offset compensated amplifier


Selected References (2)

• T.L. Brooks et al., "A low-power differential CMOS bandgap reference," IEEE Int. Solid-State Conf., pp. 248-249, Feb. 1994.– Differential output, stacked diodes

• H. Banda et al. "A CMOS bandgap reference circuit with sub-1-V operation," IEEE J. Solid-State Circuits, pp. 670 - 674, May 1999 .

• P. Malcovati et al., "Curvature-compensated BiCMOS bandgap with 1-V supply voltage," IEEE J. Solid-State Circuits, pp. 1076-1081, July 2001.

285


VBE Revisited

• Last lecture, we assumed that

⎟⎟⎠

⎞⎜⎜⎝

⎛−≅

C

00GBE I

Ilnq

kTVV

• A more accurate, but empirical model is given by

⎟⎟⎠

⎞⎜⎜⎝

⎛ ⋅−≅C

r1

0GBE ITKln

qkTVV

• The temperature dependence inside the logarithm slightly curves the VBE vs. temperature characteristic– TC of VBE is not quite independent of temperature

• Parameter r depends on technology, typically 3…6


Curvature

[Lee, 2nd ed., p.322]

286


Collector Current

• Another superficial assumption was to assume that the current IC is independent of temperature

– Actually PTAT in the example circuit from last lecture

– Also affected by TC of resistors

• To capture the temperature behavior of IC, we can introduce yet another empirical fudge factor and write

⎟⎟⎠

⎞⎜⎜⎝

⎛−≅ n

r

0GBE TTKln

qkTVV

• The factor n is 1 for ideal PTAT current behavior


Modified TC of VBE

• With this refinement, we have

( )

( )

( )T

qkTnrVV

nrTTKln

qk

TTK

TnrKq

kTTTKln

qk

TTKln

qkT

dTd

dTdV

BE0G

n

r

n

r

1nr

n

r

n

rBE

−+−−=

⎥⎦

⎤⎢⎣

⎡−−⎟⎟

⎠

⎞⎜⎜⎝

⎛−≅

−−⎟⎟⎠

⎞⎜⎜⎝

⎛−≅

⎥⎦

⎤⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛−≅

−−

287


Modified Condition for Zero-TC

• Or, more interestingly

( )

( )

qkT

qkTnrVV

M

Tq

kTnrVV

qkTM

dTdV

qkTM0

BE0G

BE0GBE

⎥⎦

⎤⎢⎣

⎡ −+−=⇒

−+−−=+=

( )q

kTnrVV 0Gout −+=

• Must design for Vout that is a few kT/q higher than VGO


Modified Output Voltage

• Getting good temperature stability typically requires some tweaking or calibration

– Some semiconductor foundries provide tried and true bandgap cells that are optimized for a particular technology

[Lee, 2nd ed., p.323]

288


Curvature Compensation

• Control current such that the impact of "(r-n) term" is minimized

• In practice, curvature compensation may not be all that effective if other nonidealities dominate…

[Palmer]


Offset Voltage

( )

( )

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛−−⎟⎟

⎠

⎞⎜⎜⎝

⎛+=

⎟⎟⎠

⎞⎜⎜⎝

⎛−++=

⎟⎟⎠

⎞⎜⎜⎝

⎛−===

1RRVnln

qkT

RRV

Vnlnq

kTRRVVV

Vnlnq

kTR1

RV

II

1

2OS

1

21BE

OS1

2OS1BEout

OS11

BE21

∆

289


Issues

• VOS appears amplified at the bandgap output and can cause a large absolute error in Vout

– Since R2/R1-1 ≅ 8, this means that for VOS=5mV, the error in Vout will be about 40mV or roughly 3.3%

• If the bandgap is trimmed after manufacturing, e.g. to yield an output of VGO+2kT/q, then this is no longer the point of zero TC in presence of VOS

• In CMOS, VOS drift is typically 1…10µV/K– This means Vout will drift at least 8µV/K, which corresponds

to about 6.6 ppm/K• Good CMOS bandgaps achieve about 10…50ppm/K

• Possible solutions– Mitigate impact of offset by stacking two VBE

– Cancel offset or use low offset BJT differential pair


SC Bandgap with Offset Cancellation

[Nicollini]

290


Bandgap with stacked VBE

[Brooks]


Sub-1-V Bandgap

• Idea: Add currents proportional to VBE and kT/q, instead of stacking voltages

≅1.2V

( )

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

+=3R

Nlnq

kT

2RVRV BE

4ref[Banba]

291


Variant with Curvature Compensation

[Malcovati]

Low offset amplifier


Performance

292


Lecture 28Technology Scaling


[email protected]



Overview

• Introduction

– The trend of continuously shrinking feature sizes in integrated circuits has resulted in enormous performance gains in both digital and analog circuits. However, since device scaling necessitates the use of smaller supply voltages, it is often argued that noise limited circuits can no longer benefit from scaling. In this lecture, we will take a closer look at this argument and also review basic analog device performance trends in light of feature size reduction.

293


The Age of "Moore's Law"

• In 1965, Gordon Moore predicted that there will be an exponential growth in the number of transistors per integrated circuit


… And He was Right

[Moore, ISSCC 2003]

294


Smaller

Min

imum

Fea

ture

Siz

e


Faster

295


Cheaper

Ave

rage

Tra

nsi

stor

Pric

e


Misnomer

• The term "Moore's Law" was coined by the press

– Of course, the exponential progress rate is not set by fundamental law

– Merely a rate of progress that makes sense for the industry and keeps things predictable for all involved players

• Device technologists

• Makers of manufacturing equipment

• Circuit designers

• Sales and marketing

• The dirty truth is that Moore's law is mostly just a gigantic economic feedback loop

– With lot's of great innovation fueled by $$$

296


Moore's Law in Action

$$$


Worldwide Semiconductor Sales

[European Nanotechnology

Roadmap]

297


State-of-the-Art Semiconductor Fab

• Cost ~ $3,000,000,000


State-of-the-Art Silicon Technology

• 90nm feature sizes, electrical channel length of 50nm

• Gate oxide thickness 1.2nm, roughly 5 atomic layers

• 8 Layers of metal routing

298


State-of-the-Art Chips

Pentium 4 Processor, 125 Million Transistors[Schutz, ISSCC 2004]

Single-Chip 802.11 Transceiver

[Zargari, ISSCC 2004]


Impact of Technology Scaling

• Scaling is great from a digital perspective!

• Can show that scaling down features and voltages achieves three things simultaneously

– Higher speed

– More transistors/area

– Lower energy per operation

• How about analog circuits?

299


Quotes

• [Vertregt, ESSCIRC 2004]

– "Significant power efficiency improvements are predicted as a result of scaling to deep sub-micron technology nodes."

• [Annema, IEEE J. Solid-State Circuits, 12/2005 ]

– "In summary: unlike digital designs, analog circuits can benefit from technology scaling if the supply voltages are not scaled down."

• [Nauta, ESSCIRC 2005]

– "The evolution of CMOS technology will continue for many years to come, which is beneficial for digital circuits but which is not so for analog."


List of Concerns

• Reduced supply voltage

• Low intrinsic gain

• Variability

• Distortion

• Gate leakage

• Isolation

• …

• Cost (mask & wafer)

• Model accuracy

• …

300


gm/ID and fT trends

• gm/ID essentially unaffected by scaling

• Very high fT in recent technologies

– Enables RF CMOS

-0.4 -0.2 0 0.2 0.4 0.60

200

400

600

800

1000

1200(b)

VGS

-Vt [V]

(gm

/I D)*

f T [G

Hz*

S/A

]

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.60

10

20

30

40(a)

gm

/I D [S

/A]

VGS

-Vt [V]

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.60

40

80

120

160

f T [G

Hz]

180nm130nm90nm

180nm130nm90nm


Available Signal Swing

0

1

2

3

4

5

0.50um 0.35um 0.25um 0.18um 0.12um 90nm 65nm 45nm 32nm

Technology Node

VD

D [

V]

> 4kT/q

> 4kT/q

VDD

qkT8V SwingAvailable DD −<

301


Noise Limited Circuit Performance

C/kTSwingDR

CgBWIVP

2m

DDD ∝∝⋅∝

D

m2

DDDD I

gVSwingV

PDRBW ⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛⋅∝⋅

• Low VDD is generally bad news, but– Analog designers have worked hard to maintain or even

improve Swing/VDD

• Typical ADC in 0.5µm: Swing/VDD=2/5• Typical ADC in 90nm: Swing/VDD=0.5/1

– How about gm/ID?


Leveraging fT

• Example– fT = 50GHz, 130nm: gm/ID = 8S/A, 90nm: gm/ID = 16S/A

• For "fixed-speed" applications, high fT can be leveraged to mitigate low VDD penalty

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.60

10

20

30

40

gm

/I D [S

/A]

VGS

-Vt [V]

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.60

40

80

120

160

f T [G

Hz]

180nm130nm90nm

302


Further Considerations

• Analog building blocks are never completely limited by thermal noise

– Not uncommon to have ~50% dynamic power

• Decreases with scaling

• Designers are continuing to develop/refine low-voltage design techniques

– Recent publications show very good analog building block performance at 1V

• Bottom line

– Analog design is challenging at 1V, but it's neither impossible nor detrimental


Intrinsic Gain

• A real issue

– How to design a high-gain op-amp with devices that have intrinsic gain of ~10?

• How much worse does this get at 45nm/65nm?

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60

50

100

150

200

250(a)

VDS

[V]

I D [ µ

A]

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60

10

20

30

40

50(b)

VDS

[V]

gm

/gd

s

180nm130nm90nm

180nm130nm90nm

(VGS-Vt=100mV)

303


Intrinsic Gain in the Near Future

• Pretty bad…

• Solutions– Use non-minimum length device (NML-device)– Use asymmetric device without drain-side pocket implant (A-

device)– Or, don't try to build op-amps in these technologies…

• E.g. "Digitally Assisted ADC" research in my group

0 0.2 0.4 0.6 0.8 10

5

10

15

VDS

[V]

gm

/gd

s

45nm (TCAD)

65nm (TCAD)

90nm (BSIM4)(VGS-Vt=100mV)


A-Device vs. Standard Device

HoleImpactIonizationSigned Log

0

2.9

5.8

8.7

11.6

14.5

17.4

20.3

23.2

26.52

-0.16 -0.12 -0.08 -0.04 0 0.04 0.08 0.12 0.16

-0.1

6-0

.12

-0.0

8-0

.04

00.

040.

080.

120.

160.

20.

240.

280.

320.

360.

40.

44

HoleImpactIonizationSigned Log

0

2.9

5.8

8.7

11.6

14.5

17.4

20.3

23.2

26.58

-0.16 -0.12 -0.08 -0.04 0 0.04 0.08 0.12 0.16

-0.1

6-0

.12

-0.0

8-0

.04

00.

040.

080.

120.

160.

20.

240.

280.

320.

360.

40.

44

• Removing halo widens depletion region– Reduces impact ionization and improves output resistance

304


Intrinsic Gain of Alternate Devices (45nm)

• For both NML and A-device Lphysical=80nm (Lphysical=24nm for minimum length device)

• Great, lots of gain!

– But how about fT?

(VGS-Vt=100mV)

0 0.2 0.4 0.6 0.8 10

50

100

150( )

VDS

[V]

gm

/gd

s

Min. length

NML-device

A-device

(VGS-Vt=100mV)


gm/ID and fT for Alternate Devices (45nm)

• fT much lower than for minimum length 45-nm device

– But still better than minimum length device in 90nm…

• Who needs fT > 200GHz in an op-amp…?

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

1000

2000

3000

4000

5000(b)

VGS

-Vt [V]

(gm

/I D)*

f T [G

Hz*

S/A

]

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

10

20

30

40(a)

VGS

-Vt [V]

gm

/I D [S

/A]

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

200

400

600

800

f T [G

Hz]

Minimum length

NML-device

A-device

Minimum length

NML-device

A-device

305


Variability (1)

[Courtesy A. Bowling, Texas Instruments]


Variability (2)

• Must keep in mind that even if we draw nice colorful rectangles in our CAD tools, things won't come out like that…

• Device shape strongly depends on surroundings

• Good old layout recipes become more important and must be applied even when only "moderate" matching in required

– Use unit devices

– Match surroundings of unit devices

306


Variability (3)

• Device mismatch larger than process corner variations!– For small "digital" transistors…

[Marcel Pelgrom, Philips]


Variability (4)

Analog

• A well known problem

– Designers are used to "caring" about mismatch

• Lots of options and potential solutions

– Layout techniques, analog or digital calibration, dynamic element matching, larger device area, …

• Usually care about matching for a few up to a few hundred transistors

Digital

• A "new" problem

– Significant impact on achievable performance, yield, design methodology, EDA, …

• Big difference compared to analog

– Care about millions if not billions of devices!

307


An Interesting Hike Lies Ahead…

Bag of Tricks

A

D


Cost – The "Real" End of The Roadmap?

• Reference point: 30 mm2 die in 0.12µm CMOS

[Marcel Pelgrom, Philips][Marcel Pelgrom, Philips]

308


Lecture 29Class Summary

Project Discussion


[email protected]



Transistor Models

• Any model is an approximation of the real world

– Must leave many details out

– Must retain the important details (to be useful)

– Appropriate level depends on questions you want to answer• BSIM model/Spice

• gm/ID approach

• Long channel equations

• When designing and analyzing circuits, we are usually forced to use much simpler models than the ones available in Spice

– gm/ID methodology partially closes this gap

• A "good" IC designer is always on the lookout for modeling limitations!

309


Transistor Figures of Merit


gs

mT C

g=ω


D

mIg

• Intrinsic Gain

omrg


Circuit Analysis

• Once we have appropriate models, we can in principle analyze any circuit using KCL/KVL

– Usually too difficult and also won’t allow us to reason about design choices and tradeoffs

• Crutches for circuit analysis

– Small signal approximation

– Zero value time constant method

– Miller approximation

– Return ratio analysis

– Blackman's impedance formula

– …

• Again, a good designer will always be on the lookout for potential limitations of the respective analysis method

310


The "Atoms" of Analog Circuit Design

• Common source

– Basic voltage amplifier

• Common gate

– Good for "shielding"

– Can help boost output impedance, mitigate Miller effect

• Common drain

– Buffer, level shifter

• Differential pair


Feedback (1)

• Desensitizes circuit to (forward-) gain variations

• Modifies port impedances

• Central quantity of interest: Loop gain T

– Quantifies static error

– Used to assess stability, phase and/or gain margin

– Helpful in calculating closed loop port impedances

• Finding T is simple

– E.g. break loop at transconductor, inject test current, calculate ratio of return and test current

• Typically need a dominant pole

– Hard to use more than 2-3 amplifier stages and maintain sufficient phase margin

311


Feedback (2)

• Impact of phase margin on step response – Excessive "ringing" for phase margin <60°– Fast settling for phase margin ~70°

• Impact of phase margin on closed loop AC response– Gain peaking for small phase margin; leads to larger 3-dB

bandwidth as a side effect

• Compensation techniques– Can use simple load compensation for single stage OTAs– Miller compensation is most popular for two-stage designs

• Can push parasitic zero to infinity using nulling resistor• Beware of tricks such as pushing the zero into the LHP to avoid

pole-zero doublets

– Cascode compensation• For designers with experience…


OTAs with Capacitive Feedback

• Primary application: Switched capacitor circuits

• Important performance metric: Settling time

– Small signal model fails when input exceeds "linear range"

– Slew rate ~ I/C

– ts = tlin + tslew

• High performance OTAs are usually implemented as fully differential circuits

– Need CMFB

– Better XXX-rejection than single ended circuits

– Easy to analyze, since circuit is "perfectly" balanced• Exceptions occur during transients, in presence of mismatch,

etc.

312


Electronic Noise

• Tends to set achievable power dissipation in circuits with high DR requirements

• Fundamental noise

– Thermal noise

• Technology related noise

– 1/f noise

• Increasing (noise limited) precision by "one bit" quadruples power dissipation!


References

• Self-biasing concept

– Beware of stability issues!

• Current references

– VDD, VGS, ∆VGS, VBE, ∆VBE - based approaches

– To first order, ∆VGS bias yields constant gm over temperature and process

• Voltage reference

– Bandgap

– Useful as a reference whenever there's a need to convert "bits to Volts" or "Volts to bits"

– Conceptually simple, but lots of second order issues

313

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