Mixed-Signal Group

Murmann

Mixed-Signal Group

Murmann

Future Directions in

Mixed-Signal IC Design

March 15, 2010

Boris Murmann

murmann@stanford.edu

Outline

A (superficial) snapshot of the semiconductor industry

The need for analog/mixed-signal interfaces

Research examples High-performance A/D converters

Medical ultrasound systems

Structural health monitoring

Neural prosthetics

Large area electronics

2

3

The Beginning of an Industry

Transistor

Bardeen, Brattain, Shockley, 1948

Integrated Circuit

Kilby, 1958

4

Moore’s Law

In 1965, Gordon Moore predicted exponential growth in the

number of transistors per integrated circuit

5

… And He was Right

[ITRS 2007]

6

A Gigantic (Economic) Feedback Loop

Science

+ ConstraintsEngineering/

Design MillState-of-the-Art

Time

Leverage

Mechanism

$$$

7

State-of-the-Art Semiconductor Fab

E.g. Intel’s “Fab 32” (Chandler, Arizona) ~ $3 Billion

8

State-of-the-Art Silicon Chips

Intel “Tukwila”

>2 Billion Transistors

Single-Chip GSM Radio

[Staszewski, ISSCC 2008]

45nm Technology (Intel)

Steve Cowden

THE OREGONIAN

July 2007

Transistors Will Continue to Shrink

10

Increasingly Complex Applications

11

[Walden Rhines]

Outline

A (superficial) snapshot of the semiconductor industry

The need for analog/mixed-signal interfaces

Research examples High-performance A/D converters

Medical ultrasound systems

Structural health monitoring

Neural prosthetics

Large area electronics

12

The Age of “Digital” Stuff

13

(!)

The Reality of Modern Electronic Systems

14

Signal

Processing

A/D

D/A

Signal

Conditioning

Signal

Conditioning

Sensors,

Transducers,

Antennas,

etc.

DigitalAnalog

CLK

Analog Interfaces are Everywhere

15

Digitally Assisted A/D Converters

Signal

Processing

A/D

D/A

Signal

Conditioning

Signal

Conditioning

Analog Media

and

Transducers

DigitalAnalog

CLK

Additional digital processing for

performance enhancement

16

ADC for a “Digital” Link

No analog error accumulation

Better scalability

Need efficient digital processing hardware

Need efficient high-speed ADC, typically > 10GS/s

17

ADC1

ADC2

ADCN

text

X(t) Y[n]

Time-Interleaving

1

2

N

18

Popular way to increase ADC throuhgput

ADC1

ADC2

ADCN

X(t) Y[n]

G1

Voff_2

G2

Voff_N

GN

Voff_1

text

Imperfections

1

2

N

19

Mismatches result in signal distortion Gain

Offset

Timing Skew

Our Focus: Timing Skew

20

1

2

(2-channel example)

Digital Backend

ADC1

ADC2

ADCN

X(t)

ADCCal

Y[n]

Clock

Skew Calibration Using Extra ADC

Statistics-based skew measurement in digital backend

Correction through analog adjustments

21

1

2

N

Cal

1 2

Digitally

adjustable

delay cells

N

Timing of Auxiliary ADC Phase

1

2

N

Cal

1

2

N

Cal

1 2

Digital Backend

ADC1

ADC2

ADCN

X(t)

ADCCal

Y[n]

Clock

22

1

2

N

Cal

Calibration Scheme

For each channel, adjust delay cells until correlation between

calibration ADC output and each slice are maximized

ADCCal can be 1-bit, “slow”

23

ADC1

ADC2

ADCN

X(t)

ADCCal

Y[n]

ClockMax

1

2

N

Cal

1 2

R()

Experimental results deleted….

24

Cell Phones vs. Medical Ultrasound

Today’s cell phones Leverage highly

optimized, power & cost

efficient integration

Today’s ultrasound

machines Lots of progress in

miniaturization

Insufficient progress in

holistic system

optimization, SoC

integration and cost

reduction

Today’s System Architecture

N = 16…512

Piezo Elements

Digitization path

(~12b, 50MS/s)

using discrete

components

replicated N times

[TI]

Working on the Next-Gen Front-End

Fly-by-Feel Aircraft

28

Fly-by-Feel Autonomous Vehicle

Intelligent, Self-Repairing Materials

Multi-Scale Fabrication and

Integration

Stretchable Network

[Fu-Kuo Chang]

Stretchable Network

29

[Fu-Kuo Chang]

Interface for Structural Health Monitoring

30

Neural Prosthetics

Cortical motor prosthetics Neurons in the motor cortical areas of the brain encode

information about intended movement

31Courtesy K.V. Shenoy Courtesy L.R. Hochberg

Nature Magazine June „06

Neural Signal Acquisition

Electrode signals consist of multiple sources DC Offset, about 15mV from electrode/tissue interface

Local field potential (LFP), ≤3mV peak, 10Hz to 100Hz

Spikes from nearby neurons, 35μV – 1mV peak, 500Hz to 5kHz

32

Courtesy C.L. KlaverCourtesy M. Sahani

Specs

33

Spikes Local Field Potential

Gain 600 V/V 200 V/V

Lower Cutoff 300Hz 1Hz

Upper Cutoff 10kHz 1kHz

Input Referred Noise

(total from sampling node)2.0µVrms 1.0µVrms in 10-100Hz

Total Power (96x Array) 3mW 100µW

Separate the fast and slow signal acquisition for DR Custom front end design for each path

Spike Path Front-End

34

Input Stage

SC

Bandpass

Filter

SAR ADC

Input Cap

Output

Buffers

Sampling Phase

35

Integrate signal current on

CB and sample

High-pass for DC block

using Cac and Rbig (off-

resistance)

A1 contains a pole that

helps minimize noise

folding

A1 Implementation Details

36

ITAIL I<< ITAIL

Voutp

Voutm

VB1

VB2

M1a M1b

Flicker noise

reduction

Anti-alias for

thermal noise

from M1a,b

Processing Phase

37

Process charge on CB

SC biquadratic filter

Output buffers make a

post-filtering pole and

reduce A2’s load cap

Static Power

38

Two-Channel Interface Pixel

39

Frontend

SAR ADC

Die Photo (96 channels, 5mm x 5mm)

40

The Future?

41

Organic Semiconductors

Mechanically flexible

Suitable for solution processing Cover large areas at low cost

Make disposable devices

42

Jellyfish Autonomous Node

43

http://muri.mse.vt.edu/

Jellyfish Bell Prototype (Virginia Tech)

44

A bio-inspired shape memory alloy composite (BISMAC) actuator

A .A .Villanueva, et al., 2010 Smart Mater. Struct. 19 025013 (17pp)

Want to Make Plastic ADCs !

45

6-bit A/D Converter Prototype

46

W. Xiong, U. Zschieschang, H. Klauk, and B.

Murmann, “A 3V, 6b Successive Approximation ADC

using Complementary Organic Thin-Film Transistors

on Glass,” ISSCC 2010.

Substrate Glass

Interconnect Ti/Au evaporation, litho, wet etch

Gate electrodes Al evaporation, shadow masking

Source/Drain Au Evaporation, shadow masking

Dielectric 5.7nm AlOx/SAM

PFET DNTT, ~0.5 cm2/Vs

NFET F16CuPc, ~0.02 cm2/Vs

Area 28mm x 22mm

Component count 74

ADC Schematic

47

VREFN

C/32 C/32C/32

...

...

Bit 0 Bit 1 Bit 5Bit 2, 3, 4

Input

SAR Logic

(off-chip)

Output

To DAC

ComparatorDAC with

Sampler

C CCC 2C 2C

VREFN VREFNVREFP VREFNVREFP VREFP VMID

VREFPVMID

VREFN

Calibration DAC

Main DAC

Calibration enables 6-bit

precision despite poorly

matched capacitors

C-2C structure

possible due

small stray

caps (glass)

Comparator

48

CS1 CS2 CS3 CS4

CLK

CLK

CLK

CLK

CLK

CLK

CLK

CLK

Wp = 500um

Wn = 500um

Lp = Ln = 20um

CS1 = 1.1nF

A0 = -7.8

= 3.0ms

Wp = 400um

Wn = 400um

Lp = Ln = 20um

CS2 = 1.1nF

A0 = -9.8

= 4.0ms

Wp = 400um

Wn = 400um

Lp = Ln = 20um

CS3 = 1.1nF

A0 = -9.8

= 4.0ms

Wp = 100um

Wn = 300um

Lp = Ln = 20um

CS4 = 1.1nF

A0 = -19.6

= 16.4ms

Transmission Gates:

Wp = Wn = 100um

Lp = Ln = 20um

CF1 CF2 CF3 CF4

+ -

Input Output

Auto-zeroing

cancels threshold

voltage drift

Anti-parallel PFET/NFET

layout minimizes variations

if CF due to misalignment

CgdnCgdp

0 8 16 24 32 40 48 56 63-4

-2

0

2

4D

NL

(L

SB

)

Code

0 8 16 24 32 40 48 56 63-4

-2

0

2

4

Code

INL

(L

SB

)

Measured DNL/INL

49

Before calibration, 100 Hz clock rate

0 8 16 24 32 40 48 56 63-1

-0.5

0

0.5

1D

NL

(L

SB

)

Code

0 8 16 24 32 40 48 56 63-1

-0.5

0

0.5

1

Code

INL

(L

SB

)

Measured DNL/INL

50

After calibration, 100 Hz clock rate

ADC Summary

51

Process3 metal complementary

organic thin-film

Minimum feature size 20 mm

Chip area 28 mm x 22 mm

Resolution 6 bits

Full-scale range 2 V

Max DNL / INL -0.6 LSB / 0.6 LSB

Clock rate / Update rate 100 Hz / 16.7 Hz

Power consumption 3.6 mW @ 3 V

Summary

More than 50 years of R&D in integrated circuit

technology & design have created an incredibly powerful

platform for electronic information processing We are only beginning to understand what we can do with the

“billions” of transistors available today

Virtually all of today’s systems rely on highly

sophisticated analog-digital interfaces This makes my job exciting

No apparent “technological” end of innovation in sight

52

53

Murmann Mixed-Signal Group