[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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1. Tabel Kebenaran AND Gate

A B Output

0 0 0

0 1 0

1 0 0

1 1 1

A B Output

0 0 0

A B Output

0 1 0

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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A B Output

1 0 0

A B Output

1 1 1

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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Tabel Kebenaran OR Gate

A B Output

0 0 0

0 1 1

1 0 1

1 1 1

A B Output

0 0 0

A B Output

0 1 1

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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A B Output

1 0 0

A B Output

1 1 1

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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Tabel Kebenaran NOT Gate

A Output

0 1

1 0

A Output

0 1

A Output

1 0

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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Tabel Kebenaran NAND Gate

A B Output

0 0 1

0 1 1

1 0 1

1 1 0

A B Output

0 0 1

A B Output

0 1 1

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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A B Output

1 0 1

A B Output

1 1 0

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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Tabel Kebenaran NOR Gate

A B Output

0 0 1

0 1 0

1 0 0

1 1 0

A B Output

0 0 1

A B Output

0 1 0

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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A B Output

1 0 0

A B Output

1 1 0

[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015

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