Siste Digital Logika Gate
10
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015 1 | Page 1. Tabel Kebenaran AND Gate A B Output 0 0 0 0 1 0 1 0 0 1 1 1 A B Output 0 0 0 A B Output 0 1 0
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Transcript of Siste Digital Logika Gate
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
1 | P a g e
1. Tabel Kebenaran AND Gate
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
A B Output
0 0 0
A B Output
0 1 0
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
2 | P a g e
A B Output
1 0 0
A B Output
1 1 1
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
3 | P a g e
Tabel Kebenaran OR Gate
A B Output
0 0 0
0 1 1
1 0 1
1 1 1
A B Output
0 0 0
A B Output
0 1 1
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
4 | P a g e
A B Output
1 0 0
A B Output
1 1 1
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
5 | P a g e
Tabel Kebenaran NOT Gate
A Output
0 1
1 0
A Output
0 1
A Output
1 0
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
6 | P a g e
Tabel Kebenaran NAND Gate
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
A B Output
0 0 1
A B Output
0 1 1
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
7 | P a g e
A B Output
1 0 1
A B Output
1 1 0
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
8 | P a g e
Tabel Kebenaran NOR Gate
A B Output
0 0 1
0 1 0
1 0 0
1 1 0
A B Output
0 0 1
A B Output
0 1 0
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
9 | P a g e
A B Output
1 0 0
A B Output
1 1 0
[JASA EVAN SIPAYUNG - 141421003] 30 Maret 2015
10 | P a g e
