June 9, 2006
Revision B
Development Board Instruction Manual ADC08D1000DEV - Dual 8-Bit, 1.0 GSPS, 1.6W A/D Converter with
Xilinx Virtex 4 (XC4VLX15) FPGA
© Copyright 2006 National Semiconductor Corporation
AD
C08D
1000DEV D
evelopment B
oard User’s G
uide
2
ADC08D1000EVAL BOARD USER MANUAL – TABLE OF CONTENTS
ADC08D1000EVAL BOARD USER MANUAL – TABLE OF CONTENTS ................................................. 2 1.0 Introduction ........................................................................................................................................... 3 2.0 Board Assembly .................................................................................................................................... 3 3.0 Quick Start ............................................................................................................................................ 3 4.0 Functional Description .......................................................................................................................... 4
4.1 Input circuitry ...................................................................................................................................... 4 4.2 ADC reference ................................................................................................................................... 4 4.3 ADC clock........................................................................................................................................... 4 4.4 Digital Data Output............................................................................................................................. 4 4.5 Power Requirements.......................................................................................................................... 5 4.6 Power Supply Connections................................................................................................................ 5
5.0 Obtaining Best Results ......................................................................................................................... 5 5.1 Clock Jitter.......................................................................................................................................... 5
6.0 Evaluation Board Specifications ........................................................................................................... 5 7.0 Schematic Drawing ADC08D1000DEV – Onboard Clock (VCO + PLL) .............................................. 6
7.1 Schematic Drawing ADC08D1000DEV – Analog Inputs (I,Q) & Digital Trigger Input....................... 7 7.2 Schematic Drawing ADC08D1000DEV – ADC connected to Virtex4 FPGA..................................... 8 7.3 Schematic Drawing ADC08D1000DEV – USB Interface................................................................... 9 7.4 Schematic Drawing ADC08D1000DEV – Power Supplies 1 ........................................................... 10 7.5 Schematic Drawing ADC08D1000DEV – Power Supplies 2 ........................................................... 11 7.6 Schematic Drawing ADC08D1000DEV – Expansion Header Interface .......................................... 12
8.0 Bill of Materials (Page 1 of 2).............................................................................................................. 13 8.1 Bill of Material (Page 2 of 2)............................................................................................................. 14
9.0 Using the Wavevision4 software with the ADC08D1000DEV ............................................................ 15 9.1 Getting Started ................................................................................................................................. 15 9.2 Control Panel ................................................................................................................................... 17 9.3 Serial Control Mode ......................................................................................................................... 19 9.4 Capturing Waveforms ...................................................................................................................... 20
10.0 Appendix A - Hardware Information.................................................................................................. 20 10.1 LED functions................................................................................................................................. 20 10.2 Expansion Header.......................................................................................................................... 21 10.3 System Block Diagram................................................................................................................... 22
11.0 Appendix B - Installing and running the Wavevision 4 software....................................................... 23 11.1 Install the WaveVision Software. ................................................................................................... 23 11.2 Java™ Technology ........................................................................................................................ 23 11.3 Automatic Device Detection & Configuration................................................................................. 23 11.4 Windows Driver .............................................................................................................................. 23
12.0 Appendix C - Using WaveVision Plots.............................................................................................. 24 The Waveform Plot ................................................................................................................................ 24 The FFT Plot .......................................................................................................................................... 24 FFT Options ........................................................................................................................................... 25 Histogram Plots ...................................................................................................................................... 26 Information Viewer ................................................................................................................................. 26 Data Import and Export .......................................................................................................................... 26
3
1.0 Introduction The ADC08D1000DEV Board is designed to allow quick evaluation and design development of National Semiconductor’s ADC08D1000 8-bit Analog-to-Digital Converter. This device is specified for 1.0 GSPS operation in 2 channel mode or it can be configured as a 2GSPS Converter in Dual Edge Sampling mode (DES)
This development board is designed to function with National Semiconductor’s WaveVision Software, for fast evaluation. It requires only 3 connections to get started: a Power Supply, a USB Interface to PC and a Signal Source. A 1.0GHz Clock generator is provided on board
and the system also allows an external clock to be used if alternative sample rates are required.
The ADC connects to a Xilinx Virtex4 FPGA which stores up to 4K of data from each channel before transferring it through the USB interface to the PC.
2.0 Board Assembly The ADC08D1000 Development Board comes in a low profile plastic enclosure and requires no assisted cooling due to its low power consumption. The ADC08D1000 device is configured entirely through software and also allows changes to easily be made to the FPGA configuration to enable system development.
Analog Q Channel Input
USB
Figure 1 Component Placement & Front Panel
PWR INPUT
Clock Input
Trigger Input
Expansion
PWR SWITCH
Analog I Channel Input
4
3.0 Quick Start Refer to Figure 1 for locations of the power connection, signal input and USB port.
IMPORTANT NOTE: Install the Wavevision 4 Software before connecting this product to the PC. See Appendix B – Installing Wavevision. For quick start operation:
1. Connect the 12V DC power source (included with the development board) to the rear Power Connector labeled (8-12V DC).
2. Connect a stable sine wave source capable of supplying the desired input frequencies at up to 8 dBm. Connect this signal to the front panel SMA connector labeled “I CH.” through a band pass filter. The exact level needed from the generator will depend upon the insertion loss of the filter used.
3 Connect the USB cable (included) from the USB port to the PC. If this is the first time the board has been connected, Windows may install the drivers for this product at this time.
5. Push the Power Switch to the ON position on the rear panel and check that the Green LED between the switch and the power connector illuminates.
6. Start the Wavevision 4 Software 7. Once loaded the “Firmware Download”
Progress bar should be displayed. See Appendix B for more information.
8. Upon Firmware Download completion, the control panel for the board should automatically be displayed on the PC and the CLK LED on the front panel should be flashing.
8. Set the signal source for the analog input to 8 dBm at the desired frequency. Observe the Out of Range LED labeled OVR on the front panel is illuminated. If this LED is not on, increase the input signal source until it is.
9. Reduce the input level until the OVR LED just turns off.
10. From the Wavevision 4 pull-down menu select Acquire and then Samples. The system will then capture the input waveform and display the results in the time domain.
11. For FFT Analysis click the FFT Tab.
4.0 Functional Description The ADC08D1000 Development Board schematic is shown in Section 7.0.
4.1 Input circuitry The input signal(s) to be digitized should be applied to the front panel SMA connectors labeled “I CH.” and “Q CH.”. These 50 Ohm inputs are intended to accept low-noise sine wave signals. To accurately evaluate the dynamic performance of this converter, the input test signals will have to be passed through a high-quality bandpass filter with at least 10-bit equivalent noise and distortion characteristics.
This evaluation board as delivered is set up for operation with two single-ended analog inputs, which are converted to differential signals on board.
Signal transformers T2 and T3, are connected as baluns, and provide the single-ended to differential conversion. The differential PCB traces to the ADC analog input pins have a characteristic differential impedance of 100 Ohms.
No scope or other test equipment should be connected anywhere in the signal path while gathering data.
4.2 ADC reference The ADC08D1000 has an internal reference that can not be adjusted. However, the Full-Scale (differential) Range may adjusted with the Software Control Panel Refer to Section 9.0 for more information
4.3 ADC clock The ADC clock is supplied on board and is fixed at 1.0GHz. An external clock signal may be applied to the ADC through the SMA Connector labeled “CLOCK” on the front panel. The balun-transformer (T1) converts the single ended clock source to a differential signal to drive the ADC clock pins
Note that it is very important that the ADC clock should be as free of jitter as possible or the apparent SNR of the ADC08D1000 will be compromised.
4.4 Digital Data Output The two channel digital output data from the ADC08D1000 is connected to a Xilinx Virtex 4 FPGA. Up to 4K Bytes of data per channel can be stored and then uploaded over the USB interface to the Wavevision 4 software. The FPGA logic usage is low allowing further code to be written and tested for product development.
5
4.5 Power Requirements The power supply requirement for the ADC08D1000 Evaluation Board is 12V at 800mA.
Most of the regulators on board are switching regulators for increased power efficiency.
The board typically draws around 500mA but it is always good practice to have extra power reserve in the power supply over the typical power requirements.
A Universal 100-240V AC input to 12V DC Brick Power Supply is included with the development board.
4.6 Power Supply Connections Power to this board is supplied through the power connector on the rear panel. It is advised that only the supplied PSU is used with this board.
The ADC08D1000 supply voltage has been set to 1.9V, ±50 mV using on board regulators.
5.0 Obtaining Best Results Obtaining the best results with any ADC requires both good circuit techniques and a good PC board layout. For layout information for this product please contact you nearest National Semiconductor representative.
5.1 Clock Jitter When any circuitry is added after a signal source, some jitter is almost always added to that signal. Jitter in a clock signal, depending upon how bad it is, can degrade dynamic performance. We can see the effects of jitter in the frequency domain (FFT) as "leakage" or "spreading" around the input frequency, as seen in Figure 2a. Compare this with the more desirable plot of Figure 2b. Note that all dynamic performance parameters (shown to the right of the FFT) are improved by eliminating clock jitter.
Figure 2a. Jitter causes a spreading around the input signal, as well as undesirable signal spurs.
Figure 2b. Eliminating or minimizing clock jitter results in a more desirable FFT that is more representative of how the ADC actually performs.
6.0 Evaluation Board Specifications
Board Size: 168mm x 100mm
Power Requirements: +12V, 800mA
Clock Frequency Range : 200 MHz to 1.0 GHz
Analog Input Range (AC Coupled) 30MHz to 1800MHz
Nominal Analog Input Voltage: 560 mV P-P to 870 mV P-P
Impedance: 50 Ohms
6
7.0 Schematic Drawing ADC08D1000DEV – Onboard Clock (VCO + PLL)
R1 10
5VRF
1V8I
O R6 10
C19
10n
L8 100M
Hz
C10
10n
C17
10n
SCLK
P4,5
PLL_
LEP5
SDAT
AP4
,5
C110
0pF
C2 100p
F
C3 470p
FC4 1u
F
C18
100p
FC1
610
0pF
PROJ
ECT
NAME
:
LAST
MOD
IFIE
D:Sh
eet
OF
THIS
DOC
UMEN
T CO
NTAI
NS IN
FORM
ATIO
N P
ROPR
IETA
RY T
O NA
TION
AL S
EMIC
ONDU
CTOR
COR
PORA
TION
. USE
WIT
HOUT
WRI
TTEN
PER
MIS
SION
IS E
XPRE
SSLY
FOR
BIDD
EN. C
OPYR
IGHT
2001
.
DATE
:
DATE
:CH
ECKE
D:
DRAW
N:
SCHE
MATI
C RE
V:
DOC
# :NA
TION
AL S
EMIC
ONDU
CTOR
COR
PORA
TION
DCS
PROD
UCT
LINE
2900
Sem
icond
ucto
r Driv
e, S
anta
Clar
a
DESI
GNED
:DA
TE:
PAGE
TIT
LE
28
BIG
GIG
REFE
RENC
E BO
ARD
1.1
____
____
____
IAN
KING
24 /
OCT
/ 200
5
DD /
MMM
/ YYY
Y
____
____
____
Wed
nesd
ay, F
ebru
ary
08, 2
006
IAN
KING
24 /
OCT
/ 200
5__
____
____
____
____
___
____
____
____
____
____
_
____
____
____
____
____
_
CLOC
K IN
PUT
1V8I
O
5VRF
1V8I
OP3
,5,7
,8
R147
18
C9 100p
F
R17 10K
U2
LMX2
31x
NC-1
1CP
o2
GND
3Fi
n4
Finb
5OS
Cin
6NC
-27
OSCout8 FoLD9 CLOCK10
NC-3
11
Data
12
LE13
GND
14
CE15
Vuc
16
NC-4
17VCC 18FL 19Vp 20
CERAMIC ON
LY
VIN
P6,7
,8
5VRF
VIN
VIN
R149
10K
R150 10K
C
BE
31
2
Q8 BC81
7-25
T1
ADTL
2-18
16
34
25
R148
100K
C12
1500
pF
C8 27nF
R9 2K7
C5 470p
F
U3 VCO1
90
GND-
11
Vt2
GND-
23
GND-
34
GND-4 5MOD 6GND-5 7GND-6 8GN
D-7
9RF
_OUT
10GN
D-8
11GN
D-9
12
GND-1013 VCC14 GND-1115 GND-1216
R13
NA
3V3I
OP3
,5,6
,7,8
3V3I
O
3V3I
O
R810
K
C13
470p
F
5VRL
YP3
,6
5VRL
Y
Y110
MHz
EXTE
RNAL
CLOC
KIN
PUT
C159
470p
F
C15
4n7
C14
4n7
J3
SMA
1 2 3
4 5
U1 RELA
Y-RF
303
C11XA2X13X24 Y2 6
Y1 7
YA 8
C2 95VRL
Y
C
BE
31
2
Q1 BC81
7-25
R7 10K
1V8I
O
C7
100p
F
R4 270R3
18
R5 270
C6
100p
F
C11
100p
F
R14
100
R16
10K
EXT_
CLK_
SELE
CTP5
CLKI
N_P
P4
CLKI
N_N
P4
R2 680
U24
LP29
86
GROU
ND1
FEED
BACK
2
TAP
3
INPU
T4
OUTP
UT5
SENS
E6
ERRO
R7
SHDN
8
C110
10uF
R143
18R1
4418
C111
10uF
R10
18
R12
18
C112
100n
7
7.1 Schematic Drawing ADC08D1000DEV – Analog Inputs (I,Q) & Digital Trigger Input
+-
VOC
MXP
AD
U5
LMH
6555
11
5 16
6
8 13 10
912
12
34
714
15
17
RELA
YBYPA
SSOPTI
ONS
NC A GND
YVCC
U8
74LV
C1G
17
1 2 345
1V8I
O
5VR
LY
C23
100n
C21
100n
C28
100n
5VR
LY
C20
100n
I-CHANNEL
Q-CH
ANNEL
TRIGGER_
IN
R35 10K
R26
10K
R13
1
47
R18
N/A
3V3I
O
R21
0
R14
518
K
R14
610
0K
CHANGE
R A
BOVE T
OCA
P FO
R AC
COUPLI
NG T
O LM65
55
VCM
OP4
DC
_SEL
ECT
P5
I_P
P4
I_N
P4
Q_N
P4
Q_P
P4
TRIG
_IN
P5
R13
8
0
C22
N/A
3V3I
O
1V8I
O
5VR
LY
1V8I
OP2
,5,7
,8
5VR
LYP2
,6
3V3I
OP2
,5,6
,7,8
NO S
TUFF
WIRE
MOD
IFICAT
ION
AS S
PECIFI
ED I
N MANU
FACT
URING
AND
ASSE
MBLY D
OC
C15
810
0n
R24
N/A
12
JP3
C15
610
0n
3V3I
OL1
410
0MH
z
PRO
JEC
TN
AME:
LAST
MO
DIF
IED
:Sh
eet
OF
THIS
DO
CU
MEN
T C
ON
TAIN
S IN
FOR
MAT
ION
PR
OPR
IETA
RY
TO N
ATIO
NAL
SEM
ICO
ND
UC
TOR
CO
RPO
RAT
ION
. USE
WIT
HO
UT
WR
ITTE
N P
ERM
ISSI
ON
IS E
XPR
ESSL
Y FO
RBI
DD
EN. C
OPY
RIG
HT
2001
.
DAT
E:
DAT
E:C
HEC
KED
:
DR
AWN
:
SCH
EMAT
IC R
EV:
DO
C #
:NAT
ION
AL S
EMIC
ON
DU
CTO
R C
OR
POR
ATIO
ND
CS
PRO
DU
CT
LIN
E
2900
Sem
icon
duct
or D
rive,
San
ta C
lara
DES
IGN
ED:
DAT
E:
PAG
E TI
TLE
38
BIG
GIG
REFE
RENC
E BO
ARD
1.1
____
____
____
IAN
KIN
G24
/ O
CT
/ 200
5
DD
/ M
MM
/ Y
YY
Y
____
____
____
Tues
day,
Apr
il 04
, 200
6
IAN
KIN
G24
/ O
CT
/ 200
5__
____
____
____
____
___
____
____
____
____
____
_
____
____
____
____
____
_
ANAL
OG
INPU
TS
C15
733
uF
R13
50
R13
2N
A
R13
3N
A
R13
6N
/A
J2
SMA
1 2 3
4 5
J1
SMA
1 2 3
4 5 J4
SMA
1 2 3
4 5
U4
REL
AY-R
F303
C1
1
XA2
X13
X24
Y2
6Y
17
YA
8C
29
U6 REL
AY-R
F303
C11XA2X13X24 Y2 6
Y1 7
YA 8
C2 9
5VR
LY
V+ VSS
V-YVC
C
U31
LM32
1_SO
T23
1 2 345
C15
510
0n
R13
7N
/A
T2
ADTL
2-18
16
34
25
T3
ADTL
2-18
16
34
25
C24
4n7
R27 100
C25
4n7
C
BE
31
2
Q2
BC81
7-25
C
BE
31
2
Q3
BC81
7-25
C27
4n7
R30 100
C26
4n7
R28
10K
R29 10
K
VCMO
CON
NECTS
TO G
ROUND
WHEN
AC C
OUPL
ING IS
SEL
ECTED
R25
10K
R19 0
R22 0
R13
449
.9
8
7.2 Schematic Drawing ADC08D1000DEV – ADC connected to Virtex4 FPGA
9
7.3 Schematic Drawing ADC08D1000DEV – USB Interface
C50
100n
R68
10k
C51
100n
C52
100n
R63
1M
C53
100n
C54
100n
3V3I
O
SLAV
E SE
RIAL
MAST
ER S
ERIA
L
3V3
A B
R76 N
/A
R12
73.
3K
J51 2 3 4 5 6
3V3I
O
PR
OG
RA
MB
A B
R59
10K
MAST
ERSE
RIAL
SLAV
ESE
RIAL
MS
TR_S
DA
TA
3V3I
O
MS
TR_S
CLK
PR
OJE
CT
NA
ME
:
LAS
T M
OD
IFIE
D:
She
etO
F
THIS
DO
CU
MEN
T C
ON
TAIN
S IN
FOR
MAT
ION
PR
OPR
IETA
RY
TO N
ATIO
NAL
SEM
ICO
ND
UC
TOR
CO
RPO
RAT
ION
. USE
WIT
HO
UT
WR
ITTE
N P
ERM
ISSI
ON
IS E
XPR
ESSL
Y FO
RBI
DD
EN. C
OPY
RIG
HT
2001
.
DA
TE:
DA
TE:
CH
EC
KE
D:
DR
AW
N:
SC
HE
MA
TIC
RE
V:
DO
C #
:NA
TIO
NA
L S
EM
ICO
ND
UC
TOR
CO
RP
OR
ATI
ON
DC
S P
RO
DU
CT
LIN
E
2900
Sem
icon
duct
or D
rive,
San
ta C
lar a
DE
SIG
NE
D:
DA
TE:
PA
GE
TIT
LE
58
BIG
GIG
REF
EREN
CE
BO
AR
D
1.1
____
____
____
IAN
KIN
G24
/ O
CT
/ 20
05
DD
/ M
MM
/ Y
YY
Y
____
____
____
Wed
nesd
ay,
Feb
ruar
y 0
8, 2
006
IAN
KIN
G24
/ O
CT
/ 20
05V
4 F
LAS
H C
ON
FIG
LED
STA
TUS
____
____
____
____
____
_
US
B C
ON
TRO
LLE
R
U16
74LV
C54
1
I02
I13
I24
I35
I46
I57
I68
I79
OE11
OE
219
O0
18O
117
O2
16O
315
O4
14O
513
O6
12O
711
GND10
VC
C20
R75
N/A
R77
N/A
R12
833
0R
3V3I
O
CY
_DA
TA12
3V3I
O
CO
NF
_CC
LK
RE
SE
TB
TRIG
_IN
P3
MS
TR_D
ATA
P8
MS
TR_S
CLK
P8
FP
GA
_RE
SE
TP
8
CY
_DA
TA13
DC
_SE
LEC
TP
3
3V3I
O
EXT
_CLK
_SE
LEC
TP
2
DC
_SE
LEC
T
C69
100n
U15
24C
02/S
O8
A0
1
A1
2
A2
3
GN
D4
SD
A5
SC
L6
WP
7
VC
C8
EXT
_CLK
_SE
LEC
T
C68
100n
CY
_DA
TA14
C70
100n
C67
100n
C71
100n
3V3
V4_
TMS
FP
GA
_RE
SE
TP
8
EC
M_F
SR
P4
CA
LIB
RA
TEP
4
V4_
TDO
SC
LKP
2,4
SD
ATA
P2,
4
AD
C_C
SP
4
TP3
TP_C
Y_C
LK
1
PO
WE
R_D
OW
NP
4 PO
WE
R_D
OW
N_Q
P4
V4_
TCK
MS
TR_S
DA
TA
Y3
OS
C (
SM
)
VDD4
GND2
OE
1O
UT
3
C57
100n
MS
TR_S
CLK
U9C
XC4V
LX15
_363
FB
GA
IO_L
1P_G
C_C
C_L
C_3
B12
IO_L
8N_G
C_C
C_L
C_4
W8
IO_L
1N_G
C_C
C_L
C_3
A11
IO_L
2P_G
C_V
RN
_LC
_3A
10
IO_L
2N_G
C_V
RP
_LC
_3B
9
IO_L
3P_G
C_L
C_3
C11
IO_L
3N_G
C_L
C_3
B11
IO_L
4P_G
C_L
C_3
B10
IO_L
4N_G
C_V
RE
F_L
C_3
C10
IO_L
5P_G
C_L
C_3
B13
IO_L
5N_G
C_L
C_3
A13
IO_L
6P_G
C_L
C_3
A8
IO_L
6N_G
C_L
C_3
B8
IO_L
7P_G
C_L
C_3
B14
IO_L
7N_G
C_L
C_3
A14
IO_L
8P_G
C_L
C_3
A7
IO_L
8N_G
C_L
C_3
B7
IO_L
1P_G
C_L
C_4
W13
IO_L
1N_G
C_L
C_4
W12
IO_L
2P_G
C_L
C_4
Y5
IO_L
2N_G
C_L
C_4
W5
IO_L
3P_G
C_L
C_4
Y12
IO_L
3N_G
C_L
C_4
Y11
IO_L
4P_G
C_L
C_4
Y6
IO_L
4N_G
C_V
RE
F_L
C_4
W6
IO_L
5P_G
C_L
C_4
W11
IO_L
5N_G
C_L
C_4
W10
IO_L
6P_G
C_L
C_4
Y7
IO_L
6N_G
C_L
C_4
W7
IO_L
7P_G
C_V
RN
_LC
_4Y
10
IO_L
7N_G
C_V
RP
_LC
_4Y
9
IO_L
8P_G
C_C
C_L
C_4
W9
C15
41n
PO
WE
R_D
OW
N
C62
1n
CY
_DA
TA15
3V3I
O
2V5I
O
C63
100n
1V8I
O
C61
1n
3V3
C56
1uF
3V3
P7,
8
U14
XCF
08P
_VO
48 N
/A
OE
/RS
T11
CE
O10
CLK
OU
T9
VC
CO
-18
GN
D-2
7C
F6
BU
SY
5V
CC
INT-
14
DN
C-1
142
DN
C-1
041
DN
C-9
40
DN
C-8
39
VC
CO
-338
DN
C-7
37
GN
D-7
36
DN
C-6
35
VC
CIN
T-3
34
DN
C-2
3G
ND
-12
VC
CIN
T-2
15
GN
D-4
17
TDI
19
TMS
21
VC
CJ
24R
V_S
EL0
26D
028
VC
CO
-230
DN
C-4
16
DN
C-5
18
TCK
20
TDO
22
EN
_XS
EL
25R
V_S
EL1
27D
129
GN
D-6
31
DN
C-1
1
CLK
12
DN
C-3
14
D3
33
D4
43D
544
CE
13
D2
32
GN
D-5
23
VC
CO
-445
GN
D-8
46D
647
D7
48
US
B_P
OW
ER
P7
SC
LS
DA
CO
NF
_CC
LK
3V3I
O
C60
100n
CY
_DA
TA13
CY
_DA
TA11
CY
_DA
TA9
CY
_DA
TA15
CY
_DA
TA7
CY
_DA
TA0
CY
_DA
TA8
CY
_DA
TA14
CY
_DA
TA12
CY
_DA
TA6
CY
_DA
TA1
CY
_DA
TA2
D1 1N
4148
W
12
U9B
XC4V
LX15
_363
FB
GA
IO_L
1P_D
31_L
C_1
F15
IO_L
8N_D
0_LC
_2U
9
IO_L
1N_D
30_L
C_1
E15
IO_L
2P_D
29_L
C_1
E6
IO_L
2N_D
28_L
C_1
F6
IO_L
3P_D
27_L
C_1
D15
IO_L
3N_D
26_L
C_1
E14
IO_L
4P_D
25_L
C_1
E7
IO_L
4N_D
24_V
RE
F_L
C_1
D6
IO_L
5P_D
23_L
C_1
D13
IO_L
5N_D
22_L
C_1
C13
IO_L
6P_D
21_L
C_1
C8
IO_L
6N_D
20_L
C_1
D8
IO_L
7P_D
19_L
C_1
D12
IO_L
7N_D
18_L
C_1
C12
IO_L
8P_D
17_C
C_L
C_1
C9
IO_L
8N_D
16_C
C_L
C_1
D9
IO_L
1P_D
15_C
C_L
C_2
V16
IO_L
1N_D
14_C
C_L
C_2
V15
IO_L
2P_D
13_L
C_2
V6
IO_L
2N_D
12_L
C_2
V5
IO_L
3P_D
11_L
C_2
T14
IO_L
3N_D
10_L
C_2
U13
IO_L
4P_D
9_LC
_2U
8
IO_L
4N_D
8_V
RE
F_L
C_2
T7
IO_L
5P_D
7_LC
_2V
13
IO_L
5N_D
6_LC
_2V
12
IO_L
6P_D
5_LC
_2V
9
IO_L
6N_D
4_LC
_2V
8
IO_L
7P_D
3_LC
_2U
12
IO_L
7N_D
2_LC
_2V
11
IO_L
8P_D
1_LC
_2V
10
3V3I
OP
2,3,
6,7,
8
2V5I
OP
4,6,
7
U13
LM95
221C
IMM
D1-
2
D2+
3
D2-
4G
ND
5V
DD
6S
MB
DA
T7
SM
BC
LK8
D1+
1
U12
Cy
pres
s C
Y7C
6461
3-80
NC
VCC41 VCC321 VCC241 VCC161
GND110
GND220
GND329
GND440
GND543
GND660
GND772
GND880
AVCC5
AGND8
NC
179
NC
278
NC
377
NC
467
NC
566
NC
656
NC
755
NC
846
NC
945
NC
1044
RE
SE
RV
ED
124
RE
SE
RV
ED
222
RE
SE
RV
ED
39
RE
SE
T#42
WA
KE
UP
#4
XIN
6
XOU
T7
DIS
CO
NN
#28
US
BD
-38
US
BD
+39
SD
A3
SC
L2
PA
0/T0
OU
T11
PA
1/T1
OU
T12
PA
2/O
E#
13
PA
3/C
S#
14
PA
4/F
WR
#/R
DY
415
PA
5/F
RD
#/R
DY
516
PA
6/R
XD0O
UT
17
PA
7/R
XD1O
UT
18
PB
0/T2
/D0/
GD
A0/
AF
I047
PB
1/T2
EX/
D1/
GD
A1/
AF
I148
PB
2/R
XD1/
D2/
GD
A2/
AF
I249
PB
3/TX
D1/
D3/
GD
A3/
AF
I350
PB
4/IN
T4/D
4/G
DA
4/A
FI4
51
PB
5/IN
T5#/
D5/
GD
A5/
AF
I552
PB
6/IN
T6/D
6/G
DA
6/A
FI6
53
PB
7/T2
OU
T/D
7/G
DA
7/A
FI7
54
PC
0/R
XD0/
RD
Y0
68
PC
1/TX
D0/
RD
Y1
69
PC
2/IN
T0#
70
PC
3/IN
T1#/
RD
Y3
71
PC
4/T0
/CTL
173
PC
5/T1
/CTL
374
PC
6/W
R#/
CTL
475
PC
7/R
D#/
CTL
576
PD
0/G
DB
0/B
FI0
30
PD
1/G
DB
1/B
FI1
31
PD
2/G
DB
2/B
FI2
32
PD
3/G
DB
3/B
FI3
33
PD
4/G
DB
4/B
FI4
34
PD
5/G
DB
5/B
FI5
35
PD
6/G
DB
6/B
FI6
36
PD
7/G
DB
7/B
FI7
37
RD
Y0/
AS
EL
63
PD
Y1/
BS
EL
64
RD
Y2/
AO
E65
RD
Y3/
BO
E25
RD
Y4/
SLW
R26
RD
Y5/
SLR
D27
CTL
0/A
INF
LAG
62
CTL
1/B
INF
LAG
57
CTL
2/A
OU
TFLA
G58
XCLK
59
XCLK
SE
L23
CLK
OU
T19
1V8I
OP
2,3,
7,8
C58
33pF
3V3
R60
47
C
BE
31
2
Q5
BC
817-
25
CO
NF
_DIN
C59
33pF
CO
NF
_DIN
V4_
TMS
P8
V4_
TDI
P8
V4_
TCK
P8
CO
NF
_DO
NE
CO
NF
_IN
ITB
NC A
GN
DYVC
C
U11
74LV
C1G
17
1 2 3
45
R61
47
CO
NF
_IN
ITB
3V3I
O
V4_
TCK
CY
_DA
TA[1
5:0]
CO
NF
_DO
NE
C55
100n
3V3I
O
R67
47
V4_
TMS
R79
51R
8051
DCI
RESI
STOR
SFO
R LV
DS
2V5I
O
nPO
WE
R_E
NP
6,8
1V8I
O
V4_
TDO
P8
R66
47
CA
PTU
RE
P8
RE
AD
P8
nAD
C_1
V9_
EN
nAD
C_1
V9_
EN
P6
R70
3.3K
C72
100n
R81
10k
STA
TE0
R82
10k
UPL
R83
10k
R84
10k
R85
10k
J6U
SB
-B
VB
US
1
D-
2
D+
3
GN
D4
SH
ELL
_15
SH
ELL
_26
STA
TE1
TRG
IDL
CLK
_AC
TIV
E_Q
STA
TE2
STB
CLK
R54
10k
R58
330R
PWR
R78
47
FLS
H_T
DO
OVR
SMP
STA
TE3
LOA
D_S
TATE
C64
100n
OV
RA
NG
E_Q
1V8I
O
3V3
SA
MP
LE
UP
LOA
DTR
IGG
ER
SA
MP
LE_Q
CY
_RE
Q
TRIG
GE
R_Q
RE
SE
TB
R62
0
UP
LOA
D_Q
FLS
H_T
DI
CY
_VA
LID
FP
GA
_RE
SE
T
BANK1 - 1.8V IOBANK3 - 2.5V LVDS
BANK2 - 3.3V CMOS
UP
LOA
D_Q
CO
NF
_DO
NE
TRIG
GE
R_Q
SC
LS
DA
SA
MP
LE_Q
3V3
OV
RA
NG
E_Q
R53
4.7K
IDLE
_QC
LK_A
CTI
VE
_Q
nPO
WE
R_E
N
nPOW
ER_E
N =
1 -
SWIT
CH R
EGS
SHUT
DOWN
(ST
ANDB
Y)nP
OWER
_EN
= 0
- SW
ITCH
REG
S AR
E ON
SDA/SCL - CROSSED WIRES - LIFT PINS
AND FIX WITH WIRE MODIFICATION
DC
LK_P
P4
DC
LK_N
P4
OV
R_N
P4
OV
R_P
P4
NC A GN
DYVC
C
U18
74LV
C1G
04
1 2 3
45
BANK4 - 3.3V CMOS
PR
OG
RA
MB
TP8
GN
D
1
C73
100n
CO
NF
_CC
LK
TP9
GN
D
1
CO
NF
_DIN
LD4
LED
_2x1
1234
STA
TE2
STA
TE1
CY
_VA
LID
R86
330R
STA
TE0
CY
_RE
Q
LOA
D_S
TATE
STA
TE3
Y2
12M
Hz
CO
NF
_IN
ITB
TP10
GN
D
1
R87
330R
PLL
_LE
P2
PLL
_LE
TP11
GN
D
1
R57 0
R88
330R
R89
330R
R90
330R
R91
330R
R92
330R
IDLE
LED
WILL
ILLU
MINM
ATE ON
LYWH
EN F
PGA
ISCO
NFIG
URED
3V3I
O
R93
330R
1V8I
O
C65
100n
C66
100n
1V8I
O
R74
1KR
731K
3V3I
O
3V3I
O
DO NOT FIT V4
CONFIG FLASH IF
CYPRESS USB
CONTROLLER IS
INSTALLED
FIT
IFCO
NFIG
FLAS
H NO
TIN
STAL
LED
AD
C_T
D_P
P4
AD
C_T
D_N
P4
LD1
LED
_2x1
1234
R64
47
LD2
LED
_2x1
1234
FIF
O_E
MP
TYP
8F
IFO
_FU
LLP
8
LD3
LED
_2x1
1234
AIN
BIN
GN
DYVC
C
U17
74LV
C1G
00
1 2 3
45
RE
SE
TB
1V8I
O
C74
100n
CY
_DA
TA5
OV
RA
NG
EID
LEC
LK_A
CTI
VE
3V3I
OC
Y_D
ATA
3
R94
3.3K
R95
3.3K
CY
_DA
TA0
CY
_DA
TA4
CY
_DA
TA10
CY
_DA
TA1
PO
WE
R_D
OW
N_Q
AD
C_C
S
CY
_DA
TA2
SC
LK
UP
LOA
D_Q
SA
MP
LE_Q
SD
ATA
CY
_DA
TA3
EC
M_F
SR
CA
LIB
RA
TE
CY
_DA
TA4
CY
_DA
TA5
R71
24.3
SW
1R
ES
ET
1 2
R69
3.3K
CY
_DA
TA6
3V3
A B
R56
0
CO
NF
_DO
NE
P8
CY
_DA
TA7
3V3
CY
_DA
TA8
PR
OG
RA
MB
USB POWER ON
& PB RESET
USB =>
EEPROM
CY
_DA
TA9
100MHz FPGA CLOCK REF
LVDS
CLO
CK A
ND O
VER
RANG
E IN
PUTS
FRO
M AD
C
R72
24.3
JTAG HEADER
TEMP SENSOR
CY
_DA
TA10
SC
LP
8S
DA
P8
U9A
XC4V
LX15
_363
FB
GA
HS
WA
PE
N_0
E13
CC
LK0
E11
D_I
N_0
E9
PR
OG
RA
M_B
_0F
12
INIT
_0E
12
CS
_B_0
E8
DO
NE
_0F
11
RD
WR
_B_0
F9
VB
ATT
_0T1
3
M2_
0R
11
PW
RD
WN
_B_0
T10
TMS
_0T8
M0_
0R
12
TDO
_0R
10
TCK
_0T9
M1_
0T1
2
DO
UT_
BU
SY
_0T1
1
TDI_
0R
9
TDN
_0E
10
TDP
_0F
10
CY
_DA
TA11
TRIG
_IN
R55
0
R65
1.5K
10
7.4 Schematic Drawing ADC08D1000DEV – Power Supplies 1
C89
10n
L17
100M
Hz
C16
522
uF
5VR
LY
13
2
L4PNCD
2
BZX8
4C5V
1
PLAC
E CL
OSE
TO P
IN 5
L3 10uH
SW2
RO
CKE
R2 13
3V3I
O
VIN
BST
GN
D
FBENSW
U19
LM27
34 T
SOT-
6
1 3
5 4
2
6
R10
44.
12K
C87
100n
13
2
L4PNCD
8
BZX8
4C5V
1
C75
10uF
PRO
JEC
TN
AME:
LAST
MO
DIF
IED
:Sh
eet
OF
THIS
DOC
UMEN
T CO
NTAI
NS IN
FORM
ATIO
N P
ROPR
IETA
RY T
O NA
TION
AL S
EMIC
ONDU
CTOR
COR
PORA
TION
. USE
OW
ITHO
UT W
RITT
EN P
ERM
ISSI
ON IS
EXP
RESS
LY F
ORBI
DDEN
. COP
YRIG
HT 20
01.
DAT
E:
DAT
E:C
HEC
KED
:
DR
AWN
:
SCH
EMAT
IC R
EV:
DO
C #
:NAT
ION
AL S
EMIC
ON
DU
CTO
R C
OR
POR
ATIO
ND
CS
PRO
DU
CT
LIN
E
2900
Sem
icon
duct
or D
rive,
San
ta C
lara
,
DES
IGN
ED:
DAT
E:
PAG
E TI
TLE
68
BIG
GIG
REFE
RENC
E BO
ARD
1.1
____
____
____
IAN
KIN
G24
/ O
CT
/ 200
5
DD
/ M
MM
/ Y
YY
Y
____
____
____
Wed
nesd
ay, F
ebru
ary
08, 2
006
IAN
KIN
G24
/ O
CT
/ 200
5__
____
____
____
____
___
____
____
____
____
____
_
____
____
____
____
____
_
POW
ER S
WIT
CH
ERS
C85
10uF
C76
10uF
C86
10uF
LD5
RED
12R
101
10.2
K
PLAC
E CL
OSE
TO P
IN 5
L5 10uH
R98 680
D11
10BQ
030
12
R99
22.1
K
C90
22uF
VIN
BST
GN
D
FBENSW
U21
LM27
34 T
SOT-
6
1 3
5 4
2
6
D9
1N41
48W
1 2
1V9
VIN
BST
GN
D
FBENSW
U20
LM27
34 T
SOT-
6
1 3
5 4
2
62V
5AU
XP7
L4 10uH
R10
510K
C78
100n
2V5I
OP4
,5,7
D5
1N41
48W
1 2
1V9
P43V
3IO
P2,3
,5,7
,8
D7
10BQ
030
12
C82
22uF
R10
210
.2K
POWE
R IN
LED
VIN
P2,7
,8
R97 4.12
K
POW
ER_E
N_T
P7
R10
022
.1K
13
2
L4PNCD
3
BZX8
4C5V
1
PLAC
E CL
OSE
TO P
IN 5
1 234
L2 CM
CH
OKE
nPO
WER
_EN
P5,8
J7 CO
NN
PW
R J
ACK231
C83
47uF
C84
100n
VIN
BST
GN
D
FBENSW
U22
LM27
34 T
SOT-
6
1 3
5 4
2
6
L6 10uH
D10
BAT4
2W 12
D12
10BQ
030
12
C91
22uF
R11
110
.2K
R10
932
.4K
PLAC
E CL
OSE
TO P
IN 52V
5IO
VIN
C
BE
31
2
Q7
BC81
7-25
C
BE
31
2
Q6
BC81
7-25
R10
6
10K1
2JP
1
R11
4
10K1
2JP
2
nAD
C_1
V9_E
NP5
R11
3
10K
D16
1N41
48W
1 2
D17
10BQ
030
12
C16
310
n
C16
422
uF
R14
254
K
C16
210
0n
R11
21K
13
2
L4PNCD
15
Z523
8BLT
1
R14
04.
12K
VIN
BST
GN
D
FBENSW
U32
LM27
34 T
SOT-
6
1 3
5 4
2
6
3V3I
O
PLAC
E CL
OSE
TO P
IN 5
ADC
SHOU
LD B
E PO
WERE
D OF
FWHIL
E FP
GA I
S CO
NFIG
URED
L16
10uH
R14
110
.2K
5VR
LYP2
,3
C16
110
uF
D6
10BQ
030
12
C81
22uF
D4
1N41
48W
1 2
R11
010
.2K
R10
814
.3K
R10
310
0K
R10
710
0K
R96 4.12
K
C88
10n
C77
100n
2V5A
UX
C79
10n
C80
10n
11
7.5 Schematic Drawing ADC08D1000DEV – Power Supplies 2
DO N
OT I
NSTA
LL
C12
447
uF
1V8I
O
3V3I
O
3V3
P5,8
1V8I
OP2
,3,5
,8
1V2
3V3I
O
1V9
A B
R11
8
02V
5IO
C12
610
0n
0402
FPG
A De
coup
lers2V
5AU
X
2V5I
O
C12
510
uF
CMOS
3V3I
OP2
,3,5
,6,8
LVDS
2V5I
OP4
,5,6
2V5A
UX
P6
1V9
P4,6
C12
110
uF
BANK
1BA
NK3
BANK
0
BANK
7
BANK
4
BANK
8
BANK
5
VCC
AUX
BANK
2
VCC
INT
BANK
6
C12
710
0nC
128
100n
C12
910
0nC
131
100n
C13
010
0nC
132
100n
USB
_PO
WER
P5
C13
310
0n
3V3I
O
2V5I
O
2V5I
O
3V3I
O2V
5IO
1V8I
O3V
3IO
3V3I
O
3V3I
O
C13
510
0nC
134
100n
3V3I
O
VEXT
2V5I
O
C13
610
0nC
137
100n
C13
810
0nC
140
100n
C13
910
0nC
141
100n
2V5I
O
C12
210
0nC
123
100n
L910
0MH
z
C11
810
uF
U25 LP
2989
LV
BYPA
SS1
NC
2
GR
OU
ND
3
INPU
T4
OU
TPU
T5
SEN
SE6
ERR
OR
7SH
DN
81V
8IO
C11
310
0n
VEXT
P8
C14
710
0nC
146
100n
C14
510
0nC
144
100n
C14
310
0nC
142
100n
2V5I
O
C12
010
0n
PRO
JEC
TN
AME:
LAST
MO
DIF
IED
:Sh
eet
OF
THIS
DO
CU
MEN
T C
ON
TAIN
S IN
FOR
MAT
ION
PR
OPR
IETA
RY
TO N
ATIO
NAL
SEM
ICO
ND
UC
TOR
CO
RPO
RAT
ION
. USE
WIT
HO
UT
WR
ITTE
N P
ERM
ISSI
ON
IS E
XPR
ESSL
Y FO
RBI
DD
EN. C
OPY
RIG
HT
2001
.
DAT
E:
DAT
E:C
HEC
KED
:
DR
AWN
:
SCH
EMAT
IC R
EV:
DO
C #
:NAT
ION
AL S
EMIC
ON
DU
CTO
R C
OR
POR
ATIO
ND
CS
PRO
DU
CT
LIN
E
2900
Sem
icon
duct
or D
rive,
San
ta C
lara
DES
IGN
ED:
DAT
E:
PAG
E TI
TLE
78
BIG
GIG
REF
EREN
CE
BOAR
D
1.1
____
____
____
IAN
KIN
G24
/ O
CT
/ 200
5
DD
/ M
MM
/ Y
YY
Y
____
____
____
Wed
nesd
ay, F
ebru
ary
08, 2
006
IAN
KIN
G24
/ O
CT
/ 200
5PE
RIP
HER
AL P
OW
ER
____
____
____
____
____
_
____
____
____
____
____
_
VIR
TEX
4 PO
WER
VEXT
C10
710
0n
U9G XC
4VLX
15_3
63FB
GA
VCC
O_0
D10
VCC
INT
P15
VCC
O_0
U11
VCC
O_1
D7
VCC
O_1
D14
VCC
O_2
U7
VCC
O_2
U14
VCC
O_3
A9
VCC
O_3
A12
VCC
O_4
Y8
VCC
O_4
Y13
VCC
O_5
K15
VCC
O_5
L15
VCC
O_5
A17
VCC
O_5
E17
VCC
O_5
L18
VCC
O_5
D20
VCC
O_5
J20
VCC
O_5
N20
VCC
O_6
D1
VCC
O_6
J1
VCC
O_6
N1
VCC
O_6
L3
VCC
O_6
A4
VCC
O_6
E4
VCC
O_6
K6
VCC
O_6
L6
VCC
O_7
T16
VCC
O_7
Y18
VCC
O_7
U20
VCC
O_8
U1
VCC
O_8
Y3
VCC
O_8
T5
VREF
P_SM
W14
VREF
N_S
MW
15
AVD
D_S
MW
16
VP_S
MY
14
VN_S
MY
15
AVSS
_SM
Y16
GN
DB1
GN
DW
1
GN
DY
1
GN
DA2
GN
DG
3
GN
DP3
GN
DC
7
GN
DH
7
GN
DJ7
GN
DK7
GN
DL7
GN
DM
7
GN
DN
7
GN
DV7
GN
DG
8
GN
DP8
GN
DG
9
GN
DP9
GN
DG
10
GN
DP1
0
GN
DU
10
GN
DD
11
GN
DG
11
GN
DP1
1
GN
DG
12
GN
DP1
2
GN
DG
13
GN
DP1
3
GN
DC
14
GN
DH
14
GN
DJ1
4
GN
DK1
4
GN
DL1
4
GN
DM
14
GN
DN
14
GN
DV1
4
GN
DG
18
GN
DY
2
GN
DP1
8
GN
DA1
9
GN
DY
19
GN
DA2
0
GN
DB2
0
GN
DY
20G
ND
W20
VCC
AUX
H6
VCC
AUX
N6
VCC
AUX
F8
VCC
AUX
R8
VCC
AUX
F13
VCC
AUX
R13
VCC
AUX
H15
VCC
AUX
N15
VCC
INT
G6
VCC
INT
P6
VCC
INT
F7
VCC
INT
G7
VCC
INT
P7
VCC
INT
R7
VCC
INT
F14
VCC
INT
G14
VCC
INT
P14
VCC
INT
R14
VCC
INT
G15
C10
610
0n
VEXT
C10
910
0nC
108
100n
C97
3.3u
F
C99
33uF
C96
3.3u
F
C10
033
uF
L11
100M
Hz
C10
133
uF
L7 8.86
uH
D13
B340
LB-1
3
12
D14
SMAZ
6V2
R11
6N
/A
R11
910
K
U26 LM
1117
MPX
VIN
3VO
UT
2
TAB/
VOU
T4
ADJ/
GN
D1
R11
71K
VIN
VIN
P2,6
,8
3V3
5VU
SB
1V2
2V5A
UX
SINK
- G
ND
U23 LM
2676
SWITCH_OUT 1INPUT 2C BOOST 3GND 4CURRENT ADJ 5FEEDBACK 6ON / OFF 7
C11
410
0nC
115
100n
C11
610
0nC
117
100n
2V5A
UX
R11
510
POW
ER_E
N_T
P6
VOUT
= 1
.24
VOUT
= 1
.21
* (1
+(R1
15/R
117)
)
3V3I
O
CERA
MIC
ONLY
C11
910
uF
C94
100n
C92
100n
C95
100n
1V2
C93
100n
C10
410
0nC
102
100n
C10
510
0n
1V2
C10
310
0n
C98
10n
L10
N/A
12
7.6 Schematic Drawing ADC08D1000DEV – Expansion Header Interface
13
8.0 Bill of Materials (Page 1 of 2)
NATIONAL SEMICONDUCTOR
BIG GIG REF BOARD (ADC08D1000) B0 BUILD Last Updated:
Assembly Revision: Pre-ProductionSchematic Revision: 1.1
Number of Boards to Build =
Item Qty Part Reference Value Description Manufacturer Manufacturer Part Number
SMT Capacitors1 8 C1,C2,C6,C7,C9,C11,C16, 100pF Capacitor, SMT 0603, MLC, NPO, 5%, 50V Panasonic ECJ-1VC1H101J
C182 4 C3,C5,C13,C159 470pF Capacitor, SMT 0603, MLC, NPO, 5%, 50V Panasonic ECJ-1VC1H471J3 2 C56,C4 1uF Capacitor, SMT 0603, MLC, X5R, 10%, 16V Panasonic ECJ-1VB1C105K4 1 C8 27nF Capacitor, SMT 0603, MLC, X7R, 10%, 16V Panasonic ECJ-1VB1C273K5 9 C10,C17,C19,C79,C80,C88, 10n Capacitor, SMT 0603, MLC, X7R, 10%, 16V Panasonic ECJ-1VB1C103K
C89,C98,C1636 1 C12 1500pF Capacitor, SMT 0603, MLC, X7R, 10%, 50V Panasonic ECJ-1VB1H152K7 6 C14,C15,C24,C25,C26,C27 4n7 Capacitor, SMT 0603, MLC, X7R, 10%, 50V Panasonic ECJ-1VB1H472K9 60 C20,C21,C23,C28,C31,C32, 100n Capacitor, SMT 0603, MLC, X7R, 10%, 16V Panasonic ECJ-1VB1C104K
C33,C34,C35,C36,C37,C38,C39,C40,C41,C42,C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55,C57,C60,C63,C64,C65,C66,C67,C68,C69,C70,C71,C72,C73,C74,C77,C78,C84,C87,C112,C113,C120,C122,C123,C148,C149,C150,C151,C152,C155,C158,C162
10 8 C30,C81,C82,C90,C91,C160, 22uF CAP 22UF 16V TANTALUM TEL SMD EPCOS Inc B45197A3226K309C164,C165
11 2 C59,C58 33pF CAP CERAMIC 33PF 50V 0603 SMD Panasonic ECJ-1VC1H330J12 4 C61,C62,C153,C154 1n Capacitor, SMT 0603, MLC, X7R, 10%, 50V Panasonic ECJ-1VB1H222K13 9 C75,C76,C85,C86,C110, 10uF CAP 10UF 20V TANTALUM TEL SMD Kemet T491C106K020AS
C118,C121,C125,C16114 2 C124,C83 47uF CAP 47UF 20V TANTALUM TEL SMD AVX TAJC476K020R15 38 C92,C93,C94,C95,C102, 100n Capacitor, SMT 0402, MLC, X5R, 10%, 10V Panasonic ECJ-0EB1A104K
C103,C104,C105,C106,C107,C108,C109,C114,C115,C116,C117,C126,C127,C128,C129,C130,C131,C132,C133,C134,C135,C136,C137,C138,C139,C140,C141,C142,C143,C144,C145,C146,C147
16 2 C97,C96 3.3uF Capacitor, SMT 1206, MLC, X5R, 10%, 25V Kemet C1206C335K3PACTU17 3 C99,C100,C101 33uF CAP 33UF 16V TANTALUM TEL SMD, 10% Kemet T491C336K016AS18 2 C119,C111 10uF CAP 10UF 20V CERAMIC TEL SMD Kemet C1210C106K4PACTU19 1 C157 33uF CAP 33UF 10V TANTALUM TEL SMD 25V, 10% Kemet T495X336K025ASE175
Diodes20 5 D1,D4,D5,D9,D16 1N4148W DIODE SWITCH 75V 400MW SOD-123 Diodes Inc 1N4148W-721 3 D2,D3,D8 BZX84C5V1 DIODE ZENER 5.1V 350MW SOT-2 Diodes Inc BZX84C5V1-722 5 D6,D7,D11,D12,D17 10BQ030 DIODE SCHOTTKY 30V 1A DO-214AA International Rectifier 10BQ03023 1 D10 BAT42W DIODE SCHOTTKY 30V 200MW SOD-123 Diodes Inc BAT42W-724 1 D13 B340LB-13 RECTIFIER SCHOTTKY 40V 3A SMB Diodes Inc B340LB-1325 1 D14 SMAZ6V2 DIODE ZENER SMD 6.2V 1W SMA DIODES INC. SMAZ6V2-1326 1 D15 Z5238BLT1 DIODE ZENER 8.7V 225MW SOT-23 ON Semiconductor MMBZ5238BLT1
Connectors27 3 JP3,JP2,JP1 JUMPER 2X1 HEADER 2X1 0.1" SP MALE STR Sullins PTC36SAAN28 4 J1,J2,J3,J4 SMA CONN JACK SMA RT ANG PCB GOLD AMP/Tyco Electronics 221790-129 1 J5 CONN 6 PIN SINGLE ROW HEADER 6X1 0.1" SP MALE STR Sullins PTC36SAAN30 1 J6 USB-B USB Connector Type B, Single Through Hole Mill-Max 897-30-004-90-00000031 1 J7 CONN PWR JACK CONN PWR JACK 2.5X5.5MM HIGH CUR CUI Inc PJ-102BH32 1 J8 CONN 38 PIN MICTOR MICTOR VERTICAL RECEPT. 38 POS AMP/Tyco Electronics 767054-141 3 P1,P2,P3 FUTUREBUS_24 CONN RCEPT RTANG 2MM 24POS 30AU AMP/Tyco Electronics 536511-1
Ferrites35 9 L1,L8,L9,L11,L12,L13,L14, 100MHz FERRITE CHIP 120 OHM 3000MA 1206 Murata BLM31PG121SN1L
L15,L1736 1 L2 CM CHOKE CHOKE COMMON MODE 170 OHMS PCB Steward CM2545X171B-0037 5 L3,L4,L5,L6,L16 10uH INDUCTOR SHIELD PWR 10UH 7032 TDK SLF7032T-100M1R4-2-PF38 1 L7 8.2uH INDUCTOR SHIELD PWR 8.2UH SMD Coiltronics DR127-8R2-R
Resistors45 2 R98,R2 680 RES 680 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ681V46 6 R3,R10,R12,R143,R144, 18 RES 18 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ180V
R14747 2 R5,R4 270 RES 270 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ271V48 3 R1,R6,R115 10 RES 10 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ100V49 24 R7,R8,R16,R17,R25,R26, 10K RES 10K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ103V
R28,R29,R35,R54,R68,R81,R82,R83,R84,R85,R105,R106,R113,R114,R119,R124,R149,R150
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO NATIONAL SEMICONDUCTOR CORPORATION. USE OR DISCLOSURE WITHOUT WRITTEN PERMISSION IS EXPRESSLY FORBIDDEN. COPYRIGHT 2006.
14
8.1 Bill of Material (Page 2 of 2)
Item Qty Part Reference Value Description Manufacturer Manufacturer Part Number
Resistors (cont.)50 1 R9 2K7 RES 2K7 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ272V53 3 R14,R27,R30 100 RES 100 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ101V56 7 R19,R21,R22,R55,R57,R62, 0 RES 0 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEY0R00V
R13559 11 R40,R41,R42,R43,R44,R45, 3K3 RES 3.3K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ332V
R46,R47,R48,R49,R5060 1 R53 4.7K RES 4.7K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ472V
61A 1 R56 0 RES 0 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEY0R00V61B 1 R118 0 RES 0 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEY0R00V
62 10 R58,R86,R87,R88,R89,R90, 330R RES 330 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ331VR91,R92,R93,R128
63 1 R59 10K RES 10K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ103V64 9 R60,R61,R64,R66,R67,R78, 47 RES 47 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ470V
R129,R130,R13165 1 R63 1M RES 1.0M OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ105V66 1 R65 1.5K RES 1.5K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ152V67 5 R69,R70,R94,R95,R127 3.3K RES 3.3K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ332V68 2 R71,R72 24.3 RES 24.3 OHM 1/16W 1% 0603 SMD Panasonic ERJ-3EKF24R3V69 4 R73,R74,R112,R117 1K RES 1K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ102V70 6 R79,R80,R120,R121,R122, 51 RES 51 OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ510V
R12373 4 R96,R97,R104,R140 4.12K RES 4.12K OHM 1/10W 0.1% 0603 SMD Susumu Co Ltd RR0816P-4121-B-T5-60H74 2 R99,R100 22.1K RES 22.1K OHM 1/10W 0.1% 0603 SMD Susumu Co Ltd RR0816P-2212-D-34C75 5 R101,R102,R110,R111,R141 10.2K RES 10.2K OHM 1/10W 0.5% 0603 SMD Susumu Co Ltd RR0816P-1022-D-02C76 4 R103,R107,R146,R148 100K RES 100K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ104V77 1 R108 14.3K RES 14.3K OHM 1/10W 0.5% 0603 SMD Susumu Co Ltd RR0816P-1432-D-16C78 1 R109 32.4K RES 32.4K OHM 1/10W 0.5% 0603 SMD Susumu Co Ltd RR0816P-3242-D-50C79 1 R134 49.9 RES 49.9 OHM 1/10W 1% 0603 SMD Panasonic ERJ-3EKF49R9V81 1 R142 54.9K RES 54.9K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3EKF5492V82 1 R145 18K RES 18K OHM 1/10W 5% 0603 SMD Panasonic ERJ-3GEYJ183V
IC's89 3 U1,U4,U6 RELAY-RF303 RF RELAY DPDT Teledyne RF303-590 1 U2 LMX2312 Frequency Systhesizer (PLL) - LMX2312 NSC LMX2312USLDX91 1 U3 VCO190-992 1GHz Centre Frequency VCO, 5V VARIL VCO190-992T92 1 U5 LMH6555 NSC94 4 U8,U11,U27,U28 74LVC1G17 IC SCHMITT-TRIG BUFF SOT-23-5 TI SN74LVC1G17DBVR95 1 U9 XC4VLX15_363FBGA VIRTEX 4 363 pin FPGA Xilinx XC4VLX15-10SF363C96 1 U10 ADC08Dxxxx ADC08D1000 128 PIN Exposed Pad TQFP NSC ADC08D1000-CIYB97 1 U12 Cypress CY7C64613-80NC EZ USB Microcontroller 80 Pin PQFP Cypress CY7C64613-80NC98 1 U13 LM95221CIMM LM95221 Dual Remote Diode Digital Temperature Sensor NSC LM95221CIMM
100 1 U15 24C02/SO8 EEPROM 2 WIRE 2Kbit (256 x 8) 8 Pin SOIC ATMEL AT24C02N-10SI-2.7101 1 U16 74LVC541 IC OCT BUFF/DRVR TRI-ST 20-SSOP Texas Instruments SN74LVC541ADBR102 1 U17 74LVC1G00 IC NAND GATE 2-IN SOT-23-5 Texas Instruments SN74LVC1G00DBVR103 1 U18 74LVC1G04 IC SINGLE INVERTER-GATE SOT-23-5 Texas Instruments SN74LVC1G04DBVR104 5 U19,U20,U21,U22,U32 LM2734 TSOT-6 IC PWM STP-DWN REG 1A SOT23-6 NSC LM2734YMK105 1 U23 LM2676 IC REG SIMPLE SWITCHER TO-263-7 NSC LM2676S-ADJ106 1 U24 LP2986 IC REGULATOR MICROPWR LDO 8-SOIC NSC LP2986IM-5.0107 1 U25 LP2989LV IC REGULATOR MICROPWR LDO 8-SOIC NSC LP2989IM-1.8108 1 U26 LM1117MPX IC REG 3.3V 800MA LDO SOT-223 National Semiconductor LM1117MPX-3.3109 1 U29 74LVC1G06 IC INVERTER BUFF/DRVR SOT-23-5 TI SN74LVC1G06DBVR110 1 U31 LM321_SOT23 LM321 Low POwer Single Op-Amp National LM321MF
Misc33 4 LD1,LD2,LD3,LD4 LED_2x1 LED 3MM 2-HIGH GREEN/GREEN PCMNT Lumex SSF-LXH2103GGD/434 1 LD5 GREEN LED LED 3MM RA FAULT-IND GRN PC MNT Lumex SSF-LXH103GD42 7 Q1,Q2,Q3,Q5,Q6,Q7,Q8 BC817-25 TRANS NPN GP 500MA 45V SOT23 ON Semiconductor BC817-25LT182 1 SW1 RESET SWITCH TACT MOM 130GF H=5MM ITT INDUSTRIES PTS635SL5083 1 SW2 ROCKER SWITCH ROCKER SPDT HORZ ACT RA ITT Industries/C&K Div 7101J1AQE288 3 T1,T2,T3 ADTL2-18 RF TRANSFORMER SMT 6 PINS upto 1.8GHz Mini Circuits ADTL2-18
111 1 Y1 10MHz CRYSTAL 10.000MHZ SERIES HC49/US ECS Inc. ECS-100-S-4112 1 Y2 12MHz CRYSTAL 12.000MHZ SERIES HC49/US ECS Inc. ECS-120-S-4113 1 Y3 OSC (SM) OSCILLATOR 100.0000 MHZ SMT Citizen CSX750ABB100.000MTR
9.0 Using the Wavevision4 software with the ADC08D1000DEV IMPORTANT NOTE: Before connecting this board to the PC, please install the Wavevision 4 Software from the CDROM included with the development kit. (See Appendix B)
Connecting the Development Board before installation may result in the board being registered as an unknown USB device. If this happens you will need to uninstall the device using the Windows Device Manager before installing the Wavevision 4 Software.
9.1 Getting Started This development board is designed to connect over a USB interface to a PC running the Wavevision 4 Software.
Ensure the board is connected to the 12V power supply (included in the package) and that the switch on the rear panel is pushed to the “ON” position. The Green LED on the rear panel should be illuminated if on.
Connect the USB cable between the PC which has Wavevision 4 software installed and the ADC08D1000DEV board. The USB port can also be found on the rear panel (shown below).
If this is the first time the board has been connected to the PC, Drivers may be required to be installed (automatic) by the Operating System. Follow the on screen instructions and use the recommended settings.
Start the Wavevision 4 software (Start -> All Programs -> Wavevision -> Wavevision 4) The software may take several seconds to initialize, but should display a welcome screen similar to the following.
16
If the board is connected correctly the following popup box should appear to indicate that the board has been recognized and the firmware for the FPGA is being downloaded over the USB interface
If the “Downloading firmware” box does not appear automatically, click on the “Settings” pulldown menu and then click Capture Settings as shown below.
This will display the System Settings Window which should appear as below
17
If the board has not been detected click the “Test” button under the Communication heading and the development board should be found. If the communications fail, check that the USB drivers are installed correctly, then disconnect and re-connect the USB cable. Finally restart the Wavevision 4 software See Appendix B for more information.
9.2 Control Panel Once the FPGA Firmware download has completed the development board Control Panel will automatically be displayed as shown below.
The Following section describes the Function of the pull-down selection tabs in the left hand side of the ADC08D1000DEV product Control Panel
Channel Selection I – Displays the data captured from the I Channel Only after acquiring Samples
Q- Displays the data captured from the Q Channel Only after acquiring Samples
I and Q – Displays the data captured from I and Q channels in 2 windows after acquiring samples.
I/Q Interleaved – Displays the data captured from the I and Q channels interleaved in a single window,
after acquiring samples (Use when DES mode is enabled).
Temp Sensor Displayed below the Channel Selection tab is the die temperature of both the FPGA and the ADC.
18
Hardware/Serial Control Hardware Pin Control – The ADC is controlled by the logic states on the dedicated control pins. The logic on these pins is determined by the setting of OUTV, OUTEDGE, DDR, DES and FSR below. Serial Register Program – The ADCs registers are accessed through the Extended Control Mode. In this mode the hardware pin control is disabled and the programmable registers are available for fine tuning.
NOTE: The Following Pull-down Tabs are available only when Hardware Pin Control is selected.
Out V Low Amplitude – LVDS output voltage amplitude is set to 510mV pk-pk.
High Amplitude – LVDS output voltage amplitude is set to 710mV pk-pk.
OutEdge Falling Edge – Data outputs are changed on the falling edge of DCLK+ (Single Data rate mode only).
Rising Edge – Data outputs are changed on the rising edge of DCLK+ (Single Data rate mode only).
DDR Disable Dual Data Rate – DDR Mode is disabled (data output follows OutEdge Setting).
Enable Dual Data Rate – Data is output with rising and falling edge of DCLK (Default for 1.0GHz clock).
DES Disable Dual Edge Sample – DES Mode is disabled (I and Q are independent).
Enable Dual Edge Sample – The I channel is sampled on the rising and falling edge of the clock.
FSR 650mV Full Scale – Sets the full scale range to 650mV pk-pk.
870mV Full Scale – Sets the full scale range to 870mV pk-pk.
NOTE: The Following Pull-down Tabs are available regardless of Hardware/Serial Control setting.
Standby Disable Standby – Enable all on-board power regulators.
Enable Standby – Board is put into standby mode – All power is shutdown except USB power.
PDQ Disable Q Shutdown – The ADC’s Q Channel is powered up and Active.
Enable Q Shutdown – The ADC’s Q Channel is shutdown.
PD Disable Shutdown – The ADC is powered up and Active.
Enable Shutdown – The ADC is put into low power mode. Register Settings are retained.
19
DC_Coup AC Coupling – The I Channel is AC coupled to the ADCs input
DC Coupling – The I Channel is DC coupled to the ADCs input (not available on AC only model)
Ext_Clock Internal Clock – The ADC is clocked using the on-board 1.0GHz clock
External Clock – The ADC is clocked from an External clock source connected to the “CLOCK” input.
Reset FPGA This button resets the FPGA, and also returns all the pulldown tabs to their default values.
Calibrate ADC This button issues an on-command calibration to the ADC by toggling the ADCs calibrate pin.
9.3 Serial Control Mode When the Hardware/Serial Control tab is selected as “Serial Register Program”, the control panel display
will be changed to the following view.
In this mode the register settings can be changed simply by clicking on the bits. Doing so will toggle the bit
value and any linear values such as Full Scale Range or Offset will automatically be updated.
The “Reset Registers” button at the bottom of the Control Panel will reset and write all the values to the
power-on default settings.
Please refer to the ADC08D1000 datasheet for a full description of the ADCs internal registers.
20
9.4 Capturing Waveforms When the ADC has been configured as required, the selected input(s) can be sampled by clicking the
“Acquire” pull-down menu and selecting “Samples”. Alternatively press F1 then the Escape key.
10.0 Appendix A - Hardware Information
10.1 LED functions The function of the LEDs on the front panel of the boards is as follows
STB – STANDBY, illuminates when the board is in standby mode.
TRG – TRIGGER EVENT, illuminates when the Trigger Input makes low to high transition
OVR – ADC OVER RANGE, illuminates when the I or Q channel exceeds the full scale range of the ADC
CLK – CLOCK INPUT, flashes with 50% duty cycle if the ADC is receiving a good clock input.
PWR – POWER, illuminates when the external 12V is connected and the system is not in Standby.
UPL – UPLOAD, illuminates when the FPGA is uploading sample data to the PC
SMP – SAMPLE, illuminates when the FPGA is sampling data and storing to the FIFO buffers
IDL – IDLE, illuminates when the system is IDLE.
21
10.2 Expansion Header A 72 pin Future Bus Expansion Header is provided on the rear panel to allow easy connection to a third party microprocessor board to allow for the reading and analysis of the data captured by the FPGA. The signals connector to this expansion bus will be as follows PIN DESCRIPTION PIN DESCRIPTION A1 I2C - SDA B1 GROUND A2 I2C - SCL B2 GROUND A3 SSP - SERIAL DATA B3 GROUND A4 SSP - SERIAL CLOCK B4 GROUND A5 FPGA RESET B5 GROUND A6 READ FIFO B6 GROUND A7 WRITE FIFO B7 GROUND A8 FIFO FULL B8 GROUND A9 FIFO EMPTY B9 GROUND A10 ADC DCLK RESET B10 GROUND A11 FPGA CONF DONE B11 GROUND A12 FPGA JTAG – TMS B12 GROUND A13 FPGA JTAG - TCK B13 GROUND A14 FPGA JTAG – TDI B14 GROUND A15 FPGA JTAG – TDO B15 GROUND A16 notSHUTDOWN B16 GROUND A17 3.3V SUPPLY B17 GROUND A18 12V SUPPLY B18 GROUND C1 DATA BUS A P0 (LVDS or CMOS) D1 DATA BUS A N0 (LVDS or CMOS) C2 DATA BUS A P1 (LVDS or CMOS) D2 DATA BUS A N1 (LVDS or CMOS) C3 DATA BUS A P2 (LVDS or CMOS) D3 DATA BUS A N2 (LVDS or CMOS) C4 DATA BUS A P3 (LVDS or CMOS) D4 DATA BUS A N3 (LVDS or CMOS) C5 DATA BUS A P4 (LVDS or CMOS) D5 DATA BUS A N4 (LVDS or CMOS) C6 DATA BUS A P5 (LVDS or CMOS) D6 DATA BUS A N5 (LVDS or CMOS) C7 DATA BUS A P6 (LVDS or CMOS) D7 DATA BUS A N6 (LVDS or CMOS) C8 DATA BUS A P7 (LVDS or CMOS) D8 DATA BUS A N7 (LVDS or CMOS) C9 INPUT STROBE P D9 INPUT STROBE N C10 DATA BUS B P0 (LVDS or CMOS) D10 DATA BUS B N0 (LVDS or CMOS) C11 DATA BUS B P1 (LVDS or CMOS) D11 DATA BUS B N1 (LVDS or CMOS) C12 DATA BUS B P2 (LVDS or CMOS) D12 DATA BUS B N2 (LVDS or CMOS) C13 DATA BUS B P3 (LVDS or CMOS) D13 DATA BUS B N3 (LVDS or CMOS) C14 DATA BUS B P4 (LVDS or CMOS) D14 DATA BUS B N4 (LVDS or CMOS) C15 DATA BUS B P5 (LVDS or CMOS) D15 DATA BUS B N5 (LVDS or CMOS) C16 DATA BUS B P6 (LVDS or CMOS) D16 DATA BUS B N6 (LVDS or CMOS) C17 DATA BUS B P7 (LVDS or CMOS) D17 DATA BUS B N7 (LVDS or CMOS) C18 OUTPUT STROBE P D18 OUTPUT STROBE N The Data busses on this header can be configured as follows
• Two 8 bit busses with LVDS differential signaling, plus two LVDS strobes • Four 8 bit busses with LVCMOS (3.3V IO) signaling plus four CMOS strobes
All control signals on pins A1 to A15 will be at LVCMOS 3.3V levels.
22
10.3 System Block Diagram
23
11.0 Appendix B - Installing and running the Wavevision 4 software
11.1 Install the WaveVision Software. • Insert the WaveVision CD-ROM into your computer’s CD-ROM drive. • The WaveVision software requires a Java™ Runtime Environment or Java™ Development Kit,
version 1.4 or higher, from Sun Microsystems, Inc. For detailed information on WaveVision’s use of Java technology, please see below. If your computer does not have this software, the WaveVision installer will instruct you on how to install it.
• Locate and run the WaveVision 4 Setup.exe program on the CD-ROM. Follow the on-screen instructions to finish the install.
11.2 Java™ Technology The WaveVision software uses Sun Microsystems® Java technology. The underlying Java software must be installed on your computer in order for the WaveVision software to run. The software can run on top of either the Java Runtime Environment (JRE) or the Java Development Kit (JDK), version 1.4 or higher. A suitable copy of the JRE is included on your WaveVision CD-ROM. The WaveVision installer will first look for an existing copy of the JRE or JDK on your computer. If neither is found, the installer will instruct you to first install a JRE. To do this, run the J2RE*.exe installer program off the CD-ROM. Follow the on-screen instructions to finish the install. After a suitable JRE or JDK is installed, run the WaveVision installer again. The installer will detect the Java software and configure the WaveVision software to use it. Java technology can allow software to run on different platforms. However, the WaveVision software contains Windows specific hardware interface code and therefore is only currently supported under Windows.
11.3 Automatic Device Detection & Configuration The WaveVision system provides automatic hardware detection and configuration for the device under test. The FPGA is re-programmed on the fly by the host PC when the Development board is turned on. Normally, the configuration process is totally transparent to the user, and requires no intervention. However, this process can be overridden if required by specifying a new Xilinx configuration image by clicking the Xilinx Image Settings button within the Capture Setting window (Settings -> Capture Settings).
11.4 Windows Driver The WaveVision software communicates with the WaveVision hardware through the Windows device driver software. If you are unable to connect to the Wavevision board after installing the software, do the following to uninstall and reinstall the driver. Go to the Windows Control Panel and select System. If you are using Windows 2000/XP select the Hardware tab. Then click on Device Manager and go down to the Universal Serial Bus controllers. With the WaveVision board connected, you will see it (or an unknown device) listed. Right click on it and uninstall the driver. Then unplug and plug in the board again to reinstall the driver.
24
12.0 Appendix C - Using WaveVision Plots The WaveVision software provides several tools to help you interact with plots. A toolbar appears above each plot, similar to Figure 4.
Figure 4: WaveVision Plot Tools
Seen from left to right, the following tools are available: Plot Actions menu: This menu contains commands that pertain to this particular plot. You may export the plot data to a file, print the plot, save it as a graphic, or change the plot’s colors. Plot Options: This button opens a dialog box with options that pertain to this particular plot. You may turn off labels, annotations, or other elements in this dialog. The WaveVision software maintains default options for new plots. You may edit the default options by choosing Default Plot Options from the Settings menu. FFT Options: The toolbar shown in Figure 4 is from an FFT plot, and thus contains a button to edit the options for the FFT calculation. Depending upon the type of plot, various options may be present on the toolbar. Please consult the appropriate section below for more information about these options. Magnifying glass tool: This tool allows you to zoom in and out to see fine details in the plot. Click and drag a box from upper-left to lower-right to zoom in on a particular region of your plot. Click and drag a box from lower-right to upper-left to zoom out. With the magnifying glass tool selected, click the right mouse button to return to a normal, 100% view. Arrow Tool: The arrow tool is used to select, move, and edit annotations. To edit an annotation, double click it with the arrow tool. To delete an annotation, select it with the arrow tool and press the Delete key on your keyboard. Line Annotation Tool: To draw lines on the plot, select this tool. Drag to draw new lines. To add arrowheads or fix the endpoints of the line, double-click it with the arrow tool. Text Annotation Tool: To draw labels on the plot, select this tool and click at the desired location in the plot. To edit the justification, location, or text of an annotation, double-click it with the arrow tool.
The Waveform Plot The Waveform plot shows you the raw samples collected from the hardware. This plot is mainly used to verify the integrity of collected data – the waveform is the best view in which to diagnose a distorted signal, an irregular clock, a low-amplitude signal, and many other common ADC system problems. The Waveform plot also quickly shows you how much of the ADC’s dynamic range your signal occupies.
The FFT Plot The WaveVision software automatically computes a Fast Fourier Transform (FFT) of the sample set, and displays the results in an FFT plot. The FFT plot is, in many respects, the heart of the software. The FFT shows you the frequency content of your input signal. It marks the fundamental frequency, and a selectable number of harmonics. It also labels their order and frequencies. It shows the power in the fundamental and harmonics. Try hovering your mouse cursor over a harmonic to get information about it. The FFT can be used to diagnose common ADC problems such as input spectral impurity, clock phase noise, and clock jitter. The FFT plot also shows several statistics on the quality and purity of the collected
25
samples, such as SNR, SINAD, THD, SFDR, and ENOB. These statistics are to be interpreted with the following definitions (which are repeated in every National Semiconductor ADC datasheet): Signal to Noise Ratio (SNR) is the ratio, expressed in dB, of the RMS value of the input signal to the RMS value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. Signal to Noise Plus Distortion (S/N+D or SINAD) Is the ratio, expressed in dB, of the RMS value of the input signal to the RMS value of all of the other spectral components below half the clock frequency, including harmonics but excluding DC. Total Harmonic Distortion (THD) is the ratio, expressed in dBc, of the RMS total of the first five harmonic levels at the output to the level of the fundamental at the output. THD is calculated as
21
222log20THD
fff N++
=L
where f1 is the RMS power of the fundamental (output) frequency and f2 through fN are the RMS power in the first N harmonic frequencies. Spurious-Free Dynamic Range (SFDR) is the difference, expressed in dB, between the RMS values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. Effective Number of Bits (ENOB, or Effective Bits) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.
FFT Options FFT plots can be configured in many different ways. Clicking the “FFT Options” button at the top of the plot will display a dialog showing the options for that particular plot. The software also maintains default options for new FFT plots, which are editable. You can edit the default FFT options by choosing Default FFT Options from the Settings menu. The options are: Windowing: You may choose from one of five different window functions. The window function is applied to the samples before computing the FFT to compensate for the fact that the sample set may not be an integral number of wavelengths of the input signal. In general, Flat-Top will give the best results, but you may find it easier to compare data with other systems when the windowing functions are the same. dB Scale: You may select to represent power on the FFT in dBc (decibels relative to carrier), in which 0 dB is taken to be the fundamental (carrier) power, or dBFS (decibels relative to full-scale), in which 0 dB is taken to the be power contained in a signal which uses the entire dynamic range of the ADC. Harmonics: You may select the number of harmonics recognized (and labeled) by the software. You may also select the number of FFT bins excluded around harmonics in, for example, SNR calculations. The exclusion region around each harmonic will be shown in a different color than the rest of the data points. IMD Calculations: The WaveVision software is capable of performing Intermodulation Distortion calculations. When two fundamental frequencies within 3 dBFS are present in the waveform, The software will normally perform IMD calculations. You may inhibit this behavior by deselecting the “Allow IMD calculation” checkbox. When IMD calculation is enabled, you may also select whether the software will include only 2nd order or both 2nd and 3rd order terms.
26
Histogram Plots Histogram plots are created by counting the number of times each ADC output code appears in a dataset. Histograms may be computed by software, or by hardware. A software histogram is computed from a dataset which is normally 128k samples or smaller. A hardware histogram is collected directly by the hardware, and may include millions of counts per code. The resulting histogram will show discontinuities between comparators, gain or offset errors, and other common ADC system problems. The Histogram plot also displays the number of codes that were never counted (missing codes), followed by the first ten such missing codes.
Information Viewer The information viewer is not a plot, but it displays a variety of useful information about the dataset, such as the sampling rate, and any warnings generated by the software. You may also store comments about the dataset here, to be saved in a WaveVision file.
Data Import and Export The WaveVision software provides a variety of means to share data with others, in both textual and graphical formats. The most flexible way to import data into the software is from a tab-delimited ASCII text file. The contents can be either a sample set or a histogram, provided with or without time information. The simplest example of this would be a file with a single column of samples. You can open tab-delimited text files by choosing Open from the File menu; you can interleave data from multiple columns and/or files. You can choose ReOpen to reopen the same file later with the same settings (for example when you update the file with new data), There are a variety of ways to export data from the software:
• Save the file as a normal WV4 (*.wv4) file. WV4 files are ASCII, tab-delimited text files. Samples are stored one per line in a single column. You can open a WV4 file directly in a spreadsheet program.
• Save the file as a TXT (*.txt) file. You will produce a one- or two-column tab-delimited ASCII text file of samples or histogram information, without the header information that is contained in a WV4 file.
• You can export the contents of an individual plot by choosing Export Data… from the plot’s Plot Actions menu. The format of the data is always tab-delimited ASCII text.
• You can export a plot as either a GIF (*.gif) or Encapsulated Postscript (*.eps) graphic by choosing Export Plot as Graphic from the plot’s Plot Actions menu. GIF files are suitable for the web or for emails. Encapsulated Postscript files are high-resolution scalable files suitable for direct publication.
27
BY USING THIS PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF NATIONAL SEMICONDUCTOR'S END USER LICENSE AGREEMENT. DO NOT USE THIS PRODUCT UNTIL YOU HAVE READ AND AGREED TO THE TERMS AND CONDITIONS OF THAT AGREEMENT. IF YOU DO NOT AGREE WITH THEM, CONTACT THE VENDOR WITHIN TEN (10) DAYS OF RECEIPT FOR INSTRUCTIONS ON RETURN OF THE UNUSED PRODUCT FOR A REFUND OF THE PURCHASE PRICE PAID, IF ANY. The ADC08D1000DEV Development Boards are intended for product evaluation purposes only and are not intended for resale to end consumers, is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC, or for compliance with any other electromagnetic compatibility requirements.
National Semiconductor Corporation does not assume any responsibility for use of any circuitry or software supplied or described. No circuit patent licenses are implied
.LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National does not assume any responsibility for any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor Corporation Americas Customer Support Center Tel: 1-800-272-9959 Email: [email protected]
National Semiconductor Europe Customer Support Center Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 699508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +49 (0) 141 91 8790
National Semiconductor Asia Pacific Customer Support Center Email: [email protected]
National SemiconductorJapan Customer Support Center Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Email: [email protected]
Top Related