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CMOS: Fabrication principles and design rules

João Canas Ferreira

University of PortoFaculty of Engineering

2016-02-29

Topics

1 Overview of the CMOS fabrication process

2 Geometric design rules

João Canas Ferreira (FEUP) CMOS: Fabrication principles and design rules 2016-02-29 2 / 38

CMOS technology evolution

Fonte: [Weste11]


Ingots of doped silicone

Fonte: [May04]

à Diameters: 300 mm and 400 mm


Czochralski method

Fonte: [May04]


Ingot production

Fonte: [http://www.tf.uni-kiel.de/matwis/amat/elmat_en/kap_6/illustr/i6_1_2.html]


http://www.tf.uni-kiel.de/matwis/amat/elmat_en/kap_6/illustr/i6_1_2.html

Photolithography

Fonte: [Weste11]


Masks

Fonte: [May04]


Mask projection

Fonte: [May04]


Transfer

Fonte: [May04]


Optical correction (pre-distortion)

Fonte: [Weste11]


Inverter: cut view

Fonte: [Weste11]


Inverter: masks

Fonte: [Weste11]


Triple-well process

Fonte: [Weste11]


Well isolation (trenches)

Fonte: [Weste11]


Gate oxide

Fonte: [Weste11]


Source and drain formation

Fonte: [Weste11]


Improvements

Fonte: [Weste11]


Metal connections

Fonte: [Weste11]


Example: 11 levels of metal

Fonte: [Weste11]


If things go wrong . . .

Fonte: R. Rodríguez-Montañés et al., “Bridging Defects Resistance in the Metal Layer of a CMOS

Process”, J. Electronic Testing: Theory and Applications 8, 35–46 (1996)


Topics

1 Overview of the CMOS fabrication process

2 Geometric design rules


Design rules

I The geometric design rules are a “contract” between the foundry and thedesigner.

I These rules are the designer’s interface to the fabrication process.

I They guarantee that the transfers onto the wafer preserve the topologyand geometry of the patterns.

I Rules specify: minimum separations, minimum and maximum widths,overlap rules

I Scalable rules: distances are specified as multiples of λ

I Minimum gate width: 2λ

I Industrial processes generally state their rules in microns (non-scalable).


Masks for an inverter (n-well)

Fonte: [Weste11]


Substrate contacts

Fonte: [Weste11]


Terminology used in design rules

I Width: shortest distance from the inside of the edge of a shape to theinside of the edge of the same shape.

I Length: the measurement of the longest edge of a shape.

I Spacing: distance from the outside of the edge of a shape to the outsideof the edge of another shape.

I Enclosure: distance from the inside of the edge of a shape to the outsideof the edge of another shape.

I Overlap: distance from the inside of the edge of a shape to the inside ofthe edge of another shape

I Butting - outside of the edge of a shape touching the outside of the edgeof another shape.


Visualization of some rule typesà Spacing

à Enclosure

à Overlap and butting


Classes of rules

Well Definition of: p-well, n-well, deep-n-well. For twin-tubprocesses only one well may be specified (n-well).

Transistors Three masks:I oxide (active, diffusion), n-select (n-implant), p-select (p-implant),

polyI oxide + n-implant + poly : NMOS transistorI oxide + p-implant + n-well + poly : PMOS transistorI oxide + n-implant + contact : contact to wellI oxide + p-implant + n-well + contact : contact to well/substrate

Contacts One maskI metal1/p-active, metal/n-active, metal/poly, metal/substrateI fixed size; use more than one contact in parallel

Metal Rule values depend on the level (increasingly larger and moreseparated)Rules for connection between metal levels (vias): modernprocesses allow stacked vias.


Transistor layoutà NMOS: Oxide and n-implant contains poly

à PMOS:


N-well rules

Rule Description Value (µm)

NW.W.1 Minimum Nwell Width 0.3NW.SP.1 Minimum Nwell spacing to Nwell (same potential) 0.3NW.SP.2 Minimum Nwell spacing to Nwell (different potential) 0.6NW.SE.1 Minimum Nwell spacing to N+ Active Area 0.16NW.SE.2 Minimum Nwell spacing to P+ Active Area 0.16


Active area (Oxide)


OXIDE.W.1 Minimum Active Area width 0.05OXIDE.SP.1 Minimum N+ Active Area to N+ Active Area spacing 0.08OXIDE.SP.2 Minimum P+ Active Area to P+ Active Area spacing 0.08OXIDE.SP.3 Minimum N+ Active Area to P+ Active Area spacing 0.1OXIDE.A.1 Minimum area for Active Area 0.035


Poly rules


POLY.W.1 Minimum N-channel gate length 0.045POLY.W.2 Minimum P-channel gate length 0.045POLY.SP.2 Minimum Poly gate space 0.06POLY.SP.3 Minimum Poly interconnect space 0.06POLY.W.5 Minimum Poly interconnect width 0.045


P-implant rules (1/2)


PIMP.W.1 Minimum P+ Implant width 0.12PIMP.SP.1 Minimum P+ Implant spacing 0.12PIMP.E.1 Minimum P+ Implant to Active Area enclosure 0.07PIMP.O.1 Minimum P+ Implant to Active Area overlap 0.08PIMP.SE.1 Minimum P+ Implant to N+ Active Area (outside Nwell) spacing 0.08


P-implant rules (2/2)


PIMP.E.2 Minimum P+ Implant to Active Area (substrate tie) enclosure 0.01PIMP.E.3 Minimum P+ Implant to gate side enclosure 0.1PIMP.SE.2 Minimum P+ Implant to N+ Active Area (Nwell tie) spacing 0.02PIMP.E.4 Minimum P+ Implant to gate (endcap) enclosure 0.1


Contact rules


CONT.W.1 Maximum and minimum Contact width/length 0.06CONT.SP.1 Minimum Contact to Contact spacing 0.06CONT.SE.1 Minimum Contact on Active Area to gate spacing 0.05CONT.SE.3 Minimum gate Contact on Active Area spacing 0.06CONT.E.1 Minimum Active Area to Contact enclosure 0.03CONT.E.2 Minimum Poly to Contact enclosure 0.02CONT.E.3 Minimum Poly to Contact enclosure on at least two opposite sides 0.03CONT.E.4 Minimum N+/P+ Implant on Active Area to Contact enclosure 0.03CONT.X.1 Contact on gate is NOT allowed —


Metal rulesà Metal 1


METAL1.W.1 Minimum Metal 1 width 0.06METAL1.W.2 Maximum Metal 1 width 6.0METAL1.SP.1.1 Minimum Metal 1 to Metal 1 spacing 0.06METAL1.E.2 Minimum Metal 1 to Contact enclosure around contact 0.03

à Metal k (K= 2 . . . 9)Rule Description Value (µm)

METALk.W.1 Minimum Metal k width 0.08METALk.W.2 Maximum Metal k width 6.0METALk.SP.1.1 Minimum Metal k to Metal k spacing 0.07METALk.E.2 Minimum Metal k to Via k-1 enclosure around via 0.03

à Metal k (K= 10, 11)Rule Description Value (µm)

METALk.W.1 Minimum Metal k width 0.22METALk.W.2 Maximum Metal k width 6.0METALk.SP.1.1 Minimum Metal k to Metal k spacing 0.20METALk.E.2 Minimum Metal k to Via k-1 enclosure around via 0.03


Once upon a time . . .

Fonte: [Weste11]


References

à Sources of the figures:

May04 G.S. May, S. M. Sze, Fundamentals of Semiconductor Fabrication,Wiley, 2004.

Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2ndedition,Prentice Hall, 2003.http://bwrc.eecs.berkeley.edu/icbook/

Weste11 N. Weste, D. Harris, CMOS VLSI Design, 4th ed., PearsonEducation, 2011.http://www3.hmc.edu/~harris/cmosvlsi/4e/index.html


http://bwrc.eecs.berkeley.edu/icbook/

http://www3.hmc.edu/~harris/cmosvlsi/4e/index.html