Workload distribution in satellites Part A Final Presentation

Performed by : Grossman Vadim

Maslovksy Eugene

Instructor: Rivkin Inna

Spring 2004

An introduction

Several I/O peripherals require lots of “attention”

Degrading the overall performance

Some systems should prioritize computational power over I/O latency

We were appointed to design a system that would enable that

Concept

Before

Main CPU

I/O per.

I/O per.

I/O per.

Before : Main CPU deals with ALL the I/O ALL the time!

After

EV04S (I/O CPU)

Main CPU

I/O per.

I/O per.

I/O per.

After : Main CPU deals ONLY with the device ONLY when needed!

What can we improve?

Implement the I/O protocols elsewhere– Using an I/O CPU

Reduce the number of distractions– Less interrupts– I/O CPU polling– Using Buffers

What are the possible implementations?

Possible solution #1

Advantages:– Faster access from the PPC– Only one IPIF

Disadvantages:– Additional load on the PLB– An additional bridge is required

A device connected to the PLB bus

PLB OPB

Main CPU

I/O CPU

PLB2OPB

OPB2PLB

EV04S

DDR

Possible solution #2

Advantages:– “The” place for peripherals– Only one IPIF– Less load on the PLB

Disadvantages:– Additional load on the OPB– Longer I/O data transfer times for the PPC

PLB OPB

Main CPU

I/O CPU

PLB2OPB

EV04S

A device connected to the OPB bus

Possible solution #3

Advantages:– Faster access from the PPC– Less load on the busses

Disadvantages:– More complex design– More hardware needed

PLB OPB

Main CPU

I/O CPU

PLB2OPB

EV04S

A hybrid of the previous two

Possible solution #4

Advantages:– Less issues with bus differences– The device is more transparent to the PPC

Disadvantages:– More complex design– Increased latency for all plb2opb transactions

PLB OPB

Main CPU

I/O CPU

PLB2OPB

EV04S

A “filter” device after bridge

So?

PLB OPB

Main CPU

I/O CPU

PLB2OPB

OPB2PLB

EV04S 1st

design

DDR

EV04S 2nd

design

PLB OPB

Main CPU

I/O CPU

PLB2OPB

EV04S 4th

design

EV04S 3rd

design

The hybrid (3rd) solution was chosen Slave or master?

– Slave using Interrupts!

Interrupts…

PPC has two interrupt inputs– Critical and Non-Critical

MB has one interrupt input For more signals, we’ll use an Inter. Cont.

– Number of signals limited by Bus data width– Controller accessed via OPB interface

Architecture diagram

PPCPPC

MBMB Peri. #1 Peri. #2 Peri. #3

OPB

PLB

Bram + Controller

PLB2OPB

DLMB

ILMB

Bram + Controller

EV04SEV04S

MB Intc PPC Intc

Deeper and deeper

IPIFIPIF

IPIFIPIF

Control Control UnitUnit

Buffers Buffers UnitUnit

OPB

PLB

PPC int.

MB int.

64 bits

32 bits

Buffers

Implemented using 2 FIFO sets (per device) Using Xilinx FIFO Core

– Synchronous FIFO, 1 clock– Asynchronous FIFO, 2 clocks– Asynchronous fits better

A new problem:– Different busses have different data widths!

Possible Solutions

Use only 32bits on the PLB– Slow!

Logic for double writes & double reads– Complicated!

FIFO

FIFO

64 bits

32 bits

32 bits

MUX32 bits

Co

ntro

l in

Double FIFO sets + a mux \ switch

Deeper into the buffers

FIFO SET PLB2OPB FIFO SET PLB2OPB

FIFO SET OPB2PLB FIFO SET OPB2PLB

Controls in/out

Controls in/out

64 bits

64 bits

32 bits

32 bits

• One unit for each device

• A register could be used for behavioral settings

Optional Reg.

Deeper into the controls

PLB

Controller

FIFO SET PLB2OPBFIFO SET PLB2OPB

FIFO SET OPB2PLBFIFO SET OPB2PLB

OPB

Controller

OPB clkR_req

W_req

Ack

Err

Busy

PLB clk

R_reqW_req

AckErr

Busy

PLB clk OPB clk

PLB clk OPB clk

W_

en

Ack

/Err

Fu

ll

Co

un

twrite read

R_

en

Ack

/Err

Em

pty

Co

un

t

W_

en

Ack/E

rr

Fu

ll

Co

un

t

writeread

R_

en

Ack/E

rr

Em

pty

Co

un

t

MB int. PPC int.

PLB

IPIF

PLB

IPIF

OP

B IP

IFO

PB

IPIF

Deeper into the FIFO set

FIFO 1FIFO 1

FIFO 2FIFO 2

64 bits

32 bits

32 bits

MUX32 bits

ControllerPLB2OPB set

R_en 1

R_en 2

W_en

MUX

From each FIFO

OPB clk

PLB clk

R_en

W_en

From upper level

R_

ack

W_

ack

Fu

ll

Em

pty

To upper level

Counter

R_

ack

W_

ack

Fu

ll1

Em

pty

Counter

ControllerThe controller:

• Create multiple control signals

• Manage the read switching

Controller

Deeper into the FIFO set

FIFO 1FIFO 1

FIFO 2FIFO 2

64 bits

32 bits

32 bits

DEC32 bits

ControllerOPB2PLB set

ControllerThe controller:

• Create multiple control signals

• Manage the write switching

Controller

OPB clk

PLB clk

W_en

R_en

From upper level

R_

ack

W_

ack

Fu

ll

Em

pty

To upper level

Counter

From each FIFO

R_

ack

W_

ack

Fu

ll1

Em

pty

Counter

W_en 1

W_en 2

R_en

MUX

Multiple devices

How about several I/O peripherals?

A unified device1) Use one “communication line” and protocol

Several devices2) A device for each peripheral3) Groups of 3 on a single IPIF

We currently aim for the 2nd solution The 1st will be considered as well

Tasks, scheduled (and completed?)

Making 2 CPUs work simultaneously

Implementing the buffer: FIFO, IPIF

Making the 2 CPUs exchange data via a shared BRAM

Debugging

Unscheduled work - interrupts

Current project status

PPC and MB system Buffer connected to PLB and OPB Two FIFO’s for each direction, 8bits data. Full signal connected to interrupts No controller, PLB FIFO makes double writes

and reads (next semester goal)

Demonstration

We pass data between the CPUs via our system

There are 3 phases:1. The CPUs pass a pair of numbers to each other

2. One CPU writes to the FIFO until it’s full.Then an interrupt occurs and the data is read

3. Repeat the 2nd phase the other way around

Demonstration (cont.)

Step 1: exchange data

Step 2: Test MB int.

Step 3: Test PPC int.Double writes & reads

Double writes & reads

Schedule

HDL flow and connection to EDK - 2 weeks

Writing a controller for IPIF2FIFO transactions - 2 weeks

Writing a controller for the FIFO set - 2 weeks

Unexpected bugs, issues, debugging - 2 week

Implementing the protocols:

Ethernet - 3 weeks

2 RS232 ports - 1 week

Simulation C programs - 1 week

Final tunings - 1 last week

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Thank you for your attention!

Thanks