What is this class all about?bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f12/...EE141 5...
Transcript of What is this class all about?bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f12/...EE141 5...
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EE141EECS141 1Lecture #1
EE141-Fall 2012Digital Integrated Circuits
TuTh 11-12:30pm247 Cory
Instructor: Elad Alon
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What is this class all about? Introduction to digital integrated circuit design
engineering Will describe models and key concepts needed to be a good
digital IC designer
Models allow us to reason about circuit behavior Allow analysis and optimization of the circuit’s performance,
power, cost, etc. Understanding circuit behavior is key to making sure it will
actually work
Teach you how to make sure your circuit works Do you want your transistor to be the one that screws up a 1
billion transistor chip?
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Detailed Topics CMOS devices and manufacturing technology CMOS gates Memories Propagation delay, noise margins, power Combinational and sequential circuits Interconnect Timing and clocking Arithmetic building blocks Design methodologies
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What will you learn? Understanding, designing, and optimizing
digital circuits for various quality metrics:
Performance (speed)
Power dissipation
Cost
Reliability
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Practical Information Instructor Prof. Elad Alon
519 Cory Hall, 642-0237, elad@eecsOffice hours: Tu. 3:30-4:30pm, Thurs. 2:30-3:30pm
TAs: Alberto Puggelli, puggelli@eecs (OH: Wed. 4-5pm) Bonjern Yang, byang@eecs (OH: Wed. 3-4pm)
Web page: http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f12/
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Discussions and LabsDiscussion sessions F 2-3pm (Bonjern) M 5-6pm (Alberto) Same material in all sessions!
Labs (125 Cory) M 3-6pm (Bonjern) Tu 3-6pm (Alberto) Machines to left of double doors, with larger monitors
Please choose one lab session and stick with it!
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M
T
W
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F
8 9 10 11 12 1 2 3 4 5 6
Lab(Alberto)125 Cory
Lab(Bonjern)
125 Cory
DISC*(Bonjern)
299 Cory
Lec(Elad)277 Cory
ProblemSets Due
Lec(Elad)277 Cory
* Discussion sections will cover identical material
OH(Elad)519 Cory
Your EECS141 Week
DISC*(Alberto)299 Cory
OH(Bonjern)TBD Cory
OH(Elad)519 Cory
OH(Alberto)TBD Cory
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Class Organization
9 Assignments
One design project (with a few phases)
Labs: 5 software
2 midterms, 1 final Midterm 1: Thurs., October 4, evening (TBD)
Midterm 2: Thurs., November 1, evening (TBD)
Final: Wed., December 12, 8-11am
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EE141EECS141 9Lecture #1
Some Important Announcements Please use piazza for asking questions (more
later) Can work together on homework But you must turn in your own solution
Lab reports due 1 week after the lab session Lab rules:
http://california.eecs.berkeley.edu/iesg/labs/labinfo/labrules.asp
Project is done in pairs No late assignments Solutions available shortly after due date/time
Don’t even think about cheating!
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Grading Policy
Homeworks: 12%
Labs: 8%
Projects: 20%
Midterms: 30%
Final: 30%
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Class Material
Textbook: “Digital Integrated Circuits – A Design Perspective”, 2nd ed, by J. Rabaey, A. Chandrakasan, B. Nikolic
Class notes: Web page Lab Reader: Web page Check web page for the availability of tools
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The Web Sitehttp://bwrc.eecs.berkeley.edu/icdesign/eecs141_f10
Class and lecture notes Assignments and solutions Lab and project information Exams Many other goodies …
Print only what you need: Save a tree!
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EE141EECS141 13Lecture #1
The Web Site #2 All announcements made at:
https://piazza.com/berkeley/fall2012/ee141
Be sure to enroll!
Piazza will also be the main forum for posting and answering questions Please post your questions there to minimize response time Also, check that your question hasn’t been answered already
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Software
Cadence Widely used in industry
Online tutorials and documentation
HSPICE for simulation
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Getting Started
Assignment 1: Getting SPICE to work –see web-page
Due next Thursday, August 30, 5pm
NO discussion sessions or labs this week.
First discussion sessions in Week 2
First software lab in Week 3
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Introduction
Digital Integrated Circuit Design: The Past, The Present and The Future What made Digital IC design what it is
today
Why is designing digital ICs different today than it was before?
Will it change in the future?
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EE141EECS141 17Lecture #1
The First Computer
The Babbage Difference Engine 25,000 parts
cost: £17,470
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ENIAC - The First Electronic Computer (1946)
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The Transistor Revolution
First transistorBell Labs, 1948
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The First Integrated Circuits
Bipolar logic1960’s
ECL 3-input GateMotorola 1966
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Intel 4004 Microprocessor
Intel, 1971.2,300 transistors (12mm2)740 KHz operation (10m PMOS technology)
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Intel Pentium 4 Microprocessor
Intel, 2005.125,000,000 transistors (112mm2)3.8 GHz operation (90nm CMOS technology)
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EE141EECS141 23Lecture #1
Intel Xeon (E7-8800)
Intel, 2011.2,600,000,000 transistors (513mm2)2.4 GHz operation (32nm CMOS technology)
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Still Happening - Intel Test-Chip (2009)
22nm364 MByte SRAM>2.91 billion transistors
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EE141EECS141 25Lecture #1
Moore’s Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
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Moore’s Law
16151413121110
9876543210
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LO
G2 O
F T
HE
NU
MB
ER
OF
CO
MP
ON
EN
TS
PE
R I
NT
EG
RA
TE
D F
UN
CT
ION
Electronics, April 19, 1965.
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Evolution in Complexity
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Transistor Counts
Doubles every 2 years
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Frequency
Has been doublingevery 2 years, but is now slowing down
Frequency Trends in Intel's Microprocessors
0.1
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005
Fre
qu
ency
[M
Hz]
4004
8008
8080
8086
8088
80286
386DX
486DX486DX4
Pentium
Pentium ProPentium II
Pentium MMX
Pentium III
Pentium 4
Itanium
Itanium II
Core2
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Power Dissipation Prediction (2000)
5KW 18KW
1.5KW 500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Po
wer
(W
atts
)
Courtesy, Intel
Did this really happen?
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Power Dissipation Data
Has been > doublingevery 2 years
Has to stay ~constant
Power Trends in Intel's Microprocessors
0.1
1
10
100
1000
1970 1975 1980 1985 1990 1995 2000 2005
Po
wer
[W
]
4004
8008 8080
8086
8088
80286
386DX
486DX
Pentium
Pentium Pro
Pentium II
Pentium IIIPentium 4
Itanium
Itanium II Core 2
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Cause: Power Density
400480088080
8085
8086
286386
486Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Po
wer
Den
sity
(W
/cm
2)
Hot Plate
Nuclear Reactor
Rocket Nozzle
S. Borkar
Sun’s Surface
Power density too high for cost-effective cooling
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Not enough cooling…
*Pictures from http://www.tomshardware.com/2001/09/17/hot_spot/
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Not Only Microprocessors
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband
(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)
CellPhone
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Challenges in Digital Design
“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”• Complexity• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.
…and There’s a Lot of Them!
DSM 1/DSM
?
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Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./ChipTr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Lo
gic
Tra
nsi
sto
r p
er C
hip
(M)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
du
ctiv
ity
(K)
Tran
s./S
taff
-M
o.
Source: Sematech
Complexity outpaces design productivity
Co
mp
lexi
ty
Courtesy, ITRS Roadmap
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EE141EECS141 37Lecture #1
Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more
functions per chip; chip cost does not increase significantly
Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every
two years…
Hence, a need for more efficient design methods Exploit different levels of abstraction
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Design Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM