UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land Forces

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land Forces

WBG Device Reliability TeamShort-Circuit Robustness of SiC Trench MOSFETs

Ron Green, Ph. D, Damian Urciuoli, Aivars Lelis, Ph. D,

Daniel Habersat, Franklin Nouketcha

2017 August

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 2

Performance Driven Design

Existing trend is to drive down Ron,sp by

cell optimization, substrate thinning, etc.

or by using alternative gate structures.

• Ron,sp is a measure of the current

handling capability for a given die

size

• Smaller Ron,sp value enables one to

shrink the die size

• 150 mm wafers coupled with smaller

die size and higher yields, lowers

device cost

• Lower static and dynamic losses in

comparison to Si IGBT

What is the impact on SC robustness for

SiC MOSFETs having

• Submicron channel lengths,

reduced cell pitch, and small

volume in which to dissipate power

Thanh-That Nguyen, Ashraf Ahmed, T. V.

Thang, and Joung-Hu Park, IEEE

TRANSACTIONS ON POWER ELECTRONICS,

VOL. 30, NO. 5, MAY 2015Tsunenobu Kimoto, Japanese Journal of

Applied Physics 54, 040103 (2015)

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 3

Novel Trench MOSFET Cell Designs

VGS = 15 V

D. Peters et al., "Performance

and ruggedness of 1200V SiC

— Trench — MOSFET," 2017

29th International Symposium

on Power Semiconductor

Devices and IC's (ISPSD),

Sapporo, Japan, 2017, pp.

239-242.

R. Nakamura et al., "1200V

4H-SiC Trench Devices,"

PCIM, Nuremberg, Germany,

2014, pp. 441-447.

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 4

Short-Circuit Behavior of SiC MOSFETs

Established D-S short-circuit failure

mechanisms

• A – represents a thermal failure

due to excessive power

dissipation.

• B – device overvoltage at turn-off.

This failure is not typically

observed experimentally.

• C – thermal runaway due to high

leakage current.

• The withstand time (tcrit) is the

primary short-circuit robustness

parameter.

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 5

SCWT and Peak Isc Dependence on VDS

0

5

10

15

20

25

200 400 600 800 1000t S

C[μ

s]

VDS [V]

MOSFET-A (single pulse)

GE 2015

MOSFET-B

MOSFET-A

MOSFET-C

100

140

180

220

260

300

100 200 300 400 500 600

Pe

ak

sh

ort

-cir

cuit

cu

rre

nt

(A)

DC link voltage, VDC (V)

MOSFET-C

MOSFET-A

MOSFET-BTPW = 2.5 us

VGS = 20.0 V

1.2 kV DMOSFET Short-Circuit Behavior

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 6

I sc

[A]

Time [μs]

0

200

400

600

800

0 2 4 6 8

En

erg

y [

mJ

]

Pulse Width [μs]

Trench Short-Circuit Characterization

• We utilize a series of short pulses

from 1 µs to failure

• Drain leakage current increases with

increasing pulse width

• No degradation observed in short-

circuit current transient

• An estimate of the critical energy was

calculated to be 0.7 J for this design,

with a SCWT of 7 µs at this condition

Ileakage

VGS = 18 V; VDS = 600 V

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 7

SC Current dependence on VGS

I sc

[A]

Time [μs]

VGS = 20 VVGS = 18 V

VGS = 16 V

VDS = 600 V

D. Peters et al., "Performance and

ruggedness of 1200V SiC — Trench —

MOSFET," 2017 29th International

Symposium on Power Semiconductor

Devices and IC's (ISPSD), Sapporo, Japan,

2017, pp. 239-242.

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 8

SCWT Comparison

0

5

10

15

20

25

14 16 18 20 22

t SC

[μs]

VGS [V]

Trench

DMOS-A

DMOS-B

VDS = 600 V

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 9

Critical Energy Estimation

0.0

0.2

0.4

0.6

0.8

0E+0 2E-6 4E-6 6E-6 8E-6 1E-5

EC

[J]

Time [s]

VGS = 20V

VGS = 18V

VGS = 16V

0.00.10.20.30.40.50.60.7

14 16 18 20 22

EC

[J]

VGS [V]

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 10

Differences in SC Failure Modes

I sc

[A],

VD

S[V

]

Time [s]

TrenchDMOS-ADMOS-B

Soft gate failure

D-S failure

D-S failure

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 11

Gate-Oxide Degradation

Time [μs]

VG

S[

V]

Trench

DMOS-ADMOS-B

Pre

Post

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesSlide 12

Summary

• Trench devices show adequate robustness but the SCWT is generally smaller in

comparison to planar DMOSFETs under similar test conditions.

• The SC behavior of trench devices is very similar to DMOSFETs.

• Trench and DMOSFET failures modes do differ. We observed insignificant gate

droop in comparison to DMOSFET devices, but the gate leakage current showed

some degradation due to stress.

• The critical energy varies insignificantly with gate-drive voltage and was to be less

than 0.7 J at 600 V bus voltage.