WAFERS DESCRIPTION NOMENCLATURE€¦ · ADVANCED TECHNOLOGY FOR RESEARCH & INDUSTRY: KNOWLEDGE BASE...

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WAFERS DESCRIPTION NOMENCLATURE ADVANCED TECHNOLOGY FOR RESEARCH & INDUSTRY KNOWLEDGE BASE FACT SHEET • SCOPE: This article explains the nomenclature used to identify wafer types and specification, along with the key descriptive criteria to consider when choosing wafers. Semiconductor wafer selection is key to a successful use of wafers and substrates for your process. Wafers are manufactured with very high precision, with attributes specific to the electronic and mechanical properties and any coatings applied after manufacture. Wafers are manufactured from four main materials: • Silicon • Glass and Fused Quartz • 3-5 or 2-6 Compound Semiconductors • Sapphire The figure below describes Inseto’s nomenclature chart for Silicon wafers: The second category of wafers we classify is coated wafers. These are wafers with an added layer either on both the top and bottom surfaces of the silicon or just one of the surfaces – usually the top. The figure below shows Inseto’s nomenclature chart for Coated Wafers:

Transcript of WAFERS DESCRIPTION NOMENCLATURE€¦ · ADVANCED TECHNOLOGY FOR RESEARCH & INDUSTRY: KNOWLEDGE BASE...

  • WAFERS DESCRIPTION NOMENCLATURE

    ADVANCED TECHNOLOGY FOR RESEARCH & INDUSTRY

    KNOWLEDGE BASE FACT SHEET

    • SCOPE: This article explains the nomenclature used to identify wafer types and specification, along with the key

    descriptive criteria to consider when choosing wafers. Semiconductor wafer selection is key to a successful use of wafers and substrates for your process. Wafers are manufactured with very high precision, with attributes specific to the electronic and mechanical properties and any coatings applied after manufacture. Wafers are manufactured from four main materials:

    • Silicon • Glass and Fused Quartz • 3-5 or 2-6 Compound Semiconductors • Sapphire

    The figure below describes Inseto’s nomenclature chart for Silicon wafers:

    The second category of wafers we classify is coated wafers. These are wafers with an added layer either on both the top and bottom surfaces of the silicon or just one of the surfaces – usually the top. The figure below shows Inseto’s nomenclature chart for Coated Wafers:

  • The third category of wafers we classify is glass wafers. These are used when a transparent substrate is required and are categorised by a different set of parameters. The figure below shows Inseto’s nomenclature chart for Glass Wafers:

  • The fourth category we use to classify our wafers is SOI wafers or Silicon-on-Insulator. These wafers are a sandwich of silicon-insulator-silicon. The insulator is typically silicon oxide or sapphire and the make-up of these is highly specific to the end application. The figure below shows Inseto’s nomenclature chart for SOI Wafers:

  • The fifth category we use to classify our wafers is SOS – Silicon-on-Sapphire. These wafers have an EPI Silicon layer on Kr grown Sapphire Wafers. The figure below shows Inseto’s nomenclature chart for SOS Wafers:

  • The final category we use to classify our wafers is Sapphire. These wafers are prime grade high quality with C, A and R plane crystal orientation from 2″ to 150mm. They are single or double side polished, have low roughness and are defect free. The figure below shows Inseto’s nomenclature chart for Sapphire Wafers:

  • For further information about Inseto’s Wafers: https://www.inseto.co.uk/consumables/semiconductor-wafers-and-substrates-by-inseto/

    IAN BURNETT 26 March 2019

    IKB044, REV 4 PATH: Wafers_Selections_Nomenclature

    https://www.inseto.co.uk/consumables/semiconductor-wafers-and-substrates-by-inseto/https://www.inseto.co.uk/consumables/semiconductor-wafers-and-substrates-by-inseto/

    /ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 300 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages true /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 1200 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 1200 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile () /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False

    /CreateJDFFile false /Description > /Namespace [ (Adobe) (Common) (1.0) ] /OtherNamespaces [ > /FormElements false /GenerateStructure false /IncludeBookmarks false /IncludeHyperlinks false /IncludeInteractive false /IncludeLayers false /IncludeProfiles false /MultimediaHandling /UseObjectSettings /Namespace [ (Adobe) (CreativeSuite) (2.0) ] /PDFXOutputIntentProfileSelector /DocumentCMYK /PreserveEditing true /UntaggedCMYKHandling /LeaveUntagged /UntaggedRGBHandling /UseDocumentProfile /UseDocumentBleed false >> ]>> setdistillerparams> setpagedevice


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