Wafer Level Molded DDFN Package Project Duane...

Wafer Level Molded DDFN

Package Project

Duane Wilcoxen

Wafer Level Molded DDFN Package

Definition of DDFN (Encapsulated CSP)

• DDFN package basically is a CSP device with an epoxy coating on all

(or most) of the device sides for added protection.

• The epoxy encapsulation covers the silicon device, but leaves exposed

solderable connections for the assembly process.

• The solderable connection may be copper pads or solder bumps,

depending on the package process technology.

• The final device structure is an “epoxy brick” with solderable contacts

like a chip resistor for flip chip assembly.

Section Silicon Device

CSP Bumps

Epoxy

Encapsulation


Motivation for DDFN Package • DDFN packaging eliminates requirements for wire bonds. All

connections are direct solderable metal contacts between die and

board Higher Reliability.

• The epoxy encapsulation provides mechanical protection for the

device Better handling protection at assembly.

• DDFN device structure is similar to a standard chip resistor

Known assembly requirements.

• The DDFN process is ideally suited for small die that are difficult to

manage in a wire bonded assembly due to the pick and place

requirements of the small die.


Top View

Bottom View

Structure Cross Section

DDFN Package

Characteristics:

1. Chip scale device fully

encapsulated with epoxy.

2. Minimal overall package height.

3. Solderable metal of contact

points above die surface.

4. Epoxy covering at least five of

six sides of device.

Example DDFN Package

Outline


Example 0603 DDFN Package

Dimension

Die Thickness 0.200~0.250mm

Gold Bump Standoff Height 0.010~0.030mm

Backside Epoxy Thickness 0.025~0.030mm

Total Thickness (Max.) 0.250~0.275mm

E

Marking

depth

Die

thickness

b

D

L

Metal bump

standoff height

D 0.62+/-0.035

E 0.32+/-0.035

b 0.22+/-0.025

L 0. 20+/-0.025

D-DFN0603 vs Std. DFN0603

Top View Bottom View


Top View Bottom View


D-DFN0603 DFN0603

D-DFN eliminates WIRE connection of DFN device to improve

performance and reduce manufacturing variability.



Transferring an Existing Design into Wafer Level DDFN

• DDFN package sizes can be standardized to create specific final

package dimensions with smaller die inside.

• Device designs would include “extra silicon” to fill un-usable area

required for epoxy molding.

• For a given DDFN Package Design, there is a maximum available die

space for layout, with 0.05mm of layout area on each side of the die

required for scribe lane trenching and epoxy fill for side walls.

• DDFN device structure is an “epoxy brick” with solderable metal

connections spaced for flip chip assembly.


Advantages of Wafer Level Encapsulation • Wafer level processing leverages economies of scale manufacturing

for maximum process UPH with minimal component level processing.

Only component level operation in flow is placement of final package

into carrier tape.

• Micron level resolution of surface dimensions using wafer level photo

processing techniques for better dimensional control.

• Singulation dicing process is carried out with single scribe lane cut

with precise control of epoxy sidewall thickness.

• Precise control of materials usage and improved efficiency at wafer

level with reduced waste.


DDFN0603-2 Final Package Dimensions

Final Package Size = 0.62X0.32mm

Die Sawing Process To Be Specified with

MAXIMUM 40um Kerf


Remarks:

These values are from the DDFN Design Specification for the final targeted values. Samples will be

created to confirm the final results and the tolerance levels for each of the parameters.

DDFN Design Dimensions

Nominal Dimensions of

DDFN FeaturesDDFN1006-2 DDFN0806-2 DDFN0603-2 DDFN0402-2 DDFN1006-3 DDFN0806-3 DDFN0606-3 DDFN0505-3

Final Package Size um 1000 X 600 800 X 600 620 X 320 400 X 200 1000 X 600 800 X 600 620 X 620 540 X 540

Final Package Height um 275 275 275 175 275 275 275 275

Chip Size (Max. Layout Area) um 890 X 490 690 X 490 510 X 210 350 X 150 890 X 490 690 X 490 510 X 510 430 X 430

Stepping Distance um 1040 X 640 840 X 640 660 X 360 440 X 240 1040 X 640 840 X 640 660 X 660 580 X 580

Effective Scribe Width um 150 150 150 90 150 150 150 150

Final Bump Size um 480 X 230 480 X 230 200 X 140 140 X 90480 X 230

230 X 150

480 X 230

230 X 150

500 X 200

200 X 200

420 X 150

150 X 150

PV Opening Size um 435 X 185 435 X 185 155 X 95 110 X 60435 X 185

185 X 105

435 X 185

185 X 105

455 X 155

155 X 155

375 X 105

105 X 105

Estimated Die per Wafer

(150mm wafer) 23 000 28 000 64 000 150 000 23 000 28 000 35 000 45 000


Process Step Resp. Comments

Front End Device Fabrication Diodes Production processing on 150mm or 200mm wafers

Thick Plated Ni Metal Bumps on Bond Pads K-Bump Plated 30um Ni Bump

Trench Cut Wide Scribes

(140um wide / 300um deep)

K-Bump Open gaps between die for epoxy fill

No split – All wafers have 150um scribe

Compression Mold Epoxy Material K-Bump Epoxy surface coverage to fill trenches and

completely cover Ni bumps

Device Side Epoxy Surface Removal K-Bump Face grind of epoxy to expose Ni pads and provide

flat wafer surface

Re-Plate NiAu Surface Connection K-Bump Plate solderable metal on bump surface

Substrate Backside Grind to 10mils K-Bump Post grind substrate thickness of 250um

Backside Epoxy Lamination K-Bump Backside Epoxy Lamination Mold to 25um

Final Electrical Test / Laser Mark CAT Wafer Level E-Test and Laser Marking

Wafer Saw / Dicing CAT Singulation Process

Tape and Reel CAT Back End process can be performed as standard

CSP product or using a DFN component level

operation for test, marking and TnR.

Wafer Level DDFN Process Flow


K-Bump E-CSP Operation:

ENiG Plating

(K-Bump) Trench Partial

Saw

(K-Bump)

Epoxy Mold

(K-Bump) Polish top-side to

expose bump

(K-Bump)

Back-side

Grind

(K-Bump)

Back-side

Epoxy Coat

(K-Bump)

Test, Laser Mark

(SAT or CAT)

Singulate

(SAT or CAT) TnR w/DFN0603

setup

(SAT or CAT)

K-Bump Wafer Level DDFN Process Flow

WLM DDFN Production Module

Step Tool Process

Incoming Inspection Olympus Microscope Semi-Automatic

Thick Ni Plating Ni Plate System Automatic

Trench Cut Disco DAD3350 Saw Automatic

Epoxy Mold Front Apic Yamada Mold Automatic

Mold Cure Blue M Oven Semi-Automatic

Grind Face Side Epoxy Disco DFG8540 Automatic

ENiG Re-Plating NiAu Plate System Automatic

Tape Front-side Laminator Automatic

Grind Back Side Silicon Disco DFG8540 Automatic

Stress Relief HF Dip Tank / IPA Dryer Automatic

Detape Front-side Delaminator Automatic

Epoxy Laminate Back Lintec 3500F/8DBS Automatic

BSL Cure Blue M Oven Semi-Automatic

Ship Semitool SRD Semi-Automatic

Supporting metrology equipment are not included in the flow. These are not required to be automated.

Manual processes are prone to high breakage due to the Manual Handling aspect.


• DDFN Design Guide Established: • Device specs completed for packages of DDFN0505-3, DDFN0606-3, DDFN0603-2, DDFN0806-3,

DDFN1006-3, DDFN1006-2.

• Thick ENIG Bump Process Defined: • 30um NiAu plating process setup and verified for DDFN designs.

• Trench Dicing Process Defined: • Trench dicing process setup and defined for 140um wide trench at 300um depth.

• Adequate process control has been demonstrated for epoxy trench formation.

• Process optimization to be completed to improve UPH of process.

• Face Side Epoxy Mold Operation Defined: • Face side epoxy molding operation has shown to be capable with adequate repeatability.

• Epoxy dispense control needs additional development to improve accuracy and repeatability.

• Dispense volume targets have been established for different device designs.

• Face Side Polish Process Defined: • Face side epoxy polish process has shown to be capable to clear epoxy mold residue while maintaining

NiAu bump surface condition.

• Process optimization to be completed for volume production operations.

DDFN Project Accomplishments


• DDFN Standard Reliability Testing: • Full gamut of standard reliability testing completed on SBR2U20ECSP device.

• HS / HTRB 1000hrs at 150C

• Pressure Cooker Test (component and board level) 96hrs

• Temperature Cycle: >2500 cycles at -55C to 150C

• Solderability Testing

• No Failures

• DDFN Automotive Level Reliability Testing:

• Automotive level reliability testing completed on BJT0806ECSP device.

• HS / HTRB 1000hrs at 175C

• Pressure Cooker Test (component and board level) 96hrs

• Temperature Cycle: 1000 cycles at -55C to 175C

• Solderability Testing

• No Failures

DDFN Reliability Accomplishments

DDFN0505 Example: MOSFET DM2200UFS

DDFN0505 Example: MOSFET DM2200UFS

Package Back Side

Top View

Final Bump Surface Bottom Side View

Top View

WLM DDFN Process Flow – Back End

Diodes DDFN Back End Operation:

Wafer Level Operations

Electrical Test / Back Side

Laser Mark

Note: Patents Pending on DDFN process flow and device designs.

Singulation Process

Mount on Dicing Frame

and Wafer Saw Dicing

Final Visual Inspection

Pick and Place Operation

Place Die in Carrier Tape

Back End operation flow will be improved in near future by replacing wafer level test and laser

marking with component level processing using an automated small die handling system to

improve process UPH and reduce equipment set.


Process Sequence Options for DDFN Back End

Standard Flow Current

Equipment

Wafer Level Electrical Test TSK Handler + SineTest or

Juno Tester

Wafer Level Back Side Laser

Mark

EO Technics CSM2000

Dicing Frame Mount Longhill Mounter

Saw Dicing Singulation Disco DFD6341

Wafer Level Visual

Inspection

Camtek Falcon

Pick and Place into Carrier

Tape

Muehlbauer DS20000

Small Die Handler

Flow

Equipment

Dicing Frame Mount Longhill Mounter

Saw Dicing Singulation Disco DFD6341

Component Electrical Test

Small Die Handler

Ueno Seiki RT20

Component Back Side Laser

Mark

Component Visual Inspection

Pick and Place into Carrier

Tape

Small Die Handling Tool performs test, laser mark, inspection and TnR process.

Significantly reduces equipment set for back end process.

Visual inspection on handler includes 5 side package inspection.

Die pick up directly from dicing film frame reducing issues with bowl feed die damage.


Small Die Component Handler

UENO SEIKI CO., LTD.

PICKUP

Wafer Ring Holder

Test 1

Xyθ alignment

Test 2

Xyθ alignment

1.Laser alignment

inspection

2.Laser marking

3.Mark inspection

4.Pick up

5S inspection

6 Rank Bin

Taping

(Alignment

function)

Wafer Ring Auto

Loader MAX12”(Option)

Xyθ alignment unit

TEST1

TEST2

Ueno Seiki RT20 System Capable of

Handling Die to 400X200um

Wafer Level Molded DDFN Package Project Duane...

Documents

Transcript of Wafer Level Molded DDFN Package Project Duane...