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Functional Verification

Functional verification, in electronic design automation, is the task of verifying that the logic

design conforms to specification. In everyday terms, functional verification attempts to answer

the question "Does this proposed design do what is intended?" This is a complex task, and takes

the majority of time and effort in most large electronic system design projects.

Functional verification is very difficult - it is equivalent to program verification, and is NP-

hard or even worse - and no solution has been found that works well in all cases. However, it

can be attacked by many methods. None of them are perfect, but each can be helpful in certain

circumstances:

Logic simulation simulates the logic before it is built.

Simulation acceleration applies special purpose hardware to the logic simulation

problem.

Emulation builds a version of system using programmable logic. This is expensive, and

still much slower than the real hardware, but orders of magnitude faster than simulation. It

can be used, for example, to boot the operating system on a processor.

Formal verification attempts to prove mathematically that certain requirements (also

expressed formally) are met, or that certain undesired behaviors (such as deadlock) cannot

occur.

Intelligent verification uses automation to adapt the testbench to changes in

the register transfer level code.

HDL-specific versions of lint, and other heuristics, are used to find common problems.

Simulation based verification (also called 'dynamic verification') is widely used to "simulate" the

design, since this method scales up very easily. Stimulus is provided to exercise each line in the

HDL code. A test-bench is built to functionally verify the design by providing meaningful

scenarios to check that given certain input, the design performs to specification.

A simulation environment is typically composed of several types of components:

The generator[disambiguation needed] (or irritator) generates input vectors. Modern generators

generate random, biased, and valid stimuli. The randomness is important to achieve a high

distribution over the huge space of the available input stimuli. To this end, users of these

generators intentionally under-specify the requirements for the generated tests. It is the

role of the generator to randomly fill this gap. This mechanism allows the generator to

create inputs that reveal bugs not being searched for directly by the user. Generators also

bias the stimuli toward design corner cases to further stress the logic. Biasing and

randomness serve different goals and there are tradeoffs between them, hence different

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generators have a different mix of these characteristics. Since the input for the design must

be valid (legal) and many targets (such as biasing) should be maintained, many generators

use theConstraint satisfaction problem (CSP) technique to solve the complex testing

requirements. The legality of the design inputs and the biasing arsenal are modeled. The

model-based generators use this model to produce the correct stimuli for the target design.

The drivers translate the stimuli produced by the generator into the actual inputs for the

design under verification. Generators create inputs at a high level of abstraction, namely, as

transactions or assembly language. The drivers convert this input into actual design inputs

as defined in the specification of the design's interface.

The simulator produces the outputs of the design, based on the design’s current state

(the state of the flip-flops) and the injected inputs. The simulator has a description of the

design net-list. This description is created by synthesizing the HDL to a low gate level net-

list.

The monitor converts the state of the design and its outputs to a transaction abstraction

level so it can be stored in a 'score-boards' database to be checked later on.

The checker validates that the contents of the 'score-boards' are legal. There are cases

where the generator creates expected results, in addition to the inputs. In these cases, the

checker must validate that the actual results match the expected ones.

The arbitration manager manages all the above components together.

Different coverage metrics are defined to assess that the design has been adequately exercised.

These include functional coverage (has every functionality of the design been exercised?),

statement coverage (has each line of HDL been exercised?), and branch coverage (has each

direction of every branch been exercised?).

Functional Verification Tools

Avery Design Systems: SimCluster (for parallel logic simulation) and Insight (for formal

verification)

Cadence Design Systems

EVE/ZeBu

Mentor Graphics

Nusym Technology

Obsidian Software

Synopsys

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Test Bench

A test bench is a virtual environment used to verify the correctness or soundness of a design or

model (e.g., a software product).

The term has its roots in the testing of electronic devices, where an engineer would sit at a lab

bench with tools of measurement and manipulation, such as oscilloscopes, multimeters,

soldering irons, wire cutters, and so on, and manually verify the correctness of the device under

test.

In the context of software or firmware or hardware engineering, a test bench refers to an

environment in which the product under development is tested with the aid of a collection of

testing tools. Often, though not always, the suite of testing tools is designed specifically for the

product under test.

A test bench or testing workbench has four components.

1.INPUT: The entrance criteria or deliverables needed to perform work

2.PROCEDURES TO DO: The tasks or processes that will transform the input into the output

3.PROCEDURES TO CHECK: The processes that determine that the output meets the standards.

4.OUTPUT: The exit criteria or deliverables produced from the workbench

First create an empty folder in desktop to keep all your files and name it as “exercise”

The following is the path for opening ModelSim SE:

Start All Programs ModelSim SE 6.6c ModelSim

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Now change your working directory to “exercise” folder

File Change Directory

Browse for exercise folder which is on desktop

Click ok

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To create a new project, go to

File New Project

Enter project name as “basic” and click ok

Give name as file name “counter” and click ok

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Observe there is one project tab added, in which your project name is counter

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Double click counter.v, and start coding for counter in open space

Click library tab, work is default working library of modelsim. It is empty because we have not yet

compiled our counter code.

Now add test bench to our project

Click project tab, select counter.v

Right click counter.v Add to Project New File

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Click New File, name counter_test and type as “Verilog” and click ok

Double click counter_test.v and start typing test bench

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Now select both files counter.v and counter_test.v ( use ctrl key to select both files)

To compile, go to compile Compile All

After compilation check if your code is having any errors

Now simulate your design

Select top entity of your project i.e. counter_test.v

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Simulate Start Simulation

In the design tab, select test_counter

Disable “Enable optimization” or uncheck and click ok

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All the waves in design are added to the waveform window.

Click on Simulate button , all the input vectors written in testbench are applied to the dut and

waveforms are displayed in the window aas shown below.

After doing basic simulation, click on view and select dataflow. This option is useful for

debugging porpose.

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Once, we add a signal to wave, following wizard pops up. This is helpful for debugging. If any of

the output is X, then by using dataflow command the backtrace can be done and the source that

causes X can be found.

Code coverage

This is useful for any design which helps the verification engineer to apply all cases to the DUT

and check whether all lines of code is covered or not. There are different types of code coverages

like Statement Coverage, Line Cloverage, Expression Coverage etc.

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Compile all the files in design.

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Click Start Simulation

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Enable Code Coverage

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Again run simulation with the selected coverage directives.

All the coverages can be found with 0% covered because we did not apply he inpu stimulus till

now.

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Once we run simulation, alll the coverage directives will be displayed.

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Synsthesis

After Functional verification is done, we now do synthesis.

In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior

(typically register transfer level (RTL)) is turned into a design implementation in terms oflogic

gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog.

Some tools can generate bitstreams for programmable logic devices such asPALs or FPGAs,

while others target the creation of ASICs. Logic synthesis is one aspect of electronic design

automation.

History of logic synthesis

The roots of logic synthesis can be traced to the treatment of logic by George Boole (1815 to

1864), in what is now termed Boolean algebra. In 1938, Claude Shannon showed that the two-

valued Boolean algebra can describe the operation of switching circuits. In the early days, logic

design involved manipulating the truth table representations as Karnaugh maps. The Karnaugh

map-based minimization of logic is guided by a set of rules on how entries in the maps can be

combined. A human designer can typically only work with Karnaugh maps containing up to four

to six variables.

The first step toward automation of logic minimization was the introduction of the Quine–

McCluskey algorithm that could be implemented on a computer. This exact minimization

technique presented the notion of prime implicants and minimum cost covers that would

become the cornerstone of two-level minimization. Nowadays, the much more

efficient Espresso heuristic logic minimizer has become the standard tool for this operation.

Another area of early research was in state minimization and encoding of finite state

machines (FSMs), a task that was the bane of designers. The applications for logic synthesis lay

primarily in digital computer design. Hence, IBM and Bell Labs played a pivotal role in the early

automation of logic synthesis. The evolution from discrete logic components to programmable

logic arrays (PLAs) hastened the need for efficient two-level minimization, since minimizing

terms in a two-level representation reduces the area in a PLA.

However, two-level logic circuits are of limited importance in a very-large-scale

integration (VLSI) design; most designs use multiple levels of logic. As a matter of fact, almost

any circuit representation in RTL or Behavioural Description is a multi-level representation. An

early system that was used to design multilevel circuits was LSS from IBM. It used local

transformations to simplify logic. Work on LSS and the Yorktown Silicon Compiler spurred rapid

research progress in logic synthesis in the 1980s. Several universities contributed by making

their research available to the public, most notably SIS from University of California, Berkeley,

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RASP from University of California, Los Angeles and BOLD from University of Colorado, Boulder.

Within a decade, the technology migrated to commercial logic synthesis products offered by

electronic design automation companies.

High-level synthesis or behavioral synthesis

With a goal of increasing designer productivity, research efforts on the synthesis of circuits

specified at the behavioral level have led to the emergence of commercial solutions in 2004[1],

which are used for complex ASIC and FPGA design. These tools automatically synthesize circuits

specified at C level to a register transfer level (RTL) specification, which can be used as input to

a gate-level logic synthesis flow.[1] Today, high-level synthesis, also known as ESL synthesis and

behavioral synthesis, essentially refers to circuit synthesis from high level Languages like ANSI

C/C++ or SystemC etc., whereas Logic Synthesis refers to synthesis from structural or functional

description to RTL.

Multi-level logic minimization

Typical practical implementations of a logic function utilize a multi-level network of logic

elements. Starting from an RTL description of a design, the synthesis tool constructs a

corresponding multilevel Boolean network.

Next, this network is optimized using several technology-independent techniques before

technology-dependent optimizations are performed. The typical cost function during

technology-independent optimizations is total literal count of the factored representation of

the logic function (which correlates quite well with circuit area).

Finally, technology-dependent optimization transforms the technology-independent circuit into

a network of gates in a given technology. The simple cost estimates are replaced by more

concrete, implementation-driven estimates during and after technology mapping. Mapping is

constrained by factors such as the available gates (logic functions) in the technology library, the

drive sizes for each gate, and the delay, power, and area characteristics of each gate.

Commercial tool for logic synthesis

1. Software tools for logic synthesis targeting ASICs

Design Compiler by Synopsys

Encounter RTL Compiler by Cadence Design Systems

BuildGates, an older product by Cadence Design Systems, humorously named

after Bill Gates

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TalusDesign by Magma Design Automation

BooleDozer: Logic synthesis tool by IBM (internal IBM EDA tool)

2. Software tools for logic synthesis targeting FPGAs

Encounter RTL Compiler by Cadence Design Systems

LeonardoSpectrum and Precision (RTL / Physical) by Mentor Graphics

Synplify (PRO / Premier) by Synplicity

BlastFPGA by Magma Design Automation

Quartus II integrated Synthesis by Altera

XST (delivered within ISE) by Xilinx

DesignCompiler Ultra and IC Compiler by Synopsys

IspLever by Lattice Semiconductor

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To start Precision follow this path.

Go to Start All Programs Precision Precision RTL

Following window pops up, where we can create new project or open an existing project.

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To crate a new project, click new project

Enter project name and browse the path, where it should be saved.

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Now a new project is created named Techlabs_synthesis.

To add new .v or .vhd files, right click on input files and select add input files.

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We need to add only design files , no need to add test bench files here.

Next set up design as shown below.

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Click on synthesis design.

After synthesis, many files are added to the output files as shown below.

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All the information in the output files can be viewed by double clicking on the file.

Following is the example of RTL schematic.

Technology Schematic.

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Area Report.

No of output files that can be viewed is shown below.

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All the options that can be accessed under each category is listed below.

To create new implementation of the same design

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After running the process one can view all the files of different implementations for same project.

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Programs

adder_8bit.v

module adder_8bit ( a, b, cin , sum, cout);

//inputs

input [7:0] a;

input [7:0] b;

input cin;

//outputs

output [7:0] sum;

output cout;

//wires

wire [7:0] a;

wire [7:0] b;

wire cin;

adder_1bit a1 ( a[0] , b[0] , cin , sum[0] , c1);

adder_1bit a2 ( a[1] , b[1] , c1 , sum[1] , c2);

adder_1bit a3 ( a[2] , b[2] , c2 , sum[2] , c3);

adder_1bit a4 ( a[3] , b[3] , c3 , sum[3] , c4);

adder_1bit a5 ( a[4] , b[4] , c4 , sum[4] , c5);

adder_1bit a6 ( a[5] , b[5] , c5 , sum[5] , c6);

adder_1bit a7 ( a[6] , b[6] , c6 , sum[6] , c7);

adder_1bit a8 ( a[7] , b[7] , c7 , sum[7] , cout);

endmodule

adder_1bit.v

module adder_1bit ( a , b, cin , sum, cout );

//inputs

input a , b , cin;

//outputs

output sum, cout;

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assign sum = a ^ b ^cin;

assign cout = cin(a^b) + ab;

endmodule

test_adder.v

// test bench for 8-bit adder

module test_adder();

reg [7:0] a;

reg [7:0] b;

reg cin;

wire [7:0] sum;

wire [7:0] cout;

//instantiate the adder

adder_8bit dut( a, b, cin , sum, cout);

initial begin

a = 8'b00000000;

b = 8'b00000000;

cin = 1'b0;

#10 a = 8'b00001111 ; b = 8'b11110000; cin = 1'b1;

#20 a = 8'b11110000; b = 8'b00001111; cin = 1'b1;

#30 a = 8'b00001111; b = 8'b11110000; cin = 1'b0;

#100 $finish;

end

endmodule

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address_decoder.v

module decoder_using_case (

binary_in , // 4 bit binary input

decoder_out , // 16-bit out

enable // Enable for the decoder

);

input [3:0] binary_in ;

input enable ;

output [15:0] decoder_out ;

reg [15:0] decoder_out ;

always @ (enable or binary_in)

begin

decoder_out = 0;

if (enable) begin

case (binary_in)

4'h0 : decoder_out = 16'h0001;

4'h1 : decoder_out = 16'h0002;

4'h2 : decoder_out = 16'h0004;

4'h3 : decoder_out = 16'h0008;

4'h4 : decoder_out = 16'h0010;

4'h5 : decoder_out = 16'h0020;

4'h6 : decoder_out = 16'h0040;

4'h7 : decoder_out = 16'h0080;

4'h8 : decoder_out = 16'h0100;

4'h9 : decoder_out = 16'h0200;

4'hA : decoder_out = 16'h0400;

4'hB : decoder_out = 16'h0800;

4'hC : decoder_out = 16'h1000;

4'hD : decoder_out = 16'h2000;

4'hE : decoder_out = 16'h4000;

4'hF : decoder_out = 16'h8000;

endcase

end

end

endmodule

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test_decoder.v

module test_decoder;

reg [3:0] binary_in;

reg enable;

wire [15:0] decoder_out;

decoder_using_case dut (binary_in, decoder_out,enable);

initial begin

binary_in = 4'h0;enable = 0;

#10

enable = 1;

#10

binary_in = 4'h1;

#10

binary_in = 4'h7;

#10

binary_in = 4'hA;

#10

binary_in = 4'hF;

#10

binary_in = 4'h3;

end

endmodule

mux using if

module mux_4to1_using_if (a, b, c, d, s, o);

input a,b,c,d;

input [1:0] s;

output o;

reg o;

always @(a or b or c or d or s)

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begin

if (s == 2'b00)

o = a;

else if (s == 2'b01)

o = b;

else if (s == 2'b10)

o = c;

else

o = d;

end

endmodule

test_mux.v

module test_mux;

reg a, b, c, d;

reg [1:0] s;

wire o;

mux_4to1_using_if dut (a, b, c, d, s, o);

initial begin

a=1;b=1;c=0;d=0;

s=00;

#20

s=01;

#20

s=10;

#20

s=11;

end

endmodule

Multiplier

module multiplier_4bit( a , b , out);

//inputs

input [3:0] a;

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input [3:0] b;

//output

output [8:0] out;

//wires

wire [3:0] a;

wire [3:0] b;

assign out = a * b;

endmodule

Test_Multiplier

module test_multiplier;

reg [3:0] a;

reg [3:0] b;

wire [8:0] out;

multiplier_4bit dut( a , b , out);

initial begin

a=4'b0000, b=4'b0000;

#20

a=4'b0001, b=4'b0011;

#20

a=4'b1111, b=4'b1111;

end

endmodule

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Accumulator

module accumulator (clk, clr, d, q);

input clk, clr;

input [3:0] d;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)

begin

if (clr)

tmp = 4'b0000;

else

tmp = tmp + d;

end

assign q = tmp;

endmodule

test_accumulator

module test_acc;

reg clk, clr;

reg [3:0] d;

wire [3:0] q;

accumulator dut (clk, clr, d, q);

initial begin

forever begin

clk <= 0;

#5

clk <= 1;

#5

clk <= 0;

end

end

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initial begin

clr = 0;

#20

clr = 1;data = 0001;

#20

clr = 0; data = 0010;

#20

data = 0011;

#20 clr = 1

end

endmodule

Counter

module up_counter (

out , // Output of the counter

enable , // enable for counter

clk , // clock Input

reset // reset Input

);

//----------Output Ports--------------

output [7:0] out;

//------------Input Ports--------------

input enable, clk, reset;

//------------Internal Variables--------

reg [7:0] out;

//-------------Code Starts Here-------

always @(posedge clk)

if (reset) begin

out <= 8'b0 ;

end else if (enable) begin

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out <= out + 1;

end

endmodule

Test bench for up counter

module test_upcounter;

reg clk, reset,enable ;

wire [7:0] out;

up_counter dut (out, enable, clk ,reset);

initial begin

forever begin

clk <= 0;

#5

clk <= 1;

#5

clk <= 0;

end

end

initial begin

reset = 1;

#20

reset = 0;enable = 1;

#100

enable = 0;

#150

reset = 0;

end

endmodule

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PRBS Generator

module prbs (rand, clk, reset);

//inputs

input clk, reset;

//outputs

output rand;

//wires

wire rand;

//internal registors

reg [3:0] temp;

//always @ (posedge reset) begin

//temp <= 4'hf;

//end

always @ (posedge clk)

begin

if (reset)

temp <= 4'h1;

else

temp <= {temp[0]^temp[1],temp[3],temp[2],temp[1]};

end

assign rand = temp;

endmodule

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Test Bench for PRBS

module main;

reg clk, reset;

wire rand;

prbs pr (rand, clk, reset);

initial begin

forever begin

clk <= 0;

#5

clk <= 1;

#5

clk <= 0;

end

end

initial begin

reset = 1;

#12

reset = 0;

#90

reset = 1;

#12

reset = 0;

end

endmodule

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Experiments 5 to 8 should be worked on Tanner. The basic working on all the tools of tanner is

explained with simple Inverter Design.

The following is the path for opening S-Edit tool :

Start All Programs Tanner EDA Tanner V 15 S-Edit V15.0 32 Bit

To do schematic entry , run S-Edit tool

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To create a new design : File New Design

Enter the design name and give the path where it should be saved.

Example : techlabs_designs is the design folder

C:\Documents and Settings\phanendra\My Documents\Tanner_lab is the target location of

design folder

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Add component libraries. The path for component libraries is given below.

My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm

Click add in S-Edit window for adding the libraries and follow the path of process folder.

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Double click all the component libraries under Generic_250nm and add all tanner database files

(.tdb).

To add Spice commands and Spice Elements for setting spice simulation follow the path.

My Documents\Tanner EDA\Tanner Tools v15.0\Process\Standard_Libraries

Now , we need to create a new cell.

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Give a new name for cell

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Scroll mouse for Zoom In and Zoom Out. And to view entire design press home button on

keyboard.

Click on Generic_250nm_Devices folder on libraries

To add any component either drag the component on to the design area (black region

with grids) or click Instance , then Instance Cell pops up where a user can change the

properties . Keeping the icon on the design area , components icon can be placed N

number of times. Either press ESC button on keyboard or Done on Instance Cell window

to stop placing of cells.

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In the same way place PMOS component on the design area.

To Zoom the design area scroll the mouse or press home button on keyboard.

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Now place Vdd and Gnd Instances from the Misc folder under Library.

Now place a DC Voltage and Pulse Voltage source from the Spice Elements folder under Library.

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To place a Voltage Source, Click Spice Elements, Under Spice Elements Click Voltage Source and

then Instance.

To place a DC voltage source, change the interface to DC and edit the voltage value . Click done

only after placing the voltage source on design area.

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To place a Pulse voltage source, change the interface to DC and edit the voltage value . Click

done only after placing the voltage source on design area.

Place Vdd and Gnd even for the voltage sources as shown.

Now place Input and Output ports.

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When an input port is placed, In port window pops up where we can edit the port name , font size

and orientation. Even the port orientation can be changed by pressing r button on key board.

Now we have placed all the components on the design window. And connections are made using

the wire as shown below

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Now we need to set up simulation.

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Now , give the path of library file.

My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm\ Generic_250nm_Tech

\Generic_250nm.lib

After giving the path of Generic_250nm.lib, add TT as shown below.

My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm\ Generic_250nm_Tech

\Generic_250nm.lib TT

TT is the corner model used . There are different types of Corner models in .lib file

* TT : Typical model for NMOS & PMOS

* SS : Slow NMOS Slow PMOS model

* FF : Fast NMOS Fast PMOS model

* SF : Slow NMOS Fast PMOS model

Set Transient Analysis as shown below .

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Run Simulation.

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To view waveforms , place PrintVoltage from Spice Commands library.

Now , Run Simulation.

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Waveforms can be viewed on W-Edit tool once Simulation is Run again.

Waveforms can be expanded by clicking Chart Expand Traces on W-Edit window.

To extract the spice netlist from schematic, go to S-Edit and click the T-Spice option.

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The following spice netlist is extracted from the schematic which contains the information of the

circuit connections across its nodes, analysis setup , voltages applied and type of library used for

simulation.

Save the netlist as inverter_sch.sp

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\phanendra\My Documents\Tanner EDA\Tanner Tools

v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level *****

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MNMOS_2_5v_1 Out In Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $

$x=4793 $y=3700 $w=414 $h=600

MPMOS_2_5v_1 Out In Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $

$x=4793 $y=4700 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------

VVoltageSource_2 Vdd Gnd DC 5 $ $x=1800 $y=3800 $w=400 $h=600

VVoltageSource_1 In Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=3400 $y=3600 $w=400 $h=600

.PRINT TRAN V(In) $ $x=2850 $y=4350 $w=1500 $h=300 $r=180

.PRINT TRAN V(Out) $ $x=6250 $y=4050 $w=1500 $h=300

********* Simulation Settings - Analysis Section *********

.tran 50n 1u start=0

********* Simulation Settings - Additional SPICE Commands *********

.end

L-EDIT

CMOS Inverter Structure: -

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The following is the path for opening L-Edit tool :

Start All Programs Tanner EDA Tanner V 15 L-Edit V15.0 32 Bit

To do Layout , run L-Edit tool. Follow window pops up.

Go to File New

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Click Browse My Documents\Tanner EDA\Tanner Tools v15.0 \Process \Generic_250nm

\Generic_250nm_Tech and add Generic_250nm_TechSetup.tdb file and click ok.

Go to Cell New

Name the Cell

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Grids spacing can be minimized or maximized using – or + sign

To change the technology Goto setup-> Design

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Select Lambda or microns accordingly and click ok

Before designing layout we need to remember following equations

N Diffusion = N Implant and Active – (1)

P Diffusion = P Implant and Active - (2)

From layer palette, we can select layer then for drawing layer we need to switch at Drawing boxes

as follows

Now we can start layout designing. We are Taking Example of CMOS Layout design

Background of L-Edit is P-Substrate by default

We need to design PMOS, First draw active

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Now draw P Implant over Active with keeping in mind Lambda based design rules

Now draw poly over it accordingly

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Now draw Contact for Active region

Now draw metal1 around Contact

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We have designed source, gate and drain.

Now we have to design bulk by creating a N+ diffusion

Now we need to put this in N-Well

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We can perform DRC (Design Rule Check) at every stage

If we are violating any Design rule then it will be shown in Error verification navigator

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By clicking on the error, the tool points to the error that occur on layout.

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By increasing the poly density area in the layout we can minimize that error. And again run DRC

check.

We need to design Gate contact.

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To define port, go to (A)

We can now find the port name added to gate .

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Similarly we do NMOS layout.

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After connecting NMOS and PMOS , CMOS layout looks like as follows.

Now we can extract netlist by doing some settings

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Click options in Setup Extract above, and uncheck all Hiper Verify Options.

Run Extraction, An spice file will open as follows

This netlist is saved as inverter_layout.spc

VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 vin Gnd PULSE(0 5 0 5n 5n 95n 200n)

.PRINT TRAN V(vin)

.PRINT TRAN V(vout)

.tran 1ns 500ns

Final netlist

.lib "C:\Documents and Settings\phanendra\My Documents\Tanner EDA\Tanner Tools

v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT

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M1 Vout Vin GND GND_ NMOS25 l=1.95e-006 w=2.55e-006 ad=5.1e-012 as=4.08e-012 pd=9.1e-006

ps=8.3e-006 $(24.65 -272199 26.6 -272197)

M2 Vout Vin VDD VDD PMOS25 l=1.95e-006 w=2.55e-006 ad=5.2275e-012 as=3.9525e-012 pd=9.2e-

006 ps=8.2e-006 $(24.65 -272194 26.6 -272192)

VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 Vin Gnd PULSE(0 5 0 5n 5n 95n 200n)

.PRINT TRAN V(Vin)

.PRINT TRAN V(Vout)

.tran 1ns 500ns

.end

After saving spice file, we can simulate it, W-Edit will invoked and we can check the response:

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LVS

(Layout Vs Schematic)

We got two output files (one from S-Edit and second from L-Edit), Now we can compare results

by using LVS

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Double click on LVS, and file -> new &

Select file type-> LVS setup, then ok

We need to browse spice netlist files for layout netlist and Schematic netlist

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After including these files, we need to run verification as follows &

Results can be checked from Verification Window.

Both netlists are equal.

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Experiment No. 5:

5. Schematic Entry and SPICE simulation of MOS differential amplifier. Determination of gain, bandwidth, output impedance and CMRR.

Theory :

A differential amplifier is a type of electronic amplifier that multiplies the difference between

two inputs by some constant factor (the differential gain).

Many electronic devices use differential amplifiers internally. The output of an ideal differential

amplifier is given by:

Where and are the input voltages and Ad is the differential gain.

In practice, however, the gain is not quite equal for the two inputs. This means, for instance, that

if and are equal, the output will not be zero, as it would be in the ideal case. A more

realistic expression for the output of a differential amplifier thus includes a second term.

Ac is called the common-mode gain of the amplifier.

As differential amplifiers are often used when it is desired to null out noise or bias-voltages that

appear at both inputs, a low common-mode gain is usually considered good.

The common-mode rejection ratio, usually defined as the ratio between differential-mode gain

and common-mode gain, indicates the ability of the amplifier to accurately cancel voltages that

are common to both inputs. Common-mode rejection ratio (CMRR):

In a perfectly symmetrical differential amplifier, Ac is zero and the CMRR is infinite. Note that a

differential amplifier is a more general form of amplifier than one with a single input; by

grounding one input of a differential amplifier, a single-ended amplifier results. An operational

amplifier, or op-amp, is a differential amplifier with very high differential-mode gain, very high

input impedances, and a low output impedance. Some kinds of differential amplifier usually

include several simpler differential amplifiers. For example, an instrumentation amplifier, a fully

differential amplifier, an instrument amplifier, or an isolation amplifier are often built from

several op-amps.

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Differential amplifiers are found in many systems that utilise negative feedback, where one input

is used for the input signal, the other for the feedback signal. A common application is for the

control ofmotors or servos, as well as for signal amplification applications. In discrete electronics,

a common arrangement for implementing a differential amplifier is the long-tailed pair, which is

also usually found as the differential element in most op-amp integrated circuits. A differential

amplifier is used as the input stage emitter coupled logic gates.

Design :

In S-Edit, draw the circuit as shown below.

Convert the schematic to symbol

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Using the lines for drawing, create a symbol for op-amp as below.

Make the connections accordingly.

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Again create a symbol for the above circuit and make the connections accordingly.

Vpwr and Vpwr/2 are the instance name of the voltage souces.

Now place the spice commands for finding out the gain, bandwidth.

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Simulation setup

Then click run simulation

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Gain , Frequency and Bandwidth can be viewed from simulation window above.

And waveforms can be viewed from w-Edit

6th Experiment is already shown in the Tanner working Flow.

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7th Experiment is 10 Bit Number Controlled Oscillator.

The following schematic shows 10 bit VCO. By changing the values of D0 – D9 the input pulse

applied varies accordingly.

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