VLSI Manual

VLSI Lab Manual Department of Electronics & Communication Engineering

BALLARI INSTITUTE OF TECHNOLOGY & MANAGEMENT, BELLARY.

Program- 1

Aim: To write the verilog code for an Inverter and the Test bench for Verification, Observe the waveform

and synthesize the code

Truth Table Logic Diagram

Verilog code for inverter

module NOTgate1(A, Y);

input A;

output Y;

reg Y;

always @ (A)

begin

Y<= ~A;

end

endmodule

Test bench for verification

module Inv_tb_v; // Inputs reg A; // Outputs wire F; // Instantiate the Unit Under Test (UUT) NOTgate1 uut ( .A(A), .Y(Y) ); initial begin

// Initialize Inputs A = 0;



// Wait 100 ns for global reset to finish

#10; // Add stimulus here A = 1; end endmodule Waveforms



Program- 2

Aim: To write the verilog code for an Buffer and the Test bench for Verif ication, Observe the waveform and

synthesize the code

Logic Diagram Truth Table

Verilog code for Buffer

module BUFFER(A, B);

input A;

output B;

reg B;

always @ (A)

begin

B <= A;

end

endmodule


module BUFFER_tb_v; // Inputs reg A; // Outputs wire B; // Instantiate the Unit Under Test (UUT) BUFFER uut ( .A(A), .B(B) );



initial begin

// Initialize Inputs A = 0; // Wait 100 ns for global reset to finish #10; // Add stimulus here A = 1; end endmodule Waveforms



Program- 3

Aim: To write the verilog code for an Transmission Gate and the Test bench for Verification, Observe the

waveform and synthesize the code


Verilog code for Transmission gate

module TG(data_enable_low, in, data_bus, out1, out2);

input data_enable_low, in;

output data_bus, out1, out2;

//reg data_enable_low [4:0], in[4:0];

//wire data_bus, out1, out2;

bufif0 U1(data_bus,in, data_enable_low);

buf U2(out1,in);

not U3(out2,in);

endmodule


module TG_tb_v;

// Inputs

reg data_enable_low;

reg in;

// Outputs

data_enable_low, in Out1 Out2 Data_bus

0 0 0 1 0

1 0 1 0 1

0 1 0 1 2

1 1 1 0 2

0 1 0 1 2

1 1 1 0 2



wire data_bus;

wire out1;

wire out2;

// Instantiate the Unit Under Test (UUT)

TG uut (

.data_enable_low(data_enable_low),

.in(in),

.data_bus(data_bus),

.out1(out1),

.out2(out2)

);

initial begin

// Initialize Inputs

data_enable_low = 0;

in = 0;


#10;

// Add stimulus here

end

initial begin

$monitor(

"@%g in=%b data_enable_low=%b out1=%b out2= b data_bus=%b",

$time, in, data_enable_low, out1, out2, data_bus);

data_enable_low = 0;

in = 0;

#4 data_enable_low = 1;

#8 $finish;

end

always #2 in = ~in;

endmodule

Waveforms



Program- 4 Aim: To write the verilog code for an Basic/Universal Gate and the Test bench for Verification, Observe the


A) AND Gate


Verilog code for AND gate

module AND1 (A, B, Y); input A; input B; output Y; reg Y; always @ (A or B) begin Y <= A & B; end endmodule


module AND1_tb_v; // Inputs reg A; reg B; // Outputs wire Y; // Instantiate the Unit Under Test (UUT) AND1 uut ( .A(A), .B(B), . Y (Y) );



initial begin

// Initialize Inputs A = 0; B = 1; // Wait 100 ns for global reset to finish #10; // Add stimulus here A = 1; B = 1; end endmodule Waveforms



B) OR Gate

Truth table Logic diagram

Verilog code for OR gate

module Orgate(a, b, y);

input a;

input b;

output y;

reg y;

always @ (a or b)

begin

y <= (a | b);

end

endmodule


module Orgate_tb_v; // Inputs reg a; reg b; // Outputs wire y; // Instantiate the Unit Under Test (UUT) Orgate uut ( .a(a), .b(b), .y(y) ); initial begin // Initialize Inputs a = 0; b = 0;



// Wait 100 ns for global reset to finish #10;

// Add stimulus here a = 1; b = 1; end endmodule Waveforms



C) NAND Gate


Y= A NAND B =~ (A. B)

Verilog code for NAND gate

module NAND2gate(A, B, Y);

input A;

input B;

output Y;

reg Y;

always @ (A or B)

begin

Y <= ~(A & B);

end

endmodule


module Testbench; reg A_t, B_t; wire Y _t; NAND2gate NAND2gate_1(A_t, B_t, Y t); initial begin //case 0 A_t <= 0; B_t <= 0; #1 $display("Y _t = %b", Y _t); //case 1 A_t <= 0; B_t <= 1; #1 $display("Y _t = %b", Y _t); //case 2 A_t <= 1; B_t <= 0; #1 $display("Y _t = %b", Y _t);



//case 3 A_t <= 1; B_t <= 1; #1 $display("Y _t = %b", Y_t); end endmodule Waveforms



D) NOR Gate


Y= A NOR B

=~(A+ B)

Verilog code for NOR gate

module NOR2gate(A, B, Y); input A; input B; output Y; reg Y; always @ (A or B) begin Y <= ~(A | B); end endmodule Test bench for verification

module NOR2gate_tb_v;

// Inputs

reg A;

reg B;

// Outputs

wire Y;


NOR2gate uut (

.A(A),

.B(B),

.Y(Y)

);



initial begin


A = 0;

B = 0;


#10;


A = 1;

B = 1;

end

endmodule Waveforms



Program- 5

Aim: To write the verilog code for an Flip Flops ( RS,D,JK,MS.T) and the Test bench for Verification,

Observe the waveform and synthesize the code

Flip-flop: Flip-flop is a sequential logic circuit, which is ‘One ‘-bit memory element. OR It is a basic memory

element in digital systems (same as the bi-stable multivibrator) It has two stable state logic ‘1’ and logic ‘0’.

a) S-R Flip-flop (Set-Reset)

In a memory device set and Reset is often required for synchronization of the device in such case S-R

Flip-flop is need & this is refereed as clocked set-reset.

S-R Flip-flop Logic diagram Set-Reset Truth table

Illegal - 1 1

Set 1 0 1

Reset 0 1 0

No

Change Q 0 0

Action Q+ R S



Verilog code for SR - Flip Flop Test bench for verification

Waveforms



b) D- FF (Delay Flip-flop)

In D-Flip-flop the transfer of data from the input to the Output is delayed and hence the name delay

D-Flip-flop. The D-Type Flip-flop is either used as a delay device or as a latch to store ‘1’ bit of

binary information.

D input transferred to Q output when clock asserted

Logic Diagram Truth table

Verilog code for D - Flip Flop

module d_ff( d, clk, q, q_bar);

input d, clk;

output q, q_bar;

reg q;

reg q_bar;

always @ (posedge clk)

begin

q <= d;

q_bar <= !d;

end

endmodule


module DFF_tb_v;

// Inputs

reg d;

reg clk;

// Outputs

wire q;

wire q_bar;


d_ff uut (

.d(d),



.clk(clk),

.q(q),

.q_bar(q_bar)

);

initial begin


d = 0;

clk = 0;


#10;


d = 1;

clk = 1;

end

endmodule

Waveforms



c) J.K Flip-flop:

module jkff(clk, rst, j, k, q, qn);

input clk;

input rst;

input j;

input k;

output q;

output qn;

reg ff;

assign q=ff;

assign qn=~ff;

always @ (posedge clk)

begin

if (rst==0)

ff=1'b0;

else

case({j,k})

2'b01:ff=1'b0;

2'b10:ff=1'b1;

2'b01:ff=~ff;

default:ff=ff;

endcase

end

endmodule



d) J.K Master Slave Flip-flop:

The race conditions in S-R Flip-flop can be eliminated by converting it in to J.K, the data inputs

J and K are ANDed with ~Q and Q to obtain S & R inputs.

Here SR, T, or D depending on inputs.

S=J. ~Q

R=K.Q

JK-MS-F/F Truth table JK-MS-F/F Truth table

Verilog code for JK Masterslave- Flip Flop

module JKff(q,qb, j,k, clk); input j,k,clk; inout q,qb; //reg q,qb; wire a, b, c, d; wire y, yb; wire cbar; wire q1,qb1; not (cbar, clk); nand (a,j,qb,clk); nand (b, k, q, clk); nand ( y, a, yb); nand ( yb, b, y); nand (c, y, cbar); nand (d, yb, cbar); //q==q1; qb == qb1; nand (q, c, qb); nand (qb, d, q); endmodule

Toggle Q 1 1

Set 1 0 1

Reset 0 1 0

No

Change

Q 0 0

Action Q+ K J

Toggle Q 1 1

Set 1 0 1

Reset 0 1 0

No

Change

Q 0 0

Action Q+ K J

Toggle Q 1 1

Set 1 0 1

Reset 0 1 0

No

Change

Q 0 0

Action Q+ K J

Toggle Q 1 1

Set 1 0 1

Reset 0 1 0

No

Change

Q 0 0

Action Q+ K J




module JKMS_tb_v; // Inputs reg j; reg k; reg clk; // Bidirs wire q; wire qb; // Instantiate the Unit Under Test (UUT) JKff uut ( .q(q), .qb(qb), .j(j), .k(k), .clk(clk) ); initial begin // Initialize Inputs j = 0; k = 0; clk = 1; // Wait 100 ns for global reset to finish #10; // Add stimulus here j = 1; k = 1; clk = 1; j = 0; k = 1; clk = 1; end Waveforms



e) T-Flip-flop (Toggle Flip-flop): On every change in clock pulse the output ‘Q’ changes its state

(Toggle). A Flip-flop with one data input which changes state for every clock pulse.

T-F/F Logic Diagram T-F/F Truth table

Verilog code for T - Flip Flop module tff_async_reset (data, clk, reset ,q); //-----------Input Ports--------------- input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- reg q; //-------------Code Starts Here--------- always @ ( posedge clk or negedge reset) if (~reset) begin q <= 1'b0; end else if (data) begin q <= !q; end endmodule //End Of Module tff_async_reset Test bench for verification

module tff_tb_v; // Inputs reg data; reg clk; reg reset; // Outputs wire q; // Instantiate the Unit Under Test (UUT) tff_async_reset uut ( .data(data), .clk(clk), .reset(reset), .q(q)

initial begin // Initialize Inputs data = 0; clk = 0; reset = 0;

Toggle Q 1

No Change Q 0

Action Q+

T




// Add stimulus here end initial begin $monitor ("data =%b, clk =%b, q =%b, reset =%b", data, clk,q, reset); reset = 0; clk =1; data = 1; #5 reset= ~reset; #10 $finish; end always begin #5 clk= ~clk; end tff_async_reset to( .data(data), .clk(clk), .q(q), .reset(reset)); endmodule Waveforms



Program- 6

Aim: To write the verilog code for Serial & Parallel Adder and the Test bench for Verification, Observe the


a) Serial Adder

Logic Diagram

Truth Table



Verilog code for Serial Adder

module sradd(a,b,start,clock,ready,result);

input a,b,start,clock;

output ready;

output [7:0] result;

reg [7:0] result;

reg sum,carry,ready;

integer count;

initial count = 8;

always @(negedge clock)

begin

if (start)

begin

count =0;carry = 0; result = 0;

end

else

begin

if (count <8)

begin

count = count + 1;

sum = a ^ b ^ carry ;

carry = (a&b)|(a & carry)|(b& carry);

result ={sum,result[7:1]};

end

end

if(count == 8)

ready = 1;

else

ready = 0;

end

endmodule



Test bench for verification module sradd_tb_v; // Inputs

reg a;

reg b;

reg start;

reg clock;

// Outputs

wire ready;

wire [7:0] result;


sradd uut (

.a(a),

.b(b),

.start(start),

.clock(clock),

.ready(ready),

.result(result)

);

initial begin


a = 0;

b = 0;

start = 0;

clock = 0;


#100;


end

initial

begin

clock = 1'b1;

a = 1'b0;

b = 1'b1;

#05 start = 1'b1;

#11 start = 1'b0;

#50 $finish;

end

always #2 clock = ~ clock;

always #3.1 a = ~ a;

always #5.1 b = ~ b;

endmodule



Waveforms



b) Parallel Adder:

Logic Diagram

Truth Table



Verilog code for Parallel Adder

module addsub (A, B, C0, S);

input [3:0] A;

input [3:0] B;

input C0;

output [4:0] S;

reg [4:0] S;

always @(A or B or C0)

begin

if (C0)

S = A + B;

else

S = A - B;

end

endmodule


module padder_tb_v;

// Inputs

reg [3:0] A;

reg [3:0] B;

reg C0;

// Outputs

wire [4:0] S;


addsub uut (

.A(A),

.B(B),

.C0(C0),

.S(S)

);

initial begin


A = 0;

B = 0;

C0 = 0;


#10;


end



initial

begin

$monitor($time,

"A=%b,B=%b, c_in=%b, sum = %b\n",A,B,C0,S);

end

// These statements conduct the actual circuit test

initial

begin

A = 4'd0; B = 4'd0; C0 = 1'b0;

#50 A = 4'd3; B = 4'd4;

#50 A = 4'b0001; B = 4'b0010;

#50 A = 4'hc; B=4'h2;

end

endmodule

Waveforms



Program- 7

Aim: To write the verilog code for. 4-bit counter [Synchronous and Asynchronous counter]and the Test

bench for Verification, Observe the waveform and synthesize the code

A) Synchronous counter

Logic Diagram



Verilog code for Synchronous counter

module countr (

clock ,

reset ,

enable ,

counter_out

);

input clock ;

input reset ;

input enable ;

output [3:0] counter_out ;

//-------------Input ports Data Type-------------------

// By rule all the input ports should be wires

wire clock ;

wire reset ;

wire enable ;

//-------------Output Ports Data Type------------------

// Output port can be a storage element (reg) or a wire

reg [3:0] counter_out ;

always @ (posedge clock)

begin : COUNTER

if (reset == 1'b1) begin

counter_out <= #1 4'b0000;

end

else if (enable == 1'b1) begin

counter_out <= #1 counter_out + 1;

end

end

endmodule




module counter_tb_v;

// Inputs

reg clock;

reg reset;

reg enable;

// Outputs

wire [3:0] counter_out;


counter uut (

.clock(clock),

.reset(reset),

.enable(enable),

.counter_out(counter_out)

);

initial begin


clock = 0; reset = 0; enable = 0;



end

initial begin

$display ("time\t clk reset enable counter");

$monitor ("%g\t %b %b %b %b",

$time, clock, reset, enable, counter_out);

clock = 1; // initial value of clock

reset = 0; // initial value of reset

enable = 0; // initial value of enable

#5 reset = 1; // Assert the reset

#10 reset = 0; // De-assert the reset

#15 enable = 1; // Assert enable

#100 enable = 1; // De-assert enable

#5 $finish; // Terminate simulation

end

// Clock generator

always begin

#5 clock = ~clock; // Toggle clock every 5 ticks

end

endmodule



Waveforms



B) Asynchronous counter

Logic Diagram



Verilog code for Asynchronous counter

module acounter( clk, count );

input clk;

output[3:0] count;

reg[3:0] count;

wire clk;

initial

count = 4'b0;

always @( negedge clk )

count[0] <= ~count[0];

always @( negedge count[0] )






endmodule


module acounter_tb_v;

// Inputs

reg clk;

// Outputs

wire [3:0] count;


acounter uut (

.clk(clk),

.count(count)

);

initial begin


clk = 0;


#10;




end

initial

begin

clk = 0;

#100 $finish;

end

always

begin

#2 clk = ~clk;

end

always @( posedge clk)

$display("Count = %b", count );

endmodule

Waveforms



Program- 1

Aim: To Draw the schematic & Layout of Inverter and verify the a) DC Analysis ,b) Transient Analysis, and to draw the Layout of Inverter & verify the DRC & ERC.

Schematic design of Inverter.



Layout of Inverter



Waveforms:



Program- 2

Aim: To Draw the schematic and verify the a) DC Analysis ,b) AC Analysis c)Transient Analysis,

and to draw the Layout & verify DRC & ERC . Extract RC and back annotate the same and verify the following Design.

I. A Single Stage differential amplifier II. Common source and Common Drain amplifier

.

I. Schematic design of A Single Stage differential amplifier



Layout design of A Single Stage differential amplifier



Waveforms:



II. Schematic design of Common Drain amplifier



Layout design of Common Drain amplifier



Waveforms:



Schematic design of Common source amplifier



Layout design of Common source amplifier



Waveforms:



Program- 3

Aim: To Draw the schematic of OP-AMP using given differential amplifier Common source and Common Drain amplifier in library and verify the a) DC Analysis ,b) AC Analysis c)Transient Analysis, and to draw the Layout & verify DRC & ERC . Extract RC and back annotate the same and verify the Design.

OP-AMP Symbol

Schematic design of OP-AMP



Layout design of OP-AMP



Waveforms:



Program- 4

Aim: To Draw the schematic of 4 bit R-2R based DAC for the given specification and completing the

design flow mentioned using given op-amp in the library and verify the a) DC Analysis ,b) AC Analysis

c)Transient Analysis, and to draw the Layout & verify DRC & ERC . Extract RC and back annotate the

same and verify the Design.

Circuit Diagram of 4 bit R-2R based DAC:

Schematic design of 4 Bit R-2R based DAC



Layout design of 4 Bit R-2R based DAC



Waveforms :



Program- 5

Aim: To Draw5 the SAR based ADC mentioned in the figure below draw the mixed signal schematic and

verify the functionality by completing ASIC Design FLOW

Schematic design of SAR based ADC



Layout design of SAR based ADC



Waveforms:

VLSI Manual

Documents

Transcript of VLSI Manual