VLSI Cadance Manual

1.INVERTER

AIM. Write Verilog Code for inverter and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. CMOS inverter, a logic gate which converts a high input to low and low to high. When the input is high, the n-MOSFET on the bottom switches on, pulling the output to ground. The p-MOSFET on top switches off. When the input is low, the gate-source voltage on the n-MOSFET is below its threshold, so it switches off, and the p-MOSFET switches on to pull the output high. CIRCUIT DIAGRAM.

TRUTH TABLE

Input Output 0 1 1 0

VERILOG CODE.

timescale 1ns/1ns module not_gate(a,b); input a; output b; assign b=~a; endmodule TEST BENCH. module not_gate_test; reg a; wire b; not_gate i1(a,b); initial begin a=1'b0; #10 a=1'b1; #10 a=1'b0; #10 a=1'b1; end endmodule

TIMING DIAGRAM.

SYNTHESIS OUTPUT.

RESULT. The Inverter code and test bench is verified. Synthesis is achieved and waveforms are observed.

2.BUFFER.

AIM. Write Verilog Code for buffer and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. A buffer is a CMOS circuit used to temporarily hold data while it is being used to move from one place to another. Typically, the data is stored in a buffer as it is retrieved from an input device or just before it is sent to an output device. It is used mainly when there is a delay needed in sending a data. CIRCUIT DIAGRAM.

TRUTH TABLE. Input Output 0 0 1 1 VERILOG CODE. module buffer (a, b, y); input a, b; output y; reg y; always@ (a or b) begin if(b) y=a; else y=1'bZ; end endmodule TEST BENCH. module buffer_test(); reg a,b; wire y; buffer b1(a,b,y); initial begin #20 a=1'b0; #40 a=1'b1;

#20 a=1'b0; end initial begin #10 b=1'b0; #10 b=1'b1; #20 b=1'b1; #20 b=1'b0; #10 b=1'b0; #10 b=1'b1; end endmodule TIMING DIAGRAM.

SYNTHESIS OUTPUT.

RESULT. The Buffer code and test bench is verified. Synthesis is achieved and waveforms are observed.

3. TRANSMISSION GATE AIM. Write Verilog Code for Transmission gate and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. A transmission gate, or analog switch, is defined as an electronic element that will selectively block or pass a signal level from the input to the output. This solid-state switch is comprised of a pMOS transistor and nMOS transistor. The control gates are biased in a complementary manner so that both transistors are either on or off. When the voltage on node A is a Logic 1, the complementary Logic 0 is applied to node active-low A, allowing both transistors to conduct and pass the signal at IN to OUT. When the voltage on node active-low A is a Logic 0, the complementary Logic 1 is applied to node A, turning both transistors off and forcing a high-impedance condition on both the IN and OUT nodes. This high-impedance condition represents the third "state" (high, low, or high-Z). CIRCUIT DIAGRAM.

TRUTH TABLE. A IN OUT 0 0 Z 0 1 Z 1 0 0 1 1 1 VERILOG CODE. module trangate(out, in, cntrl1, cntrl2); output out; input in; input cntrl1,cntrl2; pmos (out,in,cntrl1); nmos (out,in,cntrl2); endmodule TEST BENCH. module trangate_test; wire out ; reg in ; reg cntrl1,cntrl2; trangate t1(out, in, cntrl1, cntrl2 ) ; task display ; begin $display ("time=%0d", $time , " ns" , " Input=" , in , " Output=", out , " Control1=",cntrl1, " Control2=",cntrl2) ; end

endtask initial begin in = 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; #10 ; display ; in = 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; #10 ; display ; in = 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; #10 ; display ; in = 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; #10 ; display ; end endmodule TIMING DIAGRAM.

RESULT. The Buffer code and test bench is verified. Synthesis is achieved and waveforms are observed.

4.BASIC/UNIVERSAL GATES

4.1 AND GATE AIM. Write Verilog Code for AND gate and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. The AND gate is a basic digital logic gate A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW output results. In another sense, the function of AND effectively finds the minimum between two binary digits. CIRCUIT DIAGRAM.

TRUTH TABLE. A B OUTPUT 0 0 0 0 1 0 1 0 0 1 1 1 VERILOG CODE. module and_gate(a, b, c); input a,b; output c; reg c; always@ (a or b) begin c<=a&b; end endmodule TEST BENCH. module and_gate_test(); reg a,b; wire c; and_gate a1(a,b,c); initial begin #20 a=1'b0; #20 a=1'b0;

#20 a=1'b1; #20 a=1'b1; end initial begin #20 b=1'b0; #20 b=1'b1; #20 b=1'b0; #20 b=1'b1; end endmodule TIMING WAVEFORM.

SYNTHESIS OUTPUT.

RESULT. The AND gate code and test bench is verified. Synthesis is achieved and waveforms are observed.

4.2 OR GATE. AIM. Write Verilogverification, observe the waveform and technological library with given Constraints. THEORY. The OR gateresults if one or both the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results. In another sense, the function of OR effectively finds the digits. CIRCUIT DIAGRAM.

Verilog Code for OR gate and Test Bench for , observe the waveform and synthesize

technological library with given Constraints.

OR gate is a digital logic gate A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results. In another sense, the function of OR effectively finds the maximum between two binary

CIRCUIT DIAGRAM.

Test Bench for synthesize the code with

A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results. In another sense, the

between two binary

TRUTH TABLE. A B OUTPUT 0 0 0 0 1 1 1 0 1 1 1 1 VERILOG CODE. module or_gate(a,b,c); input a,b; output c; reg c; always@ (a or b) begin c<=a|b; end endmodule TEST BENCH. module or_gate_test(); reg a, b; wire c; or_gate o1(a, b, c); initial begin #20 a=1'b0; #20 a=1'b0; #20 a=1'b1;

#20 a=1'b1; end initial begin #20 b=1'b0; #20 b=1'b1; #20 b=1'b0; #20 b=1'b1; end endmodule TIMING WAVEFORM.

SYNTHESIS OUTPUT.

RESULT. The OR gate code and test bench is verified. Synthesis is achieved and waveforms are observed.

4.3 NAND GATE. AIM. Write Verilogverification, observe the waveform and technological library with given Constraints. THEORY. The Negated ANDopposite of the digital corresponds to the opposite of AND gate.only if both the inputs to the gate are HIGH. If one or both inputs are LOW, a HIGH output results. CIRCUIT DIAGRAM.

4.3 NAND GATE.

Verilog Code for NAND gate and , observe the waveform and synthesize


Negated AND, NO AND or NANDopposite of the digital AND gate, and behaves in a manner that corresponds to the opposite of AND gate. A LOW output results

the inputs to the gate are HIGH. If one or both inputs are LOW, a HIGH output results.

CIRCUIT DIAGRAM.

Code for NAND gate and Test Bench for synthesize the code with

NAND gate is the , and behaves in a manner that

A LOW output results the inputs to the gate are HIGH. If one or both inputs

TRUTH TABLE. A B OUTPUT 0 0 1 0 1 1 1 0 1 1 1 0 VERILOG CODE. module nand_gate(a,b, c); input a,b; output c; reg c; always@ (a or b) begin c<=!(a & b); end endmodule TEST BENCH.

module nand_gate_test(); reg a,b; wire c; nand_gate a1(a,b,c); initial begin #20 a=1'b0; #20 a=1'b0; #20 a=1'b1;

SYNTHESIS WAVEFORM.

RESULT. The NAND gate code and test bench is verified. Synthesis is achieved and waveforms are observed.

4.4 NOR GATE. AIM. Write Verilog Code for NOR gate and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. The NOR gate is a digital logic gate A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. CIRCUIT DIAGRAM.

TRUTH TABLE. A B OUTPUT 0 0 1 0 1 0 1 0 0 1 1 0 VERILOG CODE. module nor_gate(a,b, c); input a,b; output c; reg c; always@(a or b) begin c<=!(a |b); end endmodule TEST BENCH. module nor_gate_test(); reg a,b; wire c; nor_gate a1(a,b,c); initial begin #20 a=1'b0; #20 a=1'b0; #20 a=1'b1;

SYNTHESIS WAVEFORM.

RESULT. The NOR gate code and test bench is verified. Synthesis is achieved and waveforms are observed.

4.5 XOR GATE. AIM. Write Verilogverification, observe the waveform and technological library with given Constraints. THEORY. The XOR gateis a digital logic gatetrue output (1) results if one, and only one, of the inputs to the gate is true (1). If both inputs are false (0) or boutput (0) results. It represents the inequality functionHIGH (1) if the inputs are not alike otherwise CIRCUIT DIAGRAM.

4.5 XOR GATE.

Verilog Code for XOR gate and Test Bench for , observe the waveform and synthesize


XOR gate (sometimes EOR gate, or logic gate that implements an exclusive or

true output (1) results if one, and only one, of the inputs to the gate is true (1). If both inputs are false (0) or both are true (1), a false output (0) results. It represents the inequality function

inputs are not alike otherwise output is LOW (0).

CIRCUIT DIAGRAM.

Test Bench for synthesize the code with

, or EXOR gate) exclusive or; that is, a

true output (1) results if one, and only one, of the inputs to the gate oth are true (1), a false

output (0) results. It represents the inequality function,the output is output is LOW (0).

TRUTH TABLE. A B Output 0 0 0 0 1 1 1 0 1 1 1 0 VERILOG CODE. module xor_gate(a, b, c); input a, b; output c; reg c; always@ (a or b) begin c<=a^b; end endmodule TEST BENCH. module xor_gate_test(); reg a,b; wire c; xor_gate a1(a,b,c); initial begin #20 a=1'b0; #20 a=1'b0;

#20 a=1'b1; #20 a=1'b1; end initial begin #20 b=1'b0; #20 b=1'b1; #20 b=1'b0; #20 b=1'b1; end endmodule TIMING WAVEFORM.

SYNTHESIS WAVEFORM.

RESULT. The XOR gate code and test bench is verified. Synthesis is achieved and waveforms are observed.

4.6 XNOR GATE. AIM. Write Verilog Code for XNOR gate and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. The XNOR gate (sometimes spelled "exnor" or "enor") is a digital logic gate whose function is the inverse of the exclusive OR (XOR) gate. A HIGH output (1) results if both of the inputs to the gate are the same. If one but not both inputs are HIGH (1), a LOW output (0) results. CIRCUIT DIAGRAM.

TRUTH TABLE. A B Output 0 0 1 0 1 0 1 0 0 1 1 1

VERILOG CODE. module xnor_gate(a, b, c); input a, b; output c; reg c; always@(a or b) begin c<=!(a^b); end endmodule TEST BENCH. module xnor_gate_test(); reg a, b; wire c; xnor_gate a1(a,b,c); initial begin #20 a=1'b0; #20 a=1'b0; #20 a=1'b1; #20 a=1'b1; end initial begin #20 b=1'b0; #20 b=1'b1; #20 b=1'b0; #20 b=1'b1; end

endmodule TIMING WAVEFORM.

SYNTHESIS WAVEFORM.

RESULT. The XNOR gate code and test bench is verified. Synthesis is achieved and waveforms are observed.

5.FLIP-FLOPS

5.1 RS Flip flop AIM. Write Verilog Code for RS flip flop and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate state. CIRCUIT DIAGRAM.

TRUTH TABLE

CLOCK

PULSE

INPUT PRESENT

STATE (Q)

NEXT

STATE(Q+1) S R

1 0 0 0 0

2 0 0 1 1

3 0 1 0 0

4 0 1 1 0

5 1 0 0 1

6 1 0 1 1

7 1 1 0 X

8 1 1 1 X

VERILOG CODE.

module rs_ff(r,s,clk, q,qb); input r,s,clk; output q,qb; reg q,qb; initial begin q="0";

qb="1"; end

always@(posedge clk or negedge clk) begin if(r==1'b1 && s==1'b0) begin

q<=0; qb<=1;

end if(r==1'b0 && s==1'b1) begin

q<=1; qb<=0;

end if(r==1'b1 && s==1'b1) begin

q<=1'b0; qb<=1'b0;

end end

endmodule

TEST BENCH. module rsff_test(); reg r,s,clk; wire q,qb; rs_ff d1(r,s,clk,q,qb); initial clk=1'b0; always #5 clk=~clk; initial begin #20 r=1'b1; #20 r=1'b0; #10 r=1'b1; #10 r=1'b0; #10 r=1'b1; #10 r=1'b0; end initial begin #20 s=1'b0; #20 s=1'b1; #20 s=1'b0; #20 s=1'b1; end endmodule

TIMING DIAGRAM.

SYNTHESIS OUTPUT.

RESULT. The RS flipflop code and test bench is verified. Synthesis is achieved and waveforms are observed.

5.2 D Flip flop

AIM. Write Verilog Code for D flip flop and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints.

THEORY. To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other.

CIRCUIT DIAGRAM.

TRUTH TABLE

CLOCK

PULSE

INPUT

D

PRESENT

STATE (Q)

NEXT

STATE(Q+1)

1 0 0 0

2 0 1 0

3 1 0 1

4 1 1 1

VERILOG CODE.

module d11(d,clk,q,qb); input d,clk; output q,qb; reg q,qb; initial begin q=1'b0; qb=1'b1; end always @ (posedge clk,q) begin q=d; qb=~q; end endmodule

TEST BENCH. module dff_test(); reg d,clk; wire q,qb; dff d1(d,clk,q,qb); initial clk=1'b0; always #5 clk=~clk; initial begin #40 d=1'b0; #40 d=1'b1; end endmodule

TIMING DIAGRAM.

SYNTHESIS OUTPUT.

RESULT. The D flipflop code and test bench is verified. Synthesis is achieved and waveforms are observed.

5.3 JK Flip flop AIM. Write Verilog Code for JK flip flop and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints.

THEORY. The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided.

CIRCUIT DIAGRAM.

TRUTH TABLE.

CLOCK

PULSE

INPUT PRESENT

STATE (Q)

NEXT

STATE(Q+1) J K

1 0 0 0 0

2 0 0 1 1

3 0 1 0 0

4 0 1 1 0

5 1 0 0 1

6 1 0 1 1

7 1 1 0 1

8 1 1 1 0

VERILOG CODE.

module jkff(j,k,clk, q,qb); input j,k,clk; output q,qb; reg q; always@(posedge clk or negedge clk) begin case({j,k}) 2'b01:q=1'b0; 2'b10:q=1'b1; 2'b11:q=~q; 2'b00:q=q;

default:q=1'bZ; endcase end assign qb=~q; endmodule

TEST BENCH.

module jkff_test(); reg j,k,clk; wire q,qb; jkff d1(j,k,clk,q,qb); initial clk=1'b0; always #5 clk=~clk; initial begin #20 j=1'b1; #20 j=1'b0; #10 j=1'b1; #10 j=1'b0; #10 j=1'b1; #10 j=1'b0; end initial begin

#20 k=1'b0; #20 k=1'b1; #20 k=1'b0; #20 k=1'b1; end endmodule

TIMING DIAGRAM.

SYNTHESIS OUTPUT.

RESULT. The JK flipflop code and test bench is verified. Synthesis is achieved and waveforms are observed.

5.4 T Flip flop AIM. Write Verilog Code for T flip flop and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop.

CIRCUIT DIAGRAM.

TRUTH TABLE.

CLOCK

PULSE

INPUT

T

PRESENT

STATE (Q)

NEXT

STATE(Q+1)

STATUS

1 0 0 0

2 0 1 0

3 1 0 1

4 1 1 0

VERILOG CODE.

module tff(t,clk, q,qb); Input t,clk; output q,qb; reg temp; initial begin temp=1'b0; end always@ (posedge clk) begin if (t) temp=~temp; else temp=temp; end

assign q=temp; assign qb=~q; endmodule TEST BENCH.

module tff_test(); reg t,clk; wire q,qb; tff d1(t,clk,q,qb); initial clk=1'b0; always #5 clk=~clk; initial begin #40 t=1'b0; #40 t=1'b1; end endmodule

TIMING DIAGRAM.

SYNTHESIS OUTPUT.

RESULT. The T flipflop code and test bench is verified. Synthesis is achieved and waveforms are observed.

5.5 MS Flip flop

AIM. Write Verilog Code for MS flip flop and Test Bench for verification, observe the waveform and technological library with giv

THEORY.

A master-slave flipflops. One circuit serves as a master and the other as a slave. The logic diagram of an SR flipflip- flop is enabled on the the slave flip-flop is disabled by the inverter. The information at the external R and S inputs is transmitted to the master flipWhen the pulse returns to 0, the master flipslave flip-flop is enabled. The slave flipstate as the master flip

CIRCUIT DIAGRAM

5.5 MS Flip flop

Write Verilog Code for MS flip flop and Test Bench for , observe the waveform and synthesize


slave flip-flop is constructed from two seperate flipflops. One circuit serves as a master and the other as a slave. The logic diagram of an SR flip-flop is shown in figure

flop is enabled on the positive edge of the clock pulse CP and flop is disabled by the inverter. The information at

the external R and S inputs is transmitted to the master flipWhen the pulse returns to 0, the master flip-flop is disabled and the

flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop.

CIRCUIT DIAGRAM.

Write Verilog Code for MS flip flop and Test Bench for synthesize the code with

flop is constructed from two seperate flip-flops. One circuit serves as a master and the other as a slave. The

figure. The master positive edge of the clock pulse CP and

flop is disabled by the inverter. The information at the external R and S inputs is transmitted to the master flip-flop.

flop is disabled and the flop then goes to the same

VERILOG CODE.

module msff(j,k,clk,q,qb); output q,qb; input clk; input j,k; wire j1,k1; jk11 m(j,k,clk,j1,k1); jk11 s(j1,k1,(~clk),q,qb); endmodule TEST BENCH. module jk11_test; reg clk; reg j,k; wire q,qb; msff j1 (j,k,clk,q,qb); initial begin clk=1'b0; j=1'b0; k=1'b0; #5 clk=1'b1; #5 clk=1'b0; j=1'b0; k=1'b1;

#5 clk=1'b1; #5 clk=1'b0; j=1'b1; k=1'b0; #5 clk=1'b1; #5 clk=1'b0; j=1'b1; k=1'b1; #5 clk=1'b1; #5 clk=1'b0; #5 clk=1'b1; #5 clk=1'b0; end endmodule TIMING DIAGRAM.

SYNTHESIS OUTPUT.

RESULT. The MS flipflop code and test bench is verified. Synthesis is achieved and waveforms are observed.

6.ADDERS

6.1. SERIAL ADDER

AIM: Write Verilog Code for serial adder and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints.

THEORY: The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by bit. The serial full adder has three single-bit inputs for the numbers to be added and the carry in. There are two single-bit outputs for the sum and carry out. The carry-in signal is the previously calculated carry-out signal. The addition is performed by adding each bit, lowest to highest, one per clock cycle.

CIRCUIT DIAGRAM:

TRUTHTABLE:

Inputs Outputs

Cin X Y Sum Cout

0 1 1 0 1

1 0 0 1 0

0 1 0 1 0

0 0 1 1 0

VERILOG CODE:

module serial_adder ( A,B, reset, clock, sum); input [7:0] A,B; input reset,clock; output [7:0] sum; reg [3:0] count; reg s,y,Y; wire [7:0] qa,qb,sum; wire run; parameter G=0,H=1; shiftrne shift_A (A,reset,1'b1,1'b0,clock,qa); shiftrne shift_B (B,reset,1'b1,1'b0,clock,qb); shiftrne shift_sum (8'b0,reset,run,s,clock,sum); always @(qa or qb or y) case (y) G: begin s = qa[0]^qb[0]; if (qa[0] & qb[0]) Y = H; else Y = G; end H: begin s = qa[0] ~^qb[0]; if (~qa[0] & ~qb[0]) Y =G; else

Y = H; end default : Y = G; endcase //sequential block always @(posedge clock) if (reset) y <= G; else y <= Y; //control the shifting process always @(posedge clock) if (reset) count = 8; else if (run) count = count - 1; assign run=|count; endmodule

TESTBENCH:

module serial_adder_t ; reg [7:0] A,B; reg reset,clock; wire [7:0] sum ; initial clock = 1'b0; always #5 clock =~clock; serial_adder s1 (A,B,reset,clock,sum); initial begin reset = 1'b0;A = 8'b10101010; B = 8'b11111111; #20 reset = 1'b1; #20 reset = 1'b0; #150 reset = 1'b1; A = 8'b11110000 ; B = 8'b11110011; #20 reset = 1'b0; #200 $finish; end initial $monitor ($time, " SUM = %d ", sum); endmodule

TIMING DIAGRAM

SYNTHESIS OUTPUT

RESULT. The serial adder code and test bench is verified. Synthesis is achieved and waveforms are observed.

6.2 Parallel adder AIM: Write Verilog Code for parallel adder and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY: Parallel adders are digital circuits that compute the addition of variable binary strings of equivalent or different size in parallel.

CIRCUIT DIAGRAM:

TRUTH TABLE:

VERILOG CODE:

module parallel(a,b,c,s,sum,car); input [3:0]a,b; output [3:0]sum,car; output [3:0] s; output c; assign sum[0]=a[0]^b[0]^1'b0; assign sum[1]=a[1]^b[1]^car[0]; assign sum[2]=a[2]^b[2]^car[1]; assign sum[3]=a[3]^b[3]^car[2]; assign car[0]=(a[0]& b[0])|(a[0]& 1'b0)|(b[0]& 1'b0); assign car[1]=(a[1]& b[1])|(a[1]& car[0])|(b[0]& car[0]); assign car[2]=(a[2]& b[2])|(a[2]& car[1])|(b[2]& car[1]); assign car[3]=(a[3]& b[3])|(a[3]& car[2])|(b[3]& car[2]); assign c=car[3]; assign s=sum; endmodule TESTBENCH:

module parallel_test(); reg [3:0]a,b;

wire [3:0]sum,car,s; wire c; parallel s1(a,b,c,s,sum,car); initial begin #10 a[0]=1'b0; #10 a[1]=1'b1; #10 a[2]=1'b0; #10 a[3]=1'b1; end initial begin #10 b[0]=1'b1; #10 b[1]=1'b0; #10 b[2]=1'b1; #10 b[3]=1'b0; end endmodule TIMING DIAGRAM:

SYNTHESIS OUTPUT:

RESULT: The parallel adder code and test bench is verified. Synthesis is achieved and waveforms are observed.

7.COUNTER

AIM: Write Verilog Code for counter and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY: A counter consists of a cascade of flip-flops connected so that the output of one flip-flop drives the input of the next. The signals to be counted are fed into the first flip-flop of the chain. The output Q, of any given flip-flop represents a binary digit or bit (value 0 or 1). The complete set of outputs (Q3, Q2, Q1, Q0) gives the total number of pulses in binary arithmetic, hence the name Binary Counter. CIRCUIT DIAGRAM:

TRUTH TABLE:

States Count

D C B A

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9

1 0 1 0 10

1 0 1 1 11

1 1 0 0 12

1 1 0 1 13

1 1 1 0 14

1 1 1 1 15

VERILOG CODE:

module counter(clk,reset,enable,count); output reg [3:0] count; input clk,reset,enable; always @(posedge clk)

begin if(reset==1 && enable==0) count<=4'b0000; else count<=count+1; end endmodule TESTBENCH: module counter_tb; reg clk,reset,enable; wire [3:0] count; counter counter1(clk,reset,enable,count); initial begin clk = 1'b0; #100 reset = 1; enable = 0; #100 reset=0; enable=1; end always begin #50 clk = ~ clk; end endmodule

TIMING DIAGRAM:

SYNTHESIS OUTPUT:

COUNTER SUMMARY: =================================================== ========= Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 14 2011 10:52:34 AM Module: counter Technology library: fast 1.13 Operating conditions: fast (balanced_tree) Wireload mode: segmented Area mode: timing library =================================================== ========= Timing ------ Warning : Possible timing problems have been detect ed in this design. [TIM-11] : The design is 'counter'. Slack Endpoint Cost Group --------------------------------------- +1867ps count_reg[3]/D default Area ---- Instance Cells Cell Area Net Area Wireloa d --------------------------------------------------- ----------- counter 10 333 0 TSMC18_Conser vative (D) (D) = wireload is default in technology library Design Rule Check ----------------- Max_transition design rule: no violations. Max_capacitance design rule: no violations.

TCL FILE: set_attribute library /home/admin/chotu/library/lib /fast.lib read_hdl -v1995 /home/admin/chotu/kumara_counter/co unter.v elaborate synthesize -to_generic #define_clock -period 10000 -name 100000MHz -design counter define_clock -period 10000 -name 500MHz -divide_per iod 4 clk synthesize -to_mapped report timing > timing.rpt

report power > power.rpt report area > area.rpt report clock_gating > clock_gating.rpt write_sdc > counter.sdc write_hdl > counter.vg write_sdf > counter.sdf

SDF FILE: (DELAYFILE (SDFVERSION "OVI 3.0") (DESIGN "counter") (DATE "Wed Dec 14 10:40:32 IST 2011") (VENDOR "Cadence, Inc.") (PROGRAM "Encounter(R) RTL Compiler") (VERSION "v08.10-s121_1") (DIVIDER .) (VOLTAGE ::1.98) (PROCESS "::1.0") (TEMPERATURE ::0.0) (TIMESCALE 1ps) (CELL (CELLTYPE "OAI2BB2X1") (INSTANCE g84) (DELAY (ABSOLUTE (PORT A0N (::0.0)) (PORT A1N (::0.0)) (PORT B0 (::0.0)) (PORT B1 (::0.0)) (IOPATH (posedge A1N) Y (::87) ()) (IOPATH (negedge A1N) Y () (::98)) (IOPATH (posedge B0) Y () (::27)) (IOPATH (negedge B0) Y (::94) ()) (IOPATH (posedge B1) Y () (::34)) (IOPATH (negedge B1) Y (::91) ()) (IOPATH (posedge A0N) Y (::83) ()) (IOPATH (negedge A0N) Y () (::101)) ) ) ) (CELL (CELLTYPE "OAI2BB2X1") (INSTANCE g86) (DELAY (ABSOLUTE (PORT A0N (::0.0)) (PORT A1N (::0.0)) (PORT B0 (::0.0)) (PORT B1 (::0.0)) (IOPATH (posedge A1N) Y (::88) ()) (IOPATH (negedge A1N) Y () (::102)) (IOPATH (posedge B0) Y () (::24)) (IOPATH (negedge B0) Y (::98) ())

(IOPATH (posedge B1) Y () (::32)) (IOPATH (negedge B1) Y (::96) ()) (IOPATH (posedge A0N) Y (::83) ()) (IOPATH (negedge A0N) Y () (::108)) ) ) ) (CELL (CELLTYPE "NAND2BX1") (INSTANCE g87) (DELAY (ABSOLUTE (PORT AN (::0.0)) (PORT B (::0.0)) (IOPATH (posedge B) Y () (::42)) (IOPATH (negedge B) Y (::97) ()) (IOPATH (posedge AN) Y (::99) ()) (IOPATH (negedge AN) Y () (::118)) ) ) ) (CELL (CELLTYPE "MXI2X1") (INSTANCE g89) (DELAY (ABSOLUTE (PORT S0 (::0.0)) (PORT B (::0.0)) (PORT A (::0.0)) (IOPATH (posedge A) Y () (::44)) (IOPATH (negedge A) Y (::68) ()) (IOPATH (posedge B) Y () (::43)) (IOPATH (negedge B) Y (::76) ()) (COND A == 1'b0 && B == 1'b1 (IOPATH (pos edge S0) Y () (::24))) (COND A == 1'b0 && B == 1'b1 (IOPATH (neg edge S0) Y (::70) ())) (IOPATH (posedge S0) Y (::69) (::24)) (IOPATH (negedge S0) Y (::62) (::28)) (COND A == 1'b1 && B == 1'b0 (IOPATH (pos edge S0) Y (::70) ())) (COND A == 1'b1 && B == 1'b0 (IOPATH (neg edge S0) Y () (::84))) ) ) ) (CELL (CELLTYPE "NAND2BXL") (INSTANCE g90) (DELAY (ABSOLUTE (PORT AN (::0.0)) (PORT B (::0.0)) (IOPATH (posedge B) Y () (::81)) (IOPATH (negedge B) Y (::122) ()) (IOPATH (posedge AN) Y (::144) ()) (IOPATH (negedge AN) Y () (::117)) ) ) )

(CELL (CELLTYPE "NAND2X1") (INSTANCE g91) (DELAY (ABSOLUTE (PORT A (::0.0)) (PORT B (::0.0)) (IOPATH (posedge A) Y () (::65)) (IOPATH (negedge A) Y (::104) ()) (IOPATH (posedge B) Y () (::60)) (IOPATH (negedge B) Y (::112) ()) ) ) ) (CELL (CELLTYPE "DFFTRX1") (INSTANCE count_reg\[3\]) (DELAY (ABSOLUTE (PORT CK (::0.0)) (PORT D (::0.0)) (PORT RN (::0.0)) (IOPATH (posedge CK) Q (::195) (::143)) (IOPATH (posedge CK) QN (::145) (::178)) ) ) (TIMINGCHECK (HOLD (negedge D) (posedge CK) (::-88)) (HOLD (posedge D) (posedge CK) (::-42)) (SETUP (negedge D) (posedge CK) (::147)) (SETUP (posedge D) (posedge CK) (::65)) (HOLD (negedge RN) (posedge CK) (::-113)) (HOLD (posedge RN) (posedge CK) (::-31)) (SETUP (negedge RN) (posedge CK) (::178)) (SETUP (posedge RN) (posedge CK) (::55)) ) ) (CELL (CELLTYPE "DFFTRX1") (INSTANCE count_reg\[2\]) (DELAY (ABSOLUTE (PORT CK (::0.0)) (PORT D (::0.0)) (PORT RN (::0.0)) (IOPATH (posedge CK) Q (::223) (::163)) (IOPATH (posedge CK) QN (::145) (::178)) ) ) (TIMINGCHECK (HOLD (negedge D) (posedge CK) (::-91)) (HOLD (posedge D) (posedge CK) (::-42)) (SETUP (negedge D) (posedge CK) (::150)) (SETUP (posedge D) (posedge CK) (::65)) (HOLD (negedge RN) (posedge CK) (::-113)) (HOLD (posedge RN) (posedge CK) (::-31))

(SETUP (negedge RN) (posedge CK) (::178)) (SETUP (posedge RN) (posedge CK) (::55)) ) ) (CELL (CELLTYPE "DFFTRX1") (INSTANCE count_reg\[1\]) (DELAY (ABSOLUTE (PORT CK (::0.0)) (PORT D (::0.0)) (PORT RN (::0.0)) (IOPATH (posedge CK) Q (::210) (::154)) (IOPATH (posedge CK) QN (::145) (::178)) ) ) (TIMINGCHECK (HOLD (negedge D) (posedge CK) (::-94)) (HOLD (posedge D) (posedge CK) (::-42)) (SETUP (negedge D) (posedge CK) (::152)) (SETUP (posedge D) (posedge CK) (::65)) (HOLD (negedge RN) (posedge CK) (::-113)) (HOLD (posedge RN) (posedge CK) (::-31)) (SETUP (negedge RN) (posedge CK) (::178)) (SETUP (posedge RN) (posedge CK) (::55)) ) ) (CELL (CELLTYPE "DFFTRX1") (INSTANCE count_reg\[0\]) (DELAY (ABSOLUTE (PORT CK (::0.0)) (PORT D (::0.0)) (PORT RN (::0.0)) (IOPATH (posedge CK) Q (::200) (::147)) (IOPATH (posedge CK) QN (::190) (::211)) ) ) (TIMINGCHECK (HOLD (negedge D) (posedge CK) (::-88)) (HOLD (posedge D) (posedge CK) (::-42)) (SETUP (negedge D) (posedge CK) (::146)) (SETUP (posedge D) (posedge CK) (::66)) (HOLD (negedge RN) (posedge CK) (::-113)) (HOLD (posedge RN) (posedge CK) (::-31)) (SETUP (negedge RN) (posedge CK) (::178)) (SETUP (posedge RN) (posedge CK) (::55)) ) ) )

SDC FILE: # ################################################# ################### # Created by Encounter(R) RTL Compiler v08.10-s121 _1 on Wed Dec 14 10:40:32 IST 2011 # ################################################# ################### set sdc_version 1.7 set_units -capacitance 1000.0fF set_units -time 1000.0ps # Set the current design current_design counter create_clock -name "500MHz" -add -period 2.5 -wavef orm {0.0 1.25} [get_ports clk] set_clock_gating_check -setup 0.0 set_wire_load_mode "segmented" set_dont_use [get_lib_cells fast/RF1R1WX2] set_dont_use [get_lib_cells fast/RF2R1WX2] set_dont_use [get_lib_cells fast/RFRDX1] set_dont_use [get_lib_cells fast/RFRDX2] set_dont_use [get_lib_cells fast/RFRDX4] set_dont_use [get_lib_cells fast/TIEHI] set_dont_use [get_lib_cells fast/TIELO] ## List of unsupported SDC commands ##

TIMING REPORT: =================================================== ========= Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 14 2011 10:40:31 AM Module: counter Technology library: fast 1.13 Operating conditions: fast (balanced_tree) Wireload mode: segmented Area mode: timing library =================================================== ========= Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps) --------------------------------------------------- ----------- (clock 500MHz) launch 0 R count_reg[1]/CK 0 0 R count_reg[1]/Q DFFTRX1 3 21.2 183 +210 210 R g91/B +0 210 g91/Y NAND2X1 3 19.3 123 +60 270 F g87/AN +0 270 g87/Y NAND2BX1 2 13.8 109 +118 388 F

g84/A1N +0 388 g84/Y OAI2BB2X1 1 5.8 76 +98 486 F count_reg[3]/D DFFTRX1 +0 486 count_reg[3]/CK setup 0 +147 633 R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock 500MHz) capture 2500 R --------------------------------------------------- ----------- Timing slack : 1867ps Start-point : count_reg[1]/CK End-point : count_reg[3]/D

AREA REPORT: =================================================== ========= Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 14 2011 10:40:32 AM Module: counter Technology library: fast 1.13 Operating conditions: fast (balanced_tree) Wireload mode: segmented Area mode: timing library =================================================== ========= Instance Cells Cell Area Net Area Wireloa d --------------------------------------------------- ----------- counter 10 333 0 TSMC18_Conser vative (D) (D) = wireload is default in technology library

CLOCK GATING REPORT: =================================================== ========= Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 14 2011 10:40:32 AM Module: counter Technology library: fast 1.13 Operating conditions: fast (balanced_tree) Wireload mode: segmented Area mode: timing library =================================================== ========= Summary ------- --------------------------------------------- Category Number % --------------------------------------------- RC Clock Gating Instances 0 - Non-RC Clock Gating Instances 0 - --------------------------------------------- RC Gated Flip-flops 0 0 Non-RC Gated Flip-flops 0 0 Ungated Flip-flops 4 100 Total Flip-flops 4 100 ---------------------------------------------

POWER REPORT: =================================================== ========= Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 14 2011 10:40:31 AM Module: counter Technology library: fast 1.13 Operating conditions: fast (balanced_tree) Wireload mode: segmented Area mode: timing library =================================================== ========= Leakage Dynamic Total Instance Cells Power(nW) Power(nW) Power(nW) ----------------------------------------------- counter 10 2.558 158708.200 158710.758

VERILOG CODE FOR POST SYNTHESIS:

// Generated by Cadence Encounter(R) RTL Compiler v08.10-s121_1 module counter(clk, reset, enable, count); input clk, reset, enable; output [3:0] count; wire clk, reset, enable; wire [3:0] count; wire n_0, n_1, n_2, n_3, n_4, n_5, n_6; DFFTRX1 \count_reg[3] (.CK (clk), .D (n_5), .RN (n_6), .Q (count[3]), .QN ()); DFFTRX1 \count_reg[2] (.CK (clk), .D (n_3), .RN (n_6), .Q (count[2]), .QN ()); OAI2BB2X1 g84(.A0N (count[3]), .A1N (n_4), .B0 (n_4), .B1 (count[3]),.Y (n_5)); DFFTRX1 \count_reg[1] (.CK (clk), .D (n_1), .RN (n_6), .Q (count[1]),.QN ()); OAI2BB2X1 g86(.A0N (count[2]), .A1N (n_2), .B0 (n_2), .B1 (count[2]),.Y (n_3)); DFFTRX1 \count_reg[0] (.CK (clk), .D (n_0), .RN (n_6), .Q (count[0]),.QN (n_0)); NAND2BX1 g87(.AN (n_2), .B (count[2]), .Y (n_4)); MXI2X1 g89(.S0 (count[1]), .B (count[0]), .A (n_0), .Y (n_1)); NAND2BXL g90(.AN (enable), .B (reset), .Y (n_6)); NAND2X1 g91(.A (count[0]), .B (count[1]), .Y (n_2)); endmodule

POST SYNTHESIS OUTPUT:

POSTSYNTHESIS TIMING DIAGRAMS:

8.Successive approximation register [SAR]

AIM. Write Verilog Code for Successive approximation register and Test Bench for verification, observe the waveform and synthesize the code with technological library with given Constraints. THEORY. A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation via a binary search through all possible quantization levels before finally converging upon a digital output for each conversion. CIRCUIT DIAGRAM.

VERILOG CODE. module sar ( R,L,E,w,clock,q); parameter n=8; input [n-1:0] R; input L,E,w,clock; output [n-1:0] q; reg [n-1:0] q; integer k; always @(posedge clock) if (L) q <= R; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; end endmodule TEST BENCH. module sar_t; reg [7:0] r; reg l; reg e; reg w; reg clk; wire [7:0] q; sar sf(.R(r),.L(l),.E(e),.w(w),.clock(clk),.q(q)); initial

begin clk = 1'b0; l = 1'b1; w = 1'b0; e = 1'b0; #5 r = 8'b11110000; #10 l = 1'b0; e = 1'b1; #10 w = 1'b0; #10 w = 1'b1; $finish; end always #5 clk = ~clk; endmodule TIMING WAVEFORM.

SYNTHESIS OUTPUT.

RESULT. The Successive approximation register code and test bench is verified. Synthesis is achieved and waveforms are observed.

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