usb implementation using utmi macrocell

FPGA IMPLEMENTATION OF UTMI WITH USB 2.0 SPECIFICATIONS

1. INTRODUCTION

As operating frequencies go up it becomes more difficult to compile

VHDL code without modification. This document defines an interface to

which ASIC and peripheral vendors can develop.

The figure1 shows the block diagram of USB controller, which is

present in every USB device. There are three major functional blocks in a

USB 2.0controller. the USB 2.0 Transceiver Macrocell Interface (UTMI),

the Serial Interface Engine (SIE), and the device specific logic.

Figure1: Block diagram of USB controller.

UTMI

This block handles the low level USB protocol and signaling. This

includes features such as; data serialization and deserialization, bit stuffing

and clock recovery and synchronization. The primary focus of this block is

to shift the clock domain of the data from the USB 2.0 rate to one that is

compatible with the general logic in the ASIC.

SAI SPURTHI INSTITUE OF TECHNOLOGY


The UTMI is designed to support HS/FS, FS Only and LS Only UTM

implementations. The three options allow a single SIE implementation to be

used with any speed USB transceiver. A vendor can choose the transceiver

performance that best meets their needs.

A HS/FS implementation of the transceiver can operate at either a 480

Mb/s or a 12 Mb/s rate. Two modes of operation are required to properly

emulate High-speed device connection and suspend/resume features of USB

2.0, as well as Full-speed connections if implementing a Dual-Mode device.

FS Only and LS Only UTM implementations do not require the speed

selection signals since there is no alternate speed to switch to.

Serial Interface Engine

This block can be further sub-divided into 2 types of sub-blocks; the

SIE Control Logic and the Endpoint logic. The SIE Control Logic contains

the USB PID and address recognition logic, and other sequencing and state

machine logic to handle USB packets and transactions. The Endpoint Logic

contains the endpoint specific logic: endpoint number recognition, FIFOs

and FIFO control, etc. Generally the SIE Control Logic is required for any

USB implementation while the number and types of endpoints will vary as

function of application and performance requirements.

SIE logic module can be developed by peripheral vendors or

purchased from IP vendors. The standardization of the UTMI allows

compatible SIE VHDL to drop into an ASIC that provides the macro cell.

Device Specific Logic:

This is the glue that ties the USB interface to the specific application of the

device.



2. USB TRANCIEVER MACROCELL INTERFACE

(UTMI)

2.1 Introduction to UTMI

Universal Serial Bus(USB) Transceiver Macrocell Interface (UTMI)

is one of the most important blocks of USB Controller. This block handles

the low level USB protocol and signaling. This includes features such as

data serialization, de serialization, bit stuffing, bit de stuffing, Non Return to

Zero Invert on ‘1’(NRZI) encoding, decoding, clock recovery and

synchronization. The primary focus of this block is to shift the clock domain

of the data from the USB 2.0 rate to one that this compatible with the

general logic in the ASIC.

Key features of the USB 2.0 Transceiver

Supports 480 Mbit/s "High Speed" (HS)/ 12 Mbit/s “Full Speed” (FS),

FS Only and "Low Speed" (LS) Only 1.5 Mbit/s serial data

transmission rates.

Utilizes 8-bit parallel interface to transmit and receive USB 2.0 cable

data

SYNC/EOP generation and checking

High Speed and Full Speed operation to support the development of

"Dual Mode" devices

Data and clock recovery from serial stream on the USB

Bit-stuffing/unstuffing; bit stuff error detection

Holding registers to stage transmit and receive data

Logic to facilitate Wake Up and Suspend detection

Ability to switch between FS and HS terminations/signaling



Single parallel data clock output with on-chip PLL to generate higher

speed serial data clocks.

2.2 Functional Block Diagram and Description

Figure 2.1: UTMI Functional Block Diagram.

Block level Description



This section provides descriptions of each of the blocks shown in

Figure 2.1. These blocks represent high level functionality that is required to

exist in the Macro cell.

Clock Multiplier

This module generates the appropriate internal clocks for the UTM

and the CLK output signal. All data transfer signals are synchronized with

the CLK signal.

The UTM vendor determines the frequency of the external crystal.

The Clock Multiplier circuit and the External Crystal must meet the

requirements defined in the USB 2.0 specification.

After the release of SuspendM, the CLK signal generated by the

transceiver must meet the following requirements:

1) Produce the first CLK transition no later than 5.6 ms after the

negation of SuspendM.

2) The CLK signal frequency error must be less than 10% (±6.00 MHz)

Clocking

HS/FS operation

In HS mode there is one CLK cycle per bit time. The frequency of

CLK does not change when the UTMI is switched between HS to FS modes.

In FS mode there are 5 CLK cycles per FS bit time, typically 40 CLK cycles

per FS byte time. If a received byte contains a stuffed bit then the byte

boundary can be stretched to 45 CLK cycles, and two stuffed bits would

result in a 50 CLK delay between bytes.

Figure 2.2 shows the relationship between CLK and the receive data

transfer signals in FS mode. RXActive "frames" a packet, transitioning only

at the beginning and end of a packet, however transitions of RXValid may



take place any time 8 bits of data are available. Figure 2.2 also shows how

RXValid is only asserted for one CLK cycle per byte time even though the

data may be presented for the full byte time. The Macro cell is required to

present valid data for only for one clock cycle (while RXValid is asserted),

although it may be presented until new data is received.

Figure 2.2 : FS CLK Relationship to Receive Data and Control Signals

Figure 2.3 shows relationship between CLK and the transmit data

transfer signals in FS mode. TXReady is only asserted for one CLK per byte

time. This signal acknowledges to the SIE that the data on the DataIn lines

has been read by the Macrocell (small arrows above DataIn signal. The SIE

must present the next data byte on the DataIn bus after it detects TXReady

high on a rising edge of CLK.

Transitions of TX Valid must meet the defined setup and hold times

relative to CLK. The delay between the assertion of TX Valid and the first

assertion of TX Ready is Macro cell implementation dependent



Figure 2.3 : FS CLK Relationship to Transmit Data and Control Signals

The XcvrSelect signal determines whether the HS or FS timing

relationship is applied to the data and control signals.

FS Only operation

A "FS Only" implementation of the UTM would provide 32 CLK

cycles per byte time. The frequency of CLK would be 48.0 MHz. Timing is

similar to a HS/FS UTM operating in FS mode.

LS Only operation

A "LS Only" implementation of the UTM would provide 32 CLK

cycles per byte time. The frequency of CLK would be 6.0 MHz. Timing is

similar to a HS/FS UTM operating in FS mode.

HS DLL (High Speed Delay Line PLL)

The delay line PLL extracts clock and data from the data received

over the USB 2.0 interface for reception by the Receive Deserializer. A

vendor defined number of delayed clock taps are be used to sample the

received data. The data output from the DLL is synchronous with the local

clock.

Elasticity Buffer

This buffer is used to compensate for differences between transmitting

and receiving clocks. The USB specification defines a maximum clock error



of +/-500 ppm. When the error is calculated over the maximum packet size

up to +/- 12 bits of drift can occur. The elasticity buffer is filled to a

threshold prior to enabling the remainder of the down stream receive logic.

This block may be integrated into the DLL block. An example that will meet

these requirements is a 24 bit deep, 1 bit wide FIFO with a threshold set at

the midpoint. Overflow or underflow conditions detected in the elasticity

buffer can be reported with the RXError signal.

Mux

The bulk of the logic in the transceiver can be used with HS or FS

operations. The Mux block allows the data from the HS or FS receivers to be

routed to the shared receive logic. The state of the Mux is determined by the

XcvrSelect input.

Tx Shift/Hold Register

Figure2.4 shows the Transmit Shift and Hold Register.This module is

responsible for reading parallel data from the parallel application bus

interface upon command and serializing for transmission over USB. This

module consists of an 8-bit primary shift register for parallel/serial

conversion and an 8-bit Hold register used to buffer the next data to

serialize.

Figure 2.4: Transmit shift/Hold register



NRZI Encoder

This is a standard USB 1.X compliant serial NRZI encoder module,

which can operate at full-speed or high-speed USB data rates. Whenever a

bit ‘1’ is encountered in the data stream, it is negated. A bit ‘0’ is

transmitted as it is depend on the Operational Mode.

Bitstuff Logic

In order to ensure adequate signal transitions, bit stuffing is employed

when sending data on USB. A zero is inserted after every six consecutive

ones in the data stream before the data is NRZI encoded, to enforce a

transition in the NRZI data stream. Bit stuffing is enabled beginning with the

SYNC Pattern and through the entire transmission. The data "one" that ends

the SYNC Pattern is counted as the first one in a sequence. In FS mode bit

stuffing by the transmitter is always enforced, without exception. If required

by the bit stuffing rules, a zero bit is inserted even after the last bit before the

TXValid signal is negated.

After 8 bits are stuffed into the USB data stream TXReady is negated

for one byte time to hold up the data stream on the DataIn bus. Figure 2.5

show the timing relationship between TXReady and DataIn.

Figure 2.5: Transmit Timing delays due to Bit Stuffing



The Byte CLK in Figure 2.5 is identical to the CLK signal in HS mode and

CLK/40 in FS mode.

Rx Shift/Hold Registers

Figure 2.6 shows the receive shift and hold register. This module is

responsible for converting serial data received from the USB to parallel data.

This module consists of an 8-bit primary RX Shift Register for serial to

parallel conversion and an 8-bit RX Hold Register used to buffer received

data bytes and present them to the Data Out bus.

Figure 2.6: Rx Shift/Hold Register

NRZI Decoder

This is a standard USB 1.X compliant serial NRZI decoder module,

which can operate at FS or HS USB data rates. The data received on DP,

DM lines is NRZI(1) decoded and it is sent to the bit unstuff module.

Bit Unstuff Logic

This is a standard USB 1.X compliant serial bit unstuff module, which

can operate at FS or HS USB data rates. The bit unstuff logic is a state

machine, which strips a stuffed 0 bit from the data stream and detects bit

stuff errors. In FS mode bit stuff errors assert the RXError signal. In HS

mode bit stuff errors are used to generate the EOP signal so the RXError

signal is not asserted.



The bit rate on USB is constant, however the bit rate as presented by

the UTMI to the SIE is slightly reduced due to the extraction of inserted 1

bits. Normally a byte of data is presented on the DataOut bus for every 8 bits

received, however after eight stuffed bits are eliminated from the data stream

a byte time is skipped in the DataOut stream. Figure 2.7 shows how

RXValid is used to skip bytes in the DataOut byte stream.

Figure 2.7: Receive Timing for Data with after Unstuffing Bits

The timing in Figure 2.7 is for HS mode. In FS mode, if a bit stuff

error is detected then the Receive State Machine will assert RXError.



2.3 UTMI Signal Descriptions

The Table 2.1 gives the summary of system interface signals those are

referred by the SIE and the UTMI. Each of the signals given in the table 2.1

is clearly described below.

2.3.1 System Interface Signals

Table 2.1: System Interface Signals



CLK

Conceptually, there is a "CLKUsable" signal, internal to the UTM,

which blocks any transitions of CLK until it is "usable". This "CLKUsable"

signal is also used to switch the Line State output between CLK

synchronized and combinatorial signaling.

Options

There are 3 possible implementations for a UTMI device: HS/FS, FS

Only, or LS Only. The HS/FS version has 4 interface options: 16-bit

unidirectional, 8-bit unidirectional, 16-bit bidirectional/8-bit unidirectional,

and 8-bit bi-directional. In each case, when a 16-bit option is selected CLK

is at 30 MHz, and when an 8-bit option is selected CLK is at 60 MHz.

The 16-bit bidirectional/8-bit unidirectional uses the "DataBus16_8"

signal to switch between them. This signal also switches the CLK frequency.

The FS Only, or LS Only implementations only support 48 MHz and

6 MHz clocks, respectively, and always use 8 bit interfaces (either 8-bit

unidirectional or 8-bit bi-directional).

Xcvr Select

XcvrSelect controls a number of transceiver related elements, it

selects the receiver (source for the Mux block) in the receive data path. It is

used as a gating term for enabling the respective HS or FS Transmit Driver.

Switch internal UTM clocks to shared logic.

Term Select

Term Select controls a number of termination related elements.

In HS mode the FS Driver is forced to assert an SE0 on the USB,

providing the 50 Ohm termination to ground and generating the HS Idle

state on the bus.



In FS Mode TermSelect enables the 1.5K pull-up on to the DP signal

to generate the FS Idle state on the bus.

Speed Selection

The XcvrSelect and TermSelect signals determine whether the device

is in HS or FS mode, enabling the respective transceiver and termination.

The HS Detection Handshake protocol requires independent control of

transceivers and terminations, where the device enables FS terminations but

is required to drive and listen to the bus with the HS transceiver. In all other

cases the state of the XcvrSelect and TermSelect signals are identical.

FS Only and LS Only UTM implementations do not require the

XcvrSelect and TermSelect speed selection signals since there is no alternate

speed to switch to.

Line State

The Line State signals are used by the SIE for detecting reset, speed

signaling, packet timing, and to transition from one behavior to another.

While data packets are being transmitted or received on the USB the Line

State signals may toggle randomly between the 'J' and 'K' states in FS, and

remain in the ‘J’ state in HS. The SIE should ignore these transitions.

Synchronization

To minimize unwanted transitions to the SIE during normal operation,

the Line State is internally synchronized with CLK. When synchronized, the

setup and hold timing of Line State is identical to Data Out. The exception

to this is when CLK is not "usable". If CLK is not "usable" then the Line

State signals are not synchronized, but driven with combinatorial logic

directly from the DP and DM signal lines. The UTM must multiplex

between combinatorial and synchronous Line State output depending on

whether CLK is "usable.



Bus Packet Timing

Line State must be used by the SIE for the precise timing of packet

data on the DP/DM signal lines. The SIE uses Line State transitions to

identify the beginning and end of receive or transmit packets on the bus.

Line State represents bus activity within 2 or 3 CLK times of the actual

events on the bus.

HS Mode

When XcvrSelect and TermSelect are in HS mode, the Line State

transition from the Idle state (SE0) to a non-Idle state (J) marks the

beginning of a packet on the bus. The Line State transition from a non-Idle

state (J) to the Idle state (SE0) marks the end of a packet on the bus.

FS Mode

When XcvrSelect and TermSelect are in FS mode, the LineState

transition from the J State (Idle) to a K State marks the beginning of a packet

on the bus. The SIE must then wait for the end of the packet. The LineState

transition from the SE0 to the J-State marks the end of a FS packet on the

bus.

2.3.2 USB Interface Signals

Table 2.3: USB Interface Signals

Table2.2 gives the summary of USB interface signals. These are bi-

directional signals and they are used to connect the USB device to the outer

world. The data transmission and reception occur on these two lines. If bit

‘1’ is present on DP line, bit ‘0’ will present on DM line in the same clock

duration. This is required because if bit ‘1’ i.e, +5V is present on DP line, a



magnetic field will be created around the line. This magnetic field may

affect the near by lines. To compensate the affect of magnetic field, a bit ‘0’

i.e, -5V is present on DM line. The net affect of the magnetic field will be

zero. Thus the noise is reduced.

2.3.3 Data Interface Signals

The table 2.3 gives the summary of data interface signals those are

referred by the SIE and the UTMI while data is being transmitted. Each of

the signals given in the table 2.3 is clearly described below.

Table 2.3: Data Interface Signals (Transmit)



The table 2.4 gives the summary of data interface signals those are

referred by the SIE and the UTMI while data is being received. Each of the

signals given in the table 2.4 is clearly described below.

Table 2.4: Data Interface Signals (Receive)



Receive Active

RX Active is used by the SIE to time inter-packet gaps. It is important

that RX Active accurately reflects the state of the USB. For instance, HS

implementations should not simply negate RX Active as soon as a forced bit

stuff error (EOP) is detected. Two HS cases in particular should be

considered: 1) dribble bits5 introduced by hubs and 2) long EOP s at the end

of SOF packets. In both cases, the initial bit stuff error that signals the EOP

is followed by several additional bits before the USB returns to the Idle

state. The deassertion of RX Active under normal conditions must reflect the

USB being in the Idle state, not simply timed off the recognition of EOP.

The exception is if an error is detected during a receive. In this case

RXValid will be negated after the next rising edge of CLK after the error is

detected. And RX Active maybe negated immediately or after a Bus Idle

condition is detected.

2.4 Operational Modes

The OpMode signals are capable of inhibiting normal operation of the

transceiver and evoking special test modes. The table 2.5 gives the summary

of operational modes. Each of the signals given in the table 2.5 is clearly

described below.

There are 3 test modes:

Normal Operation (0)

Non-Driving (1)

Disable Bit Stuffing and NRZI encoding (2)



Table 2.5: Operational Modes

Mode 0 allows the transceiver to operate with normal USB data

decoding and encoding.

Mode 1 allows the transceiver logic to support a soft disconnect

feature which tri-states both the HS and FS transmitters, and removes any

termination from the USB making it appear to an upstream port that the

device has been disconnected from the bus.

Mode 2 disables Bit Stuff and NRZI encoding logic so 1's loaded

from the Data In bus becomes 'J's on the DP/DM lines and 0's become 'K's.

Note that this mode affects the automatic SYNC Pattern and EOP generation

by TX Valid. It is disabled so that Chirps can be generated on the USB. The

operation of the receiver is undefined.

Changing the OP Mode signals under all other conditions, while the

transceiver is receiving or transmitting data will generate undefined results.

2.5 Bi-directional 8-bit Interface:

An option for the UTMI is to attach the block described in the figure

2.8 below to the 8-bit interface. This option provides an 8-bit bi-directional

bus, minimizing the connection count. When this option is applied, 8 data

lines will be presented by the transceiver, where Data0-7 is a bi- directional

data bus.



If TX Valid is asserted (1) then the signals Data0-7 accepts transmit data

from the SIE. If TX Valid is negated (0) then the signals Data0-7 present

received data to the SIE.

Figure 2.8: 8-Bit Bi-directional Data Bus Interface

2.6 UTM Entity Diagram:

The entity diagram of UTMI is shown in the figure 2.9. The figure

shows all the signals of UTMI and their direction. All the input signals to the

UTMI are from SIE and all the output signals are to the SIE.

Figure 2.9: 8-Bit Interface Entity Diagram



3. DESIGN ASPECTS OF UTMI

The UTMI is divided into two modules, which are the transmitter

module and the receiver module.

3.1 The Transmitter module Specifications

The transmitter module of UTMI has been implemented by considering

the following specifications.

The SYNC pattern ‘01111110’ has to be transmitted immediately after

the transmitter is initiated by the SIE.

After six consecutive ‘1’s occur in the data stream, a zero to be inserted.

The data should be encoded using Non Return to Zero Invert on 1(NRZI

-1) encoding technique.

The EOP pattern two single ended zeros (D+ and D- lines are carrying

zero for two clock cycles) and a bit 1 have to be transmitted after each

packet or after SIE suspends the transmitter.

The behavior of the Transmit State Machine given by USB 2.0

specifications is described and illustrated in Fig.3.1

The Reset signal forces the state machine into the Reset state which

negates TX Ready. When Reset is negated the transmit state machine will

enter the TX Wait state.

In the TX Wait state, the transmit state machine looks for the assertion of

TX Valid. When TX Valid is detected, the state machine will enter the Send

SYNC state and begin transmission of the SYNC pattern.

When the transmitter is ready for the first byte of the packet (PID), it will

enter the TX Data Load state, assert TX Ready and load the TX Holding

Register. The state machine may enter the TX Data Wait state while the

SYNC pattern transmission is completed.



TXReady is used to throttle transmit data. The state machine will remain

in the TX Data Wait state until the TX Data Holding register is available for

more data. In the TX Data Load state, the state machine loads the Transmit

Holding register. The state machine will remain in the TX Data Load state as

long as the transmit state machine can empty the TX Holding Register

before the next rising edge of CLK.

When TXValid is negated the transmit state machine enters the Send

EOP state where it sends the EOP. While the EOP is being transmitted

TXReady is negated and the state machine will remain in the Send EOP

state. After the EOP is transmitted the Transmit State Machine returns to the

TX Wait state.

The summary of the above description is given below.

Figure 3.1: Transmit state machine



Transmit must be asserted to enable any transmissions.

The SIE asserts TXValid to begin a transmission.

The SIE negates TXValid to end a transmission.

After the SIE asserts TXValid it can assume that the transmission has

started when it detects TXReady asserted.

The SIE assumes that the UTMI has consumed a data byte if

TXReady and TXValid are asserted.

TXValid and TXReady are sampled on the rising edge of CLK.

The SIE must use LineState to verify a bus Idle condition before

asserting TXValid in the TX Wait state.

Figure 3.2 shows the timing relationship between TXValid, DataIn,

TXReady and the transmitted data (DP/DM).

Figure 3.2: Transmit Timing for a Data packet

The SIE negates TXValid to complete a packet. Once negated, the

Transmit State Machine will never re- assert TXReady until after the EOP

has been loaded into the Transmit Shift Register.



3.1.1 FS Operations

The following sections provide examples of FS SYNC and EOP

generation by the Transmit State Machine.

3.1.1.1 FS Start of Packet

The assertion of the TXValid signal initiates packet transmission.

With the bus initially in the Idle state ( 'J' state), a SYNC pattern

("KJKJKJKK") in its NRZI encoding is generated on the USB. To generate

this pattern the SYNC data pattern (0x80) is forced into the Transmit Data

Shift Register by the Transmit State Machine. TXValid will remain asserted

if valid packet data bytes are available to be loaded into the Transmit Data

Holding Register.

Figure 3.3: Data Encoding Sequence: FS SYNC



The CLK signal is marked "not to scale" because cycles are dropped

in Figure 3.3 to show how CLK edges align with the byte boundaries of the

FS data transmission.

3.1.1.2 FS End Of Packet

In FS mode, a single ended zero (SE0) state is used to indicate EOP

and a 'J' state indicates Idle. The SE0 state is asserted for 2 bit times then a 'J'

state is asserted for 1 bit time which is shown in figure 3.4.

Negating the TXValid signal initiates the FS EOP process; bit stuffing

will cease, the bit stuff state machine will be reset, and the FS EOP (two bit

times of SE0 followed by a single 'J' bit) will be asserted on the bus.

TXReady is negated after TXValid is detected false and cannot be

reasserted (dashed line) until after the EOP pattern and 'J' state bit are

transmitted. The delay between the assertion of TXValid and the first

assertion of TXReady is UTM implementation dependent.

Figure 3.4: Data Encoding Sequence: FS EOP



3.1.2 HS Operation

The following sections provide examples of HS SYNC and EOP

generation by the Transmit State Machine.

3.1.2.1 HS Start of Packet

The assertion of TXValid will initiate the generation of the HS SYNC

pattern on the USB by the Transmit State Machine. A SYNC pattern is the

32-bit binary string "KJKJK…JKJKJKK", in its NRZI encoding. To

generate this pattern four bytes of SYNC data pattern (0x00, 0x00, 0x00,

0x80) are forced into the Transmit Shift Register by the Transmit State

Machine. As long as TXValid is asserted the Transmit State Machine will

assume that valid packet data is available on the DataIn bus to be loaded into

the Transmit Holding Register.

Figure 3.5 demonstrates how the detection of a zero to one transition

of TXValid forces the transmit state machine of the transceiver to send a 32-

bit Sync pattern then begin transmission with bit stuffing enabled.

TXReady is negated to indicate to the SIE that the data on the DataIn

bus has not been loaded into the Transmit Data Holding Register.

Figure 3.5: Data Encoding Sequence: HS SYNC



3.1.2.2 HS End of Packet

The negation of TXValid will initiate the EOP sequence in the

Transmit State Machine which is shown in figure3.6.

TXReady is negated for at least one byte time while the EOP pattern is being

transmitted.

TXReady is negated after TXValid is detected false and cannot be

reasserted (dashed line) until after the EOP pattern is transmitted. The delay

between the assertion of TXValid and the first assertion of TXReady is

UTM implementation dependent.

Figure 3.6: Data Encoding Sequence: HS EOP



3.2 The Transmitter Module Design

The transmitter module is designed by considering all the above

specifications. VHDL is used to design the transmitter module. The

transmitter module of the UTMI consists of various blocks such as SYNC

generator, transmit hold and shift register, bit stuffer, NRZI encoder and

EOP generator.

A transmit state machine is developed by considering all the states

given by USB 2.0 transmit state machine. Initially the transmitter is at Reset

state where the reset signal is high. If reset signal goes low state the state of

the transmitter is changed to TX wait state where it is waiting for assertion

of TX valid signal by the SIE.

3.2.1 SYNC generator

When the TX valid signal is asserted by the SIE, transmit state

machine enters into send Sync state where a signal called sync enable is

asserted. This signal is checked at every rising edge of the clock out side the

state machine. When this signal is enabled, a sync pattern “01111110” is

send to the NRZI encoder.

3.2.2 Transmit hold and shift register

The data byte placed on the data lines by the SIE sampled by the

UTMI at the rising edge of the clock. For this purpose, an 8-bitvector is

declared in the entity declaration of the transmitter module. This 8-bit vector

is considered as transmit hold and shift register.

The transmit hold and shift register is loaded with 8-bit parallel data

from SIE at the rising edge of the clock. At this movement the transmit state

machine is in Data load state. After the register is loaded, the data is sent to

the other modules serially. Each bit of the register is sent to the Bit stuff



module. After all the bits are serially sent to the Bit stuff module, Tx ready

signal is asserted by the transmit state machine. During parallel to serial

conversion data, the transmit state machine is in Data wait state.

3.2.3 Bit stuffer

The bit stuffer examines each bit of the stream. If six consecutive ‘1’s

are detected then a bit ‘0’ is inserted after six ‘1’s. For this purpose, a state

machine is designed which is invoked at every rising edge of the clock. If a

‘1’ is detected, the state will change to the next state until six consecutive ‘1’

are detected. Otherwise the state of machine will be in its initial state. If six

consecutive ‘1’ are detected, the state machine asserts a signal. This signal is

checked outside the state machine for every clock. If this signal is high, then

a bit ‘0’ is inserted after six consecutive ‘1’s. During Bit Stuffing, the

transmit state machine is in Data wait state.

3.2.4 NRZI Encoder

This encoder uses Non Return to Zero Invert on ‘1’encoding scheme.

When bit ‘1’ is encountered in the serial stream of data, it will be negated

and then it is transmitted on to DP, DM lines. When bit ‘0’ is encountered it

is directly transmitted onto DP, DM lines. During NRZI encoding, the

transmit state machine is in Data wait state.

3.2.5 EOP Generator

When TX valid signal is negated by the SIE, the transmit state

machine enters into send EOP state where it enables a signal called

eop_enable. This signal is checked out side the state machine for every

clock. If this signal is high then the EOP pattern: two single ended zeroes

(i.e, DP, DM lines contain zeroes) and a ‘J’ (i.e, a ‘1’ on DP line and a ‘0’ on

DM line) is transmitted on to DP, DM lines.



3.3 The Receiver Module Specification

The receiver module has been implemented by considering the fallowing

specifications.

When SYNC pattern is detected that should be intimated to the SIE.

If a zero is not detected after six consecutive ‘1’s an error should be

reported to the SIE.

When EOP pattern is detected that should be intimated to the SIE.

The behavior of the Receive State Machine is illustrated in Figure 3.7

The assertion of Reset will force the Receive State Machine into the

Reset state. The Reset state negates RXActive and RXValid. When the

Reset signal is negated the Receive State Machine enters the RX Wait state

and starts looking for a SYNC pattern on the USB. When a SYNC pattern is

detected the state machine will enter the Strip SYNC state and assert

RXActive. The length of the received SYNC pattern varies and can be up to

32 bits long. As a result, the state machine may remain in the Strip SYNC

state for several byte times before capturing the first byte of data and

entering the RX Data state.

After 8 bits of valid serial data is received the state machine enters the

RX Data state, where the data is loaded into the RX Holding Register on the

rising edge of CLK and RXValid is asserted. The SIE must clock the data

off the DataOut bus on the next rising edge of CLK.

Stuffed bits are stripped from the data stream. Each time 8 stuffed bits

are accumulated the state machine will enter the RX Data Wait state,

negating RXValid thus skipping a byte time.



When the EOP is detected the state machine will enter the Strip EOP

state and negate RXActive and RXValid. After the EOP has been stripped

the Receive State Machine will reenter the RX Wait state and begin looking

for the next packet.

If a Receive Error is detected, the Error State is entered and RXError

is asserted. Then either the Abort 1 State is entered where RXActive,

RXValid, and RXError are negated, or the Abort 2 State is entered where

only RXValid, and RXError are negated. The Abort 1 State proceeds

directly to the RX Wait State, while Abort 2 State proceeds to the Terminate

State after an Idle bus state is detected on DP and DM. The Terminate State

proceeds directly to the RX Wait State.

When the last data byte is clocked off the DataOut bus the SIE must

also capture the state of the RXError signal. The description of the receiver

given above is summarized below.

Figure 3.7: Receive state machine.



RXActive and RXValid are sampled on the rising edge of CLK.

In the RX Wait state the receiver is always looking for SYNC.

The Macrocell asserts RXActive when SYNC is detected (Strip

SYNC state).

The Macrocell negates RXActive when an EOP is detected (Strip

EOP state).

When RxActive is asserted, RXValid will be asserted if the RX

Holding Register is full.

RXValid will be negated if the RX Holding Register was not loaded

during the previous byte time. This will occur if 8 stuffed bits have

been accumulated.

The SIE must be ready to consume a data byte if RXActive and

RXValid are asserted (RX Data state).

In FS mode, if a bit stuff error is detected then the Receive State

Machine will negate RXActive and RXValid, and return to the

RXWait state.

Figure 3.8 shows the timing relationship between the received data (DP/DM)

, RXValid, RXActive,RXError and DataOut signals.

Figure 3.8: Receive Timing for Data Packet



3.3.1 Receive Error Reporting

If an error is detected by the receiver the receive state machine will

enter the Error state and assert RXError. It will then transition to the Abort1

or Abort2/Terminate state, terminating the receive operation. Any data

received while RXError is asserted should be ignored and is shown in Figure

4.7. The Receive State Machine will then enter the RX Wait state and start

looking for a valid SYNC pattern.

Possible sources of receive errors.

Bit stuff error has been detected during a FS receive operation

Elasticity Buffer over run

Elasticity Buffer under run

Loss of sync by the DLL

Alignment error, EOP not on a byte boundary

Vendor Specific errors.

Figure 3.9: RX Error Timing diagram

Bit Stuff Error Reporting

If a bit stuff error occurs in the middle of a FS receive packet it will

generate a receive error, however packet data is still on the bus so will not

be negated until an Idle state is detected on the bus.

By definition, a "bit stuff error" during a HS packet is automatically

interpreted as an EOP. In this case RX error is not asserted.



Figure 3.9 shows RX valid and RX error asserted at the same time.

The state of RX valid is a function of data flow control, while RX error is

asserted when an error is detected.

The present UTMI has been designed according to the fallowing

specifications provided by the USB2.0 protocol.

SYNC and End Of Packet (EOP) generation by the transmitter.

Parallel to Serial conversion of data by the transmitter.

Enabling or disabling the bit stuff and NRZI encoder depends on the

operational mode.

SYNC and EOP detection by the receiver.

Receive error reporting.

Suspension of the transceiver by the SIE.

3.4 The Receiver Design

The receiver module is designed by considering all the above

specifications. VHDL is used to design the receiver module. The receiver

module of the UTMI consists of various blocks such as SYNC detector,

NRZI decoder, bit un stuffer, receive shift and hold Register and EOP

detector.

A receive state machine is developed by considering all the states

given by USB 2.0 receive state machine. Initially the receiver is at Reset

state where the reset signal is high and RX active and RX valid signals are

low. If reset signal goes low the state of the receiver is changed to RX wait

state where it is waiting for SYNC pattern.



3.4.1 SYNC Detector

When the receiver detects encoded SYNC pattern “01010100”, the

Receive state machine will enter into strip sync state where the SYNC

pattern is stripped off. To detect the SYNC pattern a state machine is

developed. It checks every bit for every rising edge of the clock. If the

pattern is detected, a signal called sync detected is enabled. This signal is

checked by the Receive state machine. If the signal is high, the Receive state

machine will enter into strip sync state where RX active signal is asserted

and the state machine will enter into RX data state.

3.4.2 NRZI Decoder

The received data on DP, DM lines are NRZI decoded. The NRZI

Decoder simply XOR the present bit with the provisionally received bit.

During NRZI decoding, the receive state machine is in RX wait state.

3.4.3 Bit Unstuffer

The Bit Unstuffer examines each bit of the stream. If a zero is

detected after six consecutive ‘1’s the zero bit is deleted. For this purpose, a

state machine is designed which is invoked at every rising edge of the clock.

The state of the machine will change to the next state until six consecutive

‘1’ and a bit ‘0’ or detected. Otherwise the state of machine will change to

its initial state. During bit Unstuffing, the receive state machine is in RX

data wait state. After the zero bit has been unstuffed, the receive state

machine will enter into RX data state where it asserts RX valid signal.

If a zero is not detected after six consecutive ‘1’ the state machine

asserts a signal called rx_error. This signal is checked by the receive state

machine for every clock. If this signal is high, then the receive state machine

will enter into RX error state where RX error signal is asserted. At the next



rising edge of the clock, the receive state machine will enter into the abort1

state where RX active, RX valid and RX error signals are negated.

3.4.4 Receive Shift and Hold Register

The serial data received from the bit Unstuffer is shifted into the

receive shift register. After the shift Register is full, it is held there for one

clock duration and then the data is placed on to the data out bus. This 8-bit

data is sampled by the SIE at the next rising edge of the clock during

shifting, the receive state machine is in RX data wait state. During holding,

the receive state machine is in RX data state where it asserts RX valid

signal.

3.4.5 EOP Detector

A state machine is developed for EOP detection, which is invoked at

every rising edge of the clock. When two single ended zeroes fallowed by a

‘J’ state is detected, it asserts a signal called eop_detect which is checked by

the Receive state machine at every rising edge of the clock. When this signal

is high, the receive state machine will enter in to Strip eop state where the

EOP pattern is stripped off and RX active, RX valid signals are negated. At

the next rising edge of the clock. The Receive state machine will enter into

the RX wait state.



4. SIMULATION RESULTS

The Transmitter module and the Receiver modules of the UTMI are

designed with VHDL and they are simulated in the Model Sim 6.0

simulator. The fallowing sections give the source code, test bench and

simulation results for each module.

The UTMI is designed by combining these two modules and it is

simulated in the Model Sim 6.0. The source code, test bench and simulation

results are given in the fallowing sections.

4.1 Source Code for Transmitter Modulelibrary Ieee;use Ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity tx_sm isport( reset,txvalid:in std_logic;

clk : in std_logic;txready,txdp,txdm: out std_logic;dataln : in std_logic_vector(7 downto 0));

end tx_sm; architecture tx_sm_arch of tx_sm is

signal eop_done,sync_enable,load_data,load_eop: std_logic;signal txhldreg:std_logic_vector(7 downto 0);signal

bitstuff_enable,serial_out,serial_bs,serial_nrzi,shift_done:std_logic;signal count : std_logic_vector(2 downto 0);signal eop_cnt:std_logic_vector(1 downto 0);signal eop_start:std_logic;type st is (idle,txwait,send_sync,data_load,data_wait,send_eop);signal state : st ;

beginprocess( clk)begin if clk='1' and clk'event then



if reset ='0' thencase state is

when idle => state<=txwait;when txwait => if txvalid ='1' thenstate<=send_sync; sync_enable<='1';

else state <=txwait;

end if;when send_sync => sync_enable<='0';

load_data<='0';if(shift_done='1') then state<=data_load;

else state<=send_sync;end if;

when data_load =>txready<='1';if(txvalid='1')then

load_data<='1'; state<=data_wait;

else state<=send_eop;

load_eop<='1';end if;

when data_wait => txready<='0'; load_data<='0';

if (shift_done ='1') then state<=data_load;else state<=data_wait;

end if;when send_eop =>

txready<='0'; if (eop_done = '0') then state <=send_eop; else

load_eop<='0';

state<=idle;end if;

when others => state<=idle;end case;

elsestate<=idle; txready<='0';load_eop<='0';



eop_done<='0'; end if; end if;

end process;--process for loading & shiftingprocess(clk) begin if clk='1' and clk'event then

if(reset='0')thenif(load_data='1') then

txhldreg<=dataln;else if(load_data='0' )then serial_out<=txhldreg(7);

txhldreg<= txhldreg(6 downto 0) & '0';end if;

else txhldreg<="01111110";end if;

end if; end process;

--process for countprocess(clk)

beginif clk='1' and clk'event then if(reset='0')then if(sync_enable='1' or load_data='0')then

count<= count + "001"; if(count="111" )then

shift_done<='1'; else shift_done<='0';

end if; end if;else

count<="000";shift_done<='0';

end if; end if;end process;-- process for bit stuffing process(clk)



beginif clk='1' and clk'event then

if(reset='0')thenif (bitstuff_enable='1') then

serial_bs<='0';else serial_bs<= serial_out;end if;else serial_bs<='0';end if;end if;

end process;--process for to detect data to be bit stuffedprocess(clk)

type seq_state is (s0,s1,s2,s3,s4,s5);variable st : seq_state;

begin if clk='1' and clk'event then

if(reset='0')thenif(state=data_wait) then

case st iswhen s0 => bitstuff_enable<='0';

if (serial_out ='1') then st:= s1;else st:=s0;end if;

when s1 => bitstuff_enable<='0';if (serial_out ='1') then

st:= s2;else st:=s0;end if;

when s2 => bitstuff_enable<='0';if (serial_out ='1') then

st:= s3;else st:=s0;end if;

when s3 => bitstuff_enable<='0';if (serial_out ='1') then st:= s4;else st:=s0;end if;

when s4 => bitstuff_enable<='0';



if (serial_out ='1') then st:= s5;

else st:=s0;end if;

when s5 => if (serial_out ='1') thenbitstuff_enable<='1';st:= s0;

else st:=s0; end if;

when others=> bitstuff_enable<='0'; st:=s0;

end case; else bitstuff_enable<='0'; end if;

else bitstuff_enable<='0';

st:=s0; end if;


-- process for encoding & eopprocess(clk)

beginif clk='1' and clk'event thenif(reset='0')then

if(state=send_eop)thenif (load_eop='1') thenif(eop_cnt <="01" )thenserial_nrzi<='0';

eop_cnt<=eop_cnt+"01";eop_done<='0';eop_start<='1';else serial_nrzi<='1'; eop_done<='1';eop_cnt <="00";eop_start <=’0’;end if;



end if;else if(serial_bs='1') then

serial_nrzi<=not serial_nrzi;elseserial_nrzi<= serial_nrzi;

end if;end if;else

eop_cnt <="00";serial_nrzi<='0';eop_done<='0';eop_start<='0';

end if; end if;

end process;--process for data outprocess(clk) begin

if clk='1' and clk'event thenif(reset='0')thenif(load_eop='0')then

txdp<=serial_nrzi; txdm<= not serial_nrzi;

else if(eop_start='1') txdp<=serial_nrzi;

txdm<=serial_nrzi; else txdp<=serial_nrzi;

txdm<= not serial_nrzi;end if;

end if;end if;

end if; end process;end tx_sm_arch;

4.2 Test Bench for Transmitter Modulelibrary Ieee;use Ieee.std_logic_1164.all;use ieee.std_logic_arith.all;



use ieee.std_logic_unsigned.all;

entity tx_sm_tb isend tx_sm_tb;

architecture tx_sm_arch_tb of tx_sm_tb is component tx_sm

port ( reset,txvalid:in std_logic; clk : in std_logic;txready,txdp,txdm: out std_logic;dataln : in std_logic_vector(7 downto 0));

end component;signal reset_i:std_logic:='1';signal txvalid_i:std_logic;signal clk_i:std_logic:='0';signal txready_i:std_logic;signal dataln_i:std_logic_vector(7 downto 0);signal txdp_i:std_logic;signal txdm_i:std_logic;signal count:std_logic_vector(3 downto 0);

begininstance:tx_sm port map(reset=>reset_i,

txvalid=> txvalid_i, clk=>clk_i,

txready=>txready_i,

dataln=> dataln_i, txdp =>txdp_i,

txdm =>txdm_i);clk_i<= not clk_i after 50 ns;reset_i<= '0' after 200 ns;txvalid_i<='1' after 300 ns,'0'after 8 us;

process(clk_i)beginif clk_i='1' and clk_i'event thenif(reset_i='0')thenif(count<="0111")thencount<=count+"0001";else dataln_i<=dataln_i+"00000001";



count<="0000";end if;elsecount<="0000";dataln_i<="00000000";end if;end if;

end process; end tx_sm_arch_tb;

4.3 Simulation Results for Transmitter Module

Figure 4.10: SYNC transmission and NRZI Encoding.

The figure 4.10 shows when reset_i is low and txvalid_i signal is

asserted by the SIE, Encoded sync pattern 01010100 is sent on to the

txdp_i line. The opmode 00 shows that the transmitter is in normal mode and

the data 10110100 is NRZI encoded and sent on to the txdp_i line after sync

has been transmitted after txreday_i goes high. The txready_i signal goes

low immediately after the SIE data loaded into TXhold register. When

reset_i is high the transmitter is in reset state.



Figure 4.11: Transmitter at Operational mode 10The figure 4.11 shows that when reset_i is low and txvalid_i signal is

high and opmode is “10” NRZI encoding is disabled. The data 10111110 is

transmitted as it is on to txdp_i and txdp_i is lines. After the transmission of

data on to the serial bus, the transmitter asserts txready_i signal.

Figure 4.12: Bit stuffing Logic

The figure 4.12 shows bitstuff operation of the transmitter. When

reset_i is low and txvalid_i signal is high and six consecutive 1’s present in

the data, a zero is appended after six ones and it is NRZI encoded. The data

is transmitted on to txdp_i, txdm_i lines. The transmitter is in normal mode

i.e, the opmode signal is ‘00’. After the transmission of data on to the serial

bus, the transmitter asserts txready_i signal.



Figure 4.13: EOP Transmission

The figure 4.13 shows that when reset_i is low and txvalid_i is de

asserted by SIE, the EOP pattern (two SE0s and one J state) is transmitted

on to txdp_i, txdm_i lines after the

EOP pattern is transmitted, the transmitter enters into TX wait state

where it is waiting for the SYNC pattern.

4.4 Source Code for Receiver Modulelibrary Ieee;use Ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity rx_sm is port( reset,rxdp,rxdm:in std_logic; rxvalid,rxactive,rxerror_o:out std_logic;

clk : in std_logic; data_out: out std_logic_vector(7 downto 0)); end rx_sm;

architecture rx_sm_arch of rx_sm is signal eop_detect,sync_detect,rxerror_bs:std_logic; signal sync_error,j,k,se0:std_logic; signal rxhldreg:std_logic_vector(7 downto 0);

signal unstuff_enable,shift_done,serial_in:std_logic; signal count : std_logic_vector(3 downto 0); signal rxerror:std_logic; signal temp: std_logic; type st is



(rx_wait,strip_sync,rx_data,rxdata_wait,strip_eop,rx_error_st, abort);signal state_m : st;

beginj<= rxdp and not(rxdm);k<= not(rxdp) and rxdm;se0<= not(rxdp) and not(rxdm);

rxerror_o <= rxerror; --process for RECEIVE STATE MACHINE

process( clk,reset)begin if clk='1' and clk'event then

if reset ='0' then case state_m iswhen rx_wait => if (sync_detect ='1')then

state_m<=strip_sync; else state_m<=rx_wait;

end if;when strip_sync => rxactive<='1';

state_m<=rx_data;when rx_data =>if(rxerror_bs='0')then

if(eop_detect='0')thenrxvalid<='1';

state_m<=rxdata_wait; else state_m<=strip_eop;end if;

else state_m<=rx_error_st;end if;

when rxdata_wait => rxvalid<='0';if(rxerror_bs='0')then

if(eop_detect='0')then if(shift_done='1')then

state_m<=rx_data; else

state_m<=rxdata_wait; end if;

else state_m<=strip_eop;



end if; else

state_m<=rx_error_st; end if;

when strip_eop => rxactive <='0'; rxvalid<='0';

state_m<=rx_wait;

when rx_error_st=> rxerror<='1'; state_m<=abort;

when abort => rxactive <='0'; rxvalid<='0';

rxerror<='0';

state_m<=rx_wait;

when others => state_m<=rx_wait; end case;

elsestate_m<=rx_wait; rxactive<='0';rxvalid<='0';rxerror<='0';

end if; end if; end process;--process for SYNC detection.The encoded form of sync is

detected process(clk) type state is(s0,s1,s2,s3,s4,s5,s6,s7);

variable st :state;begin if clk='1' and clk'event then if reset ='0' then

if(sync_detect='0')then case st is

when s0 => if(k='1')thenst:=s1;

else st:=s0;



sync_error<='1'; sync_detect<='0'; end if;

when s1 => if(j='1')thenst:=s2;

else st:=s0;sync_error<='1';sync_detect<='0';

end if;when s2 => if(k='1')then

st:=s3; else st:=s0;

sync_error<='1';sync_detect<='0';

end if;when s3 => if(j='1')then






end if;when s5 => if(j='1')then


sync_error<='1';sync_detect<='0







st:=s0; sync_detect<='1';

sync_error<='0';else st:=s0;sync_error<='1';

sync_detect<='0'; end if;

when others=> st:=s0; sync_detect<='0';

end case; end if;

else st:=s0; sync_detect<='0';

sync_error<='0'; end if;


--process for eop detection //2 seo's - 1jprocess(clk) type state is(s0,s1,s2); variable st: state;

begin if clk='1' and clk'event then if(reset='0')then

if(state_m=rxdata_wait or state_m=rx_data)then case st is

when s0 => if se0='1' then st:=s1; else st:=s0; eop_detect<='0'; end if;

when s1 => if se0='1' then st:=s2; else st:=s0;

eop_detect<='0';end if;

when s2 => if j ='1' then



st:=s0; eop_detect<='1';

else st:=s0;

eop_detect<='0'; end if;

when others=> st:=s0; eop_detect<='0';

end case; else

eop_detect<='0'; end if; else

st:=s0; eop_detect<='0';

end if; end if;

end process; --process for NRZI DECODING

process(clk,rxdp) begin

if clk='1' and clk'event then if (reset='0')then if(state_m=rxdata_wait)then

if( rxdp='1'and temp ='1')then serial_in<='0'; temp<=rxdp; else if(rxdp='0'and temp='1')then serial_in<='1';

temp<=rxdp; else if(rxdp='1'and

temp ='0')then serial_in<='1';

temp<=rxdp; else if(rxdp='0'and temp

='0')thenserial_in<='0';

temp<=rxdp; end if;

end if;



end if; end if;

end if; else

serial_in<='0';temp<='0';

end if; end if;

end process;--process for bit RX ERROR REPORTProcess (clk)

type state is(s0,s1,s2,s3,s4,s5,s6); variable st:state;

begin if clk='1' and clk'event then

if (reset='0') thenif(state_m=rxdata_wait or state_m=rx_data)then case st is

when s0 => rxerror_bs<='0'; unstuff_enable<='0'; if (serial_in ='1')then st:=s1; else st:=s0; end if;

when s1 => rxerror_bs<='0'; unstuff_enable<='0'; if (serial_in ='1')then

st:=s2; else st:=s0; end if;

when s2 => rxerror_bs<='0'; unstuff_enable<='0'; if (serial_in ='1')then st:=s3; else st:=s0; end if;

when s3 => rxerror_bs<='0'; unstuff_enable<='0';



if (serial_in ='1')then st:=s4;

else st:=s0;

end if;when s4 => rxerror_bs<='0';

unstuff_enable<='0'; if (serial_in ='1')then

st:=s5; else

st:=s0; end if;

when s5 => rxerror_bs<='0'; unstuff_enable<='0'; if (serial_in ='1')then

st:=s5; else

st:=s0; end if;

when s6 => if (serial_in ='0')then unstuff_enable<='1'; rxerror_bs<='0'; st:=s0;

else rxerror_bs<='1'; unstuff_enable<='0'; st:=s0;

end if;when others=> st:=s0;

end case; else

rxerror_bs<='0'; end if; else

st:=s0;rxerror_bs<='0';unstuff_enable<='0';

end if; end if;--process



end process;--process for RX REGISTER loading

process(clk)begin

if clk='1' and clk'event thenif(reset='0') then if(state_m=rxdata_wait ) then

if(unstuff_enable='0')then rxhldreg(7 downto 0)<= rxhldreg(6 downto 0) &

serial_in; else

rxhldreg(7 downto 0)<= rxhldreg(7 downto 0);

end if; end if; if(shift_done='1')then

data_out<= rxhldreg; end if;

else rxhldreg(7 downto 0)<= "00000000";

end if; end if;

end process;--process for COUNT process(clk) begin if clk='1' and clk'event then

if(reset='0') then if(state_m=rxdata_wait)then

if(count <= "0111")then shift_done<='0';

count<= count+"0001";elseshift_done<='1';

count<="0000"; end if;



end if; else shift_done<='0';

count<="0000"; end if;

end if;end process;

end rx_sm_arch;

4.5 Test Bench for Receiver Module

library Ieee;use Ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity rx_sm_tb isend rx_sm_tb;architecture rx_sm_arch_tb of rx_sm_tb is

signal rxdp_i,rxdm_i,rxd_i: std_logic;signal reset_i:std_logic:='1';signal rxvalid_o,rxactive_o,rxerror_o:

std_logic;signal clk_i : std_logic:='0';

signal data_out:std_logic_vector(7 downto 0);signal cnt:std_logic_vector(7 downto 0);signal count:std_logic_vector(3 downto 0);

signal data_count:std_logic_vector(3 downto 0);signal eop_count:std_logic_vector(1 downto 0);

signal data_in:std_logic_vector(7 downto 0);signal eop_start:std_logic;

component rx_sm port( reset,rxdp,rxdm:in std_logic;

rxvalid,rxactive,rxerror_o:out std_logic; clk : in std_logic;

data_out : out std_logic_vector(7 downto 0));end component;



begin instance: rx_sm

port map( reset=>reset_i, rxdp=>rxdp_i, rxdm=>rxdm_i,

rxvalid=>rxvalid_o, rxactive=>rxactive_o, rxerror_o=>rxerror_o, clk=>clk_i, data_out=>data_out);

clk_i<= not clk_i after 50 ns;reset_i<= '0' after 200 ns;rxdp_i<=rxdp_i;

rxdm_i<=not(rxdp_i) when data_count <=”1010”and eop_start=’0’ else

rxdp_i;process(clk_i)beginif clk_i='1' and clk_i'event then if(reset_i='1')then

eop_start<=’0’;cnt<="01010100"; count<="0000" ;data_in<="10110101";data_count<="0000";eop_count<="00";

else if(count<="0111")then rxd_i<=cnt(7);

cnt<= cnt(6 downto 0)&'0'; count<= count+"0001";

else if(data_count<="1001")then count<="0000"; data_in<= data_in+"00000001"; cnt<=data_in;

data_count<=data_count+"0001"; else if(eop_count<="01")then

eop_start<=’1’; rxdp_i<='0';

eop_count<=eop_count+"01"; data_count=”1011";



else rxdp_i<='1'; eop_start<=’0’; data_count=”0000"; end if;

end if;

end if; end if;

end if;end process;

end rx_sm_arch_tb ;

4.6 Simulation Results for Receiver Module

Figure 4.14: SYNC detection and NRZI decoding



The figure 4.14 shows that when reset_i is low and the SYNC pattern

“01010100” is detected on the serial bus, rxactive_i is asserted and the data

“00101100” received on rxdp_i is decoded because the receiver is in

normal mode (i.e., opmode is “00”). The data is sent on to the data_out bus

and the receiver asserts rxvalid_o signal.

Figure 4.15: Receiver at opmode “10”.

The figure 4.15 shows that when reset_i is low and rxactive_i is high

and opmode is “10”, NRZI decoding is disabled and the data received on the

bus is sent on to the data_out bus as it is. The receiver asserts the rxvalid_o

signal.



Figure 4.16: EOP detection

The figure 4.16 shows that when reset _i is low and rxactive_i is

high, EOP pattern (two SEOs and one J state ) is detected on the serial bus.

Whenever the EOP pattern is detected on the bus, the receiver enters into

Strip EOP State where rxactive_o and rxvalid_i signals are de asserted. At

the raising edge of the next clock the receiver enters into RX wait state

where it is waiting for next SYNC pattern on the serial bus.

Figure 4.17: Receive error reporting

The figure 4.17 shows that when reset_i is low and rxactive_i is high

and if a zero is not detected after six consecutive one’s are detected on the

serial bus, the receiver asserts the rxerror_o signal. Consequently rxerror_o

goes low and rxvalid_o is also low. The receiver enters into RX wait state.

4.7 Source code for Transceiver (UTMI) library ieee;



use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity utmi_top isport(txvalid,xcvr,suspendM,term_select,reset : in std_logic;

rxvalid,rxactive,rxerror : out std_logic;linestate : out std_logic_vector(0 to 1);clk,dp,dm : inout std_logic;

data_bustx,data_busrx : inout std_logic_vector(0 to 7));end utmi_top;

architecture utmi_top_arch of utmi_top is component tx_sm

port( reset,txvalid:in std_logic; clk : in std_logic;

txready,txdp,txdm: out std_logic;dataln: in std_logic_vector(7 downto 0));

end component; component rx_sm

port(reset,rxdp,rxdm:in std_logic; rxvalid,rxactive,rxerror_o:out std_logic;

clk : in std_logic; data_out: out std_logic_vector(7 downto 0));

end component; signal fs_clk,hs_clk:std_logic;

begininstance1:tx_sm port map(reset=>reset,

txvalid=>txvalid,txdp=>dp,

txdm=>dm, clk=>clk,

dataln=>data_bustx);instance2:rx_sm port map(reset=>reset,

rxvalid=>rxvalid,rxactive=>rxactive,

rxerror_o=>rxerror,clk=>clk,

rxdp=>dp,

rxdm=>dm,



data_out=>data_busrx); clk<= fs_clk when xcvr='1'else hs_clk;

process(clk) begin if clk='1' and clk'event then if reset='0' thenif suspendM='1' then

linestate(1)<= dp;linestate(0)<= dm;

end if; end if;


end utmi_top_arch;

4.8 Test Bench for Transceiver (UTMI)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity utmi_top_tb is end utmi_top_tb; architecture utmi_arch_tb of utmi_top_tb is

component utmi_top port(txvalid,xcvr,suspendM,term_select,reset : in std_logic;

rxvalid,rxactive,rxerror : out std_logic; linestate : out std_logic_vector(0 to 1);

clk,dp,dm : inout std_logic;data_bustx,data_busrx : inout std_logic_vector(0 to 7));

end component;signal suspendM_i,term_select_i :std_logic;signal rxvalid_i,rxactive_i,rxerror_i : std_logic;signal linestate_i : std_logic_vector(0 to 1);signal clk_i,dp_i,dm_i : std_logic;signal reset_i:std_logic:='1';signal txvalid_i:std_logic:='0';signal data_bus_i : std_logic_vector(0 to 7);signal fs_clk:std_logic:='0';



signal hs_clk:std_logic:='1';signal xcvr_i:std_logic:= '1';signal count:std_logic_vector(0 to 3):="0000";

beginreset_i<='0' after 100 ns;xcvr_i<= '0' after 10 us;fs_clk<= not fs_clk after 84 ns;hs_clk<=not hs_clk after 2 ns;clk_i<= fs_clk when xcvr_i='1' else hs_clk;

term_select_i<='0' after 9 us when xcvr_i='0' else '1' after 9 us;

suspendM_i<='1' when term_select_i='0' else'0' ;

instance :utmi_top port map(txvalid=>txvalid_i,xcvr=>xcvr_i,

suspendM=>suspendM_i,term_select=>term_select_i,reset=>reset_i,rxvalid=>rxvalid_i,rxactive=>rxactive_i,rxerror=>rxerror_i,linestate=>linestate_i,clk=>clk_i,dp=>dp_i,dm =>dm_i,data_bustx=>data_bus_i);

process(clk_i)begin if clk_i='1' and clk_i'event then if reset_i='0'then

if(count<="1000")thentxvalid_i<='1' ;data_bus_i<="00000000";data_bus_i<=data_bus_i+"00000001";count<= count+"0001";elsetxvalid_i<='0' ;data_bus_i<="UUUUUUUU";end if;



end if;end if;end process;

end utmi_arch_tb;

4.9 Simulation Results for Transceiver (UTMI)

Figure 4.18: Full Speed Transceiver operation.



The figure 4.18 shows that when reset is low and xcvr signal is

high(i.e, full speed operation) the clock duration is 84 ns i.e., the fs_clk

signal is assigned to the clk signal. When txvalid is asserted by the SIE,

encoded SYNC pattern “01010100” is transmitted on to the serial bus (i.e,

DP, DM lines) when the receiver detects the SYNC pattern, it asserts RX

active signal. After SYNC has been transmitted, the data “00000000” is

transmitted on to the bus after NRZI encoding. After the data “00000000”

has been transmitted, the transmitter asserts TX ready signal. When the

encoded data is received on the serial bus, the receiver decodes the data

asserts rxvalid signal and the data on the data_bustx is sent onto the

data_busrx. The receiver is in normal mode (i.e, the opmode signalis “00”).

Figure 4.19: Transceiver suspension



The figure 4.19 shows that when reset is low and suspend M goes low, TX

valid signal is de asserts SIE. The EOP pattern is transmitted on to the serial

bus, whenever receiver receives EOP pattern rxactive signal goes low and

ravalid goes low whatever the data present on the data_busrx is remained as

it is until next SYNC pattern is detected.

Figure 4.20: High Speed Transceiver operation.

The figure 4.20 shows that when reset is low and xcvr signal goes low

(i.e, high speed operation) the clock duration is 2ns i.e, the hs_clk signal is

assigned to the clk signal and the data on the data_bustx is sent on the

data_busrx through DP, DM lines. All the operations are same as full speed

operation but these operations on done according to the high speed clock.



5.CONCLUSIONS AND FUTURE SCOPE

5.1 Conclusions

The individual modules of UTMI have been designed, verified

functionally using VHDL simulator.

The UTMI Transmitter is capable of converting parallel data into

serial bits, performing bit stuffing and NRZI encoding.

The UTMI Receiver is capable of performing NRZI decoding

bitunstuffing and converting serial bits into parallel data. The functional

simulation has been successfully carried out. The design has been

synthesized using FPGA technology from Xilinx. This design is targeted to

the device family→spartan2, device→xc2s30, package→cs144 and speed

grade→ -5.Thedevice belongs to the

Vertex-E group of FPGAs from Xilinx.

5.2 Future Scope

The UTMI has been implemented is 8-bit one, it can also be extended

to 16- bit UTMI.

The UTMI can be designed to generate special packets such as

preamble, Split and Ping .



It can also be designed to generate CRCs for control and data packets.

If an SIE and Device specific logic are designed, the combination of

UTMI, SIE and Device specific logic can be used as controller of a USB

device.

6.APPLICATIONS:

The UTMI has been developed into a common code (Generalized USB

Transceiver) which can be used for developing the complete USB device

stack.

Some of the Low speed and High speed USB devices, which are presently in

the market, are:

1. Optical Mouse

2. Key Board

3. Printer

4. Scanner

5. Joy Stick

6. Memory Stick

7. Flash Memory

8. Mobiles

9. Video cameras.



REFERENCE

Reference books:

A VHDL primer J.Bhaskar

VHDL With Example Douglas .L .Perry

Digital Design Morris Mano

Data and Computer Communications William Stallings

Computer Networks Andrew S.Tannenbaum

Reference websites:

www.usb.org

www.opencore.org


http://www.opencore.org/

http://www.usb.org/


www.digitalcoredesign.org

www.deeps.org


http://www.deeps.org/

http://www.digitalcoredesign.org/

usb implementation using utmi macrocell

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