October 11, 20001. 2 USB 2.0 Transceiver Macrocell Steve McGowan - Intel Corporation Clarence Lewis...

October 11, 2000 1

October 11, 2000 2

USB 2.0 Transceiver Macrocell

USB 2.0 Transceiver Macrocell

Steve McGowan - Intel CorporationSteve McGowan - Intel Corporation

Clarence Lewis - Texas InstrumentsClarence Lewis - Texas Instruments

Haoran Duan - Agilent TechnologiesHaoran Duan - Agilent Technologies

October 11, 2000 3

USB 2.0 Transceiver Macrocell InterfaceUSB 2.0 Transceiver Macrocell Interface

OverviewOverview

October 11, 2000 4

Macrocell RequirementsMacrocell Requirements

Enable PeripheralsEnable Peripherals Does not address hubs and hostsDoes not address hubs and hosts

– No downstream port supportNo downstream port support Disconnect DetectionDisconnect Detection 40 bit EOP40 bit EOP

– No repeater supportNo repeater support Very implementation dependentVery implementation dependent Requires separate portRequires separate port

October 11, 2000 5

Macrocell RequirementsMacrocell Requirements

Simplify the design process for peripheral Simplify the design process for peripheral vendorsvendors– Consolidate high speed logic in to a discrete moduleConsolidate high speed logic in to a discrete module– Provide a “standard” USB 2.0 hardware interfaceProvide a “standard” USB 2.0 hardware interface

Minimize time to marketMinimize time to market– Isolate process dependent transceiver developmentIsolate process dependent transceiver development

Enable standard library elements from ASIC vendorsEnable standard library elements from ASIC vendors– Peripheral vendors can focus on productPeripheral vendors can focus on product

specific developmentspecific development Easy port of existing USB 1.1 SIE logicEasy port of existing USB 1.1 SIE logic

OverviewOverview

Enable High Volume DevicesEnable High Volume DevicesEnable High Volume DevicesEnable High Volume Devices

October 11, 2000 6

USB Device DevelopmentUSB Device Development

AssumptionsAssumptions– PrototypingPrototyping

FPGA + UTMI Compliant Discrete TransceiverFPGA + UTMI Compliant Discrete Transceiver– ProductionProduction

Low VolumeLow Volume Gate Array + UTMI Compliant Discrete TransceiverGate Array + UTMI Compliant Discrete Transceiver

High VolumeHigh Volume ASIC + integrated UTMI Compliant Transceiver MacrocellASIC + integrated UTMI Compliant Transceiver Macrocell

OverviewOverview

October 11, 2000 7

Device AnatomyDevice Anatomy

USB Transceiver Macrocell (UTM)USB Transceiver Macrocell (UTM) Serial Interface EngineSerial Interface Engine Device Specific LogicDevice Specific Logic

OverviewOverview

ASICASICASICASIC

Serial Interface EngineSerial Interface EngineSerial Interface EngineSerial Interface Engine

DeviceDeviceSpecificSpecific

LogicLogic

DeviceDeviceSpecificSpecific

LogicLogic

Endpoint LogicEndpoint Logic

Endpoint LogicEndpoint Logic

……SIE

Control Logic

SIEControl Logic

USB 2.0USB 2.0Endpoint LogicEndpoint Logic

Device Hardware

Device Hardware

USB 2.0 USB 2.0 TransceiverTransceiver


UTM Interface

UTM Interface

October 11, 2000 8

Serial Interface EngineSerial Interface Engine

SIE Control LogicSIE Control Logic– USB Transaction State MachineUSB Transaction State Machine– PID, Address, and EP match logicPID, Address, and EP match logic– Checks receive completion statusChecks receive completion status– Chains packets into transactionsChains packets into transactions

Endpoint LogicEndpoint Logic– FIFOs and FIFO controlFIFOs and FIFO control


Endpoint Logic

Endpoint Logic

……

SIEControl Logic

Endpoint Logic

ControlControl

Data InData InData InData In

Data OutData OutData OutData Out

To Device To Device Specific Specific

LogicLogic

To TransceiverTo Transceiver

OverviewOverview

October 11, 2000 9

Transceiver MacrocellTransceiver Macrocell

Converts USB signaling into a parallel interfaceConverts USB signaling into a parallel interface– USB 2.0 compliant serial interfaceUSB 2.0 compliant serial interface– Multiple Parallel Data Interface OptionsMultiple Parallel Data Interface Options– Multiple Speed OptionsMultiple Speed Options

HS/FS, FS Only, LS OnlyHS/FS, FS Only, LS Only

USB 2.0USB 2.0USB 2.0 USB 2.0 TransceiverTransceiver


ControlControl

Data InData In

Data OutData Out

To SIETo SIE To BusTo Bus

OverviewOverview

October 11, 2000 10

Macrocell FunctionsMacrocell Functions

HS and FS signaling and terminationHS and FS signaling and termination HS receiver squelchHS receiver squelch USB clock recoveryUSB clock recovery Bit stuffingBit stuffing NRZI encodingNRZI encoding Serializing and deserializingSerializing and deserializing Data-rate toleranceData-rate tolerance Data bufferingData buffering Single interface for HS/FS, FS or LS operationSingle interface for HS/FS, FS or LS operation

OverviewOverview

October 11, 2000 11

Block DiagramBlock Diagram

ControlControlControlControlControlControl

D-D-

D+D+

DLLDLLDLLDLL

FSFSInterfaceInterface

HSHSInterfaceInterface

Shared LogicShared LogicShared LogicShared Logic

ParallelParallelInterfaceInterfaceParallelParallel

InterfaceInterfaceDLLDLLDLLDLL

muxmux

BitBitUnstufferUnstuffer

BitBitUnstufferUnstuffer DeseralizerDeseralizerDeseralizerDeseralizer RX HoldingRX Holding

RegRegRX HoldingRX Holding

RegReg

BitBitStufferStuffer

BitBitStufferStuffer SeralizerSeralizerSeralizerSeralizer TX HoldingTX Holding

RegRegTX HoldingTX Holding

RegReg

ToToSIESIE

DataData

ToToUSBUSB

OverviewOverview

October 11, 2000 12

Macrocell FunctionsMacrocell FunctionsInterface FeaturesInterface Features

Packet Engine Packet Engine – Automatically handles SYNC Pattern and EOPAutomatically handles SYNC Pattern and EOP

Flow ControlFlow Control– Compensates for Bit Stuffing and Data Rate ToleranceCompensates for Bit Stuffing and Data Rate Tolerance

Complete Primitives for Full Protocol SupportComplete Primitives for Full Protocol Support Speed SwitchingSpeed Switching Clock GenerationClock Generation Power ControlPower Control

October 11, 2000 13

Interface OptionsInterface Options

Integrated MacrocellIntegrated Macrocell– 8-Bit Uni-directional8-Bit Uni-directional– 16-Bit Uni-directional16-Bit Uni-directional

Discrete TransceiverDiscrete Transceiver– 8-Bit Bi-directional8-Bit Bi-directional– 16-Bit Bi-directional / 8-Bit Uni-directional16-Bit Bi-directional / 8-Bit Uni-directional


October 11, 2000 14

8-Bit Uni-Directional8-Bit Uni-DirectionalInterface OptionsInterface Options

DataIn(0-7)DataIn(0-7)

TXValidTXValid

ResetResetSusepsndMSusepsndM

XcvrSelectXcvrSelectTermSelectTermSelect

OpMode(0-1)OpMode(0-1)

DataOut(0-7)DataOut(0-7)

TXReadyTXReady

RXActiveRXActiveRXValidRXValid

CLKCLKRXErrorRXError

DPDPDMDM

LineState(0-1)LineState(0-1)

8-Bit Interface8-Bit Interface

October 11, 2000 15

16-Bit Uni-Directional16-Bit Uni-DirectionalInterface OptionsInterface Options


TXValidTXValidH

ResetSusepsndM

XcvrSelectTermSelect

OpMode(0-1)

DataOut(8-15)DataOut(8-15)DataOut(0-7)DataOut(0-7)

TXReadyTXReady

RXActiveRXActive

RXValidRXValidRXValidHRXValidH

CLKCLKRXErrorRXError

DPDPDMDM

LineState(0-1)LineState(0-1)

16-Bit Interface16-Bit Interface

October 11, 2000 16

8-Bit Bi-Directional8-Bit Bi-Directional

TXValid Determines data directionTXValid Determines data directionInterface OptionsInterface Options

DataOut(0-7)DataOut(0-7)

TXValidTXValid

Data(0-7)Data(0-7)


8-Bit Bi-Directional Interface8-Bit Bi-Directional Interface

October 11, 2000 17

16-Bit Bi-Directional16-Bit Bi-DirectionalInterface OptionsInterface Options

DataBus16_8DataBus16_8

DataOut(8-15)DataOut(8-15)DataOut(0-7)DataOut(0-7)

TXValidTXValid

RXValidHRXValidH

Data(8-15)Data(8-15)Data(0-7)Data(0-7)

ValidHValidH

DataIn(8-15)DataIn(8-15)DataIn(0-7)DataIn(0-7)

TXReadyTXReady

TXValidHTXValidH

16-Bit Bi-Directional Interface16-Bit Bi-Directional Interface

ValidH provides multiplexed high-byte valid flagValidH provides multiplexed high-byte valid flag

October 11, 2000 18

Protocol Primitive SupportProtocol Primitive Support

Resume AssertionResume Assertion Resume DetectionResume Detection Suspend DetectionSuspend Detection Reset DetectionReset Detection HS Detection HandshakeHS Detection Handshake


October 11, 2000 19

Clock GenerationClock Generation

Macrocell supplies clocks to the SIEMacrocell supplies clocks to the SIE Frequency depends on implementationFrequency depends on implementation

– HS/FSHS/FS 60 MHz 8-bit uni-directional60 MHz 8-bit uni-directional 30 MHz 16-bit uni- or bi-directional30 MHz 16-bit uni- or bi-directional

– FS OnlyFS Only 48 MHz 8-bit uni-directional48 MHz 8-bit uni-directional

– LS OnlyLS Only 6 MHz 8-bit uni-directional6 MHz 8-bit uni-directional


October 11, 2000 20

Power ControlPower Control

SuspendM signalSuspendM signal– Shuts down clocksShuts down clocks– Maintains terminationsMaintains terminations

Vendor determined Drive Current ControlVendor determined Drive Current Control– Enabled during transmitsEnabled during transmits– Enabled by receivesEnabled by receives– Always onAlways on

DPDP

DMDM

HS_Current_Source_EnableHS_Current_Source_Enable

HS_Drive_EnableHS_Drive_Enable

HS_Data_Driver_InputHS_Data_Driver_Input

High-speed Current DriverHigh-speed Current Driver


October 11, 2000 21

USB 2.0 Transceiver Macrocell InterfaceUSB 2.0 Transceiver Macrocell Interface

TestingTesting

October 11, 2000 22

TestingTesting

UTMI Test Connector SpecificationUTMI Test Connector Specification Test Environment - 3 board setTest Environment - 3 board set

– Off the shelf i960 eval boardOff the shelf i960 eval board– Custom SIE cardCustom SIE card

FPGA, DPRAM, and Test PointsFPGA, DPRAM, and Test Points

– Daughter Card with UTMI TransceiverDaughter Card with UTMI Transceiver FunctionalityFunctionality

– Packet BlasterPacket Blaster Single Packet operationsSingle Packet operations

– Device EmulatorDevice Emulator Transaction level operationsTransaction level operations

October 11, 2000 23

UTMI Test Connector SpecificationUTMI Test Connector Specification

UTMI Test ConnectorUTMI Test Connector– 100 Pins100 Pins

Electrical interfaceElectrical interface– TimingTiming– LevelsLevels

Mechanical designMechanical design– PCB layoutPCB layout

October 11, 2000 24

Board SetBoard Set

Processor CardProcessor Card– EVAL80960VH Evaluation Platform BoardEVAL80960VH Evaluation Platform Board– RAM, ROM, FLASH, Serial PortRAM, ROM, FLASH, Serial Port

FPGA CardFPGA Card– Dual Port RAM - 64KBDual Port RAM - 64KB– FPGA - QuicklogicFPGA - Quicklogic– Test PointsTest Points

Transceiver Daughter CardTransceiver Daughter Card– Discrete UTMI compliant transceiverDiscrete UTMI compliant transceiver– Custom circuitryCustom circuitry

TestingTesting

October 11, 2000 25

Block DiagramBlock Diagram

USB 2.0 TransceiverUSB 2.0 TransceiverUSB 2.0 TransceiverUSB 2.0 Transceiver


Transceiver / Transceiver / MacrocellMacrocell

Transceiver / Transceiver / MacrocellMacrocell

i960i960i960i960

USB 2.0USB 2.0USB 2.0USB 2.0

DPRAMDPRAMDPRAMDPRAM

I960I960Local BusLocal Bus

I960I960Local BusLocal Bus

UTM UTM InterfaceInterface

UTM UTM InterfaceInterface

UARTUARTUARTUARTFlashFlashFlashFlashDRAMDRAMDRAMDRAM

RS-232RS-232RS-232RS-232

Device Specific LogicDevice Specific LogicDevice Specific LogicDevice Specific Logic

FPGAFPGAFPGAFPGA

I960I960CardCardI960I960CardCard

FPGAFPGACardCardFPGAFPGACardCard

Transceiver Transceiver DaughterDaughter

CardCard

Transceiver Transceiver DaughterDaughter

CardCard

TestingTesting

October 11, 2000 26

MechanicalsMechanicals

To USB To USB DeviceDevice

Test Chip Daughter Test Chip Daughter CardCard

i960 Cardi960 Card

FPGA FPGA CardCard

PCI SlotsPCI Slots(Power)(Power)

RS-232 ConnectorRS-232 Connector

CPUCPUCPUCPU

FPGAFPGAFPGAFPGA

DPDPRAMRAMDPDP

RAMRAM

XcvrXcvrXcvrXcvr

100 Pin100 PinUTMI ConnectorUTMI Connector

RAMRAMRAMRAM

TestingTesting

October 11, 2000 27

Pinout FeaturesPinout Features

Vendor Status and Vendor Control supportVendor Status and Vendor Control support Multiple Datapath Options SupportedMultiple Datapath Options Supported

– 8-Bit Bi-Directional8-Bit Bi-Directional– 8-Bit Uni-Directional8-Bit Uni-Directional– 16-Bit Bi-Directional/8-Bit Uni-Directional16-Bit Bi-Directional/8-Bit Uni-Directional

Vendor IDVendor ID 13 General Purpose I/O pins13 General Purpose I/O pins Vbus ControlVbus Control

October 11, 2000 28

PinoutPinout

11 GPIO0GPIO0 2626 GPIO1GPIO1 5151 GNDGND 7676 GNDGND22 GNDGND 2727 GNDGND 5252 System ClockSystem Clock 7777 ValidHValidH33 GPIO2GPIO2 2828 VBUS_outVBUS_out 5353 GNDGND 7878 DataBus16_8DataBus16_844 GNDGND 2929 GPIO3GPIO3 5454 GNDGND 7979 VControl1VControl155 GPIO4GPIO4 3030 VendorID_0VendorID_0 5555 VControl0VControl0 8080 GNDGND66 GPIO5GPIO5 3131 Data15Data15 5656 GPIO6GPIO6 8181 VDDVDD77 GPIO7GPIO7 3232 GNDGND 5757 VDDVDD 8282 Data14Data1488 VDDVDD 3333 Data13Data13 5858 GPIO8GPIO8 8383 Data12Data1299 GNDGND 3434 Data11Data11 5959 VControl2VControl2 8484 GNDGND1010 VControl3VControl3 3535 GNDGND 6060 TxValidTxValid 8585 Data10Data101111 GPIO9GPIO9 3636 Data9Data9 6161 GPIO10GPIO10 8686 Data8Data81212 GPIO11GPIO11 3737 Data7Data7 6262 GNDGND 8787 VDDVDD1313 GNDGND 3838 VDDVDD 6363 GPIO12GPIO12 8888 Data6Data61414 VControlLoadMVControlLoadM 3939 GNDGND 6464 IFType0IFType0 8989 IFType1IFType11515 VStatus4VStatus4 4040 Force_RxErrForce_RxErr 6565 GNDGND 9090 CLKCLK1616 VDDVDD 4141 Data5Data5 6666 RxActiveRxActive 9191 Data4Data41717 ResetReset 4242 Data3Data3 6767 OpMode0OpMode0 9292 GNDGND1818 OpMode1OpMode1 4343 GNDGND 6868 GNDGND 9393 Data2Data21919 XcvrSelectXcvrSelect 4444 Data1Data1 6969 VDDVDD 9494 Data0Data02020 TermSelectTermSelect 4545 VStatus0VStatus0 7070 VStatus1VStatus1 9595 GNDGND2121 GNDGND 4646 GNDGND 7171 VStatus2VStatus2 9696 VStatus3VStatus32222 SuspendMSuspendM 4747 VBUS_inVBUS_in 7272 RxValidRxValid 9797 VStatus5VStatus52323 LineState0LineState0 4848 VStatus6VStatus6 7373 GNDGND 9898 VStatus7VStatus72424 GNDGND 4949 VDDVDD 7474 RxErrorRxError 9999 VendorID_1VendorID_12525 LineState1LineState1 5050 Vdbus16_8Vdbus16_8 7575 TxReadyTxReady 100100 GNDGND

TestingTesting

October 11, 2000 29

Next StepsNext Steps

Get the USB 2.0 Transceiver Macrocell Interface Get the USB 2.0 Transceiver Macrocell Interface (UTMI) Specification(UTMI) Specification– http://developer.intel.com/technology/usb/http://developer.intel.com/technology/usb/– No RoyaltyNo Royalty

Design to the UTMI SpecificationDesign to the UTMI Specification Get the UTMI Test Connector SpecificationGet the UTMI Test Connector Specification

– http://developer.intel.com/technology/usb/http://developer.intel.com/technology/usb/ Get your ASIC vendors to provide a UTMI Get your ASIC vendors to provide a UTMI

Compliant MacrocellsCompliant Macrocells

October 11, 20001. 2 USB 2.0 Transceiver Macrocell Steve McGowan - Intel Corporation Clarence Lewis...

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Transcript of October 11, 20001. 2 USB 2.0 Transceiver Macrocell Steve McGowan - Intel Corporation Clarence Lewis...