Upgrade of the CSC Endcap

Muon Port Card Mikhail Matveev

Rice University

1 November 2011

November 1, 2011 CSC Trigger Upgrade Meeting 2

CSC EMU Electronics

November 1, 2011 CSC Trigger Upgrade Meeting 3

MPC Upgrade Requirements

Be able to deliver all 18 trigger primitives from the EMU

peripheral crate to the upgraded Sector Processor (currently, only 3 LCTs out of 18 are delivered)

Preserve sorting capabilities of the Muon Port Card Preserve 3 “old” 1.6Gbps optical links to the present CSC

Track Finder

November 1, 2011 CSC Trigger Upgrade Meeting 4

Upgrade Path

Use existing Muon Port Card main board - TMB interface remains unchanged (2 LCTs per TMB @ 80MHz) - 3 “old” optical links are still available Replace only the FPGA mezzanine - Use modest size Virtex-5 XC5VLC110 for prototyping - Place the FPGA, 12 Texas Instruments TLK2501 serializers and one SNAP12 parallel optical transmitter on a new mezzanine - Use CERN designed QPLL2 ASIC to obtain low-jitter 120MHz clock for the TLK2501 serializers

November 1, 2011 CSC Trigger Upgrade Meeting 5

Virtex-5 Mezzanine

Version 1, August 2010 Version 2, May 2011

■ Two PROM Options: ● XCF32P ● XCF128X■ Two Voltage Regulators for the FPGA Core Voltage 1.0V ● PQ035ZN1HZPH (1.5A) ● LP38853S (3.0A)■ Discrete logic register to mask out selected TMBs

November 1, 2011 CSC Trigger Upgrade Meeting 6

Old And New Mezzanines Installed

November 1, 2011 CSC Trigger Upgrade Meeting 7

Status as of November 2011

■ Three old (ver.1) and three new (ver.2) mezzanines are installed on a spare production MPC boards■ Have one Sector Processor SP10 Receiver board at Rice (partially assembled, only one front mezzanine receiver installed)■ All mezzanines have been tested with the SP10 Receiver Prototype at 120Mhz (2.4Gbps) - PRBS test from SER to DESER, 100 m fiber, all boards tested for ~90 minutes (BER < 10-13 per ch) - Random data patterns from FPGA to FPGA■ Tested with 9 TMBs in the EMU peripheral crate

November 1, 2011 CSC Trigger Upgrade Meeting 8

Latency Measurements

■ Present system at CMS: 580 ns - TLK2501 Transmitter (80MHz) ~23 ns - 100 m optical MMF fiber ~500 ns - TLK2501 Receiver (80MHz) ~57 ns

■ New system (prototypes): 616 ns - TLK2501 Transmitter (120MHz) ~15 ns - 100 m optical MMF fiber ~500 ns - Virtex-6 GTX receiver (120MHz) ~101 ns (without Rx FIFO buffer)

November 1, 2011 CSC Trigger Upgrade Meeting 9

Irradiation Test of Virtex-5 FPGA

■ Conducted in July’11 at the TAMU cyclotron■ 5 to 15 seconds between SEU, more frequent with higher flux■ Average dose to get an error is ~12 rad. With the average flux of ~107 protons/cm2/s, the cross section of SEU is ~10-8 cm2 per device. ■ Assuming 10-year fluence of ~1011 neutrons per cm2 [1] at full LHC design luminosity, the worst case SEU rate would be 10-8 cm2 x 1011 neutrons/cm2 / 108 sec = 10-5, or 1 SEU in ~ 3 hours per MPC [1] http://cmsdoc.cern.ch/~huu/tut1.pdf

November 1, 2011 CSC Trigger Upgrade Meeting 10

Future Developments in 2012

■ Replacement of the XC5VLX110-FF1153 FPGA and 12 TLK2501 serializers with the Spartan-6 XC6LX150T-3FGG900C FPGA with embedded GTP transceivers is attractive: - significant cost saving - available from stock - all I/Os are 3.3V compatible - more compact board, simpler PCB design - increase frequency from 120MHz (2.4Gbps) to 160MHz (3.2Gbps), use 9 (or less) links out of 12 - low-jitter 160MHz clock is available directly from the QPLL - further reduce link latency at 160MHz - ~50% lower power consumption for the Vcore comparing to Virtex-5 and Virtex-6 (preliminary estimate, based on Xilinx XPower Analyzer) - Spartan-6 GTP and Virtex-6 GTX cores are compatible

November 1, 2011 CSC Trigger Upgrade Meeting 11

Cost Estimate

Virtex-5 Mezzanine Spartan-6 Mezzanine

FPGA $1610 $280

12 TLK2501 Serializers $170 None

SNAP12 Transmitter $400 $400

Other components $300 $300

Fabrication and Assembly $400 $400

Total $2,880 $1,380

● Optical cable with 12 fibers, 100 m - $429● Will need 80 mezzanines and 60 optical cables

November 1, 2011 CSC Trigger Upgrade Meeting 12

Plans

■ Continue testing of the existing MPC and SP10 prototypes - test stands at Rice and UF for firmware and hardware developments - have 6 Muon Port Cards with new mezzanines - move prototypes to bld.904 in the 1st half of 2012 and integrate into cosmic stand■ Proceed with the Spartan-6 design - 1st prototype of the MPC mezzanine by April 2012■ Production and Installation - production prototype by end of 2012 - integration tests with the SP10 board in the 1st half of 2013 - fabrication and tests of 80 mezzanine boards – 2nd half of 2013 - equip all MPC boards with new mezzanines, re-work front panels, re-test boards – end 2013 - early 2014 - install at CMS – spring 2014