Uart Spec Liem1

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Arrive Technologies Inc.

Design Specification

UART IP

< AT_asic_train_spe.odt>

Revision: [1.0] on < 04/03/12 >

This controlled document is the proprietary of Arrive Technologies Inc.

Any duplication, reproduction, or transmission to unauthorized parties is prohibited.


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1.0 < 04 March 2012 >


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Table of Contents

1. Introduction..................................................................................................................................iv

2. Feature..........................................................................................................................................iv3. Design Block Diagram.................................................................................................................iv

4. UART Subsystem.........................................................................................................................vi

4.1. Baud Rate Generator............................................................................................................................ vi

4.2. FIFO..................................................................................................................................................... vii

4.3. Transmitter........................................................................................................................................... viii

4.4. Receiver................................................................................................................................................ x

4.5. Control logic:........................................................................................................................................ xiii

4.6. Interface synchronous:......................................................................................................................... xiv

5. Functional timings.......................................................................................................................xv

5.1. Baud gen timing:................................................................................................................................... xv

5.2. FiFo timing:.......................................................................................................................................... xvi

5.3. Transmitter timing:............................................................................................................................... xvi

5.4. Receiver timing:.................................................................................................................................. xvii

5.5. Read/write operations:....................................................................................................................... xviii

6. Register Description....................................................................................................................20

6.1. Register data hold FiFo transmitter:( wq1)...........................................................................................20

6.2. Register control FiFo: (wq2).................................................................................................................20

6.3. Register tx, rx report: (wq3)..................................................................................................................20

6.4. Register control transmitter,receiver and baud generator: (wq4).........................................................21

6.5. Register data hold FiFo receiver: (wq5)...............................................................................................22

7. Configuration Sequence..............................................................................................................22

7.1. [Particular set up sequence].................................................................................................................22

7.2. [Particular set up sequence].................................................................................................................22

8. [ASIC/FPGA] Resource................................................................................................................22

8.1. Design Estimation................................................................................................................................ 22

8.2. Synthesis Report.................................................................................................................................. 23

9. Power Consumption....................................................................................................................23

10. Standard References.................................................................................................................23

11. Appendix.....................................................................................................................................23

Table of Figures

Table of Tables

Table 1 : I/O function of the UART................................................................................................3

Table 2 : [a specific register description]....................................................................................4


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1. Introduction

The UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the reception

and transmission of information, in a serial and asynchronous way.

The UART allows the communication between a computer and several kinds of devices (printer,modem, etc), interconnected via an RS-232 cable.

Figure 1 : UART connection

2. Feature

Parity error check

Framing error check

Data bus widths is 8

4-deep First-In-First-Out (FIFO) transmit data buffer, width 8.

4-deep First-In-First-Out (FIFO) receive data buffer, width 10.

Programmable:

Baud rate generator : 2400, 4800, 9600,19200

1, 1.5 , 2 or 2.5 stop bits

7 bit data + no parity

7 bit data + parity even

7 bit data + parity odd

8 bit data + no parity

3. Design Block Diagram

A basic overview of the UART is shown below. The UART consists of six independent modules.

CPU UartUart

tx_data

rxd


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FIFO : The FIFO buffer provides more buffering space and further reduces the chance of dataoverrun. We can adjust the desired number of words in FIFO to accommodate the processingneed of the main system.

BAUD GEN: The baud rate generator generates a sampling signal whose frequency is excactly16 times the UART's designated baud rate.

TRANSMITTER : convert parallel to serial data

RECEIVER: convert serial to parallel data

CONTROL LOGIC: has functionality gets feedback information from FIFO, transmitter andreceiver and then control their activity.

INTERFACE: communicate between CPU and UART core. CPU can configure transmitter,receiver and baud generator, read/write data, read status, ect

Figure 2 : UART block diagram

Pin Name Size Type Active Decription

clk 1 I Raising

edge

System clock. Every register moves on its positive edge.

CPUInterface

syn

clk

rst_

cs

rdwr

add[2:0]

data_in[7:0]

data_out[7:0]

fifo_tx tx

fifo_rx rx

baud gencontrollogic

tx_data

rxd

UART core


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Pin Name Size Type Active Decription

rst_ 1 I Low System reset. Every register resets asynchronouslywhen it is low level.

cs 1 I High Signal to select UART module

wr 1 I High Used for writing data to the register file

rd 1 I High Used for reading out data from the register file

data_in 8 I - Input data to be written in a register .

data_out 8 O - Output data read from a register.

tx_data 1 O - Transmitter serial output, tx_data will be high levelduring reset or when no data to transmit.

rxd 1 O - Receiver serial input, rxd should be held high level whenno data to receive.

add 3 I - Bus address to access address's register file

TABLE 1 : I/O Functions of the UART

4. UART Subsystem

4.1. Baud Rate Generator

sample1

Baud_gen

rst_

bd_sel [1:0]sample

Reg

+1 = 163

rst_1rst_

00:1920001:960010:480011:2400


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Figure 3: Baud generator block diagram

4.2. FIFO

FiFo

rst_

rd_en

wr_en

data_in

full

data_out

empty

ff_len

bd_sel [1:0]

sample

counter2sample1

rst_

sample2

sample3

sample4

Mux

0

1

3

2counter4

counter8

reg

rst_

rst_

rst_

sample1_1


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Figure 4: FiFo block diagram

4.3. Transmitter

Initial data will be incorporated into the frame. Each parity sel and stop sel has a different format.Then this data will be introduced into the shift register 's input. The remaining task is controlwhen this data is translated.

We will use two counter for sample count and bit count. Depending on parity and stop sel wemust count the number of samples and bits corresponding. From bit counter & sample counterwe can control shift enable signal of shift register.

When the bit counter reaches 9 or 10, flag tx_finish is active high and flag tx_busy is active low.

Control read/write

rst_

wr_en

rd_en

Ram2p

rst_

wr_en_ram

rd_en_ram

add_rd

add_wr

data_in

data_out

rd_

pt

wr_pt

status_mem

Compare 0

Compare 4

empty

full

empty

full


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Figure 5: transmitter

Figure 6: Transmitter 's components

Transmitter

rst_

data_in

sample

tx_en

pr_sel [1:0]

st_sel [1:0]

tx_data

tx_finish

tx_busy

Creat frame

rst_

data_in

pr_sel [1:0]

data_in1

Control shift

rst_

sample

pr_sel [1:0]

st_sel [1:0]

tx_enen_shift

tx_busy

en_shift

tx_finish

Reg shift

rst_

en_shift

data_in1 tx_data


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4.4. Receiver

Figure 7: Receiver

Receiver is composed of state machine, de serializer and a support logic. The main goal of the receiver is to detect the

start-bit, then de-serialize te following bit stream, detect stop bit and make the data availble to the host. State machine

will control support logic with control signal as: en_shift for shift_register, load for register, en1 & en2 for sample counter& bit counter .

State machine has 3 state: IDLE,START, RECEIVING. State IDLE receiver will wait a high to low transition of rxd pin willbe treated as the Start bit of a frame. But a signal noise also can creat a high to low transition at rxd pin so to avoidreceiving a incorrect data, Receiver will step to START state.

At START state, receiver will requirements the Start bit to be low at least 50% of the receiving baud rate clock cycle. Sothe internal signal Sample is 16 times the receiving/transmitting baud rate clock frequency, the Start bit needs to be lowat least 8 Sample to be considered as a valid Start bit. When receiver recognizes valid Start bit. State machine will stepto RECEIVING state.

At RECEIVING state, receiver will get serial data and transfer to parallel data and send to receiver's fifo.

Behavior of the receiver 's CU_rx is controlled by state machine is shown below:

Receiver

rst_

rxd

sample

data_out

rx_done

pr_sel [1:0]

st_sel [1:0]

rx_en

err_data

err_fr


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Figure 8: Receiver block diagram

Data shift Load data rx

Count sample

Count bit

CU_rx

reg

reg

rst_

sample

pr_sel

st_sel

rxd

rx_en

cnt_sp

cnt_bit

rst_1

en_1

rst_2

en_2

en_

shift

load

done

err_fr1

rst_

rst_

rx_done

err_fr

checkdata err

err_data

rst_ rst_

data_shift data_out

rxd

_syn

reg

rxd_syn

data_out


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Figure 9: CU_rx state machine

RECEIVINGen_shift = 0 or 1

rst_1 = 0 or 1rst_2 = 0 or 1en1 = 0 or 1en2 = 0 or 1

load = 0done = 0

err_fr = 0

STARTen_shift = 0rst_1 = 0 or 1

rst_2 = 0en1 = 0 or 1

en2 = 0load = 0done = 0err_fr = 0

STOPen_shift = 0

rst_1 = 0 or 1rst_2 = 0 or 1

en1 = 1en2 = 0load = 1done = 1

err_fr = 0 or 1

IDLE

en_shift = 0rst_1 = 0rst_2 = 0en1 = 0en2 = 0load = 0done = 0err_fr = 0

rxd_syn = 0

rxd_syn=1

valid

start

unvalidstart

others

pr_sel=others

&cnt_sp=4'ff

&cnt_bit=8

pr_sel=00

&cnt_sp=4'ff

&cnt_bit=7

others

st_sel=

00&cnt_s

p=8

st_sel=

01&cnt_s

p=16

st_sel=

10&cnt_s

p=24

st_sel=

11&cnt_s

p=32


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4.5. Control logic:

Figure 10: Control logic

Control logic

rst_

trans

txff_empty

tx_finish

rxff_full

err_data

rx_done

err_fr

data_out_rx

tx_busy

tx_start

rd_en_txff

overrun

wr_en_rxff

data_in_rxff


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4.6. Interface synchronous:

Figure 11: CPU interface block diagram

AddressAccess

typeRegisters Functional

000 RW Reg data hold fftx wq1 Provides the data to be transmitted to transmit FIFO

001 RW Reg control fifo wq2 Provides the control signal write/read to transmitter's FIFO

or receiver's FIFO

010 R Reg tx,rx report wq3 Provides serial communication status to the CPU

011 RW Reg control tx, rx wq4 Provides control signal as baud rate, parity, stop bit to tx,rxand baud generator

100 R Reg data hold ffrx wq5 Stores the received data from receiver 's FIFO

101110111

Reserved

TABLE 1 : Register's address

Read/writecontrol

Reg data hold fftx [7:0]

Reg control fifo [7:0]

Reg tx,rx report [7:0]

Reg control tx,rx [7:0]

Blockregister

CPUinterface

clk

rst_

cs

rdwr

add[2:0]

data_in[7:0]

data_out[7:0]

Reg data hold ffrx [7:0]

wq1wq2

wq4

data_in1[7:0]

data_in2[7:0]


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5. Functional timings

5.1. Baud gen timing:

Figure 12: baud gen timing

clk

sample1

clk/(16xbaud rate)

............ ....

sample2

sample3

sample4

01bd_sel 11

sample


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5.2. FiFo timing:

Figure 13: FiFo timing

5.3. Transmitter timing:

clk

rst_

rd_en

wr_en

empty

full

wr_en_ram

wr_pt 0 1 2 3 0

status_mem0 1 2 3 4

rd_en_ram

1 2 3 00rd_pt

data_in 07 08 09 0a 0b

3 2 1 0

data_out 00 08 09 0a 0b


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Figure 14: Transmitter timing

clk

sample ...................

...

..... .... .... ...

..... ...

..... ....

data_in 11001101 new data

16 sample

start bitbit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity bitstop bit

tx_data

.....

.

idle bit

....

tx_finish

tx_en

.....

.

.....

.clk/(16xbaud rate)

idle

rst_

...


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5.4. Receiver timing:

Figure 15: Receiver timing

clk

sample .... .... .... .... .... .... .... .... .... ....

clk/(16xbaud rate)

data_out

1xxxxxxx

unvalid data

data_shift

16 sample

start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity bit stop bitrxd

........

....

01xxxxxx 101xxxxx 1101xxxx 01101xxx 001101xx 1001101x 11001101

11001101

unvalid data

rx_finish

....

....

....

idle

8

sample


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5.5. Read/write operations:

Figure 16: Write operation

Figure 17:Read operations

clk

rst_

cs

wr

add[2:0]

data_in[7:0]

reg a,b ...

unvalid address unvalid addressaddr

unvalid data unvalid datadata write

old data new data

clk

rst_

cs

add[2:0]

data_out[7:0]

reg a,b ...

unvalid address unvalid addressaddr

unvalid data unvalid datadata reg

data reg a,b,c...

rd


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6. Register Description

6.1. Register data hold FiFo transmitter:( wq1)

Address: 0x00

Description: The register data hold FiFo transmitter stores the value data to be transmitted, to be written byCPU.

Bits Name Type Reset Value

7:0 wq1 RW 0x0

[7:0] [wq1] : Data bits 7-0 of the Transmitted Character

6.2. Register control FiFo: (wq2)

Address: 0x001

Description: This register controls the FiFo buffers used by the receiver and the transmitter, read/write thereceive/transmit FiFo.


[7:2] Reserved - -

1 wr_en W 0x0

0 rd_en W 0x0

6.3. Register tx, rx report: (wq3)

Address: 0x010

Description: This register informs the CPU about the status of the transmitter and the receiver. In order to getinformation about a received data, wq3 must be read before reading that received character from wq5.


[7:5] rxff_len R 0x0

4 err_fr R 0x0

3 err_data R 0x0

[2:0] txff_len R 0x0

[7:6] [rxff_len] : Return information to CPU about status of FiFo receiver as full, empty or has a byte datawhich has just been read or written.


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[4] [err_fr] : Framing error status bit

0 : No framing error in the current character

1 : The received data at the top of the receive FIFO did not have a valid stop bit. Of course,

generally, it might be that all the following data is corrupt. The bit is cleared upon reading from theregister

[3] [err_data] : Parity Error Status bit

0 : No parity error in the current character

1 : The character that is currently at the top of the FIFO has been received with parity error. The bitis cleared upon reading from the register.

[2:0] [txff_len]: Return information to CPU status of FiFo transmitter as full, empty or has a byte data which ishas just been read or written.

6.4. Register control transmitter,receiver and baud generator: (wq4)

Address: 0x011

Description: The line control register allows the specification of the format of the asynchronous datacommunication used. Reading from the register is allowed to check the current settings of the communication.


7 trans RW 0x0

6 rx_en RW 0x0

5:4 st_sel RW 0x0

3:2 pr_sel RW 0x0

1:0 bd_sel RW 0x0

[7] [trans]: read enable signal bit

0: transmitter can read data from FiFo

1: transmitter can't read data from FiFo

[6] [rx_en]: Receiver enable signal bit

0: receiver hasn't operation

1: receiver has operation

[5:4] [st_sel] : Stop bit selection bits

00 : 1 stop bit

01 : 1.5 stop bit

10 : 2 stop bit

11 : 2.5 stop bit


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[3:2] [pr_sel] : Parity + data selection bit

00: no parity & 7 bit data

01: parity even & 7 bit data

10: parity odd & 7 bit data

11: no parity & 8 bit data

[1:0] [bd_sel]: Baud rate selection bits

00 : 19200 bps

01 : 9600 bps

10 : 4800 bps

11 : 2400 bps

6.5. Register data hold FiFo receiver: (wq5)

Address: 0x100

Description:The wq5 register stores the received data. Before reading this register the user should check wq3for possible errors. The status shown in wq3 corresponds to the character on top of the FIFO, which is the oneready to be read from wq5.


7:0 wq5 W 0x0

[7:0] [wq5] : Data bits 7-0 of the Received Character

7. Configuration Sequence

7.1. [Particular set up sequence]

7.2. [Particular set up sequence]

Step 1: [description put here]

Step 2: [description put here]

8. [ASIC/FPGA] Resource

8.1. Design Estimation

Module

Name

LC LE Memor

y

M9K

Block

Clock Rate Comment


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8.2. Synthesis Report

ModuleName

LC LE Memory M9K Block Clock Rate Comment

9. Power Consumption

[Power consumption/requirements if needed]

10. Standard References

[1] [standard code/number], [date], [document name]

[2] [standard code/number], [date], [document name]

11. Appendix

[Text put here]

Note: This section is optional, depending on specific information shown.

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