TSV Processing and Wafer Stacking - SEMATECHsematech.org/meetings/archives/3d/8510/pres/SUSS.pdf ·...
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TSV Processing and Wafer Stacking Kathy Cook and Maggie Zoberbier, 3D Business Development
Transcript of TSV Processing and Wafer Stacking - SEMATECHsematech.org/meetings/archives/3d/8510/pres/SUSS.pdf ·...
TSV Processing and Wafer Stacking
Kathy Cook and Maggie Zoberbier, 3D Business Development
Outline
Why 3D Integration?
TSV Process Variations
Lithography Process Results
Stacking TechnologyWafer Bonding technology and process resultsMicro-bumping
SUSS Product Offerings for 3D
3D Benefits
Die size reduction (higher yield due to smaller die size leads to lower cost)
Performance improvement (shortenedsignal lines reduce latency)
Use of best native process nodes (eg. digital 65nm, analog 180nm) - optimizepower consumption
Heterogeneous integration of different substrate materials (Silicon and III-V)
Source: Prismark presentation, “3-D Wafer Bonding”, November 2005.
3D Integration Drivers
Image sensors and memory stacking (for mobile applications) are two mass volume applications for TSVs with short time-to-market
These are all potential 3D drivers:
Through Silicon Via Wafer Processing
Create Etch MaskCoatExposureDevelop
EtchingInsulation
CVD, TEOSVia Filling
Material: Copper, TungstenDifferent Materials require different deposition processes (electroplating, CVD, LPCVD)
Cu is the most widely used material today
Wafer StackingCu diffusion, adhesive or fusion bondingMicro-bumping
25 x 155 microns (6:1)
Oxide (150 nm)
CVD TiN (60 nm)
Image Courtesy of Nexx Systems
Trends in TSV Manufacturing
VIA-FIRSTVias created early in the device manufacturing processIssues with temperature compatibilty of subsequent CMOS stepsMaterials must be CMOS compatibleOnly known good wafers are used Lower cost than via-last
Image Courtesy of Amkor
Trends in TSV Manufacturing
VIA-LASTNo thermal stress issuesVia location must be considered during design phasePotentially lower yieldCreates a supply chain issue
Image Courtesy of Amkor
TSV Process Variations
3D IC Process Sequence VariationsProcess IC Wafer Step #1 Step #2 Step #3
A FEOL TSV (vias first) Wafer Thinning (temp. handle) "face-up" Bond (metal bonding)
B FEOL TSV (vias first) "face-down" Bond (metal bonding) Wafer Thinning (on 3D stack)
C BEOL TSV (vias first) Wafer Thinning (temp. handle) "face-up" Bond (metal bonding)
D BEOL TSV (vias first) "face-down" Bond (metal bonding) Wafer Thinning (on 3D stack)
E No TSV TSV from front (vias first) "face-down" Bond (metal bonding) Wafer Thinning (on 3D stack)
F No TSV TSV from front (vias first) Wafer Thinning (temp. handle) "face-up" Bond (metal bonding)
G No TSV "face-down" Bond (all methods) Wafer Thinning (on 3D stack) TSV from back (vias last)
H No TSV Wafer Thinning (temp. handle) "face-up" Bond (all methods) TSV from front (vias last)
I No TSV Wafer Thinning (temp. handle) TSV from back (vias first) "face-up" Bond (metal bonding)
3D IC Process Variations – Process A & C
Source: Phil Garrou, MCNC 2008
Step 1. Coat and exposure of pads
•ACS200 or ACS300
•MA200Compact or MA300
Step 2. Carrier wafer technology
Steps 3 and 4. Align and Bond
•CBC200 or CBC300
3D IC Process Variations – Process B & D
Source: Phil Garrou, MCNC 2008
Steps 2 and 4. Align and bond
•CBC200 or CBC300
Step 3. Coat and exposure for redistribution
•ACS200 or ACS300
•MA200 Compact or MA300
3D IC Process Variations – Process E
Source: Phil Garrou, MCNC 2008
Step 2. Top-side align (TSA), exposure and coat
•ACS200 or ACS300
•MA200 Compact or MA300
Step 3. Align and bond
•CBC200 or CBC300
Step 4. Back-side align (BSA), exposure and coat
•ACS200 or ACS300
•MA200 Compact or MA300
3D IC Process Variations – Process F
Source: Phil Garrou, MCNC 2008
Step 2. Top-side align (TSA), exposure and coat
•ACS200 or ACS300
•MA200 Compact or MA300
Step 3. Carrier wafer technology
Step 4. Back-side align (BSA), exposure and coat
•ACS200 or ACS300
•MA200 Compact or MA300
Step 5. Align and bond
•CBC200 or CBC300
3D IC Process Variations – Process G
Source: Phil Garrou, MCNC 2008
Steps 2 and 4. Align and bond
•CBC200 or CBC300
Step 4. Top-side align (TSA), exposure and coat
•ACS200 or ACS300
•MA200 Compact or MA300
3D IC Process Variations – Process H
Source: Phil Garrou, MCNC 2008
Step 3. Carrier wafer technology
Step 4. Align and bond
•CBC200 or CBC300
3D IC Process Variations – Process I
Source: Phil Garrou, MCNC 2008
Step 3. Carrier wafer technology
Step 4. Back-side align (BSA), exposure and coat
•ACS200 or ACS300
•MA200 Compact or MA300
Step 5. Align and bond
•CBC200 or CBC300
Lithography Process Results
TSV Process Results: Etch Mask Exposure
Via openings: Results based on MA200, UV400 proximity exposure
TSV Process Results: Via hole Exposure
Via holes with sidewall angle of 80 °Reliable coating using AltaSprayContact pad openingContacts of 10 µm diameter, 80 µm deep vias are clearly resolvedSpray Coat on Gamma AltaSprayExposure on MA200compactSpray Develop on Gamma
140µm
85µm65µm
93µm
TSV Process Results: Spray Coating
Resist: AZ4999 Positive Resist
SUSS AltaSpray Coater
Stacking Technology
TSV size roadmap
CIS
Mem
ory
15-10µm
35-25µm 15-10µm
75-50µm
2007 2009 2012 >2014
<5µm
...
... ...
TSV
75%~
Bonder Post-bond Alignment Accuracy Roadmap
CIS
Mem
ory
15-10µm
35-25µm 15-10µm
75-50µm
<5µm
9-5µm 4-3µm 1.75µm 0.6µm
Alig
nmen
t A
ccur
acy
...
... ...
2007 2009 2012 >2014
Primary Bonding Technology CategoriesSiO2 fusion bonding
Metal BondingMetal (Cu) diffusion bonding Metal Eutectic bonding ( Cu/Sn)
Polymer adhesive bonding
Chip 1
Chip 2
Chip 1
Chip 2
Adhesive
Adhesive
Chip 1
Chip 2
Metal
Metal
Image Courtesy of MCNC
Comparison of Bonding Methods
Metal to Metal Direct Bonding Adhesive Bonding
Mechanical / Electrical
Mechanical and electrical
Mechanical Mechanical
Requirements
nm flatCleanOxide freePlanarity
Roughness (nm)CleanTreated surface forlow Temp. Bonding
ca. 250°CSurvive post cureprocessing
Pros / Cons
High surfaceroughness and flatnessrequirements
High bond strengthSensitive to particles
TopographytolerantLow temperatureprocessPoor mechanicalproperties
25 Cu-Cu 3D TSV Aligned Pairs
Average Post Bond Overlay Accuracy 1.4 ±0.7 µm sqrt (x2+y2)
After Bond and Anneal25 Bonded PairsBonded 425C
Average Aligner Overlay Accuracy0.6 ±0.3 µm sqrt (x2+y2)
Before Bond and Anneal 25 Aligned PairsIR Alignment on BA200
BCB Pairs -Post-bond IR Images
Misalignment vs. position along horizontal wfr diameter, notch down
-5-4-3-2-1012345
-100 -50 0 50 100
position (mm)m
isal
ignm
ent (
um)
Waf 1 YWaf 1 XWaf 2 YWaf 2 XWaf 3 YWaf 3 X
Post Bond Alignment Data using Direct Bonding
Wafer # dXl " dYl dXr dYr Accuracy dX dY dR dT Alignmentin Pixels in Pixels in Pixels in Pixels in Pixels in Pixels in Pixels in Pixels in Pixels in µm
1 0.5117 -0.0939 -0.3483 -0.1078 0.1353 0.0817 -0.1008 0.4300 0.0070 0.17012 0.3503 -0.0546 -0.3620 -0.0582 0.0585 -0.0058 -0.0564 0.3562 0.0018 0.07363 -0.0613 0.1309 0.0515 -0.0471 0.1310 -0.0049 0.0419 -0.0564 0.0890 0.16484 -0.1474 0.0613 0.0544 -0.0533 0.0769 -0.0465 0.0040 -0.1009 0.0573 0.09675 0.0200 0.0034 -0.0268 -0.1261 0.1261 -0.0034 -0.0614 0.0234 0.0647 0.15866 -0.0007 -0.0032 0.0450 -0.0172 0.0280 0.0222 -0.0102 -0.0228 0.0070 0.03537 -0.0073 -0.0827 -0.0666 -0.0332 0.0906 -0.0370 -0.0579 0.0296 -0.0248 0.11398 -0.0061 0.0573 0.0253 -0.0501 0.0581 0.0096 0.0036 -0.0157 0.0537 0.07309 -0.0495 0.0091 0.0120 -0.0724 0.0748 -0.0188 -0.0317 -0.0308 0.0407 0.094110 -0.0154 0.0713 0.0252 0.0230 0.0715 0.0049 0.0472 -0.0203 0.0241 0.089911 0.0746 -0.0556 -0.1892 -0.0825 0.1005 -0.0573 -0.0691 0.1319 0.0135 0.126412 0.0804 0.0395 -0.1468 -0.0057 0.0516 -0.0332 0.0169 0.1136 0.0226 0.064913 0.5979 -0.0369 -0.6194 -0.0348 0.0385 -0.0107 -0.0359 0.6086 -0.0011 0.048414 0.4887 -0.0782 -0.4537 -0.0586 0.0801 0.0175 -0.0684 0.4712 -0.0098 0.100815 0.4940 -0.0965 -0.4090 -0.0892 0.1054 0.0425 -0.0928 0.4515 -0.0036 0.132616 0.3946 -0.1509 -0.3916 -0.1429 0.1509 0.0015 -0.1469 0.3931 -0.0040 0.189817 0.4385 0.0019 -0.4179 -0.0622 0.0630 0.0103 -0.0302 0.4282 0.0320 0.079318 0.3970 -0.0788 -0.4291 -0.0936 0.0950 -0.0161 -0.0862 0.4130 0.0074 0.119519 0.1094 -0.0827 -0.1604 -0.0701 0.0866 -0.0255 -0.0764 0.1349 -0.0063 0.108820 0.0958 0.0075 -0.1854 -0.0363 0.0577 -0.0448 -0.0144 0.1406 0.0219 0.072521 0.0960 -0.0946 -0.1713 -0.0672 0.1018 -0.0377 -0.0809 0.1336 -0.0137 0.128022 0.0190 0.0358 -0.0258 -0.0756 0.0756 -0.0034 -0.0199 0.0224 0.0557 0.095123 0.0383 -0.0758 -0.0206 -0.0997 0.1001 0.0089 -0.0878 0.0295 0.0119 0.125824 0.0852 -0.0894 -0.0366 -0.0627 0.0926 0.0243 -0.0760 0.0609 -0.0134 0.1165
Post Bond Final Alignment Accuracy
Average 0.0174 µmSt Dev 0.0386 µmMax 0.1898 µmMin 0.0353 µm
Example: Au-Ge Eutectic Bonding
Eutectic forms at 361°C for Au 28% and Ge 72%Simple Eutectic Diagram Can be driven from diffusion reaction or melted from alloy layer.Other systems Cu-Sn, Au-Sn, Au-Si, Al-Ge
Appl. Phys. Lett 64(6)1994p772.
200mm Au-SiGe
MicroBumpingMicroBumping for 3D Packaging & Integrationfor 3D Packaging & IntegrationBumps are smaller than traditional packaging sizes (<50um)Bumps are smaller than traditional packaging sizes (<50um)
Large number of bumps (>10M per wafer)Large number of bumps (>10M per wafer)
All chipAll chip--sizes (often large compared to traditional bumped chips)sizes (often large compared to traditional bumped chips)
Heterogeneous Devices (Logic, Memory, Sensors, etc.)Heterogeneous Devices (Logic, Memory, Sensors, etc.)
Bump yield extremely criticalBump yield extremely critical
Chip on Chip, Chip on SiChip on Chip, Chip on Si--Substrate, Chip on Wafer, Wafer on Substrate, Chip on Wafer, Wafer on WaferWafer
Main reason for 3D: Performance, IntegrationMain reason for 3D: Performance, Integration
200&300mm200&300mm
Applications for MicroBumping
MicroBumping for 3D
MicroBumping for 3D
UBM Deposition & Patterning
WaferInspection
Final Packaging(Dice / Sort / Pick)
Solder FillMolten solder injection
MoldInspection
Solder Transfer
Mold CleanRecycle
Process Merge Point
Failed Insp.
Empty Mold
Wafer with passivation
Any Size
C4NP MoldStd. Size (13x14”)
C4NP Bumping Process Flow
SUSS Product Offerings for 3D
Lithography: 1x Exposure tools for TSV patterningLarge Gap Optics to expose inside TSV
Resist coaters: spin on and spray coating processes for standardlithography (etch mask) and TSV processing
Permanent Bonding for 3D stacking
Inspection tools (DSM - front to backside measurement)
3D Packaging/Micro-bumping with C4NP Equipment
3D Integration - Our Solutions Set Standards
www.suss.com
