From Technologies to Markets

©2019

2.5D / 3D TSV & Wafer Level

Stacking Technology & market updates

2019

Sample

22.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019

TABLE OF CONTENT

Part 1/3

• Report scope & objectives P5

• Glossary P6

• Authors P8

• Companies cited in this report P9

• Comparison with 2017 report version P10

• The three pages report summary P13

• 3D stacking – packaging market repartition: P16

• Per 3D stacking technologiy

• Per segment

• Per market

• Executive summary P21

1. Introduction P58

• Hints for reading

• Updates from the last report

• Terminology

• From global market to advanced stacking technologies

2. High end market segment P72

• Trends P74• Artificial Intelligence

• Data center

• Super computer

• Cryptocurrency mining

• Gaming

• AR/MR/VR

• Forecasts P95• Stacked memories wafer, units production

• Stacked memories packaging revenues

• 2.5D interposer wafer, units production

• 2.5D interposer packaging revenues

• 3D SoC wafer production & packaging revenue

• Technologies & roadmaps P109• TSV

• 3D stacked memories

• 3D SoC

• 3D sequential integration

• Hardware examples, players & supply chain P125• Hardware for HPC & Networking

• GPU, FPGA supply chain

• TSV based product players

• Conclusions P150

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TABLE OF CONTENT

Part 2/3

3. Mid/Low End market segment P152

• CIS P153

• Trends

• CIS market drivers

• CIS packaging evolution

• Forecasts

• CIS market repartition per technology

• Global CIS wafer production

• Stacked CIS wafer, unit production

• Stacked CIS packaging revenue

• Technologies & roadmaps

• CIS stacking technologies:TSV & hybrid bonding

• CIS roadmap

• Hardware examples, players & supply chain

• BSI Stacked TSV

• BSI Stacked Hybrid

• BSI Multi-stack TSV

• Conclusion

• MEMS & sensors P187

• Trends

• Market evolution & packaging trends

• Forecasts

• MEMS & sensors with TSV wafer

& units production

• TSV revenues for MEMS & Sensors

• Hardware examples, players & supply chain

• MEMS & Sensors with TSV examples

• Supply chain for certain MEMS

& sensors applications and players

• Conclusions

• LED P212

• TSV in LED

• TSV in LED wafer & revenue forecasts

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TABLE OF CONTENT

Part 3/3

4. Potential future applications for

3D stacking technologies P216

• 3D NAND

• Stacked memories, 3D SoC & displays

4. Appendix P219

• Stacking technologies vs 2.5DTSV interposer

• Details of each technology

5. AboutYole Développement P245

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REPORT SCOPE & OBJECTIVES

• This report is an update of the previous 2017 release “3D TSV and 2.5D business update: Market and Technology trends2017”

• The scope of this report is to present the actual trends and their impact on the packaging need and especially the 2.5D/3Dstacking technologies. Mega trends are pushing the packaging market into more and more stacking technologies in order toanswer their stringent requirements (more performance, lower consumption & footprint). Already established stackingtechnologies like TSV will continue to flourish, but will have extended challengers as OSAT’s and other players are alsoinnovating and proposing alternative technologies & solutions for devices stacking

• This report objectives are to:

• Show the impact of the semiconductor market mutation on packaging technologies

• Outline three stacking technologies, through silicon via (TSV), 3D system on chip & hybrid bonding

• Provide an overview of the markets requiring stacking technologies

• Update market data & forecasts for stacking technologies

• Describe the hardware & key applications that are/will use stacking technologies

• Identify the main players & supply chain for stacking technologies

• Evoke novice technologies that may challenge some of the actual stacking technologies

• Predict future applications where stacking technologies may be needed

Biographie & contact

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ABOUT THE AUTHOR

Mario Ibrahim

As a Technology & Market Analyst, advanced packaging, Mario Ibrahim is a member of the Semiconductor & Software division at Yole

Développement (Yole). Mario is engaged in the development of technology & market reports as well as the production of custom consulting studies.

He is also deeply involved in test activities business development within the division.

Prior to Yole, Mario was engaged in test activities development on LEDs at Aledia. He was also in charge of several R&D advanced packaging programs.

During his five-year stay, he developed strong technical & managerial expertise in different semiconductor fields.

Mario holds an Electronics Engineering Degree from Polytech’ Grenoble (France). He apprenticed for three years in the Imaging division of

STMicroelectronics Grenoble, where he contributed to the test benches park automation within the test & validation team.

Contact: ibrahim@yole.fr

7

Alchip, Aledia, Alibaba, Amazon, AMD, Amkor, AMS, ANPEC, Apple, ASE, ASUS, Atos, Audi, Avago,

Baidu, Bosch, Bitmain, BitFury, Broadcom

Canaan, Carsem, Cisco, Cray

DARPA

EBANG, EMmicroelectronic, EPworks

Facebook, Faraday, Fingerprints, Foxconn, Fraunhofer, Fujitsu

Gigabyte, Global Foundries, Google, GUC

HalongMining, HLMC, HP, Huatian, Huawei

Ibiden, IBM, Icsens, IMEC, Inari technology, Infineon, Innosilicon, Intel, InvenSense

JCET STATS ChipPAC, Juniper

Lenovo, Leti, Lfoundry, LGinnotek

mCube, Melexis, Memsic, Mercedes-Benz, Micralyne, Micron, Microsoft

NEC, Nokia, Nvidia, NXP

Omnivision, ON Semiconductor, OpenSilicon, Osram

PTI

Samsung, SensL, Shinko, SK hynix, SMIC, Sony, SPIL, STMicroelectronics

Tencent, TF, Toshiba, TPK, TSMC

UMC, Unimicron

Xfab, Xilinx, Xintek, XMC, Xperi

YMTC

COMPANIES CITED IN THIS REPORT

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TSV TECHNOLOGY WAFER START & REVENUES

Global TSV market

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The numbers are based on each technology’s revenues (M$), meaning that 30% of margin is taken into consideration

ADVANCED PACKAGING TECHNOLOGIES REVENUES REPARTITION

Repartition per markets : HPC & Networking / Consumer / Automotive / Others

• HPC & networking markets are going to grow fast in order to follow the AI & big data trends. This market added to consumer market will

represent almost 90% of the advanced packaging (stacking) market

• Stacking technologies will be needed for autonomous vehicles where higher computing performance will be required (edge computing), but

attention to automotive stringent regulations in term of reliability

• Medical market is a small one for TSV’s but where the performance and form factor parameters are becoming more and more important

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WHAT’S NEW SINCE THE LAST REPORT (JUNE 2017)

• Updating the hardware list using TSV & other 3D stacking technologies with focus on GPUs for High Performance Computing (HPC) inaddition to MEMS & Sensors for mid / low end market segment

• Updating the 3D integration markets by adding cryptocurrency as a new market

• Updating the 3D stacked memory market by omitting HMC & MCDRAM memories from it. Micron stopped any R&D program related toHMC, they will continue to produce low volumes for some of their clients and they are switching to HBM instead

• Updating the 3D integration technologies and adding technologies like hybrid bonding, Foveros, RDL interposer as a new stacking solutions.

• Updating the CIS market and segmenting it into 3 different stacked CIS technologies (using TSV / Hybrid and combo TSV +Hybrid). More focuson this market asYole is foreseeing important usage of stacking technologies in it

• Updating the 2017 forecasts with numbers based on the actual & future market analysis & trends

• Updating the players & ecosystem for stacking technologies, showing that it’s in place and ready to fulfill clients demands

• Updating the cost structure calculation used for the forecasts:• 2017 report: the cost of packaging was including for example the DRAM wafer cost + TSV cost + bumping cost +yield loss cost

• 2019 report: the cost of packaging is only and for example the TSV cost + bumping cost + yield loss cost. Not taking into consideration the device wafercost as we want to focus on the packaging costs only

• New forecasts on Intel’s Foveros technology & updating the 3D SoC forecasts

• 3D SoC will hit the market by 2019 produced by TSMC and with HiSilicon as a first potential client for their datacenter activities

• EMIB from Intel as 3D stacking alternative to 2.5DTSV interposer, with products already launched

• DRAM is still and will further be a big playing ground for 3D stacking technologies. Samsung is prompting pre-emptive $27.7 billion in a 2nd

plant in Pyeongtaek to be able to answer growing DRAM & NAND demand. On the other hand, Micron will also invest $3 billion by 2023 toincrease memory production at its Manassas plant

• Chinese government is massively backing their memory startups. YMTC (Tsinghua Unigroup) received $24 billion to implement a new 12” 3DNAND production line in the new plant in Chengdu. Tsinghua Unigroup are also investing $30 billion in a plant in Nanjing to manufacture 3DNAND & DRAM

• TSMC CoWoS and advanced packaging production capacity extension up to 200K wafers/month. Wafer on Wafer (3D SoC with hybridbonding) new platform from TSMC for HPC and data center markets

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WHY 3D INTEGRATION IS BECOMING MORE AND MORE IMPORTANT

Moore’s law slowing down

Moore’s law pace is slowing down, if not already dead as mentioned by Forbes & Nvidia. It’s reaching some limitations as developing lower technology

nodes is doable technically but not anymore cost efficient

In this report, we will be using the “slow down” term when describing Moore’s law status

To deal with this slow down, other alternatives are currently used & will be further developed:

• Advanced packaging technologies development. 2.5D technology was first used in high performance applications. Scaling the Z axis is taking

more and more importance in what is called 3D stacking especially for HPC, but not only

• Specialized devices. Meaning 1 device = 1 function. Example of GPU VS Neural engine, that allows reduced power consumption & faster

computing speed

• Other advanced packaging technologies development (SLIT, FOCoS, SWIFT, EMIB, ...)

Only 4 players with 14/12nm Fab

(2017) Only 2-3 players still in the 7nm node race

7nm Fab

Delay in Intel’s

10nm node, so

obviously they are

late regarding

TSMC & Samsung

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MEGA TRENDS

Opportunity for various stacking advanced packaging

CPU /GPU APU MCUs ASICs FPGAs MemorySensors/

Actuators/CIS

Analog /

Discretes

Opto-

electronics

AI/ML

FC, 2.5D/3D,

FO, SiP

FC, FO,ED

FC, FO

FC, 2.5D/3D,

FO

FC, 3D,

WB,QFN,

WLCSP

Smart automotive

/Electrification/ ADAS

FC,

WB,QFN,

WLCSPFC,FO,WB, QFN,

WLCSP, SiP, 3D

FC,WB,FO,

QFN, ED,

SiP

AR/VR

HPCFC, 2.5D/3D,

FO

SiP, 2.5D/3D,

FC, WB

IoTFC,

WB,QFN,

WLCSP

FC,FO,WB, QFN,

WLCSP, SiP, 3D

FC,WB,FO,

QFN, ED,

SiP5G

FC, 2.5D/3D,

FO, SiP FC, FO,ED SiP, 2.5D/3D,

FC, WBMobile 3D

FC,FO,WB, QFN,

WLCSP, SiP, 3D

Blockchain / CryptocurrencyFC, 2.5D/3D,

FO

FC, 2.5D/3D,

FO

FC,WB,FO,

QFN, ED,

SiP

Where 2.5D/3D stacking technologies are used

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In this report

ADVANCED PACKAGING PLATFORMS

Focus on 3D stacking packaging platforms in this report

No substrate

Fan-Out WLCSP

Organic substrates

Wirebond

BGA CSP

COB

BOC

WB CSP

LGA

Flip-Chip

BGA

FC BGA

FO on Substrate

2.5/2.1D

3D*

CSP LGA

Leadframe substrates

Wire Bond

QFN/QFP

SOIC

TSOP

LCC

DIP

Flip Chip

FC QFN (MIS)

Ceramic substrates

Wirebond

Hi Rel

Flip-Chip

HTCC

LTCC

Embedded Die

*Hybrid bonding is included in 3D platform

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2.5D & 3D integration

High End segment

HPC

Artificial Intelligence

Data mining (crypto &

other data)

Super computers

Data centers, hyper scale

Networking

Switch / Router

Gaming, VR/AR/MR

Mid / Low End segment

Sensing

MEMS & sensors

CIS

Lighting

LED

2.5D & 3D INTEGRATION MARKET SEGMENTATION

The market is divided into High End & Mid/Low segments

High End segment is defined as the market where an application is less

sensitive to the cost, but requires reduced footprint in addition to high

performances & reliability

Mid/Low End segment is defined by a

good balance between cost sensitivity &

performances

Segments

Market

Applications

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2.5D & 3D STACKING TECHNOLOGIES

With / Without TSV. Foundries VS OSATs battle

i-THOP FC-EIC

Em

bedded in

substrate

EMIB

Hybrid BondingW

ith O

r

With

out T

SV

3D SoC

TSV

+ H

ybrid

Bondin

g

With TSV

Without TSV

G-ALCS

TG

V

3D Stacked memory

TSV

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2.5D INTEGRATION WITH TSV TECHNOLOGY FOR HIGH END SEGMENT

Heterogeneous integration on Si interposer

• The TSV is used as interconnection between the 2 Si facets in the so called Si interposer. It is a thinned silicon wafer with TSV’s that enableheterogeneous device integration on top of it in what is described as 2.5D integration.

• This 2.5D Si interposer is the technology created just before the 3D integration (used for example in stacked memories). It was created as anintermediate technology before accessing the 3D integration and still used in many applications that requires:

• Higher performances and lower power consumption due to shorter connections

• In the example below, the Si interposer is used as an interconnection between a X-PU (GPU for example) and a 3D stacked memory (with TSV’sinside, HBM for example)

TSV

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3D INTEGRATION WITH TSV TECHNOLOGY FOR HIGH END SEGMENT

3D Stacked memories with TSV technologies (3DS & HBM)• 2 types of stacked memories technologies using TSV are on the market:

• 3DS: this type of memory is using DDR4 DRAM stacked chips and operate as stand-alone memories for HPC & data centers markets

• HBM: this type of memory is often used beside other hardware like GPU, CPU, FPGA on top of a 2.5D interposer

• The 3DS memories are TSV based devices, where several DDR4 DRAMs are interconnected together using TSV technology. It can have a totalcapacity of 64 and 128GB. Samsung announced its availability in 256GB configuration back in October 2018

• 2 major players share the 3DS market, Samsung as a leader, SK Hynix as runner up with micron completing the podium but still far away from the2 leaders in term of volume production

• The HBM memories are also TSV based devices, where 2/4 & 8 DRAMs are interconnected together via TSV. We can see 1/2/4 HBM devicesaround a processor in a system dedicated for HPC. Samsung is the leader in this market with SK Hynix in second position. Micron will switch tothis technology instead of their HMC technology that they are letting down

• In term of market, the 3DS today is around 42% of total high performance stacked memories (3DS & HBM). Due to the fact of data collectionexploded in the last years and the entry of artificial intelligence onto our daily life, the need of 3DS will increase in the upcoming years reaching51% of the total high performance stacked memories market by 2020

Samsung

stacked

DRAM

(3DS)

Samsung

8 stack

high

HBM2

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Approach 1 (IMEC)

Approach 2 (IMEC)

Approach 3 (other possible

approach?)

3D SOC

2 or 3 potential approaches to reach 3D SoC

Source IMEC (except approach 3)

Dielectric bonding +

Si thinning + TSV last

+ bumping

Hybrid bonding + Si thinning

+ TSV middle + bumping

1 2 3?

Potential 3rd approach:

Hybrid or other

bonding + Wafer 1

complete Si removal +

bumping (No TSV)

RDL may still be needed before bumping

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3D SOC FORECAST

12’’ SoC WSPY production

• TSMC is believed to be the first to get a product on the market,

by end of 2018, start of 2019 (Die to wafer, memory on logic).

They are able to ramp up the production very quickly if a client

will manifest an interest in this technology

• TSMC WoW technology will be based on SoC wafer stacking

using hybrid bonding and intended for datacenter usage. HiSilicon

(Huawei) can be their first client,AMD is also a potential client

• Global foundries will enter the market by 2021 with as first phase

memory on logic wafer to wafer stacking using hybrid bonding

with pitches between 1 & 2µm. They will produce both wafers &

stack them in-house, which is of an interest for the yield

• Hybrid bonding will, most probably, be the bonding technology

used for 3D SoC stacking (wafer to wafer)

• 3D SoC wafer should cost 3 to 4 times less than TSV interposer

wafer

• 3D SoC can be memory on logic or logic on logic (attention heat

dissipation issues for the latter one). In the case of memory on

logic which is the most probable application for 3D SoC, memory

manufacturers & logic circuits ones should talk together to limit

the design differences & yield losses (the manufacturers having

capabilities to produce both wafers will have a big advantage)

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HIGH END HARDWARE USING STACKING TECHNOLOGIES, PRODUCTS LAUNCH

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HIGH END MARKET SEGMENT EXAMPLES, PLAYERS & SUPPLY CHAIN

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TSV IN HIGH END SEGMENT FORECAST

TSV revenues & growth in High End segment

• This graph is based on TSV revenues in High end segment:

• 3D stacked memory (HBM & 3DS)

• 2.5D interposer (active & passive)

• 2.3B$ TSV revenues by 2023 with an important growth of

57% between 2017-2023 in high end segment

• 3D stacked memories are and will still be the best friend

hardware applications for TSV technology

• We insist, it’s the TSV revenues and growth for High end

segment only. If we plot the growth of TSV for all the

combined market segments, the growth is around 25%

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2.5D “PASSIVE” INTERPOSER

A vision on its future

• TSV interposer is an expensive and complex technology in term of process steps

• All the players acting in the field of 2.5D stacking are working on replacing the TSV interposer by other

technologies. The goal is to reduce the prices, enabling the access of 2.5D to mid/low end segments, but also

simply to reduce the total module cost

• Two scenarios are possible for TSV:• Scenario 1:

On the previous 2 slides, we shown that the demand for TSV interposer will continue to grow till 2020 and starting from

2021 the growth will be slower. This is the first potential scenario where we believe that one of the TSV less technologies

will hit the market by 2020/2021 and will start replacing the TSV interposer for 2.5D gradually

• Scenario 2:

Delays in the development and commercialization of TSV less technology(ies). Meanwhile, the demand for TSV interposer

continue to grow to feed the HPC markets. In this case, the TSV interposer will continue to dominate the 2.5D market

and players like TSMC & UMC will be able to increase their production volumes to meet with the demand

• TSV interposer still have some golden years in front, both scenarios can happen even if scenario 1 is more likely to occur

after 2020 & scenario 2 till 2020

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CIS WAFER LEVEL PACKAGING EVOLUTION

From FSI to BSI multi-stack TSV sensors

Used in Iphone

I7+:

2 wafers

interconnected

via TSV

2016

Used in Galaxy

S7:

2 wafers

interconnected

via Hybrid

Bonding

Used in Sony

XZs:

3 wafers

interconnected

via TSV

2016

2017

4 stacks high CIS

& Pixel to pixel

high density

interconnection

CIS under

development.

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• Technology shift into stacked CIS driven by the willingness to go for more performances & higher image quality in parallel toreducing the footprint

• Stacking technologies enabled Rolling Shutter (RS) pixel size reduction. This will also be applied to Global Shutter pixel in thefuture

CIS ROADMAP

Stacking technologies enabled new CIS technologies

FSI

FSI SOI

BSI

BSI Stacked TSV

BSI Stacked Hybrid

BSI Multi-stacked TSV

Samsung S6

Apple i7

Samsung S7

Apple i8

Sony XZ

Apple iX

RS pixel

GS pixelToF pixel

Lenovo 2Pro

Event-based

pixel ?

Technology complexity

2000 2005 2010 2015 2020 2025 Time

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CIS STACKED TECHNOLOGIES FURTHER DETAILS [1/2]

TSV and hybrid stacked BSI processes

• BSI stacked TSV:• Oxyde /oxide permanent bonding

• Via Last TSV process + RDL

• BSI stacked Hybrid:• Copper pads on both wafers (upper & lower ones)

• Oxide deposition & planarization (very low surface roughness is required ~1nm)

• Plasma activation + alignment (able to go under 1µm of pitch alignment using a stepper) + Room temperature bonding followed by an

annealing cycle

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TSV VS HYBRID BONDING FOR CIS

Which technology is the most suited?

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STACKED CIS PACKAGING MARKET

Packaging cost & revenues for stacked CIS (M$)

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KEY PLAYERS FOR 3D STACKED CIS PRODUCTS

Still a reduced comity with few players

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PLAYERS LICENSING XPERI’S HYBRID BONDING TECHNOLOGY

From CIS to memory, more and more players are using/evaluating hybrid bonding

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THE DIFFERENT MEMS, SENSORS, AND ACTUATORS, AND WHERE THEY CAN COMBINE

ACTUATORSSENSORS

Pre

ssu

re

So

un

d a

nd

ult

ra

son

ic

Environment Optical sensors

Dru

g d

elivery

Microfluidics

Ink j

et

head

s

Au

to-F

ocu

s

Mic

rom

irro

rs

RF

µsp

eakers

Optical MEMS Micro structures

Part

icle

s

Hu

mid

ity

Movement

Gas

Magn

eto

mete

rs

Accele

rom

ete

rs

Gyro

sco

pes

Tem

pera

ture

Op

tical b

en

ch

es

Mic

ro t

ips

Pro

bes

Watc

hes

co

mp

on

en

ts

PIR

& t

herm

op

iles

Sw

itch

Filte

r

Bosch BME680

FLIR Lepton One

Infineon microphone

ST pressure sensorInvenSense

MPU9250

Debiotech micro

pump

Texas Instruments DLP

Avago-Broadcom

FBAR Filter

Spiromax Patek

Philippe

Audio Pixels M

EM

S-b

ased

spea

ker

Osc

illa

tor

Bio

ch

ips

poLight AF

SiTime oscillator

AL

S, R

GB

Fin

gerp

rin

t

Optical combos“open” package

environmental combos

Possible integration with environment

combos

Possible

integration with

opto combos

Hyp

ers

pectr

al

3D

sen

sin

g

FT

IR

Vis

ion

Mic

ro b

olo

mete

rs

Ult

ra s

on

ic

fin

gerp

rin

t

Apple dot projector

Qualcom

m fin

gerprin

t sensor

IMUs (6 to 9 DOF)

“closed” package

6 to 9+ DOF

combos

SiP

M

Application where TSV is used

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TRENDS IN MEMS PACKAGING [2/2]

Packaging trends by market

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INTEREST OF WAFER LEVEL PACKAGING + TSV ON ACCELEROMETERS?

WLCSP & TSV = smaller package dimensions

65% surface reduction due to the use of (WLCSP + TSV) VS (LGA + TSV)

25% thickness reduction due to the use of (WLCSP + TSV) VS (LGA + TSV)

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TSV FORECASTS FOR MEMS & SENSORS

TSV revenues for MEMS & Sensors

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MEMS & SENSOR (EXCEPT CIS) GLOBAL SUPPLY CHAIN THAT USE TSV IN THEIR PRODUCTS

Non exhaustive list

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RELATED REPORTS