Tornado BSP Manual2

Wind River Systems, Inc. 1997

Training Workshop

Appendix

Tornado BSPTM

Wind River Systems, Inc.1010 Atlantic AvenueAlameda, CA 94501

510-749-2148FAX: [email protected]

http://www.wrs.com/training

2

Copyright © Wind River Systems, Inc. 1986 - 1998Version 1.0.2, April 1998ALL RIGHTS RESERVED. No part of this publicationmay be reproduced in any form, by photocopy, microfilm,retrieval system, of by any other means now known or

hereafter invented without the prior written permission of Wind River System, Inc.This document is designed to support the Tornado BSP Training Workshop class. It is not designed as a stand-alone document, nor can it substitute for Wind River Systems BSP documentation. For information about the Wind River Systems training program, contact:

Training Department Wind River Systems S.A.R.L.Wind River Systems, Inc. 27, Avenue de la Baltique1010 Atlantic Avenue Bâtiment B4, LP739Alameda, CA 94501 91962 Les Ulis Cedex

France510-749-2148 (phone)510-749-2378 (fax) 33-1-69-07-78-78 (phone) EMAIL: [email protected] 33-1-69-07-08-26 (fax)

Wind River Systems Japan/Asia-PacificPola Ebisu Bldg. 11F3-9-19 HigashiShibuya-kuTokyo 150Japan

+81-03-5467-5900 (phone)+81-03-5467-5877 (fax)

VxWorks® and Wind River Systems® are registered trademarks andTornado, wind, windX, WindPower, WindNet, WindNet SNMP, WindView,VxGNU, VxGDB, VxSim, VxVMI, VxMP, and MicroWorks are trademarksof Wind River Systems, Inc. All other trademarks cited herein are theproperties of their respective owners.

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Table of Contents

Example Target - MVME2604 ...........… ACore BSP Example Code................… .... BbootInit.c ................................................ CusrConfig.c ............................................. Dmv2600.h................................................. Econfig.h ................................................... FSerial Driver Code .................................. GInterrupt Controller Library .................... HTimer Library ...................................… ... IbootConfig.c - Core Functions................. JPCI Bus.................................................... KMemory Maps.......................................... L

Appendix


Example Target -MVME2604

Appendix - A

A-2

Overview

Power On and romInit()

sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration

Example Target - MVME2604

A-3

Overview

• This appendix provides support material for understandingBSP issues associated with the MVME2604.

• MVME2604 BSP illustrates many of the practical issues a BSP developer will need to resolve:• Managing interrupts via interrupt controller.• Managing multiple busses.• Supporting standard embedded devices (LAN, serial,

SCSI, etc.)• Programming for a modern architecture.• Building a WRS compliant BSP for a complex

environment.

A-4

MVME2604 Environment

• CPU:• PowerPC 604.

• Buses:• MPC604 Processor bus.• PCI• ISA• External VME bus.

• Bus controllers:• MPC604/PCI bus bridge controller (Raven ASIC).• VME/PCI bus bridge controller (Universe ASIC).• PCI/ISA bus bridge controller (Winbond ASIC - PIB)• Memory controller (Falcon ASIC).

A-5

MVME2604 Environment - cont.

• Memory:• 1 MB socketed EEPROM/Flash on MPC604 bus.• 256 KB L2 cache on MPC604 bus.• 4 MB (or 8 MB) solderedFlash (RAM200 Mezzanine).• 16 MB to 256 MB ECC DRAM (RAM200 Mezzanine).• 8 KB NVRAM (with RTC).

• Devices accessed via local PCI bus:• DEC 21140 Ethernet controller.• NCR 53C825A SCSI controller.• PCI expansion slot devices (mezzanine & expansion)• ISA bus devices via Winbond PIB.• VME bus devices via Universe chip.

A-6

MVME2604 Environment - cont.

• Devices accessed via local ISA bus:• Zilog 85230 ESCC.• Zilog Z8536 CIO - Support for modem control lines

not supported by Z85230 SCC. Used for auxilaryclock by VxWorks.

• Super I/O ASIC - Controller for keyboard, mouse,floppy disk drive via front panel connectors; andasynchronous serial and parallel ports throughtransition module.

• Transition Module:• MVME761 or MVME712M - Provides front panel

interface for ethernet, 2 ESCC ports, and super I/Oserial/parallel ports. Separate board which plugsinto VME backplane.

A-7

MVME2604

PPC604

Falcon

Flash 4/8MB

DRAM

ROM/FlashL2 Cache

SSC SIOCIO

Raven PIB NVRAM

PCM PCI-E Universe SCSI Ethernet

A-8

Busses And Endianness

• On-board busses:• Processor bus: big-endian.• Memory bus: big-endian.• PCI bus: little-endian.• ISA bus: little-endian.• VME bus: big-endian.

• Bridge controllers and endianness:• Raven ASIC provides endian translation between

host and PCI busses. No issues for Ethernet and SCSI data,however, big-endian software needs to perform byte-swapping when accessing control registers.

• Universe ASIC manages endian translation betweenPCI and VME bus.

A-9

Example Target

• Example BSP supports the following features:• 33 and 66 MHz MPC bus clock.• L2 cache, write-through only.• 1 MB socketed EEPROM/Flash.• 4 or 8 MB (64-bit wide) soldered flash. (Used for

VxWorks images.)• DRAM - 16, 32, 64, 128, 256 MB. Interleaved with

fixed size or auto-sized.• PCI bus - 32-bit address and 32-bit data transfers.

Revision 2.1 compliant (Local Bus Specification).• ISA interface - 64 KB memory and 64 KB I/O space.• A32/A24/A16 and D32/D16/D08 VME bus master/

slave support. Full system controller support. 2location monitor/signal registers.

A-10

Example Target - cont.

• Supported peripheral devices:• 10baseT/100baseTX Ethernet controller (DEC 21140).• Single-ended fast SCSI-2 controller(NCR 53C825A).• 2 serial ports for Z85230 ESCC.• 2 serial ports (COM1 /COM2) for Super I/O ASIC.

• Unsupported features and devices:• ECC protection for DRAM.• 64-bit extensions for PCI bus.• ISA interface - RTC and DMA controllers.• VME bus - D64 transfers and programmable DMA.• Modem control lines for Z8536 CIO.• Super I/O except for serial ports.

A-11

Example Target - Device Support

• To support target devices the following BSP libraries are required:

• pciIomapLib.c - PCI configuration library.• ravenMpic.c - Library for Raven host bridge. Also

includes support for Winbond PIB.• universe.c - Library for Universe VME/PCI bridge.• ppcDecTimer.c - PowerPC decrementer timer

library (system clock).• ppcZ8536Timer.c - Z8536 CIO timer library

(auxiliary clock).• byteNvRam.c - Library for non-volatile RAM.

• Note device libraries which are not BSP specific:• Ethernet, serial, SCSI, and Falcon chip.

A-12

• The MVME2600 family of boards are differentiated byseries part numbers. The format is:

• MVME260p-tcmm

• Format parameters are:• p = processor type (3 = 603e, 4 = 604ev)• t = transition module (1 = MVME761, 2 =MVME712)• c = processor clock freq. (0 = 167 MHz, 1 = 200 MHz)• mm = ECC DRAM size (21 = 16 MB, 31 = 32 MB, ...)

• A MVME2604-1131 will use a PowerPC 604evprocessor, with clock speed of 200 MHz, 32 MB of ECCDRAM, and require a MVME761 transition module.

• See target.txt for more infomation.

MVME2600 Board Labels

A-13

Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


A-14

• Hardware properly configured prior to power on.

• BSP is responsible for partial initialization of thefollowing items at power on:

• Some CPU registers.• Disable on processor cache.• Disable L2 cache.• Host bridge controller (Raven chip). *• PCI bus. *• DRAM memory controller (Falcon chip).• DRAM.• Super I/O ASIC. *

•Initializations performed by code in romInit.s.

MVME2604 Power On

A-15

Hardware Configuration

• See target.txt and hardware documentation forinstructions on configuring particular options.

• Jumper configuration options:• Configure board as system controller (VME).• Boot from either socketed EEPROM/Flash or

soldered flash (ROM controller).• L2 cache controller (automatic write through mode).

• If booting VxWorks from socketed Flash, “burn”VxWorks into ROM and swap manufacturer’s ROM.

• If booting VxWorks from soldered Flash, followinstructions in target.txt to download VxWorks tosocketed Flash with aid of bug ROM.

A-16

CPU Register Configuration

• romInit() configures appropriate CPU registers to:• Initialize processor to a known state via the MSR.• Initialize cache.• Saving and passing boot type (warm/cold).• Initializing stack pointer for romStart().

• The processor is intialized to known state using MSR.For example:

• Disable interrupts by clearing the EE bit.• Disable the floating point unit by clearing the FP bit.• Set processor to supervisor mode by clearing PR bit.• Configure for big-endian mode by clearing LE bit.

•All MSR bits are cleared.

A-17

CPU Register Configuration - cont.

• All caches are first disabled (default for all VxWorksimages).

• For PowerPC 603/604 a check is performed to see ifinstruction cache should be enabled for faster FlashROM boots.

• If USER_I_CACHE_ENABLE is defined in configAll.h cache is enabled by writing to the processor dependent HID0 (hardwareimplementation) register.

• The boot type is saved and passed to romStart() using ageneral purpose register.

• The stack pointer for romStart() is intialized toSTACK_ADRS and then aligned by FRAMEBASESZ.

A-18

• Bridge/memory controller between processor bus andmemory bus (Falcon chip) must be intialized:

• Probe for correct memory size.• Probe for memory bus speed. • Initialize Falcon registers.

• Each possible memory bank size is tested.

• DRAM speed is obtained by probing, and processor busspeed is set accordingly. Possible values: 50, 60, or 70 ns.

• Control register addresses for Falcon chip initialized inmv2600.h

• RAM begins at address 0x00000000.

DRAM Configuration

A-19

DRAM Configuration - cont.

• Table is used to provide data for size probing:• Memory bank size.• Probe addresses.• Data patterns for probe addresses.

• There are four DRAM banks, each is probed andintialized:

• Probes and intialization of DRAM attribute registersare done in a loop.

• Attributes are then loaded using intialized attributeregisters.

• After Falcon chip is intialized, stack is intialized andprocessor jumps to romStart().

A-20

Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration


A-21

Example Target - sysHwInit()

• sysHwInit() will prepare the hardware environment forkernel activation:

• Checks CPU type.• Initializes PCI I/O space support library.• Configure bridge chips and devices on PCI bus.• Initialize some VME facilities.• Initialize two serial ports.• Access NVRAM for ethernet address and to disable

hardware watchdog.• Check for memory autosizing.

• sysHwInit() will #include driver code for board.• Both BSP specific and generic drivers.

A-22

Checking CPU Type

void sysCpuCheck (void)

• mv2600 BSP specific routine which validates CPU type.

• If appropriate CPU type is not found:• Serial interface is initialized.• Error message is printed to console channel in polled

mode.• System is restarted.

• CPU type is set in mv2600.h:#define CPU_TYPE ((vxPvrGet() >> 16) & 0xffff)

• vxPvrGet() reads the processor type from the PowerPCProcessor Version Register.

A-23

Initialization Of PCI Library

• PCI library to manage I/O mapped bus addresses mustbe initialized.

• This is necessary to initialize PCI headers for allpotential PCI bus masters:

• DEC 21140 network device.• NEC 53C825 SCSI device.• Winbond PIB chip.• Raven host bridge.• Universe chip.• PMC span bridge and mezzanine card if present.

• Routine will also check for secondary instances ofdevices on the PMC and initialize if present.

A-24

Configuration of PCI Headers -ExampleTarget

• Standard PCI header configuration for:• DEC 21140 Ethernet controller.• NCR 53C825 SCSI controller.• Universe PCI/VME bridge controller.

• Raven and Winbond ASICs power-up with correctStandard PCI header values.

• Extended PCI header configuration for:• Raven ASIC.• Winbond PIB.

• No secondary PCI devices (on PMC).

A-25

Initializing PCI Headers

• Initializing Standard PCI headers:• Verify device is on bus - pciFindDevice().• Write to configuration header for device -

pciDevConfig().

• Configuration parameters for pciFindDevice() andpciDevConfig() defined in mv2600.h.

• Initialization of extended PCI headers:• Verify device is on bus if not previously done

-pciFindDevice().• Write to configuration header for device using BSP

specific routine.• Configuration parameters in BSP device specific

header file.

A-26

Additional Initialization Of BridgeControllers

• Initialization of non-PCI configuration space registers isperformed for on-board bridge controllers:

• Raven ASIC.• Winbond PIB.• Universe ASIC.

• Raven ASIC - Initialize interrupt management facilities.

• Winbond PIB - Initalize interrupt managementregisters.

• Universe ASIC - Map access to VMEbus space, andintialize registers.

A-27

Configuration For Second PCI BusSegment Access

• Second PCI bus segment accessed through PCM Spanbridge controller.

• PCM Span bridge controller configured usingsysPciSpanConfig():

• Initializes brigde configuration header with staticparameter set using a configuration parameter arraydefined in sysLib.c

• Configuration parameters defined in config.h:• I/O and memory base addresses.• I/O and memory space sizes.• etc.

A-28

VMEbus Initialization

STATUS sysUniverseInit (void)

• BSP specific routine which:• Resets Universe chip - clears interrupts and errors.• Maps slave image windows on the Universe chip.• Initializes VMEbus latancy timer.• Clears board SYSFAIL signal.

• In addition, a routine to clear a TAS operation over theVME bus is hooked into the VxWorks shared memoryutility library.

• Universe driver code in universe.c.

A-29

Bus Probe Initializtion

STATUS sysBusProbe (adrs, mode,length, pVal)

routine Address to be probed. Variable type:char *.

mode Read/write. Variable type: int.length 1, 2, or 4 byte probe. Variable type: int.pVal Adress of value to write or location to

place vlaue read. Variable type: char *.

• This routine is hooked to vxMemProbe():• For PCI bus calls sysPciProbe().• For VME bus calls sysVmeProbe().• For local bus returns ERROR, native routine used.

A-30

Serial Interface InitialIzation

void sysSerialHwInit (void)

• This routine initializes both hardware and softwarecontrol structures for on-board serial interfaces:

• Loops through intialization of device controlstructures for each channel.

• Calls routine to initialize hardware registers.

• This routine must be called before using Tornado toolsin system mode.

• This routine, as well as using a serial channel for systemlevel debugging is discussed in detail in an upcommingchapter.

A-31

NVRAM And Initialization

• On-board M48T59 chip provies:• NVRAM• Watchdog timer.• Real-time clock (RTC).

• The six byte ethernet address for board is initilaizedusing value stored in NVRAM:

• Known three byte manufacturer code intializedwhen global ethernet address variable is declared insysLib.c.

• Three byte station specific code initialized byreading NVRAM using sysNvRamGet().

• Hardware watchdog timer disabled usingsysNvRamWrite().

A-32

Checking For Memory Autosizing

char * sysPhysMemTop (void)

• Routine returns the size of physical memory.

• This routine will provide dynamic memory sizing ifLOCAL_MEM_AUTOSIZE is defined in config.h.

• Since Falcon chip is initialized by romInit(), this routinewill simply read and interpret its DRAM atrributesregister(s) in a loop.

• Obtain DRAM size for all four banks.• Update total physical memory size.

• If autosizing is not configured, routine returns default.

A-33


Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration

A-34

MMU Memory Map

• sysPhysMemDesc[] specifies memory maps using:• End-user configurable addresses and mapping

lengths in config.h.• Non-configurable map parameters in mv2600.h.

• Memory mappings are for the Extended VME memorymodel (default map):

• Define EXTENDED_VME in config.h.

• End-user configurable parameters in config.h:• LOCAL_MEM_LOCAL_ADRS• RAM_LOW_ADRS• LOCAL_MEM_SIZE• CPU_VME_WINDOW_[A32,A24,A16,REG]_SIZE

A-35

Memory Access Caveat

• PowerPC architecture limits its relative addressing to 26bit signed offsets (+/- 32 MB):

• EABI (Embedded Application Binary Interface)standard.

• C function calls relative to the current address arerestricted to +/- 32 MB (supported by GNU).

• VxWorks images should be contained in a single 32 MBRAM block.

• Potential issues:• Target based loader if system memory pool larger

than 32 MB.• ROM-resident VxWorks images.

A-36

Bus Probes

• BSP supports hook for vxMemProbe() which allows thefollowing buses to be probed:

• PCI• VME• Processor

• Routine is sysBusProbe() in sysLib.c.• Support routines which it calls also in sysLib.c.

• sysBusProbe():• Checks address to find appropriate bus to probe.• Probes bus providing bus controller management.• If exception occurs, determine type and return error

on bus error.

A-37


Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration

A-38

Example Target - Interrupts

• Hardware management of interrupts pertormed byinterrupt controllers.

• Interrupt controllers are cascaded.

• Raven ASIC controls interrupts for:• Primary PCI bus devices (Ethernet, SCSI)).• Secondary PCI bus devices. (Ethernet, SCSI)• Winbond PIB ASIC.• Universe chip.• Raven self generated (timer, transfer error, etc.).

• Windbond PIB controls interrupts for ISA devices:• Z85230 SCC (COM3 and COM4).• Z8536 CIO (auxilary clock).

A-39

Example Target - Interrupts cont.

• Super I/O chip serial ports (COM1 and COM2).• Abort switch interrupt which returns control to ROM

or Flash.

• Universe chip controls VMEbus interrupts.

• The Falcon chip set handles memory interrupts.

• Processor handles self-generated interrupts(exceptions).

• The following interrupt controllers are cascadedthrough the Raven ASIC:

• Winbond PIB.• Universe.

A-40

Primary PCI Bus Interrupts

Raven ASIC

Winbond PIB Ethernet SCSI Universe

ISA Interrupts

VME Interrupts

To Power PC External Interrupt

A-41

Raven Interrupt Controller

• For this BSP, Raven ASIC controls all externalinterrupts:

• Four primary PCI bus interrupts.• Four secondary PCI bus interrupts.• One VME mailbox interrupt.

• Raven ASIC is capable of supporting sixteen distinctexternal interrupts (seven are not assigned for this BSP).

• ASIC supports 16 interrupt levels:• Interrupt request lines: IRQ15 - IRQ0.• Levels have priorities 15 (highest) to 0 (lowest).• Priority zero disables interrupt.

A-42

Raven Interrupt Controller - cont.

• Supported IRQs and relative priorities:

IRQ

IRQ0

IRQ5

IRQ3

IRQ10

IRQ9

IRQ11

IRQ2

IRQ14

IRQ12

Priority Source

8

14

3

10

7

6 (13)

5 (2)

4 (2)

15

Winbond PIB (ISA)

Ethernet

SCSI

Universe (VME)

PCI PMC INTA

PCI PMC INTB

PCI PMC INTC

PCI PMC INTD

VME mailbox 1

A-43

Raven Interrupt Controller - cont.

• Manufacturer assigned interrupt numbers:

Interrupt Number Source

0x10

0x12

0x13

0x15

0x19

0x1a

0x1b

0x1c

0x1e

Winbond PIB (ISA)

PCI Ethernet

PCI SCSI

Universe ASIC (VME)

PCI PMC INTA

PCI PMC INTB

PCI PMC INTC

PCI PMC INTD

VME mailbox 1

A-44

Winbond Interrupt Controller

• Handles all on-board ISA interrupts. Unit consist of twocoupled Intel 82C59A interrupt controllers providing 15distinct IRQ lines:

• First Intel 82C59A provides interrupt numbers 0 - 7,with interrupt number 2 as the cascaded interrupt tothe second Intel 82C59A.

• Second 82C59A provides interrupt numbers 8 - 15.• 15 interrupt priority levels. Due to cascading priority

levels map to vector numbers as follows (from highto low): 0x00, 0x01, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d,0x0e, 0x0f, 0x03, 0x04, 00x05, 0x06, and 0x07.

• Winbond can generate four PCI interrupts, only one isused to request service via the Raven ASIC.

A-45

• Winbond interrupt numbers and relative priorities:

Winbond Interrupt Controller - cont.

• Interrupt priorities range from 15 (highest) to 0 (lowest).

• Devices assigned to interrupt number 0x09 will need tobe demultiplexed in software:

• System interrupt table and serial ISR will handle this.

Interrupt Number SourcePriority

ISA cascade interrupt

Super I/O COM1

Super I/O COM2

Auxiliary clock, serialports 3 and 4 (Z85230)

0x02

0x04

0x03

0x09

4

3

12

--

A-46

Universe Chip

• The Universe chip handles all VME interrupts.• Configured as system arbiter via on-board jumper.

• Decouples VMEbus and PCI bus interrupters:• Resolves timing issues - VME bus is asynchronous,

PCI bus has maximum clock cycle limit forresponding to IACK transaction.

• If mv2604 board requests service from another VMEbackplane card:

• Universe chip will complete IACK cycle and placeSTATUS/ID on VMEbus.

• Manage PCI bus ACK for software generatedinterrupts (configurable).

A-47

Universe Chip - cont.

• If mv2604 board receives an interrupt request:• Universe chip completes IACK cycle and stores

STATUS/ID in dedicated register.• Asserts PCI interrupt via the Raven chip.

• One constraint, all STATUS/IDs must be even numbers.Least significant bit is masked for both requested andrequesting interrupt service.

• Universe will only transmit and respond to the sevenmost significant bits of a STATUS/ID.

• Note, VMEbus interrupt priority scheme cannot bemaintained as only one PCI interrupt line is connectedto the Raven chip.

A-48

System Interrupt Table

• System interrupt table will support up to 256 interruptservice routines. Interrupt number assignments:

Interrupt Numbers Source

ISA IRQ numbers (Winbond)

Raven timers.

Raven interprocessor dispatch.

Raven dectected internal errors.

User defined.

Universe interrupts.

User defined.

Raven interrupts - external devices.

0x00 - 0x0f

0x10 - 0x1f

0x20 - 0x23

0x24 - 0x27

0x28

0x29 - 0x55

0x56 - 0x5f

0x60 - 0xff

A-49

System Interrupt Table - cont.

• System interrupt table managed by Raven chip driver:• Provides system demultiplexer on exception table.• Provides hooks for intConnect(), intEnable(), and

intDisable().

• Each interrupt controller has its own demultiplexerroutine on the system interrupt table.

• Table is an array of linked lists:• Each array element corresponds to an interrupt

number.• If multiple interrupt services routines are connected

to the same interrupt number, they are stored on alinked list associated with that interrupt table arrayelement.

A-50

• System interrupt table declared as:INT_HANDLER_DESC * sysIntTbl [256];

• INT_HANDLER_DESC structure declared in ravenMpic.h:typedef struct intHandlerDesc

{VOIDFUNCPTR vec;int arg;struct intHandlerDesc * next;} INT_HANDLER_DESC;

• Structure members:• vec - Interrupt service routine.• arg - Optional argument for ISR.• next - Link list pointer to next INT_HANDLER_DESC

for interrupt numbers with multiple ISRs.

System Interrupt Table - cont.

A-51

System Interrupt Table Initialization

• System interrupt table is initialized by sysMpicInit()called by sysHwInit().

• Initializes elements of table to NULL.

• Connects system demultiplexer routine to the exceptiontable using excIntConnect():

• Routine is sysMpicIntHandler().

• Initializes hook routines for intArchLib:• sysMpicIntConnect()• sysMpicIntEnable()• sysMpicIntDisable()

• Initialization and demultiplexer code in ravenMpic.c.

A-52

Connecting Interrupts

• After the Wind kernel is activated intConnect() will callsysMpicIntConnect(). Both take the same arguments.

• sysMpicIntConnect() will:• First time it is called, connect the Winbond PIB PCI

interrupt.• Allocate memory for an INT_HANDLER_DESC

structure, and initialize structure.• Add element to interrupt table array. If element(s)

currently exist for this interrupt number, add newlinked list node.

• Check if interrupt is for the MPIC itself, if so convertto MPIC vector and store in appropriate MPIC vectorregister.

A-53

Connecting Interrupts - cont.

• The PCI Winbond PIB interrupt handler is the interruptdemultiplexer for ISA interrupts managed by theWinbond ASIC.

• Handler is installed by routine sysIbcMpicConnect()which calls intConnect() to put ISA demultiplexer onsystem interrupt table.

• Handler routine is sysIbcIntHandler().• Both handler and installation routines are in

ravenMpic.c.

• For this BSP the Universe chip VME demultiplexerroutine is placed on the system interrupt table by thefirst call to intConnect():

• ISA and VME demultiplexers are installed together.

A-54

System Interrupt Demultiplexer

• System interrupt demultipler routine,sysMpicIntHandler(), is connect to the PowerPC’ssingle external interrupt (exception 0x500).

• After WRS supplied PowerPC interrupt dispatch codeexecutes, system demultiplexer will:

• Read interrupt number from Raven MPIC.• Set EE bit of PowerPC MSR (allow nesting).• Call all routines from the system interrupt table

associated with interrupt number from MPIC.• Issue End Of Interrupt (EOI) code to MPIC.• Lock interrupts.

•WRS PowerPC exception code restores environment.

A-55

Example Interrupt

• As and example, consider series of events when Z85230SCC interrupt is generated:

• SCC requests interrupt service by asserting interruptnumber 0x09 on Winbond ASIC.

• Winbond registers interrupt (interrupt number 0x09),masks out lower priority interrupts (ISA level 12),and asserts PCI interrupt.

• Raven MPIC responds to PCI interrupt and masksout its lower priority interrupts (level 8 and lower).

• Raven MPIC asserts PowerPC external interrupt line.• PowerPC begins execution of WRS handler for

exception 0x500.

A-56

Example Interrupt - cont.

• WRS exception handler saves context, incrementsintCnt variable, and jumps to system interruptdemultiplexer routine.

• Demultiplexer reads interrupt number from MPIC.• Demultiplexer sets EE bit of PowerPC MSR.• Using interrupt number obtained from Raven MPIC

demultiplexer calls ISA interrupt demultiplexerroutine.

• ISA demultiplexer jumps to (first) ISR on systeminterrupt table element (interrupt number) 0x09.

• This routine is the Z8536CIO timer (auxiliary clock),which checks device and returns because devicestatus indicates it is not requesting service.

• Demultiplexer jumps to second link list element attable array element 0x09. This is the Z85230 ISR.

A-57

Example Interrupt - cont.

• Z85230 ISR determines which of its two channels arerequesting service, provides service, resets Z85230,and returns.

• ISA demultiplexer re-enables Winbond interrupt andreturns.

• No more ISRs for this interrupt number, so systemdemultiplexer issues EOI code to re-enable theWinbond PCI interrupt.

• System demultiplexer locks interrupts at theprocessor level (intLock()) before returning to WRSexception handler (restore state of system).

• Return to exception handler which decrementsintCnt variable, resets MSR, and restores savedcontext.

A-58

Interrupt Enable and Disable

• Raven MPIC supplies hook code for intEnable()/intDisable():

• sysMpicIntEnable()/sysMpicIntDisable().• Routines take interrupt level as sole argument, and

return STATUS.• Routines first check for legal interrupt level, and then:• Check if level corresponds to a ISA interrupt, if so

Winbond interrupt enable/disable routine is called.• For Raven MPIC interrupt, appropriate control

register is obtained from interrupt level, and registeris written to enable/disable interrupt.

• For enable/disable of ISA interrupts, Winbond codedetermines appropriate PIC and masks interrupt.

A-59


Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration

A-60

System Clock

• Example target uses on-processor timer for the systemclock.

• Uses PowerPC 604 decrementer timer.

• Decrement register is 64 bit counter driven from mainprocessor clock:

• Generates exception at rollover (counts down).• System clock period set by loading appropriate

decrement count value to count register.• Decrementer does not reload period count after

exception.• Driven by processor clock.• Decrementer exception disabled by setting EE bit of

MSR.

A-61

System Clock - cont.

• System clock timer library ../src/drv/timer/ppcDecTimer.c follows template. Notes:

• System clock “ISR” installed on system exceptiontable (excectption 0x900) not system interrupt table.

• Decrementer count value computed insysClkRateSet(), but reloaded to decrementer bytimer exception handler.

• Decrementer exception handler corrects for driftbetween exception generation and reload ofdecrementer count register.

• sysClkDisable() routine prevents system clockroutine from executing by setting sysClkRunning toFALSE. Does not disable decrement exception.

• Setting EE bit in MSR (external interrupts) disablesdecrementer exception.

A-62

Auxiliary Clock

• Target uses a Z8536CIO timer as auxiliary clock:• Chip supports three 16 bit counter/timers.• Timer 2 used for auxiliary clock.• Driven by 5 MHz clock input.

• Auxiliary clock driver follows template:• Code in ../src/drv/timer/ppcZ8536Timer.c• Macro INCLUDE_Z8536_AUXCLK must be defined

in config.h to identify Z8536CIO as auxiliary clock.

• If INCLUDE_Z8536_AUXCLK is defined, Z8536initialized and ISR installed in sysHwInit2():

• Routine name sysClkIntCIO().• Routine calls sysAuxClkInt().

A-63


Overview


sysHwInit()

Memory Maps

Interrupts

Timers

LAN Integration

A-64

DEC 21140 Ethernet Interface

• Environment:• Device sits on PCI bus.• Controller is little endian.

• Software interface divided into four parts:l• Initialization of PCI configuration registers.• Providing interrupt support.• Management of I/O control registers.• Management of device and network buffers.

• BSP handles PCI configuration and interrupt support:• Driver provides device ISRs.

• Ethernet driver handles the remaining portions of thedevice software interface.

A-65

BSP Device Support

• PCI configuration and interrupt support established insysHwInit().

• Call to pciDevConfig():• Intializes device I/O space base address to

PCI_IO_LN_ADRS (defined in mv2600.h).• Enables controllers I/O facilities.

• Call to sysMpicInit():• Initialized Raven interrupt controller.• Configures interrupt level priority (level 14 - IRQ2).• Configures interrupt number (0x12).

• Interrupt level and number (vector) defined inmv2600.h.

A-66

Driver Initialization

• LAN device initialization activated by call tousrNetInit() by tUsrRoot:

• All initialization performed by an driver attachroutine dcattach().

• Attach routine obtains configuration informationthrough its arguement list and uses it to initialize anetwork interface structure.

• Fixed BSP relevant parameters in mv2600.h:• LAN device address.• Memory base seen from PCI bus.• Device interrupt vector (number).• Device interrupt level.

A-67

Driver Initialization - cont.

• User configurable BSP relevant parameters in config.h:• Network memory pool address (malloc option).• Network memory pool size.• Byte with for data.• Mode of operation for device.

• Attach routine also:• Connects (demultiplexer) ISR for LAN device by

calling intConnect() initialized by BSP.• Configures cache strategy (DMA coherency).• Initializes device link layer buffers.• Initializes device control and status registers

(including imterrupt mask registers).• Enables interrupts.

A-68

Device Access

• Driver provides its own access to device registers overPCI bus:

• Command Status Register (CSR).• Receive transmit descriptor reads and writes.

• CSR example:#define READ_CSR(base,x)

(PCISWAP(*((ULONG *)CSR((base),(x)))))

• Driver uses memory to PCI bus address translationmacro routines supplied by BSP to access memory andI/O space:#define PCI_TO_MEM_PHYS(pciAdrs) \

((pciAdrs) - (pDrvCtrl->pciMemBase))


Core BSP Example Code

Appendix - B

B-2

Makefile1 # Makefile - makefile for bsp/config/mv26042 #3 # Copyright 1984-1997 Wind River Systems, Inc.4 # Copyright 1996 Motorola, Inc.5 #6 # modification history7 # --------------------8 # 01e,11jun97,mas changed bootrom_uncmp.hex to bootrom.hex for standard

RELEASE9 # 01f,18feb97,dat removed dcCsr.obj, not needed10 # 01e,10jan97,dat added CPU=PPC604 to dec21140 make rule11 # 01d,13dec96,mas upgraded for Motorola 2600 BSP (SPR 7525).12 # 01c,05mar96,tpr changed -DULTRA by -DMV1600.13 # 01b,04mar96,tpr added EXTRA_DEFINE .14 # 01a,28nov95,tpr written from bsp/mv167/Makefile 01h version.15 #16 # DESCRIPTION17 # This file contains rules for building VxWorks for the18 # Motorola MVME2600 board with a PowerPC 604 processor.19 #20 # INCLUDES21 # makeTarget22 #*/2324 CPU = PPC60425 TOOL = gnu2627 TGT_DIR=$(WIND_BASE)/target28 include $(TGT_DIR)/h/make/defs.bsp29 include $(TGT_DIR)/h/make/make.$(CPU)$(TOOL)30 include $(TGT_DIR)/h/make/defs.$(WIND_HOST_TYPE)3132 ## Only redefine make definitions below this point, or your definitions will33 ## be overwritten by the makefile stubs above.343536 TARGET_DIR= mv260437 VENDOR = Motorola38 BOARD = MVME26003940 EXTRA_DEFINE = -DMV2600 -DTARGET_DIR=”\”$(TARGET_DIR)\””4142 RELEASE = make.dec21140 vxWorks vxWorks.st bootrom.hex4344 USR_ENTRY = usrInit4546 #47 # The constants ROM_TEXT_ADRS, ROM_SIZE, and RAM_HIGH_ADRS are defined

B-3

48 # in config.h, MakeSkel, Makefile , and Makefile .*49 # All definitions for these constants must be identical.50 #5152 ROM_TEXT_ADRS= fff00100 # ROM entry address53 ROM_SIZE= 00080000 # number of bytes of ROM space5455 RAM_LOW_ADRS= 00100000 # RAM text/data address56 RAM_HIGH_ADRS= 00200000 # RAM text/data address5758 HEX_FLAGS= -a 1005960 MACH_EXTRA= dec21140.obj61626364 ## Only redefine make definitions above this point, or the expansion of65 ## makefile target dependencies may be incorrect.6667 include $(TGT_DIR)/h/make/rules.bsp68 include $(TGT_DIR)/h/make/rules.$(WIND_HOST_TYPE)6970 make.dec21140:71 (cd ./dec21140; $(MAKE) CPU=PPC604 DIR=$(TGT_DIR)/config/$(TARGET_DIR)

objs)72

B-4

romInit.s

1 /* romInit.s - Motorola MVME2600 ROM initialization module */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 /* Copyright 1996-1997 Motorola, Inc. */5 .data6 .globl copyright_wind_river7 .long copyright_wind_river89 /*10 modification history11 --------------------12 01f,25jul97,srr/ added 604r (Mach 5) support (SPR 8911).13 mas14 01e,29may97,srr Chg RAVEN #defines to support vxMemProbe and replace15 hardcoded values where appropriate. (MCG MR#67,69)16 SPRs 8289, 8560.17 01d,06may97,mas added extended VME support (SPR 8410).18 01c,24apr97,mas added Motorola MPIC support (SPR 8170).19 01b,02jan97,dat mod history fix20 01a,01sep96,mot written. (from mv1603/romInit.s, ver 01l)21 */2223 /*24 DESCRIPTION25 This module contains the entry code for the VxWorks bootrom.26 The entry point romInit, is the first code executed on power-up.27 It sets the BOOT_COLD parameter to be passed to the generic28 romStart() routine.2930 The routine sysToMonitor() jumps to the location 4 bytes31 past the beginning of romInit, to perform a “warm boot”.32 This entry point allows a parameter to be passed to romStart().3334 This code is intended to be generic across PowerPC 603/604 boards.35 Hardware that requires special register setting or memory36 mapping to be done immediately, may do so here.37 */3839 #define_ASMLANGUAGE40 #include “vxWorks.h”41 #include “sysLib.h”42 #include “asm.h”43 #include “config.h”44 #include “regs.h”4546 /* Exported internal functions */4748 .globl_romInit/* start of system code */49 .globlromInit /* start of system code */

B-5

5051 /* externals */5253 .extern romStart/* system initialization routine */5455 .text56 .align 2575859 /

************************************************************************60 *61 * romInit - entry point for VxWorks in ROM62 *6364 * romInit65 * (66 * int startType/@ only used by 2nd entry point @/67 * )6869 */7071 _romInit :72 romInit :7374 bl cold7576 bl warm7778 /* copyright notice appears at beginning of ROM (in TEXT segment) */7980 .ascii “Copyright 1984-1997 Wind River Systems, Inc.”81 .align 28283 cold:84 li r11, BOOT_COLD85 bl start /* skip over next instruction */868788 warm:89 or r11, r3, r3/* startType to r11 */9091 start:92 /*93 * Zero-out registers94 *95 */96 addis r0,r0,097 mtspr 272,r098 mtspr 273,r099 mtspr 274,r0100 mtspr 275,r0

B-6

101102 /* initialize the stack pointer */103104 lis sp, HIADJ(STACK_ADRS)105 ori sp, sp, LO(STACK_ADRS)106107 /*108 * Set MPU/MSR to a known state109 * Turn on FP110 */111112 andi.r3, r3, 0113 ori r3, r3, 0x2000114 sync115 mtmsr r3116 isync117118 /* Init the floating point control/status register */119120 mtfsfi 7,0x0121 mtfsfi 6,0x0122 mtfsfi 5,0x0123 mtfsfi 4,0x0124 mtfsfi 3,0x0125 mtfsfi 2,0x0126 mtfsfi 1,0x0127 mtfsfi 0,0x0128 isync129130 /*131 * Set MPU/MSR to a known state132 * Turn off FP133 */134135 andi.r3, r3, 0136 sync137 mtmsr r3138 isync139140 /* Init the Segment registers */141142 andi.r3, r3, 0143 isync144 mtsr 0,r3145 isync146 mtsr 1,r3147 isync148 mtsr 2,r3149 isync150 mtsr 3,r3151 isync152 mtsr 4,r3

B-7

153 isync154 mtsr 5,r3155 isync156 mtsr 6,r3157 isync158 mtsr 7,r3159 isync160 mtsr 8,r3161 isync162 mtsr 9,r3163 isync164 mtsr 10,r3165 isync166 mtsr 11,r3167 isync168 mtsr 12,r3169 isync170 mtsr 13,r3171 isync172 mtsr 14,r3173 isync174 mtsr 15,r3175 isync176177 #ifndef MV2300178 /* Turn off the GLANCE - L2 Cache */179180 lis r3, HIADJ(MV2600_SXCCR_A)181 ori r3, r3, LO(MV2600_SXCCR_A)182 addisr4, r0, 0x0183 ori r4, r4, 0x0070184 stb r4, 0x0(r3)185 #endif /* MV2300 */186187 /* Turn off data and instruction cache control bits */188189 mfspr r3, HID0190 isync191 rlwinmr4, r3, 0, 18, 15/* r4 has ICE and DCE bits cleared */192 sync193 isync194 mtsprHID0, r4 /* HID0 = r4 */195 isync196197 /* Getcpu type */198199 mfspr r28, PVR200 rlwinm r28, r28, 16, 16, 31201202 /* invalidate the MPU’s data/instruction caches */203204 lis r3, 0x0

B-8

205 cmpli0, 0, r28, CPU_TYPE_603206 beq CPU_IS_603207 cmpli0, 0, r28, CPU_TYPE_603E208 beq CPU_IS_603209 cmpli 0, 0, r28, CPU_TYPE_603P210 beq CPU_IS_603211 cmpli 0, 0, r28, CPU_TYPE_604R212 bne CPU_NOT_604R213214 CPU_IS_604R:215 lis r3, 0x0216 mtspr HID0, r3 /* disable the caches */217 isync218 ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */219220 CPU_NOT_604R:221 ori r3, r3, 0x0C00/* r3 has invalidate bits set */222 CPU_IS_603:223 ori r3, r3, 0xC000/* r3 has enable and bits set */224 or r4, r4, r3/* set bits */225 sync226 isync227 mtspr HID0, r4/* HID0 = r4 */228 andc r4, r4, r3/* clear bits */229 isync230 cmpli 0, 0, r28, CPU_TYPE_604231 beq CPU_IS_604232 cmpli 0, 0, r28, CPU_TYPE_604E233 beq CPU_IS_604234 cmpli 0, 0, r28, CPU_TYPE_604R235 beq CPU_IS_604236 mtsprHID0, r4237 isync238239 #ifdef USER_I_CACHE_ENABLE240 b I_CACHE_ON_603241 #else242 b CACHE_ENABLE_DONE243 #endif244245 CPU_IS_604:246 lis r5, 0x0247 ori r5, r5, 0x1000248 mtsprCTR, r5249 LOOP_DELAY:250 nop251 bdnz LOOP_DELAY252 isync253 mtspr HID0, r4254 isync255256 /* turn the Instruction cache ON for faster FLASH ROM boots */

B-9

257258 #ifdef USER_I_CACHE_ENABLE259260 ori r4, r4, 0x8800/* set ICE & ICFI bit */261 isync /* Synchronize for ICE enable */262 b WRITE_R4263 I_CACHE_ON_603:264 ori r4, r4, 0x8800/* set ICE & ICFI bit */265 rlwinm r3, r4, 0, 21, 19/* clear the ICFI bit */266267 /*268 * The setting of the instruction cache enable (ICE) bit must be269 * preceded by an isync instruction to prevent the cache from being270 * enabled or disabled while an instruction access is in progress.271 */272 isync273 WRITE_R4:274 mtspr HID0, r4 /* Enable Instr Cache & Inval cache */275 cmpli 0, 0, r28, CPU_TYPE_604276 beq CACHE_ENABLE_DONE277 cmpli 0, 0, r28, CPU_TYPE_604E278 beq CACHE_ENABLE_DONE279 cmpli 0, 0, r28, CPU_TYPE_604R280 beq CACHE_ENABLE_DONE281282 mtspr HID0, r3 /* using 2 consec instructions */283 /* PPC603 recommendation */284 #endif285 CACHE_ENABLE_DONE:286287 /*288 This following contains the entry code for the initialization code289 for the Raven, a Host PCI Bridge/Memory Controller used in290 Motorola’s PowerPC based boards.291 */292293 /*294 # Initialize the RAVEN MPC registers.295 # notes:296 # 1. For the standard vxWorks configuration the MPC to297 # PCI mapping registers are298 # initialized to the PReP model with some additions:299 #300 # MPC Address Range PCI Address Range Definition301 # ----------------- ----------------- ------------------------302 # 80000000 BF7FFFFF00000000 3F7FFFFFISA/PCI I/O space303 # C0000000 FCFFFFFF00000000 3CFFFFFFISA/PCI Mem space w/MPIC304 # FD000000 FDFFFFFF00000000 00FFFFFFISA/PCI Mem space305 # FE000000 FE7FFFFF00000000 007FFFFFISA/PCI I/O space306 #307 # 2. This assignments do not include the entire PReP PCI308 # address space, this is due to the conflicting local

B-10

309 # resources of the H/W.310 #311 # 3. When EXTENDED_VME is defined the mapping is as follows:312 #313 # MPC Address Range PCI Address Range Definition314 # --------------------------- --------------------------- --------------------

-315 # VME_A32_MSTR_LOCAL FBFFFFFF VME_A32_MSTR_LOCAL FBFFFFFF VME address space316 # FC000000 FCFFFFFF FC000000 FCFFFFFF MPIC/Reg space317 # FD000000 FDFFFFFF FD000000 FDFFFFFF ISA/PCI Memory space318 # FE000000 FE7FFFFF 00000000 007FFFFF ISA/PCI I/O space319 #320 */321 lis r3, HIADJ(RAVEN_BASE_ADRS)322 ori r3, r3, LO(RAVEN_BASE_ADRS)323324 addisr4,r0,0x0000/* GCSR:FLBRD=0,MBT=256us */325 ori r4,r4,0x0000/* GCSR:FLBRD=0,MBT=256us */326 sth r4,RAVEN_MPC_GCSR(r3)/* write GCSR */327 eieio /* synchronize */328 sync /* synchronize */329330 addisr4,r0,0x0000/* MARB:BRENx=1,PKEN=0,PKMD=0,DEFMx=1 */331 ori r4,r4,0x0703/* MARB:BRENx=1,PKEN=0,PKMD=0,DEFMx=1 */332 sth r4,RAVEN_MPC_MARB(r3)/* write MARB */333 eieio /* synchronize */334 sync /* synchronize */335336 addisr4,r0,0x0000/* PADJ:BE=66MHZ */337 ori r4,r4,0x00BE/* PADJ:BE=66MHZ */338 stb r4,RAVEN_MPC_PADJ(r3)/* write PADJ */339 eieio /* synchronize */340 sync /* synchronize */341342 addisr4,r0,0x0000/* MEREN:(all error enables disabled) */343 ori r4,r4,0x0000/* MEREN:(all error enables disabled) */344 sth r4,RAVEN_MPC_MEREN(r3)/* write MEREN */345 eieio /* synchronize */346 sync /* synchronize */347348 addisr4,r0,0x0000/* MERST:(clear all error status) */349 ori r4,r4,0x00ff/* MERST:(clear all error status) */350 stb r4,RAVEN_MPC_MERST(r3)/* write MERST */351 eieio /* synchronize */352 sync /* synchronize */353354 addisr4,r0,0x0000/* MSATTx:(all attributes disabled) */355 ori r4,r4,0x0000/* MSATTx:(all attributes disabled) */356 stb r4,RAVEN_MPC_MSATT0(r3)/* write MSATT0 */357 eieio /* synchronize */358 sync /* synchronize */359 stb r4,RAVEN_MPC_MSATT1(r3)/* write MSATT1 */

B-11

360 eieio /* synchronize */361 sync /* synchronize */362 stb r4,RAVEN_MPC_MSATT2(r3)/* write MSATT2 */363 eieio /* synchronize */364 sync /* synchronize */365 stb r4,RAVEN_MPC_MSATT3(r3)/* write MSATT3 */366 eieio /* synchronize */367 sync /* synchronize */368369 addisr4,r0,CPU2PCI_ADDR0_START/* MSADD0: */370 ori r4,r4,CPU2PCI_ADDR0_END/* MSADD0: */371 stw r4,RAVEN_MPC_MSADD0(r3)/* write MSADD0 */372 eieio /* synchronize */373 sync /* synchronize */374375 addisr4,r0,0x0000/* MSOFF0: */376 ori r4,r4,CPU2PCI_OFFSET0/* MSOFF0: */377 sth r4,RAVEN_MPC_MSOFF0(r3)/* write MSOFF0 */378 eieio /* synchronize */379 sync /* synchronize */380381 addisr4,r0,0x0000/* MSATT0: */382 ori r4,r4,CPU2PCI_MSATT0/* MSATT0: */383 stb r4,RAVEN_MPC_MSATT0(r3)/* write MSATT0 */384 eieio /* synchronize */385 sync /* synchronize */386387 addisr4,r0,CPU2PCI_ADDR1_START/* MSADD1: */388 ori r4,r4,CPU2PCI_ADDR1_END/* MSADD1: */389 stw r4,RAVEN_MPC_MSADD1(r3)/* write MSADD1 */390 eieio /* synchronize */391 sync /* synchronize */392393 addisr4,r0,0x0000/* MSOFF1: */394 ori r4,r4,CPU2PCI_OFFSET1/* MSOFF1: */395 sth r4,RAVEN_MPC_MSOFF1(r3)/* write MSOFF1 */396 eieio /* synchronize */397 sync /* synchronize */398399 addisr4,r0,0x0000/* MSATT1: */400 ori r4,r4,CPU2PCI_MSATT1/* MSATT1: */401 stb r4,RAVEN_MPC_MSATT1(r3)/* write MSATT1 */402 eieio /* synchronize */403 sync /* synchronize */404405 addisr4,r0,CPU2PCI_ADDR2_START/* MSADD2: */406 ori r4,r4,CPU2PCI_ADDR2_END/* MSADD2: */407 stw r4,RAVEN_MPC_MSADD2(r3)/* write MSADD2 */408 eieio /* synchronize */409 sync /* synchronize */410411 addisr4,r0,0x0000/* MSOFF2: */

B-12

412 ori r4,r4,CPU2PCI_OFFSET2/* MSOFF2: */413 sth r4,RAVEN_MPC_MSOFF2(r3)/* write MSOFF2 */414 eieio /* synchronize */415 sync /* synchronize */416417 addisr4,r0,0x0000/* MSATT2: */418 ori r4,r4,CPU2PCI_MSATT2/* MSATT2: */419 stb r4,RAVEN_MPC_MSATT2(r3)/* write MSATT2 */420 eieio /* synchronize */421 sync /* synchronize */422423 /*424 * PCI address space 3 registers supports config. space access and425 * special cycle generation. It should be configured for I/O space.426 */427428 addisr4,r0,CPU2PCI_ADDR3_START/* MSADD3: */429 ori r4,r4,CPU2PCI_ADDR3_END/* MSADD3: */430 stw r4,RAVEN_MPC_MSADD3(r3)/* write MSADD3 */431 eieio /* synchronize */432 sync /* synchronize */433434 addisr4,r0,0x0000/* MSOFF3: */435 ori r4,r4,CPU2PCI_OFFSET3/* MSOFF3: */436 sth r4,RAVEN_MPC_MSOFF3(r3)/* write MSOFF3 */437 eieio /* synchronize */438 sync /* synchronize */439440 addisr4,r0,0x0000/* MSATT3: */441 ori r4,r4,CPU2PCI_MSATT3/* MSATT3: */442 stb r4,RAVEN_MPC_MSATT3(r3)/* write MSATT3 */443 eieio /* synchronize */444 sync /* synchronize */445446 /* End of Raven Init */447448 /*449 * Do the init for the SIO, now that the Raven is configured.450 * This was moved after the Raven init for the Extended VME config.451 */452453 #ifndef MV2300454 bl .sioInit455 #endif /* MV2300 */456457 /*458 # DRAM Initialization/Sizing for FALCON Module459 # Initialize the FALCON (DRAM Controller) registers.460 # The registers are initialized with values from the461 # results of the probe (see below).462 #463 # algorithm:

B-13

464 #465 # Each memory bank size that is possible is tried. This starts466 # with the largest to the smallest. A table is used to inform467 # the sizing code of the needed information. The information468 # consists of the memory bank size, probe addresses, and the data469 # pattern associated with each of the probe address. All off the470 # probe addresses are written to first with associative write data471 # pattern, then they are read. An exact match of the data is472 # required to deem the memory bank size has been found.473 #474 # Size Key Address Lines475 # 40000000 (1GB)A2476 # 10000000 (256MB)A4/A6477 # 08000000 (128MB)A5/A6/A18478 # 04000000 (64MB)A6/A18479 # 02000000 (32MB)A7/A18/A19480 # 01000000 (16MB)N/A481 #482 # As you can see, this algorithm is coupled very tightly with the483 # H/W, if it ever changes, this algorithm will need to be modified.484 #485 # register-usage:486 # r1 = SP (not modified)487 # r2 = TOC (not modified)488 # r3 = size of DRAM in bytes489 # r4 = DRAM attributes register address490 # r5 = DRAM base-address register address491 # r6 = test pattern’s table pointer492 # r7 = DRAM bank index (0 to 3)493 # r8-r10,r12-r19= run-time (scratch)494 # r11 = VxWorks495 # r20 = saved return instruction pointer496 # r21 = verify error flag497 # r22 = FALCON base address498 # r23 = run-time (scratch)499 #500 */501502 .set NBANKS,4 /* number of DRAM banks */503504 addisr0,r0,0 /* insure r0 is zero */505 ori r0,r0,0 /* insure r0 is zero */506 or r3,r0,r0 /* set to no memory present state */507 mfsprr20,8 /* save return instruction pointer */508509 bl .falcon_i_ra/* branch around tables */510 /*511 DRAM controller register addresses table512 */513 .longFALCON_BASE_ADRS514 .longDRAM_REG_BASE/* DRAM base-address register addr */515 .longDRAM_REG_SIZE/* DRAM attributes register address */

B-14

516517 .falcon_i_ra:518 mfsprr4,8 /* load pointer to table */519 /*520 load register address values521 */522 lwz r8,0x00(r4)/* FALCON register base address */523 lwz r5,0x04(r4)/* DRAM base-address register address */524 lwz r4,0x08(r4)/* DRAM attributes register address */525 or r22,r8,r8/* save it for later use */526527 eieio /* synchronize the data stream */528 sync /* synchronize the data stream */529530 /*531 initialize to DRAM control registers to a known state532 */533534 /* get the DRAM speed (RSPD, in r3) */535536 lis r9, HIADJ(MV2600_MCR_)/* load address of Mem Config Reg */537 ori r9, r9, LO(MV2600_MCR_)538 lwz r9, 0(r9)539 lis r0, HIADJ(MV2600_MCR_MSK)/* load mask for DRAM speed */540 ori r0, r0, LO(MV2600_MCR_MSK)541 and r9, r9, r0542543 lis r0, HIADJ(MV2600_DRAM_60ns)/* load value for 60 ns DRAM */544 ori r0, r0, LO(MV2600_DRAM_60ns)545 cmpw 1, r9, r0546 bc 12, 6, dram60ns547548 lis r0, HIADJ(MV2600_DRAM_50ns)/* load value for 50 ns DRAM */549 ori r0, r0, LO(MV2600_DRAM_50ns)550 cmpw 1, r9, r0551 bc 12, 6, dram50ns552 li r3, DRAM_70ns /* default: 70 ns */553 b endDramSpd554555 dram60ns:556 li r3, DRAM_60ns557 b endDramSpd558 dram50ns:559 li r3, DRAM_50ns560561 endDramSpd:562 lis r9, HIADJ(MV2600_MCR_)/* load address of Mem Config Reg */563 ori r9, r9, LO(MV2600_MCR_)564 lwz r9,0(r9) /* read Memory Configuration Register */565 eieio /* data synchronize */566 sync /* data synchronize */567 rlwinmr9,r9,7,28,28 /* mask off all but the M_FREF bit */

B-15

568569 or r9,r3,r9 /* IHEN=0,ADIS=0,RFREF=M_FREF */570 stw r9,0x08(r8) /* general control register */571 eieio /* synchronize the data stream */572 sync /* synchronize the data stream */573574 /* get bus speed in MHZ, r3 has value */575576 lis r9, HIADJ(MV2600_CCR_)/* load address of System Config Reg */577 ori r9, r9, LO(MV2600_CCR_)578 lwz r9, 0(9)579 lis r0, HIADJ(MV2600_CCR_CLK_MSK)/* load mask for bus speed */580 ori r0, r0, LO(MV2600_CCR_CLK_MSK)581 and r9, r9, r0582583 lis r0, HIADJ(MV2600_CCR_CPU_CLK_60)/* load value for 60 */584 ori r0, r0, LO(MV2600_CCR_CPU_CLK_60)585 cmpw 1, r9, r0586 bc 12, 6, bus60mhz587588 lis r0, HIADJ(MV2600_CCR_CPU_CLK_50)/* load value for 50 */589 ori r0, r0, LO(MV2600_CCR_CPU_CLK_50)590 cmpw 1, r9, r0591 bc 12, 6, bus50mhz592 li r3, 67 /* default: 67 MHz */593 b endBusSpd594595 bus60mhz:596 li r3, 60597 b endBusSpd598 bus50mhz:599 li r3, 50600601 endBusSpd:602 slwi r3,r3,24 /* move to upper byte */603 stw r3,0x20(r8)/* CLK frequency register */604 eieio /* synchronize the data stream */605 sync /* synchronize the data stream */606607 addisr9,r0,0x0000/* SWEN=0,RTEST=000 */608 ori r9,r9,0x0000/* SWEN=0,RTEST=000 */609 stw r9,0x40(r8)/* DRAM scrub/refresh register */610 eieio /* synchronize the data stream */611 sync /* synchronize the data stream */612613 addisr9,r0,0x0100/* RWCB=0,DERC=1,xIEN=0,MCKEN=0 */614 ori r9,r9,0x0000/* RWCB=0,DERC=1,xIEN=0,MCKEN=0 */615 stw r9,0x28(r8)/* DRAM ECC control register */616 eieio /* synchronize the data stream */617 sync /* synchronize the data stream */618619 addisr9,r0,0x8000/* ELOG=1,ESEN=0,SCOF=1 */

B-16

620 ori r9,r9,0x0100/* ELOG=1,ESEN=0,SCOF=1 */621 stw r9,0x30(r8)/* DRAM ECC error-logger register */622 eieio /* synchronize the data stream */623 sync /* synchronize the data stream */624625 bl .falcon_i_ tp/* branch around tables */626 /*627 write-addresses/data-patterns table (address/hi-data/lo-data)628 */629 .set DRAM_SIZE1,0/* size index */630 .set DRAM_ATTR1,4/* attributes index */631 .set DRAM_CHCK1,8/* address/pattern starting index */632 .set TBLEND,-1/* table end marker */633 /*634 1GB635 */636 .long0x40000000,0x06637 .long0x00000000,0x01010101,0xFEFEFEFE638 .long0x20000000,0x02020202,0xFDFDFDFD639 .long-1 /* table entry end */640 /*641 256MB642 */643 .long0x10000000,0x05644 .long0x00000000,0x03030303,0xFCFCFCFC645 .long0x02000000,0x04040404,0xFBFBFBFB646 .long0x08000000,0x05050505,0xFAFAFAFA647 .long0x0A000000,0x06060606,0xF9F9F9F9648 .long-1 /* table entry end */649 /*650 128MB651 */652 .long0x08000000,0x04653 .long0x00000000,0x07070707,0xF8F8F8F8654 .long0x00002000,0x08080808,0xF7F7F7F7655 .long0x02000000,0x09090909,0xF6F6F6F6656 .long0x02002000,0x0A0A0A0A,0xF5F5F5F5657 .long0x04000000,0x0B0B0B0B,0xF4F4F4F4658 .long0x04002000,0x0C0C0C0C,0xF3F3F3F3659 .long0x06000000,0x0D0D0D0D,0xF2F2F2F2660 .long0x06002000,0x0E0E0E0E,0xF1F1F1F1661 .long-1 /* table entry end */662 /*663 64MB664 */665 .long0x04000000,0x03666 .long0x00000000,0x0F0F0F0F,0xF0F0F0F0667 .long0x00002000,0x10101010,0xEFEFEFEF668 .long0x02000000,0x11111111,0xEEEEEEEE669 .long0x02002000,0x12121212,0xEDEDEDED670 .long-1 /* table entry end */671 /*

B-17

672 32MB673 */674 .long0x02000000,0x02675 .long0x00000000,0x13131313,0xECECECEC676 .long0x00001000,0x14141414,0xEBEBEBEB677 .long0x00002000,0x15151515,0xEAEAEAEA678 .long0x00003000,0x16161616,0xE9E9E9E9679 .long0x01000000,0x17171717,0xE8E8E8E8680 .long0x01001000,0x18181818,0xE7E7E7E7681 .long0x01002000,0x19191919,0xE6E6E6E6682 .long0x01003000,0x1A1A1A1A,0xE5E5E5E5683 .long-1 /* table entry end */684 /*685 16MB686 */687 .long0x01000000,0x01688 .long0x00000000,0x1B1B1B1B,0xE4E4E4E4689 .long-1 /* table entry end */690691 .long-1 /* table end */692693 .falcon_i_ tp:694 mfsprr6,8 /* load pointer to table */695 /*696 disable all DRAM banks and set to “block not present” size697 set all DRAM banks base-address register to zero698 */699 addi r7,r0,0 /* clear DRAM bank index register */700 addi r8,r0,0x00/* disable and set to no-size */701 .falcon_i_ks:702 stbx r8,r7,r4 /* write DRAM attributes register */703 stbx r0,r7,r5 /* write DRAM bank base-address reg */704 addi r7,r7,1 /* increment bank index */705 cmpli0,0,r7,NBANKS/* are we done yet? */706 bc 4,2,.falcon_i_ks/* if not equal, no, branch */707 /*708 probe for the existance of all possible DRAM banks709710 on a DRAM bank basis, the DRAM bank is enabled with the size711 as specified by the current table entry, then perform the data712 writes at the specified addresses as specified by the current table713 entry, then read and verify the locations written with the714 expected data715716 following each probe the DRAM bank will be disabled, if the DRAM717 bank is present, its attributes register will be initialized to718 the size found (i.e., size-encoding bits set to proper state)719 */720 addi r23,r0,TBLEND/* setup table end indicator */721 addi r7,r0,0 /* clear DRAM bank index register */722 .falcon_i_pp:723 or r19,r6,r6/* copy pointer to table */

B-18

724 or r10,r6,r6/* copy pointer to table */725 /*726 write test data patterns (as specified by the current table entry)727 */728 .falcon_i_pp_i:729 or r19,r10,r10/* copy current table entry pointer */730 addi r21,r0,0 /* clear verify error flag */731 lwz r14,DRAM_ATTR1(r10)/* load DRAM attributes(encoded size)*/732 ori r14,r14,0x80/* set bank enable bit */733 stbx r14,r7,r4/* write DRAM attributes register */734 eieio /* data synchronize */735 sync /* data synchronize */736 addi r10,r10,DRAM_CHCK1/* move pointer to data patterns */737 .falcon_i_pp_w:738 lwz r12,0(r10)/* load write data pattern address */739 lwz r13,4(r10)/* load write data pattern hi */740 lwz r14,8(r10)/* load write data pattern lo */741 eieio /* data synchronize */742 sync /* data synchronize */743 stw r13,0(r12)/* write data pattern hi */744 eieio /* data synchronize */745 sync /* data synchronize */746 stw r14,4(r12)/* write data pattern lo */747 eieio /* data synchronize */748 sync /* data synchronize */749 addi r10,r10,12/* increment to next address */750 lwz r12,0(r10)/* load write data pattern address */751 cmpl 0,0,r12,r23/* check for table entry end */752 bc 4,2,.falcon_i_pp_w/* if not equal, no, branch */753754 or r10,r19,r19/* copy current table entry pointer */755 addi r10,r10,DRAM_CHCK1/* move pointer to data patterns */756 .falcon_i_pp_r:757 lwz r12,0(r10)/* load write data pattern address */758 lwz r13,4(r10)/* load write data pattern hi */759 lwz r14,8(r10)/* load write data pattern lo */760 eieio /* data synchronize */761 sync /* data synchronize */762 lwz r15,0(r12)/* read data pattern hi */763 eieio /* data synchronize */764 sync /* data synchronize */765 lwz r16,4(r12)/* read data pattern lo */766 eieio /* data synchronize */767 sync /* data synchronize */768 cmpl 0,0,r13,r15/* do they verify? */769 bc 4,2,.falcon_i_pp_f/* if not equal, no, branch */770 cmpl 0,0,r14,r16/* do they verify? */771 bc 4,2,.falcon_i_pp_f/* if not equal, no, branch */772 b .falcon_i_pp_p/* verification passed */773 .falcon_i_pp_f:774 addi r21,r21,1/* increment verify error flag */775 .falcon_i_pp_p:

B-19

776 addi r10,r10,12/* increment to next address */777 lwz r12,0(r10)/* load write data pattern address */778 cmpl 0,0,r12,r23/* check for table entry end */779 bc 4,2,.falcon_i_pp_r/* if not equal, no, branch */780781 addi r10,r10,4/* increment to one pass the end */782 cmpli0,0,r21,0/* any errors? */783 bc 4,2,.falcon_i_pp_d/* if not equal, yes, branch */784 lbzx r8,r7,r4 /* read DRAM attributes register */785 eieio /* data synchronize */786 sync /* data synchronize */787 andi.r8,r8,0x7F/* mask off the bank enable bit */788 stbx r8,r7,r4 /* write DRAM attributes register */789 eieio /* data synchronize */790 sync /* data synchronize */791 b .falcon_i_pp_n/* branch to bank by bank loop control*/792793 .falcon_i_pp_d:794 addi r8,r0,0x00/* disable and set to no-size */795 stbx r8,r7,r4 /* write DRAM attributes register */796 eieio /* data synchronize */797 sync /* data synchronize */798 lwz r12,0(r10)/* load write data pattern address */799 cmpl 0,0,r12,r23/* check for table end */800 bc 4,2,.falcon_i_pp_i/* if not equal, no, branch */801802 .falcon_i_pp_n:803 addi r7,r7,1 /* increment bank index */804 cmpli0,0,r7,NBANKS/* are we done yet? */805 bc 4,2,.falcon_i_pp/* if not equal, no, branch */806 /*807 at this point the DRAM bank attributes registers will be initialized808 to the size-encoding of the DRAM which is present (i.e., probed),809 else the DRAM attributes registers contain zero indicating no DRAM810 was found811812 the DRAM that was found must be aligned to a boundary of its size813814 the following code will begin allocating memory address spaces815 starting with the largest first, and working itself to the816 smallest817818 memory will start address zero819 */820 bl .falcon_i_ tp_s/* branch around tables */821 .long0x40000000,0x00000006/* 1024MB */822 .long0x10000000,0x00000005/* 256MB */823 .long0x08000000,0x00000004/* 128MB */824 .long0x04000000,0x00000003/* 64MB */825 .long0x02000000,0x00000002/* 32MB */826 .long0x01000000,0x00000001/* 16MB */827 .longTBLEND /* table entry end */

B-20

828829 .falcon_i_tp_s:830 mfsprr6,8 /* load pointer to table */831 or r10,r6,r6/* copy table pointer */832 addi r23,r0,TBLEND/* setup table end indicator */833 addi r12,r0,0 /* clear table index counter */834 or r13,r0,r0/* memory base address (zero) */835 .falcon_i_sz:836 addi r7,r0,0 /* clear DRAM bank index register */837 lwz r8,DRAM_ATTR1(r10)/* load DRAM attributes for this entry*/838 .falcon_i_sz_b:839 lbzx r9,r7,r4 /* read DRAM attributes register */840 andi.r9,r9,0x7/* mask off unwanted data bits */841 cmpl 0,0,r8,r9/* do the attributes match? */842 bc 4,2,.falcon_i_sz_no/* if not equal, no, branch */843844 rlwinmr9,r13,8,8,31/* extract PowerPC A0-A7 bits */845 stbx r9,r7,r5 /* write DRAM bank base-address reg */846 eieio /* data synchronize */847 sync /* data synchronize */848 lbzx r9,r7,r4 /* read DRAM attributes register */849 ori r9,r9,0x80/* set bank enable bit */850 stbx r9,r7,r4 /* write DRAM attributes register */851 eieio /* data synchronize */852 sync /* data synchronize */853 lwz r9,DRAM_SIZE1(r10)/* load DRAM size for this entry */854 add r3,r3,r9 /* add to the global size (returned)*/855 add r13,r13,r9/* add it to the memory base address */856857 .falcon_i_sz_no:858 addi r7,r7,1 /* increment bank index */859 cmpli0,0,r7,NBANKS/* are we done yet? */860 bc 4,2,.falcon_i_sz_b/* if not equal, no, branch */861862 addi r10,r10,8/* increment to next table entry */863 lwz r14,0(r10)/* load memory size variable */864 cmpl 0,0,r14,r23/* check for table end */865 bc 4,2,.falcon_i_sz/* if not equal, no, branch */866 /*867 work-around for a scrubber/refresh logic bug868 */869 lwz r4,0x10(r22)/* copy the bank enables/sizes reg */870 eieio /* data synchronize */871 sync /* data synchronize */872 addisr5,r0,0 /* gimme a zero */873 stw r5,0x10(r22)/* disable all, set sizes to zero */874 eieio /* data synchronize */875 sync /* data synchronize */876 stw r5,0x48(r22)/* clr ROW/COL addr of refresh/scrub */877 eieio /* data synchronize */878 sync /* data synchronize */879 stw r4,0x10(r22)/* restore the bank enables/sizes reg */

B-21

880 eieio /* data synchronize */881 sync /* data synchronize */882883 /* End of Falcon Init */884885 /* workaround for Extended VME config. with 2603 boards */886 #ifdef EXTENDED_VME887 lis r3, HIADJ(RAVEN_BASE_ADRS)888 ori r3, r3, LO(RAVEN_BASE_ADRS)889 addis r4,r0,(VME_A32_MSTR_LOCAL>>16) /* MSADD0: */890 ori r4,r4,CPU2PCI_ADDR0_END /* MSADD0: */891 stw r4,RAVEN_MPC_MSADD0(r3) /* write MSADD0 */892 eieio /* synchronize */893 sync /* synchronize */894 #endif895896 #if FALSE /* XXX TPR SDA not supported yet */897 /* initialize r2 and r13 according to EABI standard */898899 lis r2, HIADJ(_SDA2_BASE_)900 ori r2, r2, LO(_SDA2_BASE_)901 lis r13, HIADJ(_SDA_BASE_)902 ori r13, r13, LO(_SDA_BASE_)903 #endif904905 /* go to C entry point */906907 or r3, r11, r11908 addi sp, sp, -FRAMEBASESZ/* get frame stack */909910 lis r6, HIADJ(romStart)911 orir6, r6, LO(romStart)912913 lis r7, HIADJ(romInit)914 orir7, r7, LO(romInit)915916 lis r8, HIADJ(ROM_TEXT_ADRS)917 orir8, r8, LO(ROM_TEXT_ADRS)918919 sub r6, r6, r7920 add r6, r6, r8921922 mtlr r6923 blr924925 #ifndef MV2300926927928 .set SIO_LUNINDEX,0x07/* SIO LUN index register */929 .set SIO_CNFG1,0x21/* SIO configuration #1 register */930 .set SIO_CNFG2,0x22/* SIO configuration #2 register */931 .set SIO_PCSCI,0x23/* SIO PCS configuration index reg */

B-22

932 .set SIO_PCSCD,0x24/* SIO PCS configuration data reg */933 .set SIO_SID,0x08/* SIO identifier register */934 .set SIO_SIDPNP,0x20/* SIO identifier register - PnP */935 .set SIO_SIDMASK,0xF8/* SIO identifier mask */936 .set SIO_SID87303,0x30/* SIO identifier - 87303 */937 .set SIO_SID87323,0x20/* SIO identifier - 87323 */938 .set SIO_SID87308,0xA0/* SIO identifier - 87308 */939 .set SIO_ACTIVATE,0x30/* SIO activate register */940 .set SIO_IOBASEHI,0x60/* SIO I/O port base address, 15:8 */941 .set SIO_IOBASELO,0x61/* SIO I/O port base address, 7:0 */942 .set SIO_DBASEHI,0x60/* SIO KBC data base address, 15:8 */943 .set SIO_DBASELO,0x61/* SIO KBC data base address, 7:0 */944 .set SIO_CBASEHI,0x62/* SIO KBC command base addr, 15:8 */945 .set SIO_CBASELO,0x63/* SIO KBC command base addr, 7:0 */946 .set SIO_LUNENABLE,0x01/* SIO LUN enable */947 .set SIO_LUNDISABLE,0x00/* SIO LUN disable */948 .set SIO_LUNCNFGR,0xF0/* SIO LUN configuration register */949 .set PID_CLARIION,0xC0 /* processor identifier, CLARIION */950 .set PID_VIPER,0xD0 /* processor identifier, VIPER */951 .set PID_GENESIS2,0xE0 /* processor identifier, GENESIS2 */952 .set PID_MASK,0xF0 /* processor identifier mask */953954 /*955 ;956 ; This function initializes the superio chip to a functional957 ; state.958 ;959 ; Upon completion, SIO resource registers are mapped as follows:960 ; ResourceEnabledAddress961 ; FDC Yes PRI 3F0-3F7962 ; IDE Yes PRI 1F0-1F7 3F6, 3F7963 ; UART1 Yes COM1 3F8-3FF964 ; UART2 Yes COM2 2F8-2FF965 ; ||PORT Yes LPT1 3BC-3BE966 ; RTC Yes 070, 071967 ; KBC Yes 060, 064968 ;969 ;970 */971972 .sioInit :973 mfsprr7,8 /* save link register */974 /*975 ;976 ; check the type of superI/O that we’re dealing with (read the977 ; identifier register of the 87303/87323), all possible locations978 ; are checked, this is done in the case the configuration straps979 ; are not installed correctly, this will give us the ability to980 ; have basic serial COM for console I/O981 ;982 */983 /*

B-23

984 * Get base addr of ISA I/O space985 */986 lis r6,HIADJ(CPU_PCI_ISA_IO_ADRS)987 ori r6,r6,LO(CPU_PCI_ISA_IO_ADRS)988 /*989 * Probe the 4 possible locations of the SIO’s Index Register990 * in ISA I/O space.991 * 398/399992 * 26E/26F993 * 15C/15D994 * 02E/02F995 */996 addi r3,r6,0x0398/* Get superI/O 87303/87323 base */997 addi r4,r0,SIO_SID/* load identifier register offset */998 bl .sio_br999 addi r4,r0,0x0398/* Get superI/O 87303/87323 base */1000 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1001 cmpli0,0,r3,SIO_SID87303/* is it a 87303? */1002 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */1003 cmpli0,0,r3,SIO_SID87323/* is it a 87323? */1004 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */10051006 addi r3,r6,0x026E/* Get superI/O 87303/87323 base */1007 addi r4,r0,SIO_SID/* load identifier register offset */1008 bl .sio_br1009 addi r4,r0,0x026E/* Get superI/O 87303/87323 base */1010 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1011 cmpli0,0,r3,SIO_SID87303/* is it a 87303? */1012 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */1013 cmpli0,0,r3,SIO_SID87323/* is it a 87323? */1014 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */10151016 addi r3,r6,0x015C/* Get superI/O 87303/87323 base */1017 addi r4,r0,SIO_SID/* load identifier register offset */1018 bl .sio_br1019 addi r4,r0,0x015C/* Get superI/O 87303/87323 base */1020 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1021 cmpli0,0,r3,SIO_SID87303/* is it a 87303? */1022 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */1023 cmpli0,0,r3,SIO_SID87323/* is it a 87323? */1024 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */10251026 addi r3,r6,0x002E/* Get superI/O 87303/87323 base */1027 addi r4,r0,SIO_SID/* load identifier register offset */1028 bl .sio_br1029 addi r4,r0,0x002E/* Get superI/O 87303/87323 base */1030 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1031 cmpli0,0,r3,SIO_SID87303/* is it a 87303? */1032 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */1033 cmpli0,0,r3,SIO_SID87323/* is it a 87323? */1034 /*1035 ;

B-24

1036 ; if we make it here, the SIO device is not a 87303/87323 type,1037 ; check for an 87308 SIO device type (PnP capable), for right1038 ; now only motherboard mode addresses will be probed1039 ;1040 ;1041 ; 87308 initialization1042 ;1043 */1044 .sioInit_87308:10451046 /*1047 ;1048 ; determine the base address (motherboard mode - 15C/15D, 2E/2F)1049 ;1050 */1051 /*1052 * Get base addr of ISA I/O space1053 */1054 lis r6,HIADJ(CPU_PCI_ISA_IO_ADRS)1055 ori r6,r6,LO(CPU_PCI_ISA_IO_ADRS)10561057 addi r3,r6,0x002E/* adjust to superI/O 87308 base */1058 addi r4,r0,SIO_SIDPNP/* select SID register */1059 bl .sio_br1060 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1061 cmpli0,0,r3,SIO_SID87308/* is it a 87308? */1062 addi r4,r0,0x002E/* adjust to superI/O 87308 base */1063 bc 12,2,.sioInit_87308_fa/* if equal, yes, goto to 87308 init */10641065 addi r3,r6,0x015C/* adjust to superI/O 87308 base */1066 addi r4,r0,SIO_SIDPNP/* select SID register */1067 bl .sio_br1068 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1069 cmpli0,0,r3,SIO_SID87308/* is it a 87308? */1070 addi r4,r0,0x015C/* adjust to superI/O 87308 base */1071 bc 12,2,.sioInit_87308_fa/* if equal, yes, goto to 87308 init */10721073 b .sioInit_done/* don’t know what to do... */10741075 .sioInit_87308_fa:1076 add r6,r6,r4 /* add offset to base */1077 or r3,r6,r6 /* make a copy */1078 /*1079 ; enable PS/2 mode in SIO configuration register #11080 */1081 addi r4,r0,SIO_CNFG1/* select CNFG1 */1082 bl .sio_br1083 andi.r5,r3,0xFB/* keep all but PS/2-AT mode bit */1084 addi r4,r0,SIO_CNFG1/* select CNFG1 */1085 or r3,r6,r6 /* make a copy */1086 bl .sio_bw1087 /*

B-25

1088 ; KBC (LUN 0)1089 */1090 addi r4,r0,SIO_LUNINDEX/* select KBC LUN */1091 addi r5,r0,0x01092 bl .sio_bw1093 addi r4,r0,SIO_ACTIVATE/* disable KBC */1094 addi r5,r0,SIO_LUNDISABLE1095 bl .sio_bw1096 addi r4,r0,SIO_LUNCNFGR/* initialize KBC clock to 8 Mhz */1097 addi r5,r0,0x01098 bl .sio_bw1099 addi r4,r0,SIO_DBASEHI/* initialize KBC data base address to 0x060 */1100 addi r5,r0,0x001101 bl .sio_bw1102 addi r4,r0,SIO_DBASELO1103 addi r5,r0,0x601104 bl .sio_bw1105 addi r4,r0,SIO_CBASEHI/* initialize KBC command base address to 0x064 */1106 addi r5,r0,0x001107 bl .sio_bw1108 addi r4,r0,SIO_CBASELO1109 addi r5,r0,0x641110 bl .sio_bw1111 addi r4,r0,SIO_ACTIVATE/* enable KBC */1112 addi r5,r0,SIO_LUNENABLE1113 bl .sio_bw1114 /*1115 ; FDC (LUN 3)1116 */1117 addi r4,r0,SIO_LUNINDEX/* select FDC LUN */1118 addi r5,r0,0x31119 bl .sio_bw1120 addi r4,r0,SIO_IOBASEHI/* initialize FDC address to 0x3F0 */1121 addi r5,r0,0x031122 bl .sio_bw1123 addi r4,r0,SIO_IOBASELO1124 addi r5,r0,0xF01125 bl .sio_bw1126 addi r4,r0,SIO_LUNCNFGR/* initialize FDC to PS-2 mode */1127 addi r5,r0,0x401128 bl .sio_bw1129 addi r4,r0,SIO_ACTIVATE/* enable FDC */1130 addi r5,r0,SIO_LUNENABLE1131 bl .sio_bw1132 /*1133 ; COM2 (LUN 5)1134 */1135 addi r4,r0,SIO_LUNINDEX/* select COM2 LUN */1136 addi r5,r0,0x51137 bl .sio_bw1138 addi r4,r0,SIO_IOBASEHI/* initialize COM2 address to 0x2F8 */1139 addi r5,r0,0x02

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1140 bl .sio_bw1141 addi r4,r0,SIO_IOBASELO1142 addi r5,r0,0xF81143 bl .sio_bw1144 addi r4,r0,SIO_ACTIVATE/* enable COM2 */1145 addi r5,r0,SIO_LUNENABLE1146 bl .sio_bw1147 /*1148 ; COM1 (LUN 6)1149 */1150 addi r4,r0,SIO_LUNINDEX/* select COM1 LUN */1151 addi r5,r0,0x61152 bl .sio_bw1153 addi r4,r0,SIO_IOBASEHI/* initialize COM1 address to 0x3F8 */1154 addi r5,r0,0x031155 bl .sio_bw1156 addi r4,r0,SIO_IOBASELO1157 addi r5,r0,0xF81158 bl .sio_bw1159 addi r4,r0,SIO_ACTIVATE/* enable COM1 */1160 addi r5,r0,SIO_LUNENABLE1161 bl .sio_bw1162 /*1163 ; LPT (LUN 4)1164 */1165 addi r4,r0,SIO_LUNINDEX/* select LPT LUN */1166 addi r5,r0,0x41167 bl .sio_bw1168 addi r4,r0,SIO_IOBASEHI/* initialize LPT address to 0x3BC */1169 addi r5,r0,0x031170 bl .sio_bw1171 addi r4,r0,SIO_IOBASELO1172 addi r5,r0,0xBC1173 bl .sio_bw1174 addi r4,r0,SIO_LUNCNFGR/* Put in 87303 compatible mode. */1175 addi r5,r0,0x121176 bl .sio_bw1177 addi r4,r0,SIO_ACTIVATE/* enable LPT */1178 addi r5,r0,SIO_LUNENABLE1179 bl .sio_bw1180 b .sioInit_done/* branch to done */1181 /*1182 ; 87303/87323 initialization1183 */1184 .sioInit_87303:1185 add r6,r6,r4 /* add offset to base */1186 or r3,r6,r6 /* make a copy */11871188 addi r4,r0,0 /* initialize FER with 0x4F */1189 addi r5,r0,0x4F1190 bl .sio_bw1191 addi r4,r0,1 /* initialize FAR with 0x11 */

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1192 addi r5,r0,0x111193 bl .sio_bw1194 addi r4,r0,9 /* initialize ASC to PS-2 mode */1195 addi r5,r0,0x401196 bl .sio_bw1197 addi r4,r0,5 /* retrieve KBC/RTC control register */1198 bl .sio_br1199 andi.r5,r3,0xD0/* keep KBC_CSS, CSE */1200 ori r5,r5,0x0F/* add RTC_E, PAE, KBC_SC, KBC_E */1201 or r3,r6,r6 /* load base address of SIO device */1202 bl .sio_bw1203 .sioInit_done:1204 /*1205 ; for VIPER H/W we need to enable the CSx registers of the SIO1206 ; to point to the MCG classic RTC/NVRAM device1207 */1208 addisr3,r0,CPUCRA_HI/* load addr to CPU config reg */1209 ori r3,r3,CPUCRA_LO1210 lbz r3,0(r3) /* read CPU config reg */1211 andi.r3,r3,PID_MASK/* mask off unwanted data bits */1212 cmpli0,0,r3,PID_VIPER/* is it a VIPER? */1213 bc 4,2,.sioInit_viper_no/* if not equal, no, branch */12141215 /*1216 * Get base addr of ISA I/O space1217 */1218 lis r3,HIADJ(CPU_PCI_ISA_IO_ADRS)1219 ori r3,r3,LO(CPU_PCI_ISA_IO_ADRS)12201221 addi r3,r3,0x015C/* adjust to superI/O 87308 base */1222 or r6,r3,r3 /* make a copy */1223 /*1224 ; CS01225 */1226 addi r4,r0,SIO_PCSCI/* select PCSCIR */1227 addi r5,r0,0x001228 bl .sio_bw1229 addi r4,r0,SIO_PCSCD/* select PCSCDR */1230 addi r5,r0,0x001231 bl .sio_bw1232 addi r4,r0,SIO_PCSCI/* select PCSCIR */1233 addi r5,r0,0x011234 bl .sio_bw1235 addi r4,r0,SIO_PCSCD/* select PCSCDR */1236 addi r5,r0,0x761237 bl .sio_bw1238 addi r4,r0,SIO_PCSCI/* select PCSCIR */1239 addi r5,r0,0x021240 bl .sio_bw1241 addi r4,r0,SIO_PCSCD/* select PCSCDR */1242 addi r5,r0,0x401243 bl .sio_bw

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1244 /*1245 ; CS11246 */1247 addi r4,r0,SIO_PCSCI/* select PCSCIR */1248 addi r5,r0,0x051249 bl .sio_bw1250 addi r4,r0,SIO_PCSCD/* select PCSCDR */1251 addi r5,r0,0x001252 bl .sio_bw1253 addi r4,r0,SIO_PCSCI/* select PCSCIR */1254 addi r5,r0,0x051255 bl .sio_bw1256 addi r4,r0,SIO_PCSCD/* select PCSCDR */1257 addi r5,r0,0x701258 bl .sio_bw1259 addi r4,r0,SIO_PCSCI/* select PCSCIR */1260 addi r5,r0,0x061261 bl .sio_bw1262 addi r4,r0,SIO_PCSCD/* select PCSCDR */1263 addi r5,r0,0x1C1264 bl .sio_bw1265 /*1266 ; CS21267 */1268 addi r4,r0,SIO_PCSCI/* select PCSCIR */1269 addi r5,r0,0x081270 bl .sio_bw1271 addi r4,r0,SIO_PCSCD/* select PCSCDR */1272 addi r5,r0,0x001273 bl .sio_bw1274 addi r4,r0,SIO_PCSCI/* select PCSCIR */1275 addi r5,r0,0x091276 bl .sio_bw1277 addi r4,r0,SIO_PCSCD/* select PCSCDR */1278 addi r5,r0,0x711279 bl .sio_bw1280 addi r4,r0,SIO_PCSCI/* select PCSCIR */1281 addi r5,r0,0x0A1282 bl .sio_bw1283 addi r4,r0,SIO_PCSCD/* select PCSCDR */1284 addi r5,r0,0x1C1285 bl .sio_bw1286 /*1287 ; PMC (LUN 8)1288 */1289 addi r4,r0,SIO_LUNINDEX/* select PMC LUN */1290 addi r5,r0,0x81291 bl .sio_bw1292 addi r4,r0,SIO_IOBASEHI/* initialize PMC address to 0x460 */1293 addi r5,r0,0x041294 bl .sio_bw1295 addi r4,r0,SIO_IOBASELO

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1296 addi r5,r0,0x601297 bl .sio_bw1298 addi r4,r0,SIO_ACTIVATE/* enable PMC */1299 addi r5,r0,SIO_LUNENABLE1300 bl .sio_bw1301 .sioInit_viper_no:1302 mtspr8,r7 /* restore link register */1303 bclr 20,0 /* return to caller */1304 /*1305 ; routine:sio_bw1306 ; this function writes a register to the SIO chip1307 ; call:1308 ; sio_bw(sioaddr, regnum, value)1309 ; return:1310 ; none1311 */1312 .sio_bw:1313 stb r4,0(r3)/* write index register with register offset */1314 eieio1315 sync1316 stb r5,1(r3)/* 1st write */1317 eieio1318 sync1319 stb r5,1(r3)/* 2nd write */1320 eieio1321 sync1322 bclr 20,0 /* return to caller */1323 /*1324 ; routine:sio_br1325 ; this function reads a register from the SIO chip1326 ; call:1327 ; sioInit(sioaddr , regnum)1328 ; return:1329 ; register value1330 */1331 .sio_br:1332 stb r4,0(r3)/* write index register with register offset */1333 eieio1334 sync1335 lbz r3,1(r3)/* retrieve specified reg offset contents */1336 eieio1337 sync1338 bclr 20,0 /* return to caller */13391340 #endif /* MV2300 */13411342

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sysALib.s

1 /* sysALib.s - Motorola MVME2600 system-dependent assembly routines */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 /* Copyright 1996-1997 Motorola, Inc. */5 .data6 .globlcopyright_wind_river7 .longcopyright_wind_river89 /*10 modification history11 --------------------12 01k,05nov97,mas added eieio/sync pair to sysMemProbeSup() (SPR 9717).13 01j,25jul97,srr/ added 604r (Mach 5) support (SPR 8911).14 mas15 01i,14jul97,mas added sysMemProbeSup(), sysIn16(), sysOut16(), sysIn32(),16 sysOut32() (SPR 8022).17 01h,29may97,srr Duplicate the GLANCE, RAVEN, and SIO code in sysALib.s as in18 romInit.s. Chg the RAVEN #defines to support vxMemProbe and19 replace the hard coded values with #defines. Replace the20 isync instructions with eieio in sysPci... routines.21 (MCG MR #67, 69, 74). SPRs 8289, 8560.22 01g,06may97,mas added extended VME support: 0xfef8 -> FALCON_BASE_UPPER_ADRS23 (SPR 8410).24 01f,24apr97,mas added Moto support for MPIC: sysPciRead32, sysPciWrite3225 (SPR 8170).26 01e,11apr97,mas added sysPciInByte, sysPciOutByte, sysPciInWord,

sysPciOutWord,27 sysPciInLong, sysPciOutLong; removed doPciCSA, pciIoSync28 (SPR 8226).29 01d,19feb97,mas in sysInit changed BOOT_COLD to BOOT_WARM_AUTOBOOT (SPR 8024).30 01c,02jan97,dat documentation, mod history fix31 01b,17dec96,mas moved sysPciIo.s contents here (SPR 7525).32 01a,01sep96,mot written (mv1603/sysALib.s ver 01k)33 */3435 /*36 DESCRIPTION37 This module contains system-dependent routines written in assembly38 language.3940 This module must be the first specified in the \f3ld\f1 command used to41 build the system. The sysInit() routine is the system start-up code.42 */4344 #define _ASMLANGUAGE45 #include “vxWorks.h”46 #include “sysLib.h”47 #include “config.h”48 #include “regs.h”

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49 #include “asm.h”5051 /* globals */5253 .globl_sysInit/* start of system code */54 .globl sysInByte55 .globl sysOutByte56 .globl sysIn1657 .globl sysOut1658 .globl sysIn3259 .globl sysOut3260 .globl sysPciRead3261 .globl sysPciWrite3262 .globl sysPciInByte63 .globl sysPciOutByte64 .globl sysPciInWord65 .globl sysPciOutWord66 .globl sysPciInLong67 .globl sysPciOutLong68 .globl sysMemProbeSup69 .globl sysProbeExc707172 /* externals */7374 .extern usrInit7576 .text7778 /

*******************************************************************************

79 *80 * sysInit - start after boot81 *82 * This is the system start-up entry point for VxWorks in RAM, the83 * first code executed after booting. It disables interrupts, sets up84 * the stack, and jumps to the C routine usrInit() in usrConfig.c.85 *86 * The initial stack is set to grow down from the address of sysInit(). This87 * stack is used only by usrInit() and is never used again. Memory for the88 * stack must be accounted for when determining the system load address.89 *90 * NOTE: This routine should not be called by the user.91 *92 * RETURNS: N/A9394 * sysInit (void) /@ THIS IS NOT A CALLABLE ROUTINE @/9596 */9798 _sysInit:

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99100 /* disable external interrupts */101102 xor p0, p0, p0103 mtmsr p0 /* clear the MSR register */104105106 /*107 * Turn off the GLANCE108 * GEN2_WRKARND109 */110 addisr3, r0, FALCON_BASE_UPPER_ADRS111 ori r3, r3, 0x8000112 addisr4, r0, 0x0113 ori r4, r4, 0x0070114 stb r4, 0x0(r3)115116 /* return from decrementer exceptions */117118 addis p1, r0, 0x4c00119 addi p1, p1, 0x0064 /* load rfi (0x4c000064) to p1 */120 stw p1, 0x900(r0) /* store rfi at 0x00000900 */121122 /* initialize the stack pointer */123124 lis sp, HIADJ(RAM_LOW_ADRS)125 addi sp, sp, LO(RAM_LOW_ADRS)126127 /* disable instruction and data caches */128129 /* Getcpu type */130131 mfspr r28, PVR132 rlwinm r28, r28, 16, 16, 31133134 cmpli 0, 0, r28, CPU_TYPE_604R135 beq CPU_IS_604R136137 li r3, 0138 ori r3, r3, (_PPC_HID0_ICFI | _PPC_HID0_DCFI)139 sync140 isync141 mtsprHID0, r3 /* first invalidate I and D caches */142 b CACHE_INVALIDATE_DONE143144 CPU_IS_604R:145 li r3, 0146 mtspr HID0, r3 /* disable the caches */147 isync148 ori r3, r3, 0x0C00 /* invalidate the caches */149 ori r3, r3, 0x0002 /* disable BTAC by setting bit 30 */150 mtspr HID0, r3

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151152 /* Disable sequential instruction execution and153 enable branch history table for the 604 */154155 CACHE_INVALIDATE_DONE:156 mfsprp1,HID0157 ori p1,p1,(_PPC_HID0_SIED | _PPC_HID0_BHTE )158 mtsprHID0,p1159160 /* disable instruction and data translations in the MMU */161162 sync163 mfmsrr3 /* get the value in msr *164 /* clear bits IR and DR */165166 rlwinmr4, r3, 0, _PPC_MSR_BIT_DR+1, _PPC_MSR_BIT_IR - 1167168 mtmsrr4 /* set the msr */169 sync /* SYNC */170171 /* initialize the BAT register */172173 li p3,0 /* clear p0 */174175 isync176 mtsprIBAT0U,p3/* SPR 528 (IBAT0U) */177 isync178179 mtsprIBAT0L,p3/* SPR 529 (IBAT0L) */180 isync181182 mtsprIBAT1U,p3/* SPR 530 (IBAT1U) */183 isync184185 mtsprIBAT1L,p3/* SPR 531 (IBAT1L) */186 isync187188 mtsprIBAT2U,p3/* SPR 532 (IBAT2U) */189 isync190191 mtsprIBAT2L,p3/* SPR 533 (IBAT2L) */192 isync193194 mtsprIBAT3U,p3/* SPR 534 (IBAT3U) */195 isync196197 mtsprIBAT3L,p3/* SPR 535 (IBAT3L) */198 isync199200 mtsprDBAT0U,p3/* SPR 536 (DBAT0U) */201 isync202

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203 mtsprDBAT0L,p3/* SPR 537 (DBAT0L) */204 isync205206 mtsprDBAT1U,p3/* SPR 538 (DBAT1U) */207 isync208209 mtsprDBAT1L,p3/* SPR 539 (DBAT1L) */210 isync211212 mtsprDBAT2U,p3/* SPR 540 (DBAT2U) */213 isync214215 mtsprDBAT2L,p3/* SPR 541 (DBAT2L) */216 isync217218 mtsprDBAT3U,p3/* SPR 542 (DBAT3U) */219 isync220221 mtsprDBAT3L,p3/* SPR 543 (DBAT3L) */222 isync223224225 #ifndef MV2300226 /* Turn off the GLANCE - L2 Cache */227228 lis r3, HIADJ(MV2600_SXCCR_A)229 ori r3, r3, LO(MV2600_SXCCR_A)230 addis r4, r0, 0x0231 ori r4, r4, 0x0070232 stb r4, 0x0(r3)233 #endif /* MV2300 */234235 /*236 This following contains the entry code for the initialization code237 for the Raven, a Host PCI Bridge/Memory Controller used in238 Motorola’s PowerPC based boards.239 */240241 /*242 # Initialize the RAVEN MPC registers.243 # notes:244 # 1. For the standard vxWorks configuration the MPC to245 # PCI mapping registers are246 # initialized to the PReP model with some additions:247 #248 # MPC Address Range PCI Address Range Definition249 # ----------------- ----------------- ------------------------250 # 80000000 BF7FFFFF00000000 3F7FFFFFISA/PCI I/O space251 # C0000000 FCFFFFFF00000000 3CFFFFFFISA/PCI Mem space w/MPIC252 # FD000000 FDFFFFFF00000000 00FFFFFFISA/PCI Mem space253 # FE000000 FE7FFFFF00000000 007FFFFFISA/PCI I/O space254 #

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255 # 2. This assignments do not include the entire PReP PCI256 # address space, this is due to the conflicting local257 # resources of the H/W.258 #259 # 3. When EXTENDED_VME is defined the mapping is as follows:260 #261 # MPC Address Range PCI Address Range Definition262 # --------------------------- --------------------------- --------------------

-263 # VME_A32_MSTR_LOCAL FBFFFFFF VME_A32_MSTR_LOCAL FBFFFFFF VME address space264 # FC000000 FCFFFFFF FC000000 FCFFFFFF MPIC/Reg space265 # FD000000 FDFFFFFF FD000000 FDFFFFFF ISA/PCI Memory space266 # FE000000 FE7FFFFF 00000000 007FFFFF ISA/PCI I/O space267 #268 */269 lis r3, HIADJ(RAVEN_BASE_ADRS)270 ori r3, r3, LO(RAVEN_BASE_ADRS)271272 addisr4,r0,0x0000/* GCSR:FLBRD=0,MBT=256us */273 ori r4,r4,0x0000/* GCSR:FLBRD=0,MBT=256us */274 sth r4,RAVEN_MPC_GCSR(r3)/* write GCSR */275 eieio /* synchronize */276 sync /* synchronize */277278 addisr4,r0,0x0000/* MARB:BRENx=1,PKEN=0,PKMD=0,DEFMx=1 */279 ori r4,r4,0x0703/* MARB:BRENx=1,PKEN=0,PKMD=0,DEFMx=1 */280 sth r4,RAVEN_MPC_MARB(r3)/* write MARB */281 eieio /* synchronize */282 sync /* synchronize */283284 addisr4,r0,0x0000/* PADJ:BE=66MHZ */285 ori r4,r4,0x00BE/* PADJ:BE=66MHZ */286 stb r4,RAVEN_MPC_PADJ(r3)/* write PADJ */287 eieio /* synchronize */288 sync /* synchronize */289290 addisr4,r0,0x0000/* MEREN:(all error enables disabled) */291 ori r4,r4,0x0000/* MEREN:(all error enables disabled) */292 sth r4,RAVEN_MPC_MEREN(r3)/* write MEREN */293 eieio /* synchronize */294 sync /* synchronize */295296 addisr4,r0,0x0000/* MERST:(clear all error status) */297 ori r4,r4,0x00ff/* MERST:(clear all error status) */298 stb r4,RAVEN_MPC_MERST(r3)/* write MERST */299 eieio /* synchronize */300 sync /* synchronize */301302 addisr4,r0,0x0000/* MSATTx:(all attributes disabled) */303 ori r4,r4,0x0000/* MSATTx:(all attributes disabled) */304 stb r4,RAVEN_MPC_MSATT0(r3)/* write MSATT0 */305 eieio /* synchronize */

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306 sync /* synchronize */307 stb r4,RAVEN_MPC_MSATT1(r3)/* write MSATT1 */308 eieio /* synchronize */309 sync /* synchronize */310 stb r4,RAVEN_MPC_MSATT2(r3)/* write MSATT2 */311 eieio /* synchronize */312 sync /* synchronize */313 stb r4,RAVEN_MPC_MSATT3(r3)/* write MSATT3 */314 eieio /* synchronize */315 sync /* synchronize */316317 addisr4,r0,CPU2PCI_ADDR0_START/* MSADD0: */318 ori r4,r4,CPU2PCI_ADDR0_END/* MSADD0: */319 stw r4,RAVEN_MPC_MSADD0(r3)/* write MSADD0 */320 eieio /* synchronize */321 sync /* synchronize */322323 addisr4,r0,0x0000/* MSOFF0: */324 ori r4,r4,CPU2PCI_OFFSET0/* MSOFF0: */325 sth r4,RAVEN_MPC_MSOFF0(r3)/* write MSOFF0 */326 eieio /* synchronize */327 sync /* synchronize */328329 addisr4,r0,0x0000/* MSATT0: */330 ori r4,r4,CPU2PCI_MSATT0/* MSATT0: */331 stb r4,RAVEN_MPC_MSATT0(r3)/* write MSATT0 */332 eieio /* synchronize */333 sync /* synchronize */334335 addisr4,r0,CPU2PCI_ADDR1_START/* MSADD1: */336 ori r4,r4,CPU2PCI_ADDR1_END/* MSADD1: */337 stw r4,RAVEN_MPC_MSADD1(r3)/* write MSADD1 */338 eieio /* synchronize */339 sync /* synchronize */340341 addisr4,r0,0x0000/* MSOFF1: */342 ori r4,r4,CPU2PCI_OFFSET1/* MSOFF1: */343 sth r4,RAVEN_MPC_MSOFF1(r3)/* write MSOFF1 */344 eieio /* synchronize */345 sync /* synchronize */346347 addisr4,r0,0x0000/* MSATT1: */348 ori r4,r4,CPU2PCI_MSATT1/* MSATT1: */349 stb r4,RAVEN_MPC_MSATT1(r3)/* write MSATT1 */350 eieio /* synchronize */351 sync /* synchronize */352353 addisr4,r0,CPU2PCI_ADDR2_START/* MSADD2: */354 ori r4,r4,CPU2PCI_ADDR2_END/* MSADD2: */355 stw r4,RAVEN_MPC_MSADD2(r3)/* write MSADD2 */356 eieio /* synchronize */357 sync /* synchronize */

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358359 addisr4,r0,0x0000/* MSOFF2: */360 ori r4,r4,CPU2PCI_OFFSET2/* MSOFF2: */361 sth r4,RAVEN_MPC_MSOFF2(r3)/* write MSOFF2 */362 eieio /* synchronize */363 sync /* synchronize */364365 addisr4,r0,0x0000/* MSATT2: */366 ori r4,r4,CPU2PCI_MSATT2/* MSATT2: */367 stb r4,RAVEN_MPC_MSATT2(r3)/* write MSATT2 */368 eieio /* synchronize */369 sync /* synchronize */370371 /*372 * PCI address space 3 registers supports config. space access and373 * special cycle generation. It should be configured for I/O space.374 */375376 addisr4,r0,CPU2PCI_ADDR3_START/* MSADD3: */377 ori r4,r4,CPU2PCI_ADDR3_END/* MSADD3: */378 stw r4,RAVEN_MPC_MSADD3(r3)/* write MSADD3 */379 eieio /* synchronize */380 sync /* synchronize */381382 addisr4,r0,0x0000/* MSOFF3: */383 ori r4,r4,CPU2PCI_OFFSET3/* MSOFF3: */384 sth r4,RAVEN_MPC_MSOFF3(r3)/* write MSOFF3 */385 eieio /* synchronize */386 sync /* synchronize */387388 addisr4,r0,0x0000/* MSATT3: */389 ori r4,r4,CPU2PCI_MSATT3/* MSATT3: */390 stb r4,RAVEN_MPC_MSATT3(r3)/* write MSATT3 */391 eieio /* synchronize */392 sync /* synchronize */393394 /* End of Raven Init */395396 /*397 * Do the init for the SIO, now that the Raven is configured.398 * This was moved after the Raven init for the Extended VME config.399 */400401 #ifndef MV2300402 bl .sioInit403 #endif /* MV2300 */404405406 /* invalidate entries within both TLBs */407408 li p1,128409 xor p0,p0,p0 /* p0 = 0 */

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410 mtctrp1 /* CTR = 32 */411412 isync /* context sync req’d before tlbie */413 sysALoop:414 tlbiep0415 addi p0,p0,0x1000/* increment bits 15-19 */416 bdnz sysALoop /* decrement CTR, branch if CTR != 0 */417 sync /* sync instr req’d after tlbie */418419 /* workaround for Extended VME config. with 2603 boards */420 #ifdef EXTENDED_VME421 lis r3, HIADJ(RAVEN_BASE_ADRS)422 ori r3, r3, LO(RAVEN_BASE_ADRS)423 addis r4,r0,(VME_A32_MSTR_LOCAL>>16) /* MSADD0: */424 ori r4,r4,CPU2PCI_ADDR0_END /* MSADD0: */425 stw r4,RAVEN_MPC_MSADD0(r3) /* write MSADD0 */426 eieio /* synchronize */427 sync /* synchronize */428 #endif429430 /* initialize Small Data Area (SDA) start address */431432433 #if FALSE /* XXX TPR NO SDA for now */434 lis r2, HIADJ(_SDA2_BASE_)435 addi r2, r2, LO(_SDA2_BASE_)436437 lis r13, HIADJ(_SDA_BASE_)438 addi r13, r13, LO(_SDA_BASE_)439 #endif440441 addi sp, sp, -FRAMEBASESZ/* get frame stack */442 li r3, BOOT_WARM_AUTOBOOT443 b usrInit /* never returns - starts up kernel */444445446 /*****************************************************************************447 *448 * sysInByte - reads a byte from an address.449 *450 * This function reads a byte from a specified address.451 *452 * From a C programmers point of view, the routine is defined as follows:453 *454 * sysInByte455 * (456 * ULONG *addr; - address of data457 * )458 *459 * INPUTS:460 * r3 = address to read data from461 *

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462 * OUTPUTS:463 * r3 = data464 *465 * RETURNS: byte from address.466 */467468 sysInByte:469470 /*471 * Read byte from given address472 */473 lbzx r4,r0,r3474 /*475 * Sync I/O operation476 */477 eieio478 /*479 * Move data read to return register480 */481 or r3,r4,r4482 /*483 * Return to caller484 */485 bclr 20,0486487 /

******************************************************************************488 *489 * sysOutByte - writes a byte to an address.490 *491 * This function writes a byte to a specified address.492 *493 * From a C point of view, the routine is defined as follows:494 *495 * sysOutByte496 * (497 * ULONG *addr - address to write data to498 * UCHAR data - 8-bit data499 * )500 *501 * INPUTS:502 * r3 = address to write to503 * r4 = data to be written504 *505 * RETURNS: N/A506 */507508 sysOutByte:509510 /*511 * Write a byte to given address512 */

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513 stbx r4,r0,r3514 /*515 * Sync I/O operation516 */517 eieio518 /*519 * Return to caller520 */521 bclr 20,0522523 /*****************************************************************************524 *525 * sysIn16 - reads a 16-bit unsigned value from an address.526 *527 * This function reads a 16-bit unsigned value from a specified address.528 *529 * From a C programmers point of view, the routine is defined as follows:530 *531 * sysIn16532 * (533 * UINT16 *addr; - address of data534 * )535 *536 * INPUTS:537 * r3 = address to read data from538 *539 * OUTPUTS:540 * r3 = data541 *542 * RETURNS: 16-bit unsigned value from address.543 */544545 sysIn16:546547 lhz 3,0(3)548 eieio549 bclr 20,0550551 /

******************************************************************************552 *553 * sysOut16 - writes a 16-bit unsigned value to an address.554 *555 * This function writes a 16-bit unsigned value to a specified address.556 *557 * From a C point of view, the routine is defined as follows:558 *559 * sysOut16560 * (561 * UINT16 *addr - address to write data to562 * UINT16 data - 8-bit data563 * )

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564 *565 * INPUTS:566 * r3 = address to write to567 * r4 = data to be written568 *569 * RETURNS: N/A570 */571572 sysOut16:573574 sth 4,0(3)575 eieio576 bclr 20,0577578 /*****************************************************************************579 *580 * sysIn32 - reads a 32-bit unsigned value from an address.581 *582 * This function reads a 32-bit unsigned value from a specified address.583 *584 * From a C programmers point of view, the routine is defined as follows:585 *586 * sysIn32587 * (588 * UINT32 *addr; - address of data589 * )590 *591 * INPUTS:592 * r3 = address to read data from593 *594 * OUTPUTS:595 * r3 = data596 *597 * RETURNS: 32-bit unsigned value from address.598 */599600 sysIn32:601602 lwz 3,0(3)603 eieio604 bclr 20,0605606 /

******************************************************************************607 *608 * sysOut32 - writes a 32-bit unsigned value to an address.609 *610 * This function writes a 32-bit unsigned value to a specified address.611 *612 * From a C point of view, the routine is defined as follows:613 *614 * sysOut32

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615 * (616 * UINT32 *addr - address to write data to617 * UINT32 data - 32-bit data618 * )619 *620 * INPUTS:621 * r3 = address to write to622 * r4 = data to be written623 *624 * RETURNS: N/A625 */626627 sysOut32:628629 stw 4,0(3)630 eieio631 bclr 20,0632633634 /

******************************************************************************635 *636 * sysPciRead32 - read 32 bit PCI data637 *638 * This routine will read a 32-bit data item from PCI ( I/O or639 * memory ) space. From a C programmers point of view, the routine640 * is defined as follows:641 *642 * sysPciRead32643 * (644 * UINT32 *addr; - address of data in PCI space645 * UINT32 *pdata - pointer to data being returned646 * ) by the read call ( data is converted647 * to big-endian )648 *649 * INPUTS:650 * r3 = PCI address to read data from651 * r4 = pointer to store data to652 *653 * RETURNS: N/A654 */655656 sysPciRead32:657 lwbrx r3,r0,r3 /* get the data and swap the bytes */658 /*659 * Sync I/O operation660 */661 eieio662 stw r3,0(r4) /* store into address ptd. to by r4 */663 bclr 20,0664665

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666 /******************************************************************************

667 *668 * sysPciWrite32 - write a 32 bit data item to PCI space669 *670 * This routine will store a 32-bit data item ( input as big-endian )671 * into PCI ( I/O or memory ) space in little -endian mode. From a672 * C point of view, the routine is defined as follows:673 *674 * sysPciWrite32675 * (676 * UINT32 *addr - address to write data to677 * UINT32 data - 32-bit big-endian data678 * )679 *680 * INPUTS:681 * r3 = PCI address to write to682 * r4 = data to be written683 *684 * RETURNS: N/A685 */686687 sysPciWrite32:688 stwbrx r4,r0,r3 /* store data as little -endian */689 /*690 * Sync I/O operation691 */692 eieio693 bclr 20,0694695696 /*****************************************************************************697 *698 * sysPciInByte - reads a byte from PCI Config Space.699 *700 * This function reads a byte from a specified PCI Config Space address.701 *702 * ARGUMENTS:703 * r3 = Config Space address704 *705 * RETURNS:706 * r3 = byte from address.707 */708709 sysPciInByte:710711 /*712 * Read byte from PCI space713 */714 lbzx r3,r0,r3715 /*716 * Sync I/O operation

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717 */718 eieio719 /*720 * Return to caller721 */722 bclr 20,0723724 /*****************************************************************************725 *726 * sysPciInWord - reads a word (16-bit big-endian) from PCI Config Space.727 *728 * This function reads a word from a specified PCI Config Space (little -endian)729 * address.730 *731 * ARGUMENTS:732 * r3 = Config Space address733 *734 * RETURNS:735 * r3 = word (16-bit big-endian) from address.736 */737738 sysPciInWord:739740 /*741 * Read big-endian word from little -endian PCI space742 */743 lhbrx r3,r0,r3744 /*745 * Sync I/O operation746 */747 eieio748 /*749 * Return to caller750 */751 bclr 20,0752753 /*****************************************************************************754 *755 * sysPciInLong - reads a long (32-bit big-endian) from PCI Config Space.756 *757 * This function reads a long from a specified PCI Config Space (little -endian)758 * address.759 *760 * ARGUMENTS:761 * r3 = Config Space address762 *763 * RETURNS:764 * r3 = long (32-bit big-endian) from address.765 */766767 sysPciInLong:768

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769 /*770 * Read big-endian long from little-endian PCI space771 */772 lwbrx r3,r0,r3773 /*774 * Sync I/O operation775 */776 eieio777 /*778 * Return to caller779 */780 bclr 20,0781782 /

******************************************************************************783 *784 * sysPciOutByte - writes a byte to PCI Config Space.785 *786 * This function writes a byte to a specified PCI Config Space address.787 *788 * ARGUMENTS:789 * r3 = Config Space address790 * r4 = byte to write791 *792 * RETURNS: N/A793 */794795 sysPciOutByte:796797 /*798 * Write a byte to PCI space799 */800 stbx r4,r0,r3801 /*802 * Sync I/O operation803 */804 eieio805 /*806 * Return to caller807 */808 bclr 20,0809810 /

******************************************************************************811 *812 * sysPciOutWord - writes a word (16-bit big-endian) to PCI Config Space.813 *814 * This function writes a word to a specified PCI Config Space (little -endian)815 * address.816 *817 * ARGUMENTS:818 * r3 = Config Space address

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819 * r4 = word (16-bit big-endian) to write820 *821 * RETURNS: N/A822 */823824 sysPciOutWord:825826 /*827 * Write a big-endian word to little -endian PCI space828 */829 sthbrx r4,r0,r3830 /*831 * Sync I/O operation832 */833 eieio834 /*835 * Return to caller836 */837 bclr 20,0838839 /

******************************************************************************840 *841 * sysPciOutLong - writes a long (32-bit big-endian) to PCI Config Space.842 *843 * This function writes a long to a specified PCI Config Space (little -endian)844 * address.845 *846 * ARGUMENTS:847 * r3 = Config Space address848 * r4 = long (32-bit big-endian) to write849 *850 * RETURNS: N/A851 */852853 sysPciOutLong:854855 /*856 * Write a big-endian long to little-endian PCI space857 */858 stwbrx r4,r0,r3859 /*860 * Sync I/O operation861 */862 mr r3,r4863 eieio864 /*865 * Return to caller866 */867 bclr 20,0868

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869 /*******************************************************************************

870 *871 * sysMemProbeSup - sysBusProbe support routine872 *873 * This routine is called to try to read byte, word, or long, as specified874 * by length, from the specified source to the specified destination.875 *876 * RETURNS: OK if successful probe, else ERROR877878 STATUS sysMemProbeSup (length, src, dest)879 (880 int length, // length of cell to test (1, 2, 4, 8, 16) *881 char * src, // address to read *882 char * dest // address to write *883 )884885 */886887 sysMemProbeSup:888 addi p7, p0, 0 /* save length to p7 */889 xor p0, p0, p0 /* set return status */890 cmpwi p7, 1 /* check for byte access */891 bne sbpShort /* no, go check for short word access */892 lbz p6, 0(p1) /* load byte from source */893 eieio894 sync895 stb p6, 0(p2) /* store byte to destination */896 eieio897 sync898 isync /* enforce for immediate exception handling */899 blr900 sbpShort:901 cmpwi p7, 2 /* check for short word access */902 bne sbpWord /* no, check for word access */903 lhz p6, 0(p1) /* load half word from source */904 eieio905 sync906 sth p6, 0(p2) /* store half word to destination */907 eieio908 sync909 isync /* enforce for immediate exception handling */910 blr911 sbpWord:912 cmpwi p7, 4 /* check for short word access */913 bne sysProbeExc /* no, check for double word access */914 lwz p6, 0(p1) /* load half word from source */915 eieio916 sync917 stw p6, 0(p2) /* store half word to destination */918 eieio

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919 sync920 isync /* enforce for immediate exception handling */921 blr922 sysProbeExc:923 li p0, -1 /* shouldn’t ever get here, but... */924 blr925926 #ifndef MV2300927928929 .set SIO_LUNINDEX,0x07/* SIO LUN index register */930 .set SIO_CNFG1,0x21/* SIO configuration #1 register */931 .set SIO_CNFG2,0x22/* SIO configuration #2 register */932 .set SIO_PCSCI,0x23/* SIO PCS configuration index reg */933 .set SIO_PCSCD,0x24/* SIO PCS configuration data reg */934 .set SIO_SID,0x08/* SIO identifier register */935 .set SIO_SIDPNP,0x20/* SIO identifier register - PnP */936 .set SIO_SIDMASK,0xF8/* SIO identifier mask */937 .set SIO_SID87303,0x30/* SIO identifier - 87303 */938 .set SIO_SID87323,0x20/* SIO identifier - 87323 */939 .set SIO_SID87308,0xA0/* SIO identifier - 87308 */940 .set SIO_ACTIVATE,0x30/* SIO activate register */941 .set SIO_IOBASEHI,0x60/* SIO I/O port base address, 15:8 */942 .set SIO_IOBASELO,0x61/* SIO I/O port base address, 7:0 */943 .set SIO_DBASEHI,0x60/* SIO KBC data base address, 15:8 */944 .set SIO_DBASELO,0x61/* SIO KBC data base address, 7:0 */945 .set SIO_CBASEHI,0x62/* SIO KBC command base addr, 15:8 */946 .set SIO_CBASELO,0x63/* SIO KBC command base addr, 7:0 */947 .set SIO_LUNENABLE,0x01/* SIO LUN enable */948 .set SIO_LUNDISABLE,0x00/* SIO LUN disable */949 .set SIO_LUNCNFGR,0xF0/* SIO LUN configuration register */950 .set PID_CLARIION,0xC0 /* processor identifier, CLARIION */951 .set PID_VIPER,0xD0 /* processor identifier, VIPER */952 .set PID_GENESIS2,0xE0 /* processor identifier, GENESIS2 */953 .set PID_MASK,0xF0 /* processor identifier mask */954955 /*956 ;957 ; This function initializes the superio chip to a functional958 ; state.959 ;960 ; Upon completion, SIO resource registers are mapped as follows:961 ; ResourceEnabledAddress962 ; FDC Yes PRI 3F0-3F7963 ; IDE Yes PRI 1F0-1F7 3F6, 3F7964 ; UART1 Yes COM1 3F8-3FF965 ; UART2 Yes COM2 2F8-2FF966 ; ||PORT Yes LPT1 3BC-3BE967 ; RTC Yes 070, 071968 ; KBC Yes 060, 064969 ;970 ;

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971 */972973 .sioInit :974 mfsprr7,8 /* save link register */975 /*976 ;977 ; check the type of superI/O that we’re dealing with (read the978 ; identifier register of the 87303/87323), all possible locations979 ; are checked, this is done in the case the configuration straps980 ; are not installed correctly, this will give us the ability to981 ; have basic serial COM for console I/O982 ;983 */984 /*985 * Get base addr of ISA I/O space986 */987 lis r6,HIADJ(CPU_PCI_ISA_IO_ADRS)988 ori r6,r6,LO(CPU_PCI_ISA_IO_ADRS)989 /*990 * Probe the 4 possible locations of the SIO’s Index Register991 * in ISA I/O space.992 * 398/399993 * 26E/26F994 * 15C/15D995 * 02E/02F996 */997 addi r3,r6,0x0398/* Get superI/O 87303/87323 base */998 addi r4,r0,SIO_SID/* load identifier register offset */999 bl .sio_br1000 addi r4,r0,0x0398/* Get superI/O 87303/87323 base */1001 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1002 cmpli0,0,r3,SIO_SID87303/* is it a 87303? */1003 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */1004 cmpli0,0,r3,SIO_SID87323/* is it a 87323? */1005 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */10061007 addi r3,r6,0x026E/* Get superI/O 87303/87323 base */1008 addi r4,r0,SIO_SID/* load identifier register offset */1009 bl .sio_br1010 addi r4,r0,0x026E/* Get superI/O 87303/87323 base */1011 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1012 cmpli0,0,r3,SIO_SID87303/* is it a 87303? */1013 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */1014 cmpli0,0,r3,SIO_SID87323/* is it a 87323? */1015 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */10161017 addi r3,r6,0x015C/* Get superI/O 87303/87323 base */1018 addi r4,r0,SIO_SID/* load identifier register offset */1019 bl .sio_br1020 addi r4,r0,0x015C/* Get superI/O 87303/87323 base */1021 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1022 cmpli0,0,r3,SIO_SID87303/* is it a 87303? */

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1023 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */1024 cmpli0,0,r3,SIO_SID87323/* is it a 87323? */1025 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */10261027 addi r3,r6,0x002E/* Get superI/O 87303/87323 base */1028 addi r4,r0,SIO_SID/* load identifier register offset */1029 bl .sio_br1030 addi r4,r0,0x002E/* Get superI/O 87303/87323 base */1031 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1032 cmpli0,0,r3,SIO_SID87303/* is it a 87303? */1033 bc 12,2,.sioInit_87303/* if equal, yes, goto to 87303 init */1034 cmpli0,0,r3,SIO_SID87323/* is it a 87323? */1035 /*1036 ;1037 ; if we make it here, the SIO device is not a 87303/87323 type,1038 ; check for an 87308 SIO device type (PnP capable), for right1039 ; now only motherboard mode addresses will be probed1040 ;1041 ;1042 ; 87308 initialization1043 ;1044 */1045 .sioInit_87308:10461047 /*1048 ;1049 ; determine the base address (motherboard mode - 15C/15D, 2E/2F)1050 ;1051 */1052 /*1053 * Get base addr of ISA I/O space1054 */1055 lis r6,HIADJ(CPU_PCI_ISA_IO_ADRS)1056 ori r6,r6,LO(CPU_PCI_ISA_IO_ADRS)10571058 addi r3,r6,0x002E/* adjust to superI/O 87308 base */1059 addi r4,r0,SIO_SIDPNP/* select SID register */1060 bl .sio_br1061 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1062 cmpli0,0,r3,SIO_SID87308/* is it a 87308? */1063 addi r4,r0,0x002E/* adjust to superI/O 87308 base */1064 bc 12,2,.sioInit_87308_fa/* if equal, yes, goto to 87308 init */10651066 addi r3,r6,0x015C/* adjust to superI/O 87308 base */1067 addi r4,r0,SIO_SIDPNP/* select SID register */1068 bl .sio_br1069 andi.r3,r3,SIO_SIDMASK/* mask to identifier bits */1070 cmpli0,0,r3,SIO_SID87308/* is it a 87308? */1071 addi r4,r0,0x015C/* adjust to superI/O 87308 base */1072 bc 12,2,.sioInit_87308_fa/* if equal, yes, goto to 87308 init */10731074 b .sioInit_done/* don’t know what to do... */

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10751076 .sioInit_87308_fa:1077 add r6,r6,r4 /* add offset to base */1078 or r3,r6,r6 /* make a copy */1079 /*1080 ; enable PS/2 mode in SIO configuration register #11081 */1082 addi r4,r0,SIO_CNFG1/* select CNFG1 */1083 bl .sio_br1084 andi.r5,r3,0xFB/* keep all but PS/2-AT mode bit */1085 addi r4,r0,SIO_CNFG1/* select CNFG1 */1086 or r3,r6,r6 /* make a copy */1087 bl .sio_bw1088 /*1089 ; KBC (LUN 0)1090 */1091 addi r4,r0,SIO_LUNINDEX/* select KBC LUN */1092 addi r5,r0,0x01093 bl .sio_bw1094 addi r4,r0,SIO_ACTIVATE/* disable KBC */1095 addi r5,r0,SIO_LUNDISABLE1096 bl .sio_bw1097 addi r4,r0,SIO_LUNCNFGR/* initialize KBC clock to 8 Mhz */1098 addi r5,r0,0x01099 bl .sio_bw1100 addi r4,r0,SIO_DBASEHI/* initialize KBC data base address to 0x060 */1101 addi r5,r0,0x001102 bl .sio_bw1103 addi r4,r0,SIO_DBASELO1104 addi r5,r0,0x601105 bl .sio_bw1106 addi r4,r0,SIO_CBASEHI/* initialize KBC command base address to 0x064 */1107 addi r5,r0,0x001108 bl .sio_bw1109 addi r4,r0,SIO_CBASELO1110 addi r5,r0,0x641111 bl .sio_bw1112 addi r4,r0,SIO_ACTIVATE/* enable KBC */1113 addi r5,r0,SIO_LUNENABLE1114 bl .sio_bw1115 /*1116 ; FDC (LUN 3)1117 */1118 addi r4,r0,SIO_LUNINDEX/* select FDC LUN */1119 addi r5,r0,0x31120 bl .sio_bw1121 addi r4,r0,SIO_IOBASEHI/* initialize FDC address to 0x3F0 */1122 addi r5,r0,0x031123 bl .sio_bw1124 addi r4,r0,SIO_IOBASELO1125 addi r5,r0,0xF01126 bl .sio_bw

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1127 addi r4,r0,SIO_LUNCNFGR/* initialize FDC to PS-2 mode */1128 addi r5,r0,0x401129 bl .sio_bw1130 addi r4,r0,SIO_ACTIVATE/* enable FDC */1131 addi r5,r0,SIO_LUNENABLE1132 bl .sio_bw1133 /*1134 ; COM2 (LUN 5)1135 */1136 addi r4,r0,SIO_LUNINDEX/* select COM2 LUN */1137 addi r5,r0,0x51138 bl .sio_bw1139 addi r4,r0,SIO_IOBASEHI/* initialize COM2 address to 0x2F8 */1140 addi r5,r0,0x021141 bl .sio_bw1142 addi r4,r0,SIO_IOBASELO1143 addi r5,r0,0xF81144 bl .sio_bw1145 addi r4,r0,SIO_ACTIVATE/* enable COM2 */1146 addi r5,r0,SIO_LUNENABLE1147 bl .sio_bw1148 /*1149 ; COM1 (LUN 6)1150 */1151 addi r4,r0,SIO_LUNINDEX/* select COM1 LUN */1152 addi r5,r0,0x61153 bl .sio_bw1154 addi r4,r0,SIO_IOBASEHI/* initialize COM1 address to 0x3F8 */1155 addi r5,r0,0x031156 bl .sio_bw1157 addi r4,r0,SIO_IOBASELO1158 addi r5,r0,0xF81159 bl .sio_bw1160 addi r4,r0,SIO_ACTIVATE/* enable COM1 */1161 addi r5,r0,SIO_LUNENABLE1162 bl .sio_bw1163 /*1164 ; LPT (LUN 4)1165 */1166 addi r4,r0,SIO_LUNINDEX/* select LPT LUN */1167 addi r5,r0,0x41168 bl .sio_bw1169 addi r4,r0,SIO_IOBASEHI/* initialize LPT address to 0x3BC */1170 addi r5,r0,0x031171 bl .sio_bw1172 addi r4,r0,SIO_IOBASELO1173 addi r5,r0,0xBC1174 bl .sio_bw1175 addi r4,r0,SIO_LUNCNFGR/* Put in 87303 compatible mode. */1176 addi r5,r0,0x121177 bl .sio_bw1178 addi r4,r0,SIO_ACTIVATE/* enable LPT */

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1179 addi r5,r0,SIO_LUNENABLE1180 bl .sio_bw1181 b .sioInit_done/* branch to done */1182 /*1183 ; 87303/87323 initialization1184 */1185 .sioInit_87303:1186 add r6,r6,r4 /* add offset to base */1187 or r3,r6,r6 /* make a copy */11881189 addi r4,r0,0 /* initialize FER with 0x4F */1190 addi r5,r0,0x4F1191 bl .sio_bw1192 addi r4,r0,1 /* initialize FAR with 0x11 */1193 addi r5,r0,0x111194 bl .sio_bw1195 addi r4,r0,9 /* initialize ASC to PS-2 mode */1196 addi r5,r0,0x401197 bl .sio_bw1198 addi r4,r0,5 /* retrieve KBC/RTC control register */1199 bl .sio_br1200 andi.r5,r3,0xD0/* keep KBC_CSS, CSE */1201 ori r5,r5,0x0F/* add RTC_E, PAE, KBC_SC, KBC_E */1202 or r3,r6,r6 /* load base address of SIO device */1203 bl .sio_bw1204 .sioInit_done:1205 /*1206 ; for VIPER H/W we need to enable the CSx registers of the SIO1207 ; to point to the MCG classic RTC/NVRAM device1208 */1209 addisr3,r0,CPUCRA_HI/* load addr to CPU config reg */1210 ori r3,r3,CPUCRA_LO1211 lbz r3,0(r3) /* read CPU config reg */1212 andi.r3,r3,PID_MASK/* mask off unwanted data bits */1213 cmpli0,0,r3,PID_VIPER/* is it a VIPER? */1214 bc 4,2,.sioInit_viper_no/* if not equal, no, branch */12151216 /*1217 * Get base addr of ISA I/O space1218 */1219 lis r3,HIADJ(CPU_PCI_ISA_IO_ADRS)1220 ori r3,r3,LO(CPU_PCI_ISA_IO_ADRS)12211222 addi r3,r3,0x015C/* adjust to superI/O 87308 base */1223 or r6,r3,r3 /* make a copy */1224 /*1225 ; CS01226 */1227 addi r4,r0,SIO_PCSCI/* select PCSCIR */1228 addi r5,r0,0x001229 bl .sio_bw1230 addi r4,r0,SIO_PCSCD/* select PCSCDR */

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1231 addi r5,r0,0x001232 bl .sio_bw1233 addi r4,r0,SIO_PCSCI/* select PCSCIR */1234 addi r5,r0,0x011235 bl .sio_bw1236 addi r4,r0,SIO_PCSCD/* select PCSCDR */1237 addi r5,r0,0x761238 bl .sio_bw1239 addi r4,r0,SIO_PCSCI/* select PCSCIR */1240 addi r5,r0,0x021241 bl .sio_bw1242 addi r4,r0,SIO_PCSCD/* select PCSCDR */1243 addi r5,r0,0x401244 bl .sio_bw1245 /*1246 ; CS11247 */1248 addi r4,r0,SIO_PCSCI/* select PCSCIR */1249 addi r5,r0,0x051250 bl .sio_bw1251 addi r4,r0,SIO_PCSCD/* select PCSCDR */1252 addi r5,r0,0x001253 bl .sio_bw1254 addi r4,r0,SIO_PCSCI/* select PCSCIR */1255 addi r5,r0,0x051256 bl .sio_bw1257 addi r4,r0,SIO_PCSCD/* select PCSCDR */1258 addi r5,r0,0x701259 bl .sio_bw1260 addi r4,r0,SIO_PCSCI/* select PCSCIR */1261 addi r5,r0,0x061262 bl .sio_bw1263 addi r4,r0,SIO_PCSCD/* select PCSCDR */1264 addi r5,r0,0x1C1265 bl .sio_bw1266 /*1267 ; CS21268 */1269 addi r4,r0,SIO_PCSCI/* select PCSCIR */1270 addi r5,r0,0x081271 bl .sio_bw1272 addi r4,r0,SIO_PCSCD/* select PCSCDR */1273 addi r5,r0,0x001274 bl .sio_bw1275 addi r4,r0,SIO_PCSCI/* select PCSCIR */1276 addi r5,r0,0x091277 bl .sio_bw1278 addi r4,r0,SIO_PCSCD/* select PCSCDR */1279 addi r5,r0,0x711280 bl .sio_bw1281 addi r4,r0,SIO_PCSCI/* select PCSCIR */1282 addi r5,r0,0x0A

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1283 bl .sio_bw1284 addi r4,r0,SIO_PCSCD/* select PCSCDR */1285 addi r5,r0,0x1C1286 bl .sio_bw1287 /*1288 ; PMC (LUN 8)1289 */1290 addi r4,r0,SIO_LUNINDEX/* select PMC LUN */1291 addi r5,r0,0x81292 bl .sio_bw1293 addi r4,r0,SIO_IOBASEHI/* initialize PMC address to 0x460 */1294 addi r5,r0,0x041295 bl .sio_bw1296 addi r4,r0,SIO_IOBASELO1297 addi r5,r0,0x601298 bl .sio_bw1299 addi r4,r0,SIO_ACTIVATE/* enable PMC */1300 addi r5,r0,SIO_LUNENABLE1301 bl .sio_bw1302 .sioInit_viper_no:1303 mtspr8,r7 /* restore link register */1304 bclr 20,0 /* return to caller */1305 /*1306 ; routine:sio_bw1307 ; this function writes a register to the SIO chip1308 ; call:1309 ; sio_bw(sioaddr, regnum, value)1310 ; return:1311 ; none1312 */1313 .sio_bw:1314 stb r4,0(r3)/* write index register with register offset */1315 eieio1316 sync1317 stb r5,1(r3)/* 1st write */1318 eieio1319 sync1320 stb r5,1(r3)/* 2nd write */1321 eieio1322 sync1323 bclr 20,0 /* return to caller */1324 /*1325 ; routine:sio_br1326 ; this function reads a register from the SIO chip1327 ; call:1328 ; sioInit(sioaddr, regnum)1329 ; return:1330 ; register value1331 */1332 .sio_br:1333 stb r4,0(r3)/* write index register with register offset */1334 eieio

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1335 sync1336 lbz r3,1(r3)/* retrieve specified reg offset contents */1337 eieio1338 sync1339 bclr 20,0 /* return to caller */13401341 #endif /* MV2300 */

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sysHwInit()

1 * sysHwInit - initialize the system hardware2 *3 * This routine initializes various features of the CPU board. It is called4 * by usrInit() in usrConfig.c. This routine sets up the control registers5 * and initializes various devices if they are present.6 *7 * NOTE: This routine should not be called directly by the user application. It8 * cannot be used to initialize interrupt vectors.9 *10 * RETURNS: N/A11 */1213 void sysHwInit (void)14 {15 int pciBusNo; /* PCI bus number */16 int pciDevNo; /* PCI device number */17 int pciFuncNo; /* PCI function number */1819 /*20 * Validate CPU type21 */22 sysCpuCheck();2324 /*25 * Initialize PCI driver library.26 */27 if (pciIomapLibInit (PCI_MECHANISM_1, PCI_PRIMARY_CAR, PCI_PRIMARY_CDR, 0)28 != OK)29 {30 sysToMonitor (BOOT_NO_AUTOBOOT);31 }3233 /*34 * The Raven powers up with the correct PCI Header values.35 * So, no initialization of the PCI Header is performed.36 */3738 /*39 * The IBC powers up with the correct PCI Header values.40 * So, no initialization of the PCI Header is performed.41 */4243 /*44 * Due to a bug in the Universe 1.0 chip, the chip must be disabled45 * prior to reseting the PCI bus. Refer to Universe Device Errata #1646 * and the MVME2600 Series Single Board Computer Programmer’s47 * Reference Guide, Chapter 4, “Universe Chip Problems after a PCI

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48 * Reset”. This code may be removed for boards using the 1.1 rev chip.49 */50 sysUniverseReset ();5152 #ifdef INCLUDE_NETWORK53 /*54 * Initialize the Standard PCI Header of the LANCE device if present55 */56 if ((DEVICE_PRESENT(MV2600_BMFR_LANP) == TRUE) )57 {58 if ((pciFindDevice ((PCI_ID_LN_DEC21140 & 0xFFFF),59 (PCI_ID_LN_DEC21140 >> 16) & 0xFFFF, 0,60 &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR))61 {62 (void)pciDevConfig (pciBusNo, pciDevNo, pciFuncNo,63 PCI_IO_LN_ADRS,64 NULL,65 (PCI_CMD_MASTER_ENABLE | PCI_CMD_IO_ENABLE));66 }67 else68 {69 sysToMonitor (BOOT_NO_AUTOBOOT);70 }71 }72 #endif /* INCLUDE_NETWORK */7374 #ifdef INCLUDE_SCSI75 /*76 * Initialize the Standard PCI Header of the SCSI device if present77 */78 if ((DEVICE_PRESENT(MV2600_BMFR_SCIP) == TRUE) &&79 (pciFindDevice ((PCI_ID_SCSI & 0xFFFF), (PCI_ID_SCSI >> 16) & 0xFFFF,80 0, &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR))81 {82 (void)pciDevConfig (pciBusNo, pciDevNo, pciFuncNo,83 PCI_IO_SCSI_ADRS,84 NULL,85 (PCI_CMD_MASTER_ENABLE | PCI_CMD_IO_ENABLE));86 }87 #endif /* INCLUDE_SCSI */8889 /*90 * Initialize the Standard PCI Header of the VME device if present91 */92 if ((DEVICE_PRESENT(MV2600_BMFR_VMEP) == TRUE) &&93 (pciFindDevice ((PCI_ID_UNIVERSE & 0xFFFF),94 (PCI_ID_UNIVERSE >> 16) & 0xFFFF, 0,95 &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR))96 {97 (void)pciDevConfig (pciBusNo, pciDevNo, pciFuncNo,98 NULL,99 PCI_MEM_UNIVERSE_ADRS,

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100 (PCI_CMD_MASTER_ENABLE | PCI_CMD_MEM_ENABLE));101 }102103 #ifdef INCLUDE_SECONDARY_ENET104 /*105 * Initialize the Standard PCI Header of the dec21040 device106 * (Secondary Ethernet) if present107 */108 if (pciFindDevice (PCI_ID_LN_DEC21040 & 0xFFFF,109 (PCI_ID_LN_DEC21040 >> 16) & 0xFFFF, 0,110 &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)111 {112 (void)pciDevConfig (pciBusNo, pciDevNo, pciFuncNo,113 PCI_IO_LN2_ADRS,114 NULL,115 (PCI_CMD_MASTER_ENABLE | PCI_CMD_IO_ENABLE));116 }117 #endif /* INCLUDE_SECONDARY_ENET */118119 #ifdef INCLUDE_SECONDARY_SCSI120 /*121 * Initialize the Standard PCI Header of the Secondary SCSI device122 * (SYM53C825A) if present.123 */124 if (pciFindDevice (PCI_ID_NCR825 & 0xFFFF, (PCI_ID_NCR825 >> 16) & 0xFFFF,125 1, &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)126 {127 (void)pciDevConfig (pciBusNo, pciDevNo, pciFuncNo,128 PCI_IO_SCSI_ADRS2,129 NULL,130 (PCI_CMD_MASTER_ENABLE | PCI_CMD_IO_ENABLE));131 }132 #endif /* INCLUDE_SECONDARY_SCSI */133134 /*135 * Initialize the extended portion of the Raven’s PCI Header.136 * The non-PCI Config Space registers have already been137 * initialized in the initial startup code.138 */139 if (pciFindDevice ((PCI_ID_RAVEN & 0xFFFF), (PCI_ID_RAVEN >> 16) & 0xFFFF,140 0, &ravPciBusNo, &ravPciDevNo, &ravPciFuncNo) != ERROR)141 {142 (void)sysPciExtRavenInit(ravPciBusNo, ravPciDevNo, ravPciFuncNo);143 }144145 #ifndef INCLUDE_MPIC146 /* Initialize the extended portion of the IBC’s PCI Header. */147148 if (pciFindDevice ((PCI_ID_IBC & 0xFFFF), (PCI_ID_IBC >> 16) & 0xFFFF, 0,149 &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)150 {151 (void)sysPciExtIbcInit(pciBusNo, pciDevNo, pciFuncNo);

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152 }153 #endif /* INCLUDE_MPIC */154155 /*156 * Initialize the non-PCI Config Space registers of the157 * IBC which doesn’t have a true device driver.158 */159 sysIbcInit();160161 /*162 * Reset the MPIC.163 */164 sysPciWrite32( MPIC_ADDR(MPIC_GLOBAL_CONFIG_REG), RESET_CNTRLR );165166 #ifdef INCLUDE_MPIC167 /*168 * Initialize the non-PCI Config Space registers of the169 * Raven Mpic.170 */171 sysMpicInit();172 #endif /* INCLUDE_MPIC */173174 #ifdef INCLUDE_PMC_SPAN175 /*176 * Initialize and configure PMC Span (bridge) to secondary PCI bus.177 */178 if ((DEVICE_PRESENT(MV2600_BMFR_BRGP) == TRUE) &&179 (pciFindDevice ((PCI_ID_BR_DEC21150 & 0xFFFF),180 (PCI_ID_BR_DEC21150 >> 16) & 0xFFFF, 0,181 &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR))182 {183 (void)sysPmcSpanConfig (pciBusNo, pciDevNo, pciFuncNo, sysPmcSpanParm);184 }185 #endif /* INCLUDE_PMC_SPAN */186187 /*188 * The LANCE has a real driver associated with it, so189 * no additional initialization is done here. It’s done190 * at kernel init time.191 */192193 /*194 * The SCSI has a real driver associated with it, so195 * no additional initialization is done here. It’s done196 * at kernel init time.197 */198199 /*200 * Initialize the non-PCI Config Space registers of the201 * Universe which doesn’t have a true device driver.202 */203 sysUniverseInit();

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204205 #ifdef INCLUDE_SECONDARY_ENET206 /*207 * The dec21040 (Secondary Ethernet) has a real driver208 * associated with it, so209 * no additional initialization is done here. For now,210 * the application must create, configure, and establish211 * a route for the device.212 */213 #endif /* INCLUDE_SECONDARY_ENET */214215 #ifdef INCLUDE_SECONDARY_SCSI216 /*217 * The Secondary SCSI (SYM53C825A on the mezzanine) has a218 * real driver associated with it, so no additional219 * initialization is done here. To access it, use220 * pSysScsiCtrl2 when issuing the appropriate calls.221 */222 #endif /* INCLUDE_SECONDARY_SCSI */223224 /* set shared memory TAS Clear routine pointer */225226 smUtilTasClearRtn = (VOIDFUNCPTR)sysBusTasClear;227228 /* set pointer to bus probing hook */229230 _func_vxMemProbeHook = (FUNCPTR)sysBusProbe;231232 /* Initialize COM1 and COM2 serial channels */233234 sysSerialHwInit();235236 /* Extract the Ethernet address out of non-volatile RAM.237 * The Motorola convention for the Ethernet address is that they only238 * save the low 3 bytes in BBRAM. The high three bytes are the239 * manufacturers code, and Motorola software knows its own.240 * The Motorola code is 0x08003Exxx.241 */242 sysNvRamGet ((char *)lnEnetAddr, 6, ((int) BB_ENET - NV_BOOT_OFFSET));243244 /* Disable the watchdog timer */245246 sysNvWrite ((ULONG)WD_TIMER, 0);247248 /*249 * If mmu tables are used, this is where we would dynamically250 * update the entry describing main memory, using sysPhysMemTop().251 * We must call sysPhysMemTop () at sysHwInit() time to do252 * the memory autosizing if available.253 */254255 sysPhysMemTop ();

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256257 /* clear Raven error conditions */258259 sysRavenErrClr ();260261 /* Upon completion, clear BFL (Board Fail) LED */262263 *(UINT8 *)z8536_PORTA_DATA &= ~z8536_PORTA_BRDFAIL;264 }

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sysCpuCheck()

1 void sysCpuCheck (void)2 {3 int msgSize;4 int msgIx;5 SIO_CHAN * pSioChan; /* serial I/O channel */67 /* Check for a valid CPU type; If one is found, just return */89 #if (CPU == PPC603)1011 if ((CPU_TYPE == CPU_TYPE_603) || (CPU_TYPE == CPU_TYPE_603E) ||12 (CPU_TYPE == CPU_TYPE_603P))13 {14 return;15 }1617 #else /* (CPU == PPC604) */1819 if ((CPU_TYPE == CPU_TYPE_604) || (CPU_TYPE == CPU_TYPE_604E) ||20 (CPU_TYPE == CPU_TYPE_604R))21 {22 return;23 }2425 #endif /* (CPU == PPC604) */2627 /* Invalid CPU type; print error message and terminate */2829 msgSize = strlen (wrongCpuMsg);3031 sysSerialHwInit ();3233 pSioChan = sysSerialChanGet (0);3435 sioIoctl (pSioChan, SIO_MODE_SET, (void *) SIO_MODE_POLL);3637 for (msgIx = 0; msgIx < msgSize; msgIx++)38 {39 while (sioPollOutput (pSioChan, wrongCpuMsg[msgIx]) == EAGAIN);40 }4142 sysToMonitor (BOOT_NO_AUTOBOOT);43 }

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sysPhysMemTop()

1 * sysPhysMemTop - get the address of the top of physical memory2 *3 * This routine returns the address of the first missing byte of memory,4 * which indicates the top of memory.5 *6 * Normally, the user specifies the amount of physical memory with the7 * macro LOCAL_MEM_SIZE in config.h. BSPs that support run-time8 * memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.9 * If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the10 * true size of physical memory.11 *12 * NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application13 * use. See sysMemTop() for more information on reserving memory.14 *15 * RETURNS: The address of the top of physical memory.16 *17 * SEE ALSO: sysMemTop()18 */1920 char * sysPhysMemTop (void)21 {22 UINT32 dramAttr;23 UINT32 dramIndex;24 int i;25 static char * sysPhysMemSize = NULL; /* ptr to top of mem + 1 */26 static UINT32 dramSize[8] =27 /* 0, 16MB, 32MB, 64MB,28 128MB, 256MB, 1GB, 0 */29 {0x00000000, 0x01000000, 0x02000000, 0x04000000,30 0x08000000, 0x10000000, 0x40000000, 0x00000000};3132 if (sysPhysMemSize == NULL)33 {34 #ifdef LOCAL_MEM_AUTOSIZE35 /*36 * Do dynamic memory sizing.37 *38 * Since Falcon memory controller chip has already been set to39 * control all memory, just read and interpret its DRAM Attributes40 * Register.41 */4243 dramAttr = sysIn32 ((UINT32 *)FALCON_DRAM_ATTR);44 for (i = 0; i < 4; ++i)45 {46 if ((dramAttr & 0x80) != 0)47 {

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48 dramIndex = dramAttr & 0x07;49 (UINT32)sysPhysMemSize += dramSize [dramIndex];50 }51 dramAttr >>= 8;52 }5354 /* Adjust initial DRAM size to actual physical memory. */5556 sysPhysMemDesc[1].len = (ULONG)sysPhysMemSize -57 (ULONG)sysPhysMemDesc[1].physicalAddr;5859 #else /* not LOCAL_MEM_AUTOSIZE */60 /* Don’t do auto-sizing, use defined constants. */6162 sysPhysMemSize = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);63 #endif /* LOCAL_MEM_AUTOSIZE */64 }6566 return sysPhysMemSize;67 }

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sysHwInit2()

1 /****************************************************************************23 * sysHwInit2 - initialize additional system hardware4 *5 * This routine connects system interrupt vectors and configures any6 * required features not configured by sysHwInit().7 *8 * RETURNS: N/A9 */1011 void sysHwInit2 (void)12 {13 static BOOL configured = FALSE;1415 /* Int connects for various devices */1617 if (!configured)18 {19 /* connect Vme to PCI interrupt */2021 intConnect (INUM_TO_IVEC(UNIV_INT_VEC), sysUnivVmeIntr, 0);2223 /* interrupts can only be turned on ultimately by the PIC int ctrlr */2425 intEnable (UNIV_INT_LVL);2627 #ifndef MV230028 sysZ8536Init();29 intConnect (INUM_TO_IVEC(Z8536_INT_VEC), sysClkIntCIO, 0);30 intEnable (Z8536_INT_LVL);31 #endif /* MV2300 */3233 /* initialize serial interrupts */3435 sysSerialHwInit2();3637 /* connect a dummy routine for the spurious interrupt (0x07) */3839 intConnect (INUM_TO_IVEC(PP_INT_LVL), sysSpuriousIntHandler, 0);4041 #ifdef INCLUDE_CACHE_L242 #ifdef INCLUDE_CACHE_SUPPORT43 #ifdef USER_L2_CACHE_ENABLE44 /* initialize the L2 cache */4546 sysL2CacheInit();47 #else

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48 sysL2CacheDisable();49 #endif50 #endif51 #endif5253 configured = TRUE;54 }55 }

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dcattach()

1 /****************************************************************************2 * dcattach - publish the `dc’network interface.3 *4 * This routine publishes the `dc’interface by filling in a network interface5 * record and adding this record to the system list. This routine also6 * initializes the driver and the device to the operational state.7 *8 * The <unit> parameter is used to specify the device unit to initialize.9 *10 * The <devAdrs> is used to specify the I/O address base of the device.11 *12 * The <ivec> parameter is used to specify the interrupt vector associated13 * with the device interrupt.14 *15 * The <ilevel> parater is used to specify the level of the interrupt which16 * the device would use.17 *18 * The <memAdrs> parameter can be used to specify the location of the19 * memory that will be shared between the driver and the device. The value20 * NONE is used to indicate that the driver should obtain the memory.21 *22 * The <memSize> parameter is valid only if the <memAdrs> parameter is not23 * set to NONE, in which case <memSize> indicates the size of the24 * provided memory region.25 *26 * The <memWidth> parameter sets the memory pool’s data port width (in bytes);27 * if it is NONE, any data width is used.28 *29 * The <pciMemBase> parameter defines the main memory base as seen from PCI bus.30 *31 * The <dcOpMode> parameter defines the mode in which the device should be32 * operational.33 *34 * BUGS35 * To zero out LANCE data structures, this routine uses bzero(), which36 * ignores the <memWidth> specification and uses any size data access to37 * write to memory.38 *39 * RETURNS: OK or ERROR.40 */4142 STATUS dcattach43 (44 int unit, /* unit number */45 ULONG devAdrs, /* LANCE I/O address */46 int ivec, /* interrupt vector */47 int ilevel, /* interrupt level */

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48 char * memAdrs, /* address of memory pool (-1 = malloc it) */49 ULONG memSize, /* only used if memory pool is NOT malloc()’d */50 int memWidth, /* byte-width of data (-1 = any width) */51 ULONG pciMemBase, /* main memory base as seen from PCI bus */52 int dcOpMode /* mode of operation */53 )54 {55 DRV_CTRL * pDrvCtrl; /* pointer to drvctrl */56 unsigned int sz; /* temporary size holder */57 char * pShMem; /* start of the LANCE memory pool */58 char * buf; /* temp buffer pointer */59 void * pTemp; /* temp pointer */60 DC_RDE * rmd; /* pointer to rcv descriptor */61 DC_TDE * tmd; /* pointer to xmit descriptor */62 int ix; /* counter */63 ULONG uTemp; /* temporary storage */6465 /* Sanity check the unit number */6667 if (unit < 0 || unit >= MAX_UNITS)68 return (ERROR);6970 uTemp = 0;7172 /* Ensure single invocation per system life */7374 pDrvCtrl = & drvCtrl [unit];7576 if (pDrvCtrl->attached)77 return (OK);7879 pDrvCtrl->ivec = ivec; /* interrupt vector */80 pDrvCtrl->ilevel= ilevel; /* interrupt level */81 pDrvCtrl->devAdrs = devAdrs; /* LANCE I/O address */82 pDrvCtrl->pciMemBase = pciMemBase; /* pci memory base */83 pDrvCtrl->memWidth = memWidth; /* memory width */84 pDrvCtrl->dcOpMode = dcOpMode; /* mode of operation */8586 /* Publish the interface data record */8788 ether_attach (89 & pDrvCtrl->idr.ac_if,90 unit,91 “dc”,92 (FUNCPTR) NULL,93 (FUNCPTR) dcIoctl,94 (FUNCPTR) dcOutput,95 (FUNCPTR) dcReset96 );9798 #ifdef DC_DEBUG99 bzero ((char *)&pDrvCtrl->errStats, sizeof (DC_STATS));

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100 #endif /* DC_DEBUG */101102 dcInit(pDrvCtrl->devAdrs);103104 /* Create the transmit semaphore. */105106 if ((pDrvCtrl->TxSem = semMCreate (SEM_Q_PRIORITY | SEM_DELETE_SAFE |107 SEM_INVERSION_SAFE)) == NULL)108 {109 printf (“dc: error creating transmitter semaphore\n”);110 return (ERROR);111 }112113 /* Establish size of shared memory region we require */114115 if ((int) memAdrs != NONE) /* specified memory pool */116 {117 sz = ((memSize - FLTR_FRM_SIZE + RMD_SIZ + TMD_SIZ) /118 ((3 * DC_BUFSIZ) + RMD_SIZ + TMD_SIZ));119 dcNumRds = max (sz, MIN_RDS);120 dcNumTds = max (sz, MIN_TDS);121 dcLPool = min (dcNumRds, DC_L_POOL);122 }123124 /* add it all up - allow for alignment adjustment */125126 sz = ((dcNumRds + 1) * RMD_SIZ) + (dcNumRds * DC_BUFSIZ) +127 ((dcNumTds + 1) * TMD_SIZ) + (dcNumTds * DC_BUFSIZ) +128 (DC_BUFSIZ * dcLPool) + FLTR_FRM_SIZE;129130 /* Establish a region of shared memory */131 /*132 * OK. We now know how much shared memory we need. If the caller133 * provides a specific memory region, we check to see if the provided134 * region is large enough for our needs. If the caller did not135 * provide a specific region, then we attempt to allocate the memory136 * from the system, using the cache aware allocation system call.137 */138139 switch ((int) memAdrs)140 {141 default : /* caller provided memory */142 if (memSize < sz) /* not enough space */143 {144 printf (“dc: not enough memory provided\n”);145 return (ERROR);146 }147 else148 dcNumRds += (memSize - sz) / (DC_BUFSIZ + TMD_SIZ);149150 pShMem = memAdrs; /* set the beginning of pool */151

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152 /* assume pool is cache coherent, copy null structure */153154 pDrvCtrl->cacheFuncs = cacheNullFuncs;155156 break;157158 case NONE : /* get our own memory */159160161 /*162 * Because the structures that are shared between the device163 * and the driver may share cache lines, the possibility exists164 * that the driver could flush a cache line for a structure and165 * wipe out an asynchronous change by the device to a neighboring166 * structure. Therefore, this driver cannot operate with memory167 * that is not write coherent. We check for the availability of168 * such memory here, and abort if the system did not give us what169 * we need.170 */171 if (!CACHE_DMA_IS_WRITE_COHERENT ())172 {173 printf (“dc: device requires cache coherent memory\n”);174 return (ERROR);175 }176177 pShMem = (char *) cacheDmaMalloc (sz);178179 if ((int)pShMem == NULL)180 {181 printf (“dc: system memory unavailable \n”);182 return (ERROR);183 }184185 /* copy the DMA structure */186187 pDrvCtrl->cacheFuncs = cacheDmaFuncs;188189 break;190 }191192 if (intConnect ((VOIDFUNCPTR *)INUM_TO_IVEC(ivec),dcInt,(int)pDrvCtrl)193 == ERROR)194 return (ERROR);195196 /* Turkey Carving197 * --------------198 * LOW MEMORY199 * |--------------------------------------------|200 * | The Rx descriptors |201 * | (dcNumRds * sizeof (DC_RDE)) |202 * |--------------------------------------------|203 * | The receive buffers |

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204 * | (DC_BUFSIZ * dcNumRds) |205 * |-------------------------------------------|206 * | The Rx loaner pool |207 * | (DC_BUFSIZ * dcLPool) |208 * |------------------------------------------|209 * | The Tx descriptors |210 * | (dcNumTds * sizeof (DC_TDE)) |211 * |------------------------------------------|212 * | The transmit buffers |213 * | (DC_BUFSIZ * dcNumTds) |214 * |------------------------------------------|215 * | Setup Filter Frame |216 * | (FLTR_FRM_SIZE) |217 * |-----------------------------------------|218 */219220 /* zero the shared memory */221222 bzero ( (char *) pShMem, (int) sz );223224 /* carve Rx memory structure */225226 pDrvCtrl->rxRing = (DC_RDE *) (((int)pShMem + 0x03) & ~0x03); /* wd align */227 pDrvCtrl->dcNumRds = dcNumRds; /* receive ring size */228 pDrvCtrl->rxIndex = 0;229230 /* Set up the Rx descriptors */231232 rmd = pDrvCtrl->rxRing; /* receive ring */233 buf = (char *)(rmd + pDrvCtrl->dcNumRds);234 for (ix = 0; ix < pDrvCtrl->dcNumRds; ix++, rmd++, buf += DC_BUFSIZ)235 {236 pTemp = DC_CACHE_VIRT_TO_PHYS (buf); /* convert to PCI phys addr */237 pTemp = (void *)(MEM_TO_PCI_PHYS((ULONG)pTemp));238 rmd->rDesc2 = PCISWAP((ULONG)pTemp); /* buffer address 1 */239 rmd->rDesc3 = 0; /* no second buffer */240241 /* buffer size */242243 rmd->rDesc1 = PCISWAP(RDESC1_RBS1_VAL(DC_BUFSIZ) |244 RDESC1_RBS2_VAL(0));245246 if (ix == (pDrvCtrl->dcNumRds - 1)) /* if its is last one */247 rmd->rDesc1 |= PCISWAP(RDESC1_RER); /* end of receive ring */248249 rmd->rDesc0 = PCISWAP(RDESC0_OWN); /* give ownership to lance */250 }251252 /* setup Rx loaner pool */253254 pDrvCtrl->nLoanRx = dcLPool;255 for (ix = 0; ix < dcLPool; ix++, buf += DC_BUFSIZ)

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256 {257 pDrvCtrl->lPool[ix] = buf;258 pDrvCtrl->refCnt[ix] = 0;259 pDrvCtrl->pRefCnt[ix] = & pDrvCtrl->refCnt[ix];260 }261262 /* carve Tx memory structure */263264 pDrvCtrl->txRing = (DC_TDE *) (((int)buf + 0x03) & ~0x03); /* word align */265 pDrvCtrl->dcNumTds = dcNumTds; /* transmit ring size */266 pDrvCtrl->txIndex = 0;267 pDrvCtrl->txDiIndex = 0;268269 /* Setup the Tx descriptors */270271 tmd = pDrvCtrl->txRing; /* transmit ring */272 buf = (char *)(tmd + pDrvCtrl->dcNumTds);273 for (ix = 0; ix < pDrvCtrl->dcNumTds; ix++, tmd++, buf += DC_BUFSIZ)274 {275 pTemp = DC_CACHE_VIRT_TO_PHYS (buf); /* convert to PCI phys addr */276 pTemp = (void *)(MEM_TO_PCI_PHYS((ULONG)pTemp));277 tmd->tDesc2 = PCISWAP((ULONG)pTemp); /* buffer address 1 */278 tmd->tDesc3 = 0; /* no second buffer */279280 tmd->tDesc1 = PCISWAP((TDESC1_TBS1_PUT(0) |281 TDESC1_TBS2_PUT(0) |282 TDESC1_IC | /* intrpt on xmit */283 TDESC1_LS | /* last segment */284 TDESC1_FS)); /* first segment */285286 if (ix == (pDrvCtrl->dcNumTds - 1)) /* if its is last one */287 tmd->tDesc1 |= PCISWAP(TDESC1_TER); /* end of Xmit ring */288289 tmd->tDesc0 = 0 ; /* clear status */290 }291292 /* carve Setup Filter Frame buffer */293294 pDrvCtrl->pFltrFrm = (ULONG *)(((int)buf + 0x03) & ~0x03); /* word align */295 buf += FLTR_FRM_SIZE;296297 /* Flush the write pipe */298299 CACHE_PIPE_FLUSH ();300301 /* Device Initialization */302303 dcChipReset (pDrvCtrl); /* reset the chip */304305 pTemp = DC_CACHE_VIRT_TO_PHYS (pDrvCtrl->rxRing);306 pTemp = (void *)(MEM_TO_PCI_PHYS((ULONG)pTemp));307

B-74

308 dcCsrWrite (devAdrs, CSR3, ((ULONG)pTemp)); /* recv descriptor */309310 pTemp = DC_CACHE_VIRT_TO_PHYS (pDrvCtrl->txRing);311 pTemp = (void *)(MEM_TO_PCI_PHYS((ULONG)pTemp));312313 dcCsrWrite (devAdrs, CSR4, ((ULONG)pTemp)); /* xmit descriptor */314315 /* get the ethernet address */316317 if (!DEC21140(pDrvCtrl->dcOpMode))318 {319 if (dcEnetAddrGet (devAdrs, (char *) pDrvCtrl->idr.ac_enaddr, 6) != OK)320 logMsg (“dc: error reading ethernet rom\n”, 0,0,0,0,0,0);321 }322 else323 {324 if (dc21140EnetAddrGet (devAdrs, (char *) pDrvCtrl->idr.ac_enaddr, 6)325 != OK)326 logMsg (“dc21140: error reading ethernet rom\n”, 0,0,0,0,0,0);327 }328329 if (!DEC21140(pDrvCtrl->dcOpMode))330 {331 dc21040AuiTpInit (devAdrs); /* configure AUI or 10BASE-T */332 dcCsrWrite (devAdrs, CSR6, 0x0);333 pDrvCtrl->dcMediaBlocks.DontSwitch = 1;334 }335 else336 {337 dcCsrWrite (devAdrs, CSR6, 0x0);338 dc21140AuiMiiInit (pDrvCtrl, devAdrs, uTemp);339 }340341 if ((pDrvCtrl->dcOpMode & DC_FULLDUPLEX_FLAG) &&342 (pDrvCtrl->dcOpMode != NONE))343 dcCsrWrite (devAdrs, CSR6, (dcCsrRead(devAdrs, CSR6) | CSR6_FD));344345 /* clear the status register */346347 dcCsrWrite (devAdrs, CSR5, 0xffffffff);348349 /* set the operating mode to start Xmitter only */350351 dcCsrWrite (devAdrs, CSR6,352 (dcCsrRead (devAdrs, CSR6) | CSR6_ST | CSR6_BIT25));353354 if ((pDrvCtrl->dcOpMode & DC_ILOOPB_FLAG) &&355 (pDrvCtrl->dcOpMode != NONE))356 dcCsrWrite (devAdrs, CSR6, (dcCsrRead(devAdrs, CSR6) | CSR6_OM_ILB));357 else358 if ((pDrvCtrl->dcOpMode & DC_ELOOPB_FLAG) &&359 (pDrvCtrl->dcOpMode != NONE))

B-75

360 dcCsrWrite (devAdrs, CSR6, (dcCsrRead(devAdrs, CSR6) | CSR6_OM_ELB));361362 /* Xmit a Filter Setup Frame */363364 dcFltrFrmXmit (pDrvCtrl, (char *) pDrvCtrl->idr.ac_enaddr, 1);365366 /* set operating mode any additional operational mode set by user */367368 dcCsrWrite (devAdrs, CSR6, (dcCsrRead(devAdrs, CSR6) |369 CSR6_SR | /* start receiver */370 (((pDrvCtrl->dcOpMode & DC_MULTICAST_FLAG) &&371 (pDrvCtrl->dcOpMode != NONE)) ? CSR6_PM: 0) |372 (((pDrvCtrl->dcOpMode & DC_PROMISCUOUS_FLAG) &&373 (pDrvCtrl->dcOpMode != NONE)) ? CSR6_PR: 0)374 ));375376 /* set up the interrupts */377378 if (!DEC21140(pDrvCtrl->dcOpMode))379 dcCsrWrite (devAdrs, CSR7, (380 CSR7_NIM | /* normal interrupt mask */381 CSR7_AIM | /* abnormal interrupt mask */382 CSR7_SEM | /* system error mask */383 CSR7_RIM | /* rcv interrupt mask */384 CSR7_RUM | /* rcv buff unavailable mask */385 CSR7_TUM /* xmit buff unavailble mask */386 ));387 else388 dcCsrWrite (devAdrs, CSR7, (389 CSR7_NIM | /* normal interrupt mask */390 CSR7_AIM | /* abnormal interrupt mask */391 CSR7_SEM | /* system error mask */392 CSR7_RIM | /* rcv interrupt mask */393 CSR7_RUM | /* rcv buff unavailable mask */394 CSR7_TUM /* xmit buff unavailble mask */395 ));396397 sysLanIntEnable (ilevel); /* enable LANCE interrupts */398399 pDrvCtrl->idr.ac_if.if_flags |= (IFF_UP | IFF_RUNNING | IFF_NOTRAILERS);400401 /* Set our flag */402403 pDrvCtrl->attached = TRUE;404 pDrvCtrl->txFlushScheduled = FALSE;405406 return (OK);407 }408


Appendix - C

bootInit.c

C-2

bootInit.c

1 /* bootInit.c - ROM initialization module */23 /* Copyright 1989-1997 Wind River Systems, Inc. */4 #include “copyright_wrs.h”56 /*7 modification history8 --------------------9 04p,12feb97,dat Added USER_RESERVED_MEM, SYS_MEM_TOP, SYS_MEM_BOTTOM, SPR 803010 04o,04feb97,ms fixed compiler warning about protoype for bcopyLongs.11 04n,03sep96,hdn added the compression support for pc[34]86 BSP.12 04m,19aug96,ms added UNCMP_RTN macro to use inflate instead of uncompress13 04l,21jun96,jmb long modhist -- deleted entries prior to 1994. SPR #652814 03k,10jun96,tam added rom resident support for PPC architecture.15 03j,14may96,dat fixed compiler warnings for copyLongs , fillLongs. SPR #653616 03i,06mar96,tpr changed absEntry to be volatile for PowerPC.17 03h,22aug95,hdn added support for I80X86.18 03g,14mar95,caf restored mips resident rom support (SPR #3856).19 03f,16feb95,jdi doc format change.20 03f,23may95,yao define binArrayStart and binArrayEnd for PowerPC21 because tools don’t prepend “_”.22 03e,09dec94,caf undid mod 03a, use sdata for resident roms (SPR #3856).23 03d,22jun94,caf undid 16-byte alignment portion of mod 03c, below.24 03c,14jun94,cd corrected definitions of etext, edata and end.25 +caf for R4000 resident ROMs: data starts on 16-byte boundary.26 for R4000 uncompressed ROMs: added volatile to absEntry type.27 */2829 /*30 DESCRIPTION31 This module provides a generic boot ROM facility. The target-specific32 romInit.s module performs the minimal preliminary board initialization and33 then jumps to the C routine romStart(). This routine, still executing out34 of ROM, copies the first stage of the startup code to a RAM address and35 jumps to it. The next stage clears memory and then uncompresses the36 remainder of ROM into the finalVxWorks ROM image in RAM.3738 A modified version of the Public Domain \f3zlib\fP library is used to39 uncompress the VxWorks boot ROM executable linked with it. Compressing40 object code typically achieves over 55% compression, permitting much41 larger systems to be burned into ROM. The only expense is the added few42 seconds delay while the first two stages complete.4344 ROM AND RAM MEMORY LAYOUT45 Example memory layout for a 1-megabyte board:46 .bS 2247 -------------- 0x00100000 = LOCAL_MEM_SIZE = sysMemTop()48 | |49 | RAM |

C-3

50 | 0 filled |51 | |52 |-------------------- | = (romInit+ROM_COPY_SIZE) or binArrayStart53 | ROM image |54 |-------------------- | 0x00090000 = RAM_HIGH_ADRS55 | STACK_SAVE |56 |--------------------- |57 | | 0x00080000 = 0.5 Megabytes58 | |59 | |60 | 0 filled |61 | |62 | | 0x00001000 = RAM_ADRS & RAM_LOW_ADRS63 | |64 | | exc vectors, bp anchor, exc msg, bootline65 | |66 | |67 ---------------------- 0x00000000 = LOCAL_MEM_LOCAL_ADRS68 .bE69 .bS 670 ----------------------71 | ROM |72 | | 0xff8xxxxx = binArrayStart73 | |74 | | 0xff800008 = ROM_TEXT_ADRS75 ---------------------- 0xff800000 = ROM_BASE_ADRS76 .bE7778 SEE ALSO:79 inflate(), romInit(), and deflate8081 AUTHOR82 The original compression software for zlib was written by Jean-loup Gailly83 and Mark Adler. See the manual pages of inflate and deflate for84 more information on their freely available compression software.85 */8687 #include “vxWorks.h”88 #include “sysLib.h”89 #include “config.h”90 #include “errno.h”91 #include “sioLib.h”9293 #defineUNCMP_RTNinflate9495 #ifndef USER_RESERVED_MEM96 # define USER_RESERVED_MEM 097 #endif9899 /*100 * If memory is to be cleared, it will be cleared from SYS_MEM_BOTTOM101 * up to (but not including) SYS_MEM_TOP, except for text and data segments.

C-4

102 * The user reserved area is not cleared.103 */104105 #defineSYS_MEM_TOP \106 (LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE - USER_RESERVED_MEM)107108 #define SYS_MEM_BOTTOM \109 (LOCAL_MEM_LOCAL_ADRS + RESERVED)110111 IMPORT voidromInit ();112 IMPORT STATUSUNCMP_RTN ();113 IMPORT voidusrInit ();114 IMPORT voidsysInitAlt ();115 IMPORT voidstart ();116117 #if ((CPU_FAMILY == MIPS) || (CPU_FAMILY==PPC))118 #definebinArrayStart_binArrayStart119 #definebinArrayEnd_binArrayEnd120 #defineRESIDENT_DATARAM_DST_ADRS121 #else122 #defineRESIDENT_DATA(&sdata)123 IMPORT charsdata; /* defined in romInit.s */124 #endif125126 IMPORT UCHARbinArrayStart [];/* compressed binary image */127 IMPORT UCHARbinArrayEnd;/* end of compressed binary image */128 IMPORT charetext [];/* defined by the loader */129 IMPORT charedata [];/* defined by the loader */130 IMPORT charend []; /* defined by the loader */131132133 #ifndef RAM_DST_ADRS /* default uncompress dest. */134 #define RAM_DST_ADRS RAM_HIGH_ADRS135 #endif136137 /* If the boot code is in RAM and the RAM is already initialized,138 * clearing the RAM is not necessary. Macro BOOTCODE_IN_RAM is139 * used not to clear the RAM.140 */141 #ifdefBOOTCODE_IN_RAM/* not to clear RAM */142 #undefROM_TEXT_ADRS143 #undefROM_BASE_ADRS144 #defineROM_TEXT_ADRS((UINT)romInit)145 #defineROM_BASE_ADRS((UINT)romInit)146 #endif/* BOOTCODE_IN_RAM */147148 #if defined (UNCOMPRESS) || defined (ROM_RESIDENT)149 #defineROM_COPY_SIZE(ROM_SIZE - (ROM_TEXT_ADRS - ROM_BASE_ADRS))150 #endif/* UNCOMPRESS */151152 #define ROM_OFFSET(adr)(((UINT)adr - (UINT)romInit) + ROM_TEXT_ADRS)153

C-5

154 /* forward declarations */155156 LOCAL void copyLongs (FAST UINT *source, FAST UINT *destination, UINT nlongs);157 #ifndefBOOTCODE_IN_RAM158 LOCAL void fillLongs (FAST UINT *buf, UINT nlongs, FAST UINT val);159 #endif/* BOOTCODE_IN_RAM */160161 /

*******************************************************************************

162 *163 * romStart - generic ROM initialization164 *165 * This is the first C code executed after reset.166 *167 * This routine is called by the assembly start-up code in romInit().168 * It clears memory, copies ROM to RAM, and possibly invokes the uncompressor.169 * It then jumps to the entry point of the uncompressed object code.170 *171 * RETURNS: N/A172 */173174 void romStart175 (176 FAST int startType/* start type */177 )178179 {180 #if ((CPU_FAMILY==SPARC) || (CPU_FAMILY==MIPS) || (CPU_FAMILY==I80X86) || \181 (CPU_FAMILY==PPC))182 volatile /* to force absolute adressing */183 #endif /* (CPU_FAMILY==SPARC) */184 FUNCPTR absEntry;/* to avoid PC Relative Jump Subroutine */185186 /*187 * Copy from ROM to RAM, minus the compressed image188 * if compressed boot ROM which relies on binArray189 * appearing last in DATA segment.190 */191192 #ifdef ROM_RESIDENT193 /* If ROM resident code, then copy only data segment194 * from ROM to RAM, initialize memory and jump195 * to usrInit.196 */197198199 #if (CPU_FAMILY == SPARC)200 copyLongs ((UINT *)(etext + 8), (UINT *) RESIDENT_DATA,201 #elif((CPU_FAMILY == MIPS) || (CPU_FAMILY == PPC))202 copyLongs ((UINT *)(etext + 0), (UINT *) RESIDENT_DATA,203 #else

C-6

204 copyLongs ((UINT *)(etext + 4), (UINT *) RESIDENT_DATA,205 #endif206 ((UINT) edata - (UINT) RESIDENT_DATA) / sizeof (long));207208 #else/* ROM_RESIDENT */209210 #ifdef UNCOMPRESS211212 #if (CPU_FAMILY == MIPS)213 /*214 * copy text to uncached locations to avoid problems with215 * copy back caches216 */217 ((FUNCPTR)ROM_OFFSET(copyLongs)) (ROM_TEXT_ADRS, (UINT)K0_TO_K1(romInit),218 ROM_COPY_SIZE / sizeof (long));219 #else/* CPU_FAMILY == MIPS */220 ((FUNCPTR)ROM_OFFSET(copyLongs)) (ROM_TEXT_ADRS, (UINT)romInit,221 ROM_COPY_SIZE / sizeof (long));222 #endif/* CPU_FAMILY == MIPS */223224 #else/* UNCOMPRESS */225226 #if (CPU_FAMILY == MIPS)227 /*228 * copy text to uncached locations to avoid problems with229 * copy back caches230 * copy the entire data segment because there is no way to ensure that231 * binArray is the last thing in the data segment because of GP relative232 * addressing233 */234 ((FUNCPTR)ROM_OFFSET(copyLongs)) (ROM_TEXT_ADRS, (UINT)K0_TO_K1(romInit),235 ((UINT)edata - (UINT)romInit) / sizeof (long));236 #else/* CPU_FAMILY == MIPS */237 ((FUNCPTR)ROM_OFFSET(copyLongs)) (ROM_TEXT_ADRS, (UINT)romInit ,238 ((UINT)binArrayStart - (UINT)romInit) / sizeof (long));239 #endif/* CPU_FAMILY == MIPS */240241 #endif/* UNCOMPRESS */242 #endif/* ROM_RESIDENT */243244245 #if (CPU_FAMILY != MIPS) && (!defined (BOOTCODE_IN_RAM))246247 /* clear all memory if cold booting */248249 if (startType & BOOT_CLEAR)250 {251 #ifdef ROM_RESIDENT252 /* Clear memory not loaded with text & data.253 *254 * We are careful about initializing all memory (except255 * STACK_SAVE bytes) due to parity error generation (on

C-7

256 * some hardware) at a later stage. This is usually257 * caused by read accesses without initialization.258 */259 fillLongs ((UINT *)SYS_MEM_BOTTOM,260 ((UINT) RESIDENT_DATA - STACK_SAVE - (UINT)SYS_MEM_BOTTOM)261 / sizeof(long), 0);262 fillLongs (((UINT *) edata),263 ((UINT)SYS_MEM_TOP - ((UINT) edata)) / sizeof(long), 0);264265 #else/* ROM_RESIDENT */266 fillLongs ((UINT *)(SYS_MEM_BOTTOM),267 ((UINT)romInit - STACK_SAVE - (UINT)SYS_MEM_BOTTOM) /268 sizeof(long), 0);269270 #if defined (UNCOMPRESS)271 fillLongs ((UINT *)((UINT)romInit + ROM_COPY_SIZE),272 ((UINT)SYS_MEM_TOP - ((UINT)romInit + ROM_COPY_SIZE))273 / sizeof(long), 0);274 #else275 fillLongs ((UINT *)binArrayStart,276 ((UINT)SYS_MEM_TOP - (UINT)binArrayStart) / sizeof (long), 0);277 #endif /* UNCOMPRESS */278 #endif /* ROM_RESIDENT */279280 }281282 #endif/* (CPU_FAMILY != MIPS) && (!defined (BOOTCODE_IN_RAM)) */283284 /* jump to VxWorks entry point (after uncompressing) */285286 #if defined (UNCOMPRESS) || defined (ROM_RESIDENT)287 #if (CPU_FAMILY == I960)288 absEntry = (FUNCPTR)sysInitAlt;/* reinit proc tbl */289 #else290 absEntry = (FUNCPTR)usrInit;/* on to bootConfig */291 #endif/* CPU_FAMILY == I960 */292293 #else294 {295 #if (CPU_FAMILY == MIPS)296 volatile FUNCPTR absUncompress = (FUNCPTR) UNCMP_RTN;297 if ((absUncompress) ((UCHAR *)ROM_OFFSET(binArrayStart),298 (UCHAR *)K0_TO_K1(RAM_DST_ADRS),299 (int)((UINT)&binArrayEnd - (UINT)binArrayStart)) != OK)300 #elif(CPU_FAMILY == I80X86)301 volatile FUNCPTR absUncompress = (FUNCPTR) UNCMP_RTN;302 if ((absUncompress) ((UCHAR *)ROM_OFFSET(binArrayStart),303 (UCHAR *)RAM_DST_ADRS, &binArrayEnd - binArrayStart) != OK)304 #else305 if (UNCMP_RTN ((UCHAR *)ROM_OFFSET(binArrayStart),306 (UCHAR *)RAM_DST_ADRS, &binArrayEnd - binArrayStart) != OK)307 #endif/* (CPU_FAMILY == MIPS) */

C-8

308 return; /* if we return then ROM’s will halt */309310 absEntry = (FUNCPTR)RAM_DST_ADRS;/* compressedEntry () */311 }312 #endif/* defined UNCOMPRESS || defined ROM_RESIDENT */313314 (absEntry) (startType);315 }316317318 /

*******************************************************************************

319 *320 * copyLongs - copy one buffer to another a long at a time321 *322 * This routine copies the first <nlongs> longs from <source> to <destination>.323 */324325 LOCAL void copyLongs (source, destination, nlongs)326 FAST UINT *source;/* pointer to source buffer */327 FAST UINT *destination;/* pointer to destination buffer */328 UINT nlongs;/* number of longs to copy */329330 {331 FAST UINT *dstend = destination + nlongs;332333 while (destination < dstend)334 *destination++ = *source++;335 }336337 #ifndefBOOTCODE_IN_RAM338 /

*******************************************************************************

339 *340 * fillLongs - fill a buffer with a value a long at a time341 *342 * This routine fills the first <nlongs> longs of the buffer with <val>.343 */344345 LOCAL void fillLongs (buf, nlongs , val)346 FAST UINT *buf;/* pointer to buffer */347 UINT nlongs;/* number of longs to fill */348 FAST UINT val;/* char with which to fill buffer */349350 {351 FAST UINT *bufend = buf + nlongs;352353 while (buf < bufend)354 *buf++ = val;355 }

C-9

356 #endif/* BOOTCODE_IN_RAM */


Appendix - D

usrConfig.c

D-2

usrConfig.c

1 /* usrConfig.c - user-defined system configuration library */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 #include “copyright_wrs.h”56 /*7 modification history8 --------------------9 18o,26feb97,dat added INCLUDE_USER_APPL and USER_APPL_INIT, spr 8071.10 18n,13dec96,elp changed syncLibInit() into symSyncLibInit().11 18m,18nov96,dds SPR 2529: return status for sysScsiInit is now checked.12 18l,06nov96,ms removed 17n hack to usrClock.13 18k,01nov96,hdn added support for PCMCIA.14 18j,21oct96,hdn changed paramerters for new LPT driver.15 18i,04oct96,elp added INCLUDE_SYM_TBL_SYNC (SPR# 6775).16 18h,11jul96,tam changed copyright year from 1995 to 1996.17 18l,19jul96,hdn added support for ATA driver.18 18k,25jun96,jmb Eliminated alternative WDB macro names (SPR #5707).19 18j,25jun96,dbt Initialized _func_selWakeupListInit before tyLib (SPR #3314).20 18i,21jun96,jmb update copyright. SPR #636421 18h,21jun96,jmb long modhist -- deleted entries prior to 1994. SPR #652822 18g,12mar96,tam removed all #if (CPU == PPC403).23 18p,06jun96,ism bumped copyright to 1996.24 18o,26jan96,ism cleaned up vxsim/solaris version25 18f,02oct95,kvk added sysHwInit2() for PPC603.26 18e,27sep95,tpr removed #if (CPU_FAMILY != PPC) staff.27 18n,07nov95,srh fixed C++ support comments.28 18m,29oct95,dat fixed warnings about printf arguments29 18l,11oct95,jdi doc: changed .pG to .tG.30 18k,10oct95,dat new BSP revision id. Added WDB Banner printing31 18j,15jun95,ms updated for new serial drivers.32 18i,09jun95,ms cleaned up console initialization33 18h,30may95,p_m added initialization of formatted I/O library.34 replaced spyStop() by spyLibInit().35 18g,22may95,p_m no longer initialize object format specific libraries if36 loader is not included.37 18f,22may95,myz modified new serial device initialization for x86 support38 18e,22may95,ms added some WDB agent support39 18e,30oct95,ism updated for SIMSPARCSOLARIS40 18d,28mar95,kkk added scalability support, changed edata and end to arrays41 (SPR #3917), changed baud rate to be a macro in configAll.h42 18g,25may95,yao changed to bzero bss segment for PPC.43 18f,04apr95,caf added PPC cache support.44 18e,03mar95,yao added shsHwInit2 () for PPC403.45 18d,24feb95,caf added PPC support.46 18c,20nov94,kdl added hashLibInit() when using dosFs.47 18b,09nov94,jds additions for scsi backward compatability ; scsi[12]IfInit()48 18a,04nov94,kdl merge cleanup.49 17l,02aug94,tpr added cacheEnable (BRANCH_CACHE) for the MC68060.

D-3

50 17m,15oct94,hdn added LPT driver.51 17o,20jul94,ms changed INCLUDE_AOUT_HPPA to INCLUDE_SOM_COFF52 17n,02may94,ms added VxSim HP hack to usrClock().53 17q,15mar94,smb renamed tEvtTask parameters.54 17p,15feb94,smb defined WV_MODE, EVTBUFFER_ADDRESS for wvInstInit().55 17o,12jan94,kdl modified posix initialization; added queued signal init.56 */5758 /*59 DESCRIPTION60 This library is the WRS-supplied configuration module for VxWorks. It61 contains the root task, the primary system initialization routine, the62 network initialization routine, and the clock interrupt routine.6364 The include file config.h includes a number of system-dependent parameters used65 in this file.6667 In an effort to simplify the presentation of the configuration of vxWorks,68 this file has been split into smaller files. These additional configuration69 source files are located in ../../src/config/usr[xxx].c and are #included into70 this file below. This file contains the bulk of the code a customer is71 likely to customize.7273 The module usrDepend.c contains checks that guard against unsupported74 configurations suchas INCLUDE_NFS without INCLUDE_RPC. The module75 usrKernel.c contains the core initialization of the kernel which is rarely76 customized, but provided for information. The module usrNetwork.c now77 contains all network initialization code. Finally, the module usrExtra.c78 contains the conditional inclusion of the optional packages selected in79 configAll.h.8081 The source code necessary for the configuration selected is entirely82 included in this file during compilation as part of a standard build in83 the board support package. No other make is necessary.8485 INCLUDE FILES:86 config.h8788 SEE ALSO:89 .tG “Getting Started, Cross-Development”90 */9192 #include “vxWorks.h” /* always first */93 #include “config.h” /* board support configuration header */94 #include “usrConfig.h” /* general configuration header */95 #include “usrDepend.c” /* include dependency rules */96 #include “usrKernel.c” /* kernel configuration */97 #include “usrExtra.c” /* conditionally included packages */9899 /* global variables */100101 int consoleFd; /* fd of initial console device */

D-4

102 char consoleName[20]; /* console device name, eg. “/tyCo/0” */103 SYMTAB_IDstatSymTbl; /* system error status symbol table id*/104 SYMTAB_IDstandAloneSymTbl; /* STANDALONE version symbol table id */105 SYMTAB_IDsysSymTbl; /* system symbol table id */106 BOOT_PARAMSsysBootParams; /* parameters from boot line */107 int sysStartType; /* type of boot (WARM, COLD, etc) */108109 char * bufferAddress; /* windview: address of event buffer */110111 /

*******************************************************************************

112 *113 * usrInit - user-defined system initialization routine114 *115 * This is the first C code executed after the system boots. This routine is116 * called by the assembly language start-up routine sysInit() which is in the117 * sysALib module of the target-specific directory. It is called with118 * interrupts locked out. The kernel is not multitasking at this point.119 *120 * This routine starts by clearing BSS; thus all variables are initialized to 0,121 * as per the C specification. It then initializes the hardware by calling122 * sysHwInit(), sets up the interrupt/exception vectors, and starts kernel123 * multitasking with usrRoot() as the root task.124 *125 * RETURNS: N/A126 *127 * SEE ALSO: kernelLib128 *129 * ARGSUSED0130 */131132 void usrInit133 (134 int startType135 )136 {137 #if (CPU_FAMILY == SPARC)138 excWindowInit (); /* SPARC window management */139 #endif140141 /* configure data and instruction cache if available and leave disabled */142143 #ifdef INCLUDE_CACHE_SUPPORT144 cacheLibInit (USER_I_CACHE_MODE, USER_D_CACHE_MODE);145 #endif /* INCLUDE_CACHE_SUPPORT */146147 #if CPU_FAMILY!=SIMSPARCSUNOS && CPU_FAMILY!=SIMHPPA && CPU_FAMILY!=

SIMSPARCSOLARIS148 /* don’t assume bss variables are zero before this call */149150 bzero (edata, end - edata); /* zero out bss variables */

D-5

151 #endif /* CPU_FAMILY!=SIMSPARCSUNOS && CPU_FAMILY!=SIMHPPA && CPU_FAMILY!=SIMSPARCSOLARIS */

152153 sysStartType = startType; /* save type of system start */154155 intVecBaseSet ((FUNCPTR *) VEC_BASE_ADRS); /* set vector base table */156157 #if (CPU_FAMILY == AM29XXX)158 excSpillFillInit (); /* am29k stack cache managemt */159 #endif160161 #ifdef INCLUDE_EXC_HANDLING162 excVecInit (); /* install exception vectors */163 excShowInit (); /* install sysExcMsg handlers */164 #endif /* INCLUDE_EXC_HANDLING */165166 sysHwInit (); /* initialize system hardware */167168 usrKernelInit (); /* configure the Wind kernel */169170 #ifdef INCLUDE_CACHE_SUPPORT171 #ifdef USER_I_CACHE_ENABLE172 cacheEnable (INSTRUCTION_CACHE); /* enable instruction cache */173 #endif /* USER_I_CACHE_ENABLE */174175 #ifdefUSER_D_CACHE_ENABLE176 cacheEnable (DATA_CACHE); /* enable data cache */177 #endif /* USER_D_CACHE_ENABLE */178179 #if (CPU == MC68060)180 #ifdef USER_B_CACHE_ENABLE181 cacheEnable (BRANCH_CACHE); /* enable branch cache */182 #endif /* USER_B_CACHE_ENABLE */183 #endif /* (CPU == MC68060) */184 #endif /* INCLUDE_CACHE_SUPPORT */185186 /* start the kernel specifying usrRoot as the root task */187 kernelInit ((FUNCPTR) usrRoot, ROOT_STACK_SIZE,188 #ifdef INCLUDE_WDB189 (char *) FREE_RAM_ADRS + WDB_POOL_SIZE,190 #else191 (char *) FREE_RAM_ADRS,192 #endif193 sysMemTop (), ISR_STACK_SIZE, INT_LOCK_LEVEL);194 }195196 /

*******************************************************************************

197 *198 * usrRoot - the root task199 *

D-6

200 * This is the first task to run under the multitasking kernel. It performs201 * all final initialization and then starts other tasks.202 *203 * It initializes the I/O system, installs drivers, creates devices, and sets204 * up the network, etc., as necessary for a particular configuration. It205 * may also create and load the system symbol table, if one is to be included.206 * It may then load and spawn additional tasks as needed. In the default207 * configuration, it simply initializes the VxWorks shell.208 *209 * RETURNS: N/A210 */211212 void usrRoot213 (214 char *pMemPoolStart, /* start of system memory partition */215 unsignedmemPoolSize /* initial size of mem pool */216 )217 {218 char tyName [20];219 int ix;220221 /* Initialize the memory pool before initializing any other package.222 * The memory associated with the root task will be reclaimed at the223 * completion of its activities.224 */225226 #ifdef INCLUDE_MEM_MGR_FULL227 memInit (pMemPoolStart, memPoolSize); /* initialize memory pool */228 #else229 memPartLibInit (pMemPoolStart, memPoolSize); /* initialize memory pool */230 #endif /* INCLUDE_MEM_MGR_FULL */231232 #ifdefINCLUDE_SHOW_ROUTINES233 memShowInit (); /* initialize memShow routine */234 #endif /* INCLUDE_SHOW_ROUTINES */235236 #if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)237 usrMmuInit (); /* initialize the mmu */238 #endif /* defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL) */239240 /* set up system timer */241242 sysClkConnect ((FUNCPTR) usrClock, 0); /* connect clock ISR */243 sysClkRateSet (60); /* set system clock rate */244 sysClkEnable (); /* start it */245246 /*247 * select sould be initialized after NFS and RPC for proper delete248 * hook order but _func_selWakeupListInit should be set249 * before tyLib module (SPR #3314).250 */251

D-7

252 #ifdef INCLUDE_SELECT253 _func_selWakeupListInit = (FUNCPTR) selWakeupListInit;254 #endif /* INCLUDE_SELECT */255256 /* initialize I/O system */257258 #ifdef INCLUDE_IO_SYSTEM259 iosInit (NUM_DRIVERS, NUM_FILES, “/null”);260261 consoleFd = NONE; /* assume no console device */262263 #ifdef INCLUDE_TYCODRV_5_2264 #ifdef INCLUDE_TTY_DEV265 if (NUM_TTY > 0)266 {267 tyCoDrv (); /* install console driver */268269 for (ix = 0; ix < NUM_TTY; ix++) /* create serial devices */270 {271 sprintf (tyName, “%s%d”, “/tyCo/”, ix);272273 (void) tyCoDevCreate (tyName, ix, 512, 512);274275 if (ix == CONSOLE_TTY)276 strcpy (consoleName, tyName); /* store console name */277 }278279 consoleFd = open (consoleName, O_RDWR, 0);280281 /* set baud rate */282283 (void) ioctl (consoleFd, FIOBAUDRATE, CONSOLE_BAUD_RATE);284 (void) ioctl (consoleFd, FIOSETOPTIONS, OPT_TERMINAL);285 }286 #endif /* INCLUDE_TTY_DEV */287288 #else /* !INCLUDE_TYCODRV_5_2 */289 #ifdef INCLUDE_TTY_DEV290 if (NUM_TTY > 0)291 {292 ttyDrv(); /* install console driver */293294 for (ix = 0; ix < NUM_TTY; ix++) /* create serial devices */295 {296 #if (defined(INCLUDE_WDB) && (WDB_COMM_TYPE == WDB_COMM_SERIAL))297 if (ix == WDB_TTY_CHANNEL) /* don’t use WDBs channel */298 continue;299 #endif300 sprintf (tyName, “%s%d”, “/tyCo/”, ix);301 (void) ttyDevCreate (tyName, sysSerialChanGet(ix), 512, 512);302303 if (ix == CONSOLE_TTY) /* init the tty console */

D-8

304 {305 strcpy (consoleName, tyName);306 consoleFd = open (consoleName, O_RDWR, 0);307 (void) ioctl (consoleFd, FIOBAUDRATE, CONSOLE_BAUD_RATE);308 (void) ioctl (consoleFd, FIOSETOPTIONS, OPT_TERMINAL);309 }310 }311 }312 #endif /* INCLUDE_TTY_DEV */313314 #ifdef INCLUDE_PC_CONSOLE315 pcConDrv ();316 for (ix = 0; ix < N_VIRTUAL_CONSOLES; ix++)317 {318 sprintf (tyName, “%s%d”, “/pcConsole/”, ix);319 (void) pcConDevCreate (tyName,ix, 512, 512);320 if (ix == PC_CONSOLE)/* init the console device */321 {322 strcpy (consoleName, tyName);323 consoleFd = open (consoleName, O_RDWR, 0);324 (void) ioctl (consoleFd, FIOBAUDRATE, CONSOLE_BAUD_RATE);325 (void) ioctl (consoleFd, FIOSETOPTIONS, OPT_TERMINAL);326 }327 }328 #endif /* INCLUDE_PC_CONSOLE */329330 #endif /* !INCLUDE_TYCODRV_5_2 */331332 ioGlobalStdSet (STD_IN, consoleFd);333 ioGlobalStdSet (STD_OUT, consoleFd);334 ioGlobalStdSet (STD_ERR, consoleFd);335 #endif /* INCLUDE_IO_SYSTEM */336337 /* initialize symbol table facilities */338339 #ifdefINCLUDE_SYM_TBL340 hashLibInit (); /* initialize hash table package */341 symLibInit (); /* initialize symbol table package */342 #ifdef INCLUDE_SHOW_ROUTINES343 symShowInit (); /* initialize symbol table show */344 #endif /* INCLUDE_SHOW_ROUTINES */345 #endif /* INCLUDE_SYM_TBL */346347348 /* initialize exception handling */349350 #if defined(INCLUDE_EXC_HANDLING) && defined(INCLUDE_EXC_TASK)351 excInit (); /* initialize exception handling */352 #endif /* defined(INCLUDE_EXC_HANDLING) && defined(INCLUDE_EXC_TASK) */353354 #ifdefINCLUDE_LOGGING355 logInit (consoleFd, MAX_LOG_MSGS); /* initialize logging */

D-9

356 #endif /* INCLUDE_LOGGING */357358 #ifdefINCLUDE_SIGNALS359 sigInit (); /* initialize signals */360 #endif /* INCLUDE_SIGNALS */361362 /* initialize debugging */363364 #ifdefINCLUDE_DEBUG365 dbgInit (); /* initialize debugging */366 #endif /* INCLUDE_DEBUG */367368369 /* initialize pipe driver */370371 #ifdefINCLUDE_PIPES372 pipeDrv (); /* install pipe driver */373 #endif /* INCLUDE_PIPES */374375376 /* initialize standard I/O package */377378 #ifdefINCLUDE_STDIO379 stdioInit (); /* initialize standard I/O library */380 #ifdef INCLUDE_SHOW_ROUTINES381 stdioShowInit ();382 #endif /* INCLUDE_SHOW_ROUTINES */383 #endif /* INCLUDE_STDIO */384385 /* initialize POSIX queued signals */386387 #if defined(INCLUDE_POSIX_SIGNALS) && defined(INCLUDE_SIGNALS)388 sigqueueInit (NUM_SIGNAL_QUEUES); /* initialize queued signals */389 #endif390391 /* initialize POSIX semaphores */392393 #ifdef INCLUDE_POSIX_SEM394 semPxLibInit ();395 #ifdef INCLUDE_SHOW_ROUTINES396 semPxShowInit ();397 #endif /* INCLUDE_SHOW_POUTINES */398 #endif /* INCLUDE_POSIX_SEM */399400 /* initialize POSIX message queues */401402 #ifdef INCLUDE_POSIX_MQ403 mqPxLibInit (MQ_HASH_SIZE);404 #ifdef INCLUDE_SHOW_ROUTINES405 mqPxShowInit ();406 #endif /* INCLUDE_SHOW_ROUTINES */407 #endif /* INCLUDE_POSIX_MQ */

D-10

408409 /* initialize POSIX async I/O support */410411 #ifdef INCLUDE_POSIX_AIO412 aioPxLibInit (MAX_LIO_CALLS);413 #ifdef INCLUDE_POSIX_AIO_SYSDRV414 aioSysInit (MAX_AIO_SYS_TASKS, AIO_TASK_PRIORITY, AIO_TASK_STACK_SIZE);415 #endif /* INCLUDE_POSIX_AIO_SYSDRV */416 #endif /* INCLUDE_POSIX_AIO */417418 /* initialize filesystems and disk drivers */419420 #ifdefINCLUDE_DOSFS421 hashLibInit (); /* initialize hash table package */422 dosFsInit (NUM_DOSFS_FILES); /* init dosFs filesystem */423 #endif /* INCLUDE_DOSFS */424425 #ifdefINCLUDE_RAWFS426 rawFsInit (NUM_RAWFS_FILES); /* init rawFs filesystem */427 #endif /* INCLUDE_RAWFS */428429 #ifdefINCLUDE_RT11FS430 rt11FsInit (NUM_RT11FS_FILES); /* init rt11Fs filesystem */431 #endif /* INCLUDE_RT11FS */432433 #ifdefINCLUDE_RAMDRV434 ramDrv (); /* initialize ram disk driver */435 #endif /* INCLUDE_RAMDRV */436437 #ifdefINCLUDE_SCSI438439 /*440 * initialize either the SCSI1 or SCSI2 interface; initialize SCSI2 when441 * the SCSI2 interface is available.442 */443444 #ifndef INCLUDE_SCSI2445 scsi1IfInit ();446 #else447 scsi2IfInit ();448 #endif449450 /* initialize SCSI controller */451 if (sysScsiInit () == OK)452 {453 usrScsiConfig (); /* configure SCSI peripherals */454 }455 else456 {457 printf (“sysScsiInit() Failed, SCSI system not initialized\n”);458 }459

D-11

460 #endif /* INCLUDE_SCSI */461462 #ifdef INCLUDE_FD463 fdDrv (FD_INT_VEC, FD_INT_LVL); /* initialize floppy disk driver */464 #endif /* INCLUDE_FD */465466 #ifdef INCLUDE_IDE467 ideDrv (IDE_INT_VEC, IDE_INT_LVL, IDE_CONFIG); /* init IDE disk driver */468 #endif /* INCLUDE_IDE */469470 #ifdef INCLUDE_ATA471 { /* initialize hard disk driver */472 IMPORT ATA_RESOURCE ataResources[];473 ATA_RESOURCE *pAtaResource;474475 for (ix = 0; ix < ATA_MAX_CTRLS; ix++)476 {477 pAtaResource = &ataResources[ix];478 if (pAtaResource->ctrlType == IDE_LOCAL)479 ataDrv (ix, pAtaResource->drives, pAtaResource->intVector,480 pAtaResource->intLevel, pAtaResource->configType,481 pAtaResource->semTimeout, pAtaResource->wdgTimeout);482 }483 }484 #ifdef INCLUDE_SHOW_ROUTINES485 ataShowInit (); /* install ATA/IDE show routine */486 #endif /* INCLUDE_SHOW_ROUTINES */487 #endif /* INCLUDE_ATA */488489 #ifdef INCLUDE_LPT490 {491 IMPORT LPT_RESOURCE lptResources[];492 lptDrv (LPT_CHANNELS, &lptResources[0]); /* init LPT parallel driver */493 }494 #endif /* INCLUDE_LPT */495496 #ifdef INCLUDE_PCMCIA497 #ifdef INCLUDE_SHOW_ROUTINES498 pcmciaShowInit (); /* install PCMCIA show routines */499 #endif /* INCLUDE_SHOW_ROUTINES */500 pcmciaInit (); /* init PCMCIA Lib */501 #endif /* INCLUDE_PCMCIA */502503 #ifdef INCLUDE_FORMATTED_IO504 fioLibInit (); /* initialize formatted I/O */505 #endif /* INCLUDE_FORMATTED_IO */506507 /* initialize floating point facilities */508509 #ifdefINCLUDE_FLOATING_POINT510 floatInit (); /* initialize floating point I/O */511 #endif /* INCLUDE_FLOATING_POINT */

D-12

512513 /* install software floating point emulation (if applicable) */514515 #ifdefINCLUDE_SW_FP516 mathSoftInit (); /* use software emulation for fp math */517 #endif /* INCLUDE_SW_FP */518519 /* install hardware floating point support (if applicable) */520521 #ifdefINCLUDE_HW_FP522 mathHardInit (); /* do fppInit() & install hw fp math */523524 #ifdefINCLUDE_SHOW_ROUTINES525 fppShowInit (); /* install hardware fp show routine */526 #endif /* INCLUDE_SHOW_ROUTINES */527 #endif /* INCLUDE_HW_FP */528529 /* initialize performance monitoring tools */530531 #ifdefINCLUDE_SPY532 spyLibInit (); /* install task cpu utilization tool */533 #endif /* INCLUDE_SPY */534535 #ifdefINCLUDE_TIMEX536 timexInit (); /* install function timing tool */537 #endif /* INCLUDE_TIMEX */538539 #ifdef INCLUDE_ENV_VARS540 envLibInit (ENV_VAR_USE_HOOKS); /* initialize environment variable */541 #endif /* INCLUDE_ENV_VARS */542543544 /* initialize object module loader */545546 #ifdefINCLUDE_LOADER547 moduleLibInit (); /* initialize module manager */548549 #if defined(INCLUDE_AOUT)550 loadAoutInit (); /* use a.out format */551 #else /* coff or ecoff */552 #if defined(INCLUDE_ECOFF)553 loadEcoffInit (); /* use ecoff format */554 #else /* ecoff */555 #if defined(INCLUDE_COFF)556 loadCoffInit (); /* use coff format */557 #else /* coff */558 #if defined(INCLUDE_ELF)559 loadElfInit (); /* use elf format */560 #else561 #if defined(INCLUDE_SOM_COFF)562 loadSomCoffInit ();563 #endif

D-13

564 #endif565 #endif566 #endif567 #endif568569 #endif /* INCLUDE_LOADER */570571 /* initialize wtx client to synchronize host and target symbol tables */572 #ifdefINCLUDE_SYM_TBL_SYNC573 symSyncLibInit ();574 #endif /* INCLUDE_SYM_TBL_SYNC */575576 /* initialize network */577578 #ifdef INCLUDE_NET_INIT579 usrBootLineInit (sysStartType); /* crack the bootline */580 usrNetInit (BOOT_LINE_ADRS); /* initialize network support */581 #endif /* INCLUDE_NET_INIT */582583 #ifdefINCLUDE_PASSFS584 {585 extern STATUS passFsInit ();586 extern void *passFsDevInit ();587 char passName [256];588589 if (passFsInit (1) == OK)590 {591 extern char vxsim_hostname[];592 extern char vxsim_cwd[];593594 sprintf (passName, “%s:”, vxsim_hostname);595 if (passFsDevInit (passName) == NULL)596 {597 printf (“passFsDevInit failed for <%s>\n”, passName);598 }599 else600 {601 sprintf (passName, “%s:%s”, vxsim_hostname, vxsim_cwd);602 ioDefPathSet (passName);603 }604 }605 else606 printf (“passFsInit failed\n”);607 }608 #endif /* INCLUDE_PASSFS */609610 #ifdefINCLUDE_DOS_DISK611 {612 char unixName [80];613 extern void unixDrv ();614 extern void unixDiskInit ();615 extern char *u_progname; /* home of executable */

D-14

616 char *pLastSlash;617618 unixDrv ();619620 pLastSlash = strrchr (u_progname, ‘/’);621 pLastSlash = (pLastSlash == NULL) ? u_progname : (pLastSlash + 1);622 sprintf (unixName, “/tmp/%s%d.dos”, pLastSlash, sysProcNumGet());623 unixDiskInit (unixName, “A:”, 0);624 }625 #endif/* INCLUDE_DOS_DISK */626627 /* initialize shared memory objects */628629 #ifdef INCLUDE_SM_OBJ /* unbundled shared memory objects */630 usrSmObjInit (BOOT_LINE_ADRS);631 #endif /* INCLUDE_SM_OBJ */632633 /* write protect text segment & vector table only after bpattach () */634635 #ifdefINCLUDE_MMU_FULL /* unbundled mmu product */636 #ifdefINCLUDE_PROTECT_TEXT637 if (vmTextProtect () != OK)638 printf (“\nError protecting text segment. errno = %x\n”, errno);639 #endif /* INCLUDE_PROTECT_TEXT */640641 #ifdefINCLUDE_PROTECT_VEC_TABLE642 if (intVecTableWriteProtect () != OK)643 printf (“\nError protecting vector table. errno = %x\n”, errno);644 #endif /* INCLUDE_PROTECT_VEC_TABLE */645 #endif /* INCLUDE_MMU_FULL */646647 /* initialize select only after NFS and RPC for proper delete hook order */648649 #ifdefINCLUDE_SELECT650 selectInit ();651 #endif /* INCLUDE_SELECT */652653 /* create system and status symbol tables */654655 #ifdef INCLUDE_STANDALONE_SYM_TBL656 sysSymTbl = symTblCreate (SYM_TBL_HASH_SIZE_LOG2, TRUE, memSysPartId);657658 printf (“\nAdding %ld symbols for standalone.\n”, standTblSize);659660 for (ix = 0; ix < standTblSize; ix++) /* fill in from built in table*/661 symTblAdd (sysSymTbl, &(standTbl[ix]));662 #endif /* INCLUDE_STANDALONE_SYM_TBL */663664 #ifdef INCLUDE_NET_SYM_TBL665 sysSymTbl = symTblCreate (SYM_TBL_HASH_SIZE_LOG2, TRUE, memSysPartId);666667 netLoadSymTbl (); /* fill in table from host */

D-15

668 #endif /* INCLUDE_NET_SYM_TBL */669670 #ifdef INCLUDE_STAT_SYM_TBL671 statSymTbl = symTblCreate (STAT_TBL_HASH_SIZE_LOG2, FALSE, memSysPartId);672673 for (ix = 0; ix < statTblSize; ix ++) /* fill in from built in table*/674 symTblAdd (statSymTbl, &(statTbl [ix]));675 #endif /* INCLUDE_STAT_SYM_TBL */676677678 /* initialize C++ support library */679680 #if defined (INCLUDE_CPLUS) && defined (INCLUDE_CPLUS_MIN)681 #errorDefine only one of INCLUDE_CPLUS or INCLUDE_CPLUS_MIN, not both682 #endif683684 #ifdefINCLUDE_CPLUS /* all standard C++ runtime support */685 cplusLibInit ();686 #endif687688 #ifdefINCLUDE_CPLUS_MIN /* minimal C++ runtime support */689 cplusLibMinInit ();690 #endif691692 /* initialize windview support */693694 #ifdef INCLUDE_INSTRUMENTATION695696 /* initialize timer support for windview */697698 #ifdef INCLUDE_TIMESTAMP699 #ifdef INCLUDE_USER_TIMESTAMP700 wvTmrRegister ((UINTFUNCPTR) USER_TIMESTAMP,701 (UINTFUNCPTR) USER_TIMESTAMPLOCK,702 (FUNCPTR) USER_TIMEENABLE,703 (FUNCPTR) USER_TIMEDISABLE,704 (FUNCPTR) USER_TIMECONNECT,705 (UINTFUNCPTR) USER_TIMEPERIOD,706 (UINTFUNCPTR) USER_TIMEFREQ);707 #else /* INCLUDE_USER_TIMESTAMP */708 wvTmrRegister (sysTimestamp,709 sysTimestampLock,710 sysTimestampEnable ,711 sysTimestampDisable ,712 sysTimestampConnect,713 sysTimestampPeriod,714 sysTimestampFreq);715 #endif /* INCLUDE_USER_TIMESTAMP */716 #else /* INCLUDE_TIMESTAMP */717 wvTmrRegister (seqStamp,718 seqStampLock,719 seqEnable,

D-16

720 seqDisable ,721 seqConnect,722 seqPeriod,723 seqFreq);724 #endif /* INCLUDE_TIMESTAMP */725726727 /* initialize WindView host target connection */728729 connRtnSet (evtSockInit, evtSockClose, evtSockError , evtSockDataTransfer);730731 /* set the characteristics of the event task - tEvtTask */732733 wvEvtTaskInit (WV_EVT_STACK, WV_EVT_PRIORITY);734735 /* initialize windview instrumentation buffers and tasks */736737 bufferAddress = wvInstInit (EVTBUFFER_ADDRESS, EVTBUFFER_SIZE, WV_MODE);738739 /* initialize WindView command server */740741 #ifdef INCLUDE_WINDVIEW742 wvServerInit (WV_SERVER_STACK, WV_SERVER_PRIORITY);743 #endif /* INCLUDE_WINDVIEW */744745 #endif /* INCLUDE_INSTRUMENTATION */746747 /* initialize the WDB debug agent */748749 #ifdef INCLUDE_WDB750 wdbConfig();751752 #ifdefINCLUDE_WDB_BANNER753 #ifndef INCLUDE_SHELL754 /* short banner, like the bootPrintLogo banner */755 printf (“\n\n”);756 printf (“%17s%s”, ““,”VxWorks\n\n”);757 printf (“Copyright 1984-1996 Wind River Systems, Inc.\n\n”);758 printf (“ CPU: %s\n”, sysModel ());759 printf (“ VxWorks: “ VXWORKS_VERSION “\n”);760 printf (“ BSP version: “ BSP_VERSION BSP_REV “\n”);761 printf (“ Creation date: %s\n”, __DATE__);762 printf (“ WDB: %s.\n\n”,763 ((wdbRunsExternal () || wdbRunsTasking ()) ?764 “Ready” : “Agent configuration failed”) );765 #endif /*INCLUDE_SHELL*/766767 #endif /*INCLUDE_WDB_BANNER*/768769 #endif /* INCLUDE_WDB */770771 /* initialize interactive shell */

D-17

772773 #ifdef INCLUDE_SHELL774 #ifdefINCLUDE_SECURITY /* include shell security */775 if ((sysFlags & SYSFLG_NO_SECURITY) == 0)776 {777 loginInit (); /* initialize login table */778 shellLoginInstall (loginPrompt, NULL); /* install security program */779780 /* add additional users here as required */781782 loginUserAdd (LOGIN_USER_NAME, LOGIN_PASSWORD);783 }784 #endif /* INCLUDE_SECURITY */785786 printLogo (); /* print out the banner page */787788 printf (“ “);789 printf (“CPU: %s. Processor #%d.\n”, sysModel (), sysProcNumGet ());790 printf (“ “);791 printf (“Memory Size: 0x%x.”, (UINT)(sysMemTop () - (char

*)LOCAL_MEM_LOCAL_ADRS));792 printf (“ BSP version “ BSP_VERSION BSP_REV “.”);793 #if defined(INCLUDE_WDB) && defined(INCLUDE_WDB_BANNER)794 printf (“\n “);795 printf (“WDB: %s.”,796 ((wdbRunsExternal () || wdbRunsTasking ()) ?797 “Ready” : “Agent configuration failed”) );798 #endif /*INCLUDE_WDB && INCLUDE_WDB_BANNER*/799 printf (“\n\n”);800801 #ifdefINCLUDE_STARTUP_SCRIPT /* run a startup script */802 if (sysBootParams.startupScript [0] != EOS)803 usrStartupScript (sysBootParams.startupScript);804 #endif /* INCLUDE_STARTUP_SCRIPT */805806 shellInit (SHELL_STACK_SIZE, TRUE); /* create the shell */807808809 /* only include the simple demo if the shell is NOT included */810811 #else812 #if defined(INCLUDE_DEMO) /* create demo w/o shell */813 taskSpawn (“demo”, 20, 0, 2000, (FUNCPTR)usrDemo, 0,0,0,0,0,0,0,0,0,0);814 #endif /* mips cpp no elif */815816 #endif /* INCLUDE_SHELL */817818 #ifdef INCLUDE_USER_APPL819 /* Startup the user’s application */820821 USER_APPL_INIT; /* must be a valid C statement or block */822 #endif

D-18

823 }824825 /

*******************************************************************************

826 *827 * usrClock - user-defined system clock interrupt routine828 *829 * This routine is called at interrupt level on each clock interrupt.830 * It is installed by usrRoot() with a sysClkConnect() call.831 * It calls all the other packages that need to know about clock ticks,832 * including the kernel itself.833 *834 * If the application needs anything to happen at the system clock interrupt835 * level, it can be added to this routine.836 *837 * RETURNS: N/A838 */839840 void usrClock ()841842 {843 tickAnnounce (); /* announce system tick to kernel */844 }845846 #ifdefINCLUDE_DEMO847848 /

********************************************************************************

849 * usrDemo - example application without shell850 *851 * This routine is spawned as a task at the end of usrRoot(), if INCLUDE_DEMO852 * is defined, and INCLUDE_SHELL is NOT defined in configAll.h or config.h.853 * It is intended to indicate how a shell-less application can be linked,854 * loaded, and ROMed.855 *856 * NOMANUAL857 */858859 void usrDemo (void)860861 {862 char string [40];863864 printf (“VxWorks (for %s) version %s.\n”, sysModel (), vxWorksVersion);865 printf (“Kernel: %s.\n”, kernelVersion ());866 printf (“Made on %s.\n”, creationDate);867868 FOREVER869 {870 printf (“\nThis is a test. Type something: “);

D-19

871 fioRdString (STD_IN, string, sizeof (string));872 printf (“\nYou typed \”%s\”.\n”, string);873874 if (strcmp (string, “0”) == 0)875 memShow (0);876877 if (strcmp (string, “1”) == 0)878 memShow (1);879 }880 }881882 #endif /* INCLUDE_DEMO */


Appendix - E

mv2600.h

E-2

mv2600.h

1 /* mv2600.h - Motorola PowerPlus board header */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 /* Copyright 1996 Motorola, Inc. */56 /*7 modification history8 --------------------9 02a,07nov97,mas/ corrected VME range comments on A32 slave window; changed VME10 tb A24 base address to 0xff000000; enabled 64-bit PCI xfers for11 VME A32 slave window (SPR 9726).12 01z,05nov97,mas made all VME master windows D64 with write posting (SPR 9717).13 01y,31oct97,mas fixed P2P_NPMEM_SPACE_LIMIT_ADRS definition (SPR 9654).14 01x,10sep97,mas added PMC_INT_LVL1 - 4 for non-MPIC configurations.15 01w,02sep97,mas removed un-needed check of VME_A32_MSTR_BUS, VME_A24_MSTR_BUS.16 01v,14aug97,mas Extended VME addressing is now default; no slave VME A24 space17 (for cumulative patch release 9/97).18 01u,01aug97,mas added primary PCI bus interrupt vector numbers

PCI_PRI_INTA_VEC19 PCI_PRI_INTB_VEC, PCI_PRI_INTC_VEC, PCI_PRI_INTD_VEC (SPR 9063)20 01t,25jul97,srr/ added 604r (Mach 5) type define CPU_TYPE_604R (SPR 8911).21 mas22 01s,17jul97,mas added FALCON_DRAM_ATTR and DRAM_SIZE (SPR 8824).23 01r,14jul97,mas added IS_VME_ADDRESS and IS_PCI_ADDRESS defs (SPR 8022).24 Added reg bit masks for MPC Error Enable/Status and PCI Status.25 01q,09jul97,mas added UNIV_VOWN_INT_VEC definition (SPR 8896); added

‘volatile’26 to in-line assembler macros; disabled write posting in Universe27 VME slave setup (SPR 8897); NCR810_DELAY_MULT is now defined as28 actual loop count (SPR 8842).29 01p,05jun97,mas added support for serial ports 3 & 4 (Z85230 ESCC). (SPR 8566)30 01o,29may97,srr Add RAVEN macros for vxMemProbe, chg’d mislabelled macros31 (MCG MR #67, 69)32 01n,12may97,dat moving things between config.h and mv2600.h33 01m,09may97,mas added extended VME addressing (SPR 8410).34 added z8536 I/O port bit mappings (SPR 8432).35 01l,29apr97,dat added PCI_CLINE_SZ and PCI_LAT_TIMER, from old pci.h36 01k,24apr97,mas added Motorola support for MPIC (SPR 8170).37 01j,11apr97,dat moved macros between here and config.h. User configurable38 macros are in config.h, fixed ones are here in mv2600.h39 01i,10apr97,mas added defs for EIEIO_SYNC, EIEIO, PCI_PRIMARY_CAR,40 PCI_PRIMARY_CDR, CNFG_PMCSPAN_ADRS, PCI_PRIMARY_BUS,41 PCI_SECONDARY_BUS, PCI_SUBORD_BUS, MV2600_BMFR_BRGP,42 PCI_ID_BR_DEC21150, PCI_MAX_BUS and PMC_SPAN; updated43 PCI_ID_IBC (SPR 8226).44 01h,01apr97,dat new VME configuration macros, SPR 827145 01g,18feb97,mas added DEC_CLOCK_FREQ definition; changed UNIV_SW_IACK_INT_VEC46 to UNIV_PCI_SW_INT_VEC; added UNIV_VME_SW_IACK_INT_VEC47 (SPR 7772, 7811).

E-3

48 01f,10jan97,dat chg’d BBRAM_SIZE, to exclude RTC chip49 01e,02jan97,dat mod history fix, chg’d MV1600_SIOP* to MV2600_SIOP*50 01d,18dec96,tb [Motorola] added MV2600_MCR_ (SPR 7525).51 01c,17dec96,mas moved raven.h contents to this file (SPR 7525).52 01b,14jul96,rcp modified the reference to the PCI configuration regs.53 01a,14jul96,mot written. (from ver 01f, mv1600.h)54 */5556 /*57 This file contains I/O addresses and related constants for the58 Motorola PowerPlus VME board.59 */6061 #ifndefINCmv260xh62 #defineINCmv260xh6364 #ifdef __cplusplus65 extern “C” {66 #endif6768 /* Boot Line parameters are stored in the 2nd 256 byte block */6970 #undefNV_BOOT_OFFSET71 #define NV_BOOT_OFFSET256 /* skip 1st 256 bytes */72 #define NV_RAM_SIZE BBRAM_SIZE73 #define NV_RAM_ADRS ((char *) BBRAM_ADRS)74 #define NV_RAM_INTRVL 17576 /* Dec 21140 (unit 0) vector and level */7778 #defineINT_VEC_DCLN_INT_VEC /* interrupt vector */79 #defineINT_LVL_DCLN_INT_LVL /* interrupt level */80 #define DC_DATA_WIDTH NONE /* all data widths */81 #define IO_ADRS_DC LAN_BASE_ADRS /* Base adrs */82 #define DC_RAM_PCI_ADRS PCI2DRAM_BASE_ADRS /* RAM seen from PCI */8384 /* Dec 21040 (unit 1) vector and level */8586 #define INT_VEC_DC1 LN2_INT_VEC /* interrupt vector */87 #define INT_LVL_DC1 PMC_INT_LVL2 /* interrupt level */88 #define DC1_DATA_WIDTH NONE /* all data widths */89 #define IO_ADRS_DC1 LAN2_BASE_ADRS /* Base adrs */90 #define DC1_RAM_PCI_ADRS PCI2DRAM_BASE_ADRS /* RAM seen from PCI */9192 /* PMC-Span setup values */9394 #define P2P_IO_SPACE_BASE_ADRS ((P2P_IO_BASE & 0x0000F000) >> 8)95 #define P2P_IO_SPACE_LIMIT_ADRS ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0x0000F000)96 #defineP2P_IO_HI16_BASE_ADRS ((P2P_IO_BASE & 0xFFFF0000) >> 16)97 #defineP2P_IO_HI16_LIMIT_ADRS ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0xFFFF0000)98 #define P2P_NPMEM_SPACE_BASE_ADRS ((P2P_NONPREF_MEM_BASE & 0xFFFF0000) >> 16)99 #define P2P_NPMEM_SPACE_LIMIT_ADRS ((P2P_NONPREF_MEM_BASE + }

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100 P2P_NONPREF_MEM_SIZE - 1) & 0xFFFF0000)101 #define P2P_PREF_MEM_BASE_ADRS ((P2P_PREF_MEM_BASE & 0xFFFF0000) >> 16)102 #define P2P_PREF_MEM_LIMIT_ADRS ((P2P_PREF_MEM_BASE + P2P_PREF_MEM_SIZE - 1) &

\103 0xFFFF0000)104105 /* PCI I/O function defines */106107 #define INT_NUM_IRQ0 INT_VEC_IRQ0108109 #ifndef _ASMLANGUAGE110111 #ifndef PCI_IN_BYTE112 #define PCI_IN_BYTE(x) sysPciInByte (x)113 IMPORT UINT8 sysPciInByte (UINT32 address);114 #endif115 #ifndef PCI_IN_WORD116 #define PCI_IN_WORD(x) sysPciInWord (x)117 IMPORT UINT16 sysPciInWord (UINT32 address);118 #endif119 #ifndef PCI_IN_LONG120 #define PCI_IN_LONG(x) sysPciInLong (x)121 IMPORT UINT32 sysPciInLong (UINT32 address);122 #endif123 #ifndef PCI_OUT_BYTE124 #define PCI_OUT_BYTE(x,y) sysPciOutByte (x,y)125 IMPORT void sysPciOutByte (UINT32 address, UINT8 data);126 #endif127 #ifndef PCI_OUT_WORD128 #define PCI_OUT_WORD(x,y) sysPciOutWord (x,y)129 IMPORT void sysPciOutWord (UINT32 address, UINT16 data);130 #endif131 #ifndef PCI_OUT_LONG132 #define PCI_OUT_LONG(x,y) sysPciOutLong (x,y)133 IMPORT void sysPciOutLong (UINT32 address, UINT32 data);134 #endif135136 #endif /* _ASMLANGUAGE */137138 /* Cache Line Size - 32 32-bit value = 128 bytes */139140 #define PCI_CLINE_SZ0x20141142 /* Latency Timer value - 255 PCI clocks */143144 #define PCI_LAT_TIMER0xff145146 /* clock rates */147148 /* Calculate Memory Bus Rate in Hertz */149150 #define MEMORY_BUS_SPEED ( sysGetBusSpd() * 1000000)

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151152 /* System clock (decrementer counter) frequency determination */153154 #define DEC_CLOCK_FREQ ((sysGetBusSpd()==67)?66666666:33333333)155156 /* CIO clocks and stuff */157158 #defineCIO_RESET_DELAY5000159 #defineZCIO_HZ 2500000 /* 2.5 MHz clock */160 #defineCIO_INT_VEC9161 #defineZ8536_TCZCIO_HZ162163 /*164 * The PowerPC Decrementer is used as the system clock.165 * It is always included in this BSP. The following defines166 * are used by the system clock library.167 */168169 #define SYS_CLK_RATE_MIN 10 /* minimum system clock rate */170 #define SYS_CLK_RATE_MAX 5000 /* maximum system clock rate */171172 /*173 * Auxiliary Clock support is an optional feature that is not supported174 * by all BSPs. The following defines are used by the aux clock library.175 */176177 #define AUX_CLK_RATE_MIN 40 /* min auxiliary clock */178 #define AUX_CLK_RATE_MAX5000 /* max auxiliary clock rate */179180 /*181 * Shared Memory Interrupt Type.182 * Interrupt this target with a 1-byte write mailbox.183 * VME_A32 space, address based on procNum, value is SIG1_INTR_SET.184 */185186 #define SM_INT_ARG1 VME_AM_EXT_SUP_DATA187 #define SM_INT_ARG2 (VME_A32_REG_BASE +(sysProcNumGet() * VME_A32_REG_SIZE))188 #define SM_INT_ARG3SIG1_INTR_SET189190 /*191 * Semaphore Test-and-Set Register as seen from a slave192 * Only used with a special version of sysBusTas().193 */194195 #define OFFBRD_VME_SEM_REG1(CPU_VME_WINDOW_REG_BASE + \196 (CPU_VME_SEM_REG1 - CPU_VME_HW_REGS_BASE))197198 /* Common I/O synchronizing instructions */199200 #ifndef EIEIO_SYNC201 # define EIEIO_SYNC __asm__ volatile (“eieio;sync”)202 #endif /* EIEIO_SYNC */

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203 #ifndef EIEIO204 # define EIEIO __asm__ volatile (“eieio”)205 #endif /* EIEIO */206207 #ifndef EXTENDED_VME208209 /* Psuedo PREP memory map as seen from CPU */210211 #define CPU_PCI_ISA_IO_ADRS 0x80000000 /* base of ISA I/O space */212 #define CPU_PCI_ISA_MEM_ADRS 0xc0000000 /* base of ISA mem space */213 #define CPU_PCI_IO_ADRS 0x81000000 /* base of PCI I/O space */214 #define CPU_PCI_MEM_ADRS 0xc1000000 /* base of PCI mem space */215216 #else217218 /* Extended VME memory map as seen from the CPU */219220 #define CPU_PCI_ISA_IO_ADRS 0xfe000000 /* base of ISA I/O space */221 #define CPU_PCI_ISA_MEM_ADRS 0xfd000000 /* base of ISA mem space */222 #define CPU_PCI_IO_ADRS CPU_PCI_ISA_IO_ADRS /* base of PCI I/O space */223 #define CPU_PCI_MEM_ADRS CPU_PCI_ISA_MEM_ADRS /* base of PCI mem space */224 #endif225226 #define CPU_PCI_ISA_IO_SIZE 0x00010000 /* 64 kbytes */227 #define CPU_PCI_IO_SIZE 0x00800000 /* 8 meg */228 #define CPU_PCI_IO_UPPER_ADRS (CPU_PCI_ISA_IO_ADRS>>16)229 #define CPUCRA_HI (CPU_PCI_ISA_IO_ADRS>>16)230 #define CPUCRA_LO 0x0800231232 #define CPU_PCI_ISA_MEM_SIZE 0x00010000 /* 64 kbytes */233 #define CPU_PCI_MEM_SIZE 0x01000000 /* 16 meg */234 #define CPU_PCI_MEM_UPPER_ADRS (CPU_PCI_ISA_MEM_ADRS>>16)235236 /*237 * PCI MASTER MEMORY WINDOW LIMITS238 *239 * These values are strictly defined by the base memory addresses and window240 * sizes of the spaces defined above. These values must be correct for the241 * sysBusProbe() memory range checks for the PCI bus to work properly.242 */243244 #ifndef EXTENDED_VME245 # define PCI_MSTR_LO_ADRS (CPU_PCI_ISA_IO_ADRS)246 # define PCI_MSTR_HI_ADRS (CPU_PCI_MEM_ADRS + CPU_PCI_MEM_SIZE)247 #else248 # define PCI_MSTR_LO_ADRS (CPU_PCI_MEM_ADRS)249 # define PCI_MSTR_HI_ADRS (CPU_PCI_IO_ADRS + CPU_PCI_IO_SIZE)250 #endif /* EXTENDED_VME */251252 #ifndef INCLUDE_MPIC253254 /*

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255 * All starting addresses are correct except for CPU_PCI_IACK_ADRS.256 * This address was selected to allow a minimum 8k memory range257 * for the MMU table entry.258 */259260 #define CPU_PCI_IACK_ADRS0xbfffe000 /* covers PCI IACK space */261 /* base = 0xbffffff0; */262 #define CPU_PCI_IACK_SIZE0x00002000/* 8 kbytes */263264 #define MPIC_ADDR(reg)(MPIC_BASE_ADRS + reg)265 #define MPIC_GLOBAL_CONFIG_REG0x01020266 #define RESET_CNTRLR0x80000000267268 #endif /* INCLUDE_MPIC */269270 /* Base address of HW devices as seen from CPU */271272 #define FALCON_BASE_ADRS0xfef80000273 #defineFALCON_REG_SIZE0x00010000274 #define FALCON_BASE_UPPER_ADRS(FALCON_BASE_ADRS>>16)275 #define FALCON_DRAM_ATTR0xfef80010276 #define RAVEN_BASE_ADRS0xfeff0000277 #defineRAVEN_REG_SIZE0x00010000278 #defineFLASH_BASE_ADRS0xFF000000279 #defineFLASH_MEM_SIZE0x01000000280281 /* MPIC configuration defines */282283 #define MPIC_BASE_ADRS0xfc000000284 #define MPIC_REG_SIZE0x00040000285 #ifndef EXTENDED_VME286 # define MPIC_PCI_BASE_ADRS( MPIC_BASE_ADRS - CPU_PCI_ISA_MEM_ADRS )287 #else288 # define MPIC_PCI_BASE_ADRSMPIC_BASE_ADRS289 #endif /* Extended VME config */290291 /* memory map as seen on the PCI bus */292293 #define PCI_CNFG_ADRS0x00800000 /* base of PCI config space */294 #ifndef EXTENDED_VME295 # define PCI_IO_ADRS0x01000000 /* base of PCI I/O address */296 # define PCI_MEM_ADRS0x01000000 /* base of PCI MEM address */297 # define PCI2DRAM_BASE_ADRS0x80000000 /* memory seen from PCI bus */298 #else299 # define PCI_IO_ADRS0x00000000 /* base of PCI I/O address */300 # define PCI_MEM_ADRSCPU_PCI_MEM_ADRS /* base of PCI MEM address */301 # define PCI2DRAM_BASE_ADRS0x00000000 /* memory seen from PCI bus */302 #endif /* Extended VME config */303304 /*305 * Primary PCI bus configuration space address and data register addresses306 * as seen by the CPU on the local bus.

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307 */308309 #ifndef EXTENDED_VME310 # define PCI_PRIMARY_CAR0x80000CF8 /* PCI config address register */311 # define PCI_PRIMARY_CDR0x80000CFC /* PCI config data register */312 #else313 # define PCI_PRIMARY_CAR0xFE000CF8 /* PCI config address register */314 # define PCI_PRIMARY_CDR0xFE000CFC /* PCI config data register */315 #endif /* Extended VME config */316317318 /*319 * PCI Config Space device addresses based on their device number320 *321 * Bit 32 is set to enable CONFIG_DATA accesses to PCI Cycles322 */323324 #define CNFG_START_SEARCH0x5800 /* PCI Space starting offset */325 #define CNFG_RAVEN_ADRSCPU_PCI_ISA_IO_ADRS /* Raven PCI and MPIC ASIC*/326 #define CNFG_IBC_ADRS0x80005800 /* IBC */327 #define CNFG_SCSI_ADRS0x80006000 /* SCSI */328 #define CNFG_UNIVERSE_ADRS0x80006800 /* VMEbus Bridge */329 #define CNFG_LN_ADRS0x80007000 /* Ethernet Device */330 #define CNFG_VGA_ADRS0x80007800 /* Graphics Device */331 #define CNFG_PMC1_ADRS0x80008000 /* PMC Slot1 */332 #define CNFG_SCSI2_ADRS0x80008800 /* Secondary SCSI */333 #define CNFG_LN2_ADRS0x80009000 /* Secondary Ethernet */334 #define CNFG_PMC2_ADRS0x80009800 /* PMC Slot 2 or PCIX */335336 /* Number of PCI devices */337338 #define NUM_PCI_DEVS4339340 /* PCI Device/Vendor IDs */341342 #define PCI_ID_RAVEN 0x48011057 /* Id for RAVEN ASIC */343 #define PCI_ID_IBC 0x056510ad /* Id for W83C553 PIB */344 #define PCI_ID_UNIVERSE 0x000010e3 /* Id for Universe VME chip */345 #define PCI_ID_LN_DEC21140 0x00091011 /* Id DEC chip 21140 */346 #define PCI_ID_SCSI 0x00031000 /* Id for SYM53C825/75 Chips */347 #define PCI_ID_NCR810 0x00011000 /* Id for SYM53C810A Chip */348 #define PCI_ID_NCR860 0x00061000 /* Id for SYM53C860 Chip */349 #define PCI_ID_NCR825 0x00031000 /* Id for SYM53C825/75 Chips*/350 #define PCI_ID_LN_DEC21040 0x00021011 /* Id DEC chip 21040 */351 #define PCI_ID_5434 0x00a81013 /* Id for CL-GD534 chip */352 #define PCI_ID_5436 0x00ac1013 /* Id for CL-GD536 chip */353 #define PCI_ID_BR_DEC21150 0x00221011 /* Id DEC 21150 PCI bridge */354355 /* PCI Space Definitions -- For configuring the RAVEN */356357 /* CPU to PCI definitions */358

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359 #define CPU2PCI_MSATT_MEM0x00c2360 #define CPU2PCI_MSATT_IO0x00c0361362 #ifndef EXTENDED_VME363364 /* STANDARD ( PREP ) mapping of PCI space */365366 /* setup address space 0 for PCI MEM space */367 #define CPU2PCI_ADDR0_START_VAL0xfd00368 #define CPU2PCI_ADDR0_END_VAL0xfdff369 #define CPU2PCI_OFFSET0_VAL((0x0-CPU2PCI_ADDR0_START_VAL) & 0xffff)370371 /* setup address space 1 for PCI I/O space */372 #define CPU2PCI_ADDR1_START_VAL0xfe00373 #define CPU2PCI_ADDR1_END_VAL0xfe7f374 #define CPU2PCI_OFFSET1_VAL((0x0-CPU2PCI_ADDR1_START_VAL) & 0xffff)375 #define CPU2PCI_MSATT1_VALCPU2PCI_MSATT_IO376377 /* setup address space 2 for PCI MEM space -- maps VME address space */378 #define CPU2PCI_ADDR2_START_VALCPU_PCI_MEM_UPPER_ADRS379 #define CPU2PCI_ADDR2_END_VAL0xfcff380 #define CPU2PCI_OFFSET2_VAL((0x0-CPU2PCI_ADDR2_START_VAL) & 0xffff)381382 /* setup address space 3 for PCI I/O space */383 #define CPU2PCI_ADDR3_START_VALCPU_PCI_IO_UPPER_ADRS384 #define CPU2PCI_ADDR3_END_VAL0xbf7f385 #define CPU2PCI_OFFSET3_VAL((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)386387 #else388389 /* EXTENDED VME PCI mapping */390391 /* setup address space 0 for PCI MEM space -- maps VME address space */392 #define CPU2PCI_ADDR0_START_VAL0x4000393 #define CPU2PCI_ADDR0_END_VAL0xfbff394 #define CPU2PCI_OFFSET0_VAL0x0395396 /* setup address space 1 for PCI MEM, for MPIC regs */397 #define CPU2PCI_ADDR1_START_VAL(MPIC_BASE_ADRS >>16)398 #define CPU2PCI_ADDR1_END_VAL(((MPIC_BASE_ADRS + 0x00ffffff) \399 >> 16) & 0x0000ffff)400 #define CPU2PCI_OFFSET1_VAL0x0401 #define CPU2PCI_MSATT1_VALCPU2PCI_MSATT_MEM402403 /* setup address space 2 for PCI MEM -- maps reg. space */404 #define CPU2PCI_ADDR2_START_VAL(CPU_PCI_MEM_ADRS >>16)405 #define CPU2PCI_ADDR2_END_VAL(((CPU_PCI_MEM_ADRS + 0x00ffffff) \406 >> 16) & 0x0000ffff)407 #define CPU2PCI_OFFSET2_VAL0x0408409 /* setup address space 3 for PCI I/O */410 #define CPU2PCI_ADDR3_START_VAL(CPU_PCI_IO_ADRS >>16)

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411 #define CPU2PCI_ADDR3_END_VAL(((CPU_PCI_IO_ADRS + 0x007fffff) \412 >> 16) & 0x0000ffff)413 #define CPU2PCI_OFFSET3_VAL((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)414415 #endif416417 /* defines that are used in romInit.s */418419 #define CPU2PCI_ADDR0_STARTCPU2PCI_ADDR0_START_VAL420 #define CPU2PCI_ADDR0_ENDCPU2PCI_ADDR0_END_VAL421 #define CPU2PCI_OFFSET0CPU2PCI_OFFSET0_VAL422 #define CPU2PCI_MSATT0CPU2PCI_MSATT_MEM423 #define CPU2PCI_ADDR1_STARTCPU2PCI_ADDR1_START_VAL424 #define CPU2PCI_ADDR1_ENDCPU2PCI_ADDR1_END_VAL425 #define CPU2PCI_OFFSET1CPU2PCI_OFFSET1_VAL426 #define CPU2PCI_MSATT1CPU2PCI_MSATT1_VAL427 #define CPU2PCI_ADDR2_STARTCPU2PCI_ADDR2_START_VAL428 #define CPU2PCI_ADDR2_ENDCPU2PCI_ADDR2_END_VAL429 #define CPU2PCI_OFFSET2CPU2PCI_OFFSET2_VAL430 #define CPU2PCI_MSATT2CPU2PCI_MSATT_MEM431 #define CPU2PCI_ADDR3_STARTCPU2PCI_ADDR3_START_VAL432 #define CPU2PCI_ADDR3_ENDCPU2PCI_ADDR3_END_VAL433 #define CPU2PCI_OFFSET3CPU2PCI_OFFSET3_VAL434 #define CPU2PCI_MSATT3CPU2PCI_MSATT_IO435436 /* PCI to CPU definitions */437438 #ifdef LOCAL_MEM_AUTOSIZE439 # define DRAM_SIZE((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)440 #else441 # define DRAM_SIZE(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)442 #endif443444 #define PCI2CPU_ADDR0_START (PCI2DRAM_BASE_ADRS & 0xffff0000)445 # define PCI2CPU_ADDR0_END ((PCI2DRAM_BASE_ADRS + DRAM_SIZE \446 - 0x10001) >> 16)447 #define PCI2CPU_ADDR0_RANGE (PCI2CPU_ADDR0_START | PCI2CPU_ADDR0_END)448 #define PCI2CPU_OFFSET0 (((0x0-PCI2DRAM_BASE_ADRS)>>16) & 0x0000ffff)449 #define PCI2CPU_ATT0 0xf2450451 #define PCI2CPU_ADDR1_START ((PCI2DRAM_BASE_ADRS + DRAM_SIZE \452 - 0x10000) & 0xffff0000)453 #define PCI2CPU_ADDR1_END ((PCI2DRAM_BASE_ADRS + DRAM_SIZE \454 - 0x10000) >> 16)455 #define PCI2CPU_ADDR1_RANGE (PCI2CPU_ADDR1_START | PCI2CPU_ADDR1_END)456 #define PCI2CPU_OFFSET1 (((0x0-PCI2DRAM_BASE_ADRS)>>16) & 0x0000ffff)457 #define PCI2CPU_ATT1 0xe2458459 /*460 * Address decoders 2 and 3 are not currently used, so they are461 * set to point to an address that is not used on the PCI bus462 */

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463 #define PCI2CPU_ADDR2_RANGE 0xfff0fff0464 #define PCI2CPU_OFFSET2 0x0465 #define PCI2CPU_ATT2 0x0466 #define PCI2CPU_ADDR3_RANGE 0xfff0fff0467 #define PCI2CPU_OFFSET3 0x0468 #define PCI2CPU_ATT3 0x0469470 /*471 * Allocate PCI Memory and I/O Space Offsets for PCI devices472 *473 * All devices on the primary and secondary busses are allocated 64 kb spaces.474 * The PMC Span can control up to four PMCs.475 */476477 #define SCSI_DEV_SPACE0x10000478 #define LAN_DEV_SPACE0x20000479 #define VGA_DEV_SPACE0x30000480 #define PMC_DEV_SPACE0x40000481 #define VME_DEV_SPACE0x50000482 #define LAN2_DEV_SPACE0x60000483 #define SCSI_DEV_SPACE20x70000484 #define SPAN_IO_DEV_SPACE0x80000485 #define SPAN_IO_DEV_SIZE0x40000486 #define SPAN_MEM_DEV_SPACE0x02000000487 #define SPAN_MEM_DEV_SIZE0x01000000488 #define SPAN_PREF_DEV_SPACE0x01000000489 #define SPAN_PREF_DEV_SIZE0x01000000490491 /* PCI view of PCI I/O Space for PCI devices */492493 #define PCI_IO_SCSI_ADRS(PCI_IO_ADRS + SCSI_DEV_SPACE)/* 53C825 */494 #define PCI_IO_LN_ADRS(PCI_IO_ADRS + LAN_DEV_SPACE)/* PCnet */495 #define PCI_IO_VGA_ADRS(PCI_IO_ADRS + VGA_DEV_SPACE)/* GD5434 */496 #define PCI_IO_PMC_ADRS(PCI_IO_ADRS + PMC_DEV_SPACE)/* extra */497 #define PCI_IO_LN2_ADRS(PCI_IO_ADRS + LAN2_DEV_SPACE) /* 21040 */498 #define PCI_IO_SCSI_ADRS2(PCI_IO_ADRS + SCSI_DEV_SPACE2) /* 53C825A */499500 /* PCI view of PCI Memory Space for PCI devices */501502 #define PCI_MEM_UNIVERSE_ADRS (PCI_MEM_ADRS + VME_DEV_SPACE)/* UNIVERSE */503504 #ifndef INCLUDE_MPIC505 /* PCI IACK for ISA */506507 #define ISA_INTR_ACK_REG(CPU_PCI_IACK_ADRS + 0x1ff0)508 #endif /* INCLUDE_MPIC */509510 /* Allocated base address of HW devices as seen from CPU */511512 #define SCSI_BASE_ADRS( CPU_PCI_IO_ADRS + SCSI_DEV_SPACE )513 #define LAN_BASE_ADRS( CPU_PCI_IO_ADRS + LAN_DEV_SPACE )514 #define UNIVERSE_BASE_ADRS( CPU_PCI_MEM_ADRS + VME_DEV_SPACE )

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515 #define LAN2_BASE_ADRS( CPU_PCI_IO_ADRS + LAN2_DEV_SPACE )516 #define SCSI_BASE_ADRS2( CPU_PCI_IO_ADRS + SCSI_DEV_SPACE2 )517518 /* pc87303 ISA super IO device (ISASIO) keybrd, serial, Parallel port */519520 #define pc87303_KBD_CTRL(CPU_PCI_ISA_IO_ADRS + 0x0064)/* keyboard */521 #define pc87303_INDX_REG(CPU_PCI_ISA_IO_ADRS + 0x0398)/* index reg */522 #define pc87303_DATA_REG(CPU_PCI_ISA_IO_ADRS + 0x0399)/* data reg */523 #define pc87303_PP(CPU_PCI_ISA_IO_ADRS + 0x03bc)/* parallel */524 #define pc87303_COM1(CPU_PCI_ISA_IO_ADRS + 0x03f8)/* serial 1 */525 #define pc87303_COM2(CPU_PCI_ISA_IO_ADRS + 0x02f8)/* serial 2 */526 #define pc87303_FDC(CPU_PCI_ISA_IO_ADRS + 0x03f0)/* floppy */527528 /* z85230 synchronous & Asynchronous serial communications chip */529530 #define z85230_PORTB_CTRL(CPU_PCI_ISA_IO_ADRS + 0x0840)/* serial 4 */531 #define z85230_PORTB_DATA(CPU_PCI_ISA_IO_ADRS + 0x0841)532 #define z85230_PORTA_CTRL(CPU_PCI_ISA_IO_ADRS + 0x0842)/* serial 3 */533 #define z85230_PORTA_DATA(CPU_PCI_ISA_IO_ADRS + 0x0843)534535 /* z8536 aux timer and I/O chip */536537 #definez8536_PORTC_DATA(CPU_PCI_ISA_IO_ADRS + 0x0844)538 #definez8536_PORTB_DATA(CPU_PCI_ISA_IO_ADRS + 0x0845)539 #definez8536_PORTA_DATA(CPU_PCI_ISA_IO_ADRS + 0x0846)540 #definez8536_PORT_CTRL(CPU_PCI_ISA_IO_ADRS + 0x0847)541 #define ZCIO_CNTRL_ADRS(UINT8 *)(CPU_PCI_ISA_IO_ADRS + 0x847)542 #define ZCIO_IACK_ADRS(UINT8 *)(CPU_PCI_ISA_IO_ADRS + 0x84F)543544 /* m48TXX non volatile ram, RTC and watchdog timer */545546 #define m48TXX_LSB_REG(CPU_PCI_ISA_IO_ADRS + 0x0074)547 #definem48TXX_MSB_REG(CPU_PCI_ISA_IO_ADRS + 0x0075)548 #define m48TXX_DAT_REG(CPU_PCI_ISA_IO_ADRS + 0x0077)549550 /* CPU type */551552 #define CPU_TYPE ((vxPvrGet() >> 16) & 0xffff)553 #define CPU_TYPE_6010x01/* PPC 601 CPU */554 #define CPU_TYPE_6020x02/* PPC 602 CPU */555 #define CPU_TYPE_6030x03/* PPC 603 CPU */556 #define CPU_TYPE_603E 0x06 /* PPC 603e CPU */557 #define CPU_TYPE_603P 0x07 /* PPC 603p CPU */558 #define CPU_TYPE_6040x04/* PPC 604 CPU */559 #define CPU_TYPE_604E0x09/* PPC 604e CPU */560 #define CPU_TYPE_604R0x0A/* PPC 604r CPU */561562 /* System Configuration register */563564 #define MV2600_CCR_(FALCON_BASE_ADRS + 0x400)565 #define MV2600_CCR((unsigned int *)(FALCON_BASE_ADRS + 0x400))566

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567 #define MV2600_CCR_ID_MSK0xff000000/* System ID mask */568 #define MV2600_CCR_GEN2x0xfe000000/* genesis 2.x cpu type */569 #define MV2600_CCR_2300 0xfd000000 /* hummingbird board type */570571 #define MV2600_CCR_CLK_MSK0x00f00000/* Bus clock Mask */572 #define MV2600_CCR_CPU_CLK_660x00f00000 /* cpu external Bus clock 66 Mhz */573 #define MV2600_CCR_CPU_CLK_600x00e00000 /* cpu external Bus clock 60 Mhz */574 #define MV2600_CCR_CPU_CLK_500x00d00000 /* cpu external Bus clock 50 Mhz */575576 #define MV2600_CCR_L2_MSK0x000f0000/* l2 cache mask */577 #define MV2600_CCR_L2_2560x000e0000/* 256kb L2 cache */578 #define MV2600_CCR_L2_5120x000d0000/* 512kb L2 cache */579 #define MV2600_CCR_L2_10240x000c0000/* 1Mb L2 cache */580 #define MV2600_CCR_L2_NC0x000f0000/* no cache */581582 /* DRAM configuration registers */583584 #define MV2600_MCR_(FALCON_BASE_ADRS + 0x404)585 #define MV2600_MCR((unsigned int *)(FALCON_BASE_ADRS + 0x404))586 #define MV2600_MCR_MSK0x03000000587 #define MV2600_DRAM_50ns0x03000000588 #define MV2600_DRAM_60ns0x01000000589 #define MV2600_DRAM_70ns0x0590591 #define DRAM_70ns0x0592 #define DRAM_60ns 0x02593 #define DRAM_50ns 0x06594595 #define DRAM_REG_SIZE (FALCON_BASE_ADRS + 0x10)596 #define DRAM_REG_BASE (FALCON_BASE_ADRS + 0x18)597598 /* Base Module Feature Register */599600 #define MV2600_CCR_OLD((char *)(CPU_PCI_ISA_IO_ADRS + 0x0800))601 #define MV2600_BMFR((char *)(CPU_PCI_ISA_IO_ADRS + 0x0802))602603 #define MV2600_BMFR_GIOP0x80/* genio Module */604 #define MV2600_BMFR_SCCP0x40/* z85230 sync serial Port */605 #define MV2600_BMFR_BRGP 0x20 /* PMC Span (Bridge) present */606 #defineMV2600_BMFR_PMCP0x10/* pmc Present */607 #define MV2600_BMFR_VMEP0x08/* vme bus Present */608 #define MV2600_BMFR_GFXP0x04/* graphics Present */609 #define MV2600_BMFR_LANP0x02/* ethernet Present */610 #define MV2600_BMFR_SCIP0x01/* scsi present */611612 #define DEVICE_PRESENT(x) (!((*MV2600_BMFR) & (x)))613614 /* Base Module Status Register */615616 #defineMV2600_BMSR((char *)(CPU_PCI_ISA_IO_ADRS + 0x0803))617618 #define MV2600_BMSR_2300 0xf9 /* Hummingbird */

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619 #define MV2600_BMSR_100BT40xfa/* SlimGen with 712 and 100B T4 */620 #define MV2600_BMSR_SG7120xfb/* Slim Gen with 712 */621 #defineMV2600_BMSR_SG7610xfc/* Slim Gen with 761 */622 #define MV2600_BMSR_FG7120xfd/* Full Gen with 712 */623 #define MV2600_BMSR_FG7610xfe/* Full Gen with 761 */624 #define MV2600_BMSR_16000xff/* MV1600 */625626 /* Assembly define for L2 cache */627628 #define MV2600_SXCCR_A(FALCON_BASE_ADRS + 0x8000)629630 /* defines for L2 cache routines */631632 #define MV2600_SXCCR((unsigned char *)(FALCON_BASE_ADRS + 0x8000))633634 #define L2_DISABLE0x80635 #define L2_RESET0x40636 #define L2_ENABLE0x80637 #define L2_FLUSH0x10638 #define L2_END_FLUSH0x10639 #define L2_FLUSH_LOOP4100640641 /* z8536 I/O port bit mapping */642643 #definez8536_PORTA_BRDFAIL0x40644 #definez8536_PORTB_FUSE0x40645 #definez8536_PORTB_ABORT0x80646647 /*648 * Raven Extensions to Standard PCI Header649 *650 * Type declarations for the PCI Header and the macros in regards to the651 * PCI BUS. These definitions have been made with respect to PCI LOCAL652 * BUS SPECIFICATION REVISION 2.1. Every device on the PCI BUS has to653 * support 256 bytes of configuration space of which the first 64 bytes654 * are a predefined header portion defined by the PCI commitee. Bytes655 * 64 to 255 are dedicated to the device specific registers.656 *657 * Note: the PCI bus is inherently little endian.658 */659660 #define PCI_CFG_RAVEN_PSADD00x80661 #define PCI_CFG_RAVEN_PSATT00x84662 #define PCI_CFG_RAVEN_PSOFF00x86663 #define PCI_CFG_RAVEN_PSADD10x88664 #define PCI_CFG_RAVEN_PSATT10x8c665 #define PCI_CFG_RAVEN_PSOFF10x8e666 #define PCI_CFG_RAVEN_PSADD20x90667 #define PCI_CFG_RAVEN_PSATT20x94668 #define PCI_CFG_RAVEN_PSOFF20x96669 #define PCI_CFG_RAVEN_PSADD30x98670 #define PCI_CFG_RAVEN_PSATT30x9c

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671 #define PCI_CFG_RAVEN_PSOFF30x9e672673 /* Raven MPC registers */674675 #define RAVEN_MPC_VENID0x00676 #define RAVEN_MPC_DEVID0x02677 #define RAVEN_MPC_REVID0x05678 #define RAVEN_MPC_GCSR0x08679 #define RAVEN_MPC_FEAT0x0a680 #define RAVEN_MPC_MARB0x0e681 #define RAVEN_MPC_PADJ0x13682 #define RAVEN_MPC_MEREN0x22683 #define RAVEN_MPC_MERST0x27684 #define RAVEN_MPC_MERAD0x28685 #define RAVEN_MPC_MERAT0x2e686 #define RAVEN_MPC_PIACK0x30687 #define RAVEN_MPC_MSADD00x40688 #define RAVEN_MPC_MSOFF00x44689 #define RAVEN_MPC_MSATT00x47690 #define RAVEN_MPC_MSADD10x48691 #define RAVEN_MPC_MSOFF10x4c692 #define RAVEN_MPC_MSATT10x4f693 #define RAVEN_MPC_MSADD20x50694 #define RAVEN_MPC_MSOFF20x54695 #define RAVEN_MPC_MSATT20x57696 #define RAVEN_MPC_MSADD30x58697 #define RAVEN_MPC_MSOFF30x5c698 #define RAVEN_MPC_MSATT30x5f699 #define RAVEN_MPC_GPREG0_U0x70700 #define RAVEN_MPC_GPREG0_L0x74701 #define RAVEN_MPC_GPREG1_U0x78702 #define RAVEN_MPC_GPREG1_L0x7c703704 /*705 * Raven register bit masks706 *707 * Bits marked with ‘C’indicate conditions which can be cleared by708 * writing a 1 to the bits.709 */710711 /* Raven MPC Error Enable (MEREN) register bit masks */712713 #define RAVEN_MPC_MEREN_RTAI0x0001/* PCI mstr Recvd Target Abort Int */714 #define RAVEN_MPC_MEREN_SMAI0x0002/* PCI mstr Signld Target Abort Int */715 #define RAVEN_MPC_MEREN_SERRI0x0004/* PCI System Error Int */716 #define RAVEN_MPC_MEREN_PERRI0x0008/* PCI Parity Error Int */717 #define RAVEN_MPC_MEREN_MATOI0x0020/* MPC Address Bus Time-out Int */718 #define RAVEN_MPC_MEREN_RTAM0x0100/* RTAI machine check enable */719 #define RAVEN_MPC_MEREN_SMAM0x0200/* SMAI machine checkenable */720 #define RAVEN_MPC_MEREN_SERRM0x0400/* SERRI machine check enable */721 #define RAVEN_MPC_MEREN_PERRM0x0800/* PERRI machine check enable */722 #define RAVEN_MPC_MEREN_MATOM0x2000/* MATOI machine check enable */

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723 #define RAVEN_MPC_MEREN_DFLT0x4000/* Default MPC Master ID select */724 #define RAVEN_MPC_MEREN_VALID0x6F2F/* Mask for valid MEREN bits */725726 /* Raven MPC Error Status (MERST) register bit masks */727728 #define RAVEN_MPC_MERST_RTA0x01/* C PCI mstr Recvd Target Abort */729 #define RAVEN_MPC_MERST_SMA0x02/* C PCI mstr Signld Target Abort */730 #define RAVEN_MPC_MERST_SERR0x04/* C PCI System Error */731 #define RAVEN_MPC_MERST_PERR0x08/* C PCI Parity Error */732 #define RAVEN_MPC_MERST_MATO0x20/* C MPC Address Bus Time-out */733 #define RAVEN_MPC_MERST_OVF0x80/* C Error Status Overflow */734 #define RAVEN_MPC_MERST_VALID0xAF/* Mask for valid MERST bits */735 #define RAVEN_MPC_MERST_CLR0xAF/* Clears all errors */736737 /* Raven PCI Configuration Status register bit masks */738739 #define RAVEN_PCI_CFG_STATUS_FAST 0x0010 /* Fast back-to-back capable */740 #define RAVEN_PCI_CFG_STATUS_DPAR 0x0100 /* C Data prity error detected */741 #define RAVEN_PCI_CFG_STATUS_SELTIM0 0x0200 /* Device select timing bit 0 */742 #define RAVEN_PCI_CFG_STATUS_SELTIM1 0x0400 /* Device select timing bit 1 */743 #define RAVEN_PCI_CFG_STATUS_SIGTA 0x0800 /* C Signalled Target Abort */744 #define RAVEN_PCI_CFG_STATUS_RCVTA 0x1000 /* C Received Target Abort */745 #define RAVEN_PCI_CFG_STATUS_RCVMA 0x2000 /* C Received Master Abort */746 #define RAVEN_PCI_CFG_STATUS_SIGSE 0x4000 /* C Signalled System Error */747 #define RAVEN_PCI_CFG_STATUS_RCVPE 0x8000 /* C Detected Parity Error */748 #define RAVEN_PCI_CFG_STATUS_VALID 0xFF10 /* Valid status bits */749 #define RAVEN_PCI_CFG_STATUS_CLR 0xF900 /* Clears all conditions */750751 /*752 * PMC Span DEC21150 PCI-to-PCI Bridge device-specific registers753 *754 * These registers are in Configuration Space and are extensions to a755 * standard type 1 PCI header.756 */757758 #define PCI_CFG_DEC21150_CHIP_CTRL 0x40759 #define PCI_CFG_DEC21150_DIAG_CTRL 0x41760 #define PCI_CFG_DEC21150_ARB_CTRL 0x42761 #define PCI_CFG_DEC21150_EVNT_DSBL 0x64762 #define PCI_CFG_DEC21150_GPIO_DOUT 0x65763 #define PCI_CFG_DEC21150_GPIO_CTRL 0x66764 #define PCI_CFG_DEC21150_GPIO_DIN 0x67765 #define PCI_CFG_DEC21150_SEC_CLK 0x68 /* secondary clock controll reg */766 #define PCI_CFG_DEC21150_SERR_STAT 0x6A767768 /* programmable interrupt controller (PIC) */769770 #definePIC_REG_ADDR_INTERVAL1/* address diff of adjacent regs. */771772 /* programmable interrupt timers */773774 #define PIT_BASE_ADRSL82565_TMR1_CNT0/* timeraddrs */

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775 #define PIT_REG_ADDR_INTERVAL1776 #define PIT_CLOCK1193180777778 /* serial ports (COM1 - COM4) */779780 #ifdef INCLUDE_I8250_SIO781 # define COM1_BASE_ADRpc87303_COM1/* serial port 1 */782 # define COM2_BASE_ADRpc87303_COM2/* serial port 2 */783 # define UART_REG_ADDR_INTERVAL 1 /* addr diff of adjacent regs */784 # define N_UART_CHANNELS 2/* No. serial I/O channels */785 #endif /* INCLUDE_I8250_SIO */786787 #ifdef INCLUDE_Z85230_SIO788 # define BAUD_CLK_FREQ10000000 /* 10 MHz “P Clock” (fixed) */789 # define REG_8530_WRITE(reg,val) sysOutByte((UINT32)(reg), (UINT8)(val))790 # define REG_8530_READ(reg,pVal) *(UINT8 *)pVal = sysInByte((UINT32)reg)791 # define DATA_REG_8530_DIRECT792 /* # define Z8530_RESET_DELAY_COUNT 2000 */793 #define Z8530_RESET_DELAY \794 { \795 int i; \796 for (i = 0; i < Z8530_RESET_DELAY_COUNT; i++) \797 ; /* do nothing */ \798 }799 #endif /* INCLUDE_Z85230_SIO */800801 /* total number of serial ports */802803 #if defined(INCLUDE_I8250_SIO) && defined(INCLUDE_Z85230_SIO)804 # define N_SIO_CHANNELS4/* No. serial I/O channels */805 #elif defined(INCLUDE_I8250_SIO)806 # define N_SIO_CHANNELS2/* No. serial I/O channels */807 #elif defined(INCLUDE_Z85230_SIO)808 # define N_SIO_CHANNELS2/* No. serial I/O channels */809 #else810 # define N_SIO_CHANNELS0/* No. serial I/O channels */811 #endif812813 /* non-volatile (battery-backed) ram defines814 *815 * the top 16 bytes are used for the RTC registers816 */817818 #defineBBRAM_ADRS0 /* base address */819 #defineBBRAM_SIZE0x1ff0/* 8k NVRAM Total Size */820821 /* factoryethernet address */822823 #defineBB_ENET ((char *)(BBRAM_ADRS + 0x1f2c))824825 /* MK48TXX register settings */826

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827 /* flag register */828829 #define MK48T_FLAGS((char *)(BBRAM_ADRS + 0x1ff0))830831 /* alarm clock registers, 4 1byte locations */832833 #define ALARM_CLOCK((char *)(BBRAM_ADRS + 0x1ff2))834835 /* interrupt register */836837 #define MK48T_INTR((char *)(BBRAM_ADRS + 0x1ff6))838839 /* watchdog timer register */840841 #define WD_TIMER((char *)(BBRAM_ADRS + 0x1ff7))842843 /* MK48TXX bb time of day clk, 8 1byte locations */844845 #defineTOD_CLOCK ((char *)(BBRAM_ADRS + 0x1ff8))846847 #define NV_RAM_IO_MAPPED/* nvram is io mapped in ISA space */848 #define NV_RAM_READ(x)sysNvRead (x)849 #define NV_RAM_WRITE(x,y)sysNvWrite (x,y)850 #define NV_RAM_LSB_REGm48TXX_LSB_REG851 #define NV_RAM_MSB_REGm48TXX_MSB_REG852 #define NV_RAM_DAT_REGm48TXX_DAT_REG853854 /* ncr810/ncr825 delay loop count */855856 #define NCR810_DELAY_MULT 10857858859 /*860 * UNIVERSE REGISTER SETUP FOR CPU <-> VME MAPPING (via PCI)861 *862 * ALL VAL_LSIx and VAL_VSIx values MUST be multiples of 64KB !!!863 * Except VAL_LSI0 and VAL_VSI0, which must be multiples of 4KB !864 */865866 /*867 * VME MASTER WINDOW FOR LM/SEM (MAILBOX) REGISTERS868 *869 * Universe PCI slave (VME master) window 0870 *871 * Map access to A32 VMEbus (VME LM/SEM Regs) (64K)872 */873874 #define VME_A32_REG_SIZE0x00001000/* individual reg space */875 #defineVME_A32_REG_SPACE0x00010000/* total reg space */876877 #ifndef EXTENDED_VME878 /*

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879 * Map access to A32 VMEbus (LM/SEM Regs) - 64K MAP FOR STANDARD vxWorks880 * This maps: MPU RANGE: 0xf0000000 - 0xf000ffff881 * to: PCI RANGE: 0x30000000 - 0x3000ffff882 * to: VME RANGE: 0x40000000 - 0x4000ffff883 */884 # define CPU_VME_WINDOW_REG_BASE0xf0000000885 # define VME_A32_REG_BASE0x40000000886 # define VAL_LSI0_BS_VALUE(CPU_VME_WINDOW_REG_BASE - CPU_PCI_ISA_MEM_ADRS)887 #else888 /*889 * Map access to A32 VMEbus (LM/SEM Regs) - 64K MAP FOR EXTENDED VME vxWorks890 * This maps: MPU RANGE: 0xfb000000 - 0xfb00ffff891 * to: PCI RANGE: 0xfb000000 - 0xfb00ffff892 * to: VME RANGE: 0xfb000000 - 0xfb00ffff893 */894 # define CPU_VME_WINDOW_REG_BASE0xfb000000895 # define VME_A32_REG_BASE0xfb000000896 # define VAL_LSI0_BS_VALUE(CPU_VME_WINDOW_REG_BASE)897 #endif898 #define VAL_LSI0_BS(VAL_LSI0_BS_VALUE)899 #define VAL_LSI0_BD(VAL_LSI0_BS + VME_A32_REG_SPACE)900 #define VAL_LSI0_TO(VME_A32_REG_BASE - VAL_LSI0_BS)901 #define VAL_LSI0_CTL( LSI0_CTL_EN | LSI0_CTL_WP |\902 LSI0_CTL_D64 | LSI0_CTL_A32 |\903 LSI0_CTL_DATA | LSI0_CTL_USR |\904 LSI0_CTL_SINGLE | LSI0_CTL_PCI_MEM )905906 /*907 * Semaphore Test-and-Set Register as seen from a slave.908 * Only used with a special version of sysBusTas() (not included)909 * and when mv2300, mv2600 or mv3600 boards are the ONLY boards910 * used in the configuration.911 */912913 #define OFFBRD_VME_SEM_REG1 (CPU_VME_WINDOW_REG_BASE + \914 (CPU_VME_SEM_REG1 - CPU_VME_HW_REGS_BASE))915916 /*917 * VME MASTER WINDOW FOR A24 SPACE918 *919 * Universe PCI slave (VME master) window 2920 */921922 #ifndef EXTENDED_VME923 /*924 * Map access to A24 VMEbus - 16M MAP FOR STANDARD vxWorks925 * This maps: MPU RANGE: 0xe0000000 - 0xe0ffffff926 * to: PCI RANGE: 0x20000000 - 0x20ffffff927 * to: VME RANGE: 0xff000000 - 0xffffffff928 */929 # define VME_A24_MSTR_LOCAL0xe0000000930 # define VAL_LSI2_BS_VALUE (VME_A24_MSTR_LOCAL - CPU_PCI_ISA_MEM_ADRS)

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931 #else932 /*933 * Map access to A24 VMEbus - 16M MAP FOR EXTENDED VME vxWorks934 * This maps: MPU RANGE: 0xfa000000 - 0xfaffffff935 * to: PCI RANGE: 0xfa000000 - 0xfaffffff936 * to: VME RANGE: 0xff000000 - 0xffffffff937 */ 938 # define VME_A24_MSTR_LOCAL0xfa000000939 # define VAL_LSI2_BS_VALUE(VME_A24_MSTR_LOCAL)940 #endif941 # if (VME_A24_MSTR_SIZE > 0x01000000)942 # error Maximum VME_A24_MSTR_SIZE cannot exceed 16 MB943 # endif944 #define VAL_LSI2_BS(VAL_LSI2_BS_VALUE)945 #define VAL_LSI2_BD(VAL_LSI2_BS + VME_A24_MSTR_SIZE)946 #define VAL_LSI2_TO(0xff000000 + VME_A24_MSTR_BUS - VAL_LSI2_BS)947 #define VAL_LSI2_CTL( LSI2_CTL_EN | LSI2_CTL_WP |\948 LSI2_CTL_D64 | LSI2_CTL_A24 |\949 LSI2_CTL_DATA | LSI2_CTL_USR |\950 LSI2_CTL_SINGLE | LSI2_CTL_PCI_MEM )951952 /*953 * VME MASTER WINDOW FOR A32 SPACE954 *955 * Universe PCI slave (VME master) window 1956 */957958 #ifndef EXTENDED_VME959 /*960 * Map access to A32 VMEbus - 128M MAP FOR STANDARD vxWorks961 * This maps: MPU RANGE: 0xd8000000 - 0xdfffffff962 * to: PCI RANGE: 0x18000000 - 0x1fffffff963 * to: VME RANGE: VME_A32_MSTR_BUS - VME_A32_MSTR_BUS + VME_A32_MSTR_SIZE964 */965 # define VME_A32_MSTR_LOCAL0xd8000000966 # define VAL_LSI1_BS_VALUE(VME_A32_MSTR_LOCAL - CPU_PCI_ISA_MEM_ADRS)967 # if (VME_A32_MSTR_SIZE > 0x08000000)968 # error VME_A32_MSTR_SIZE cannot exceed 128 MB969 # endif970 #else971 /*972 * Map access to A32 VMEbus - (up to ~3.7GB) MAP FOR EXTENDED VME vxWorks973 * This maps: MPU RANGE: VME_A32_MSTR_LOCAL - VME_A32_MSTR_LOCAL +974 * VME_A32_MSTR_SIZE975 * to: PCI RANGE: VME_A32_MSTR_LOCAL - VME_A32_MSTR_LOCAL +976 * VME_A32_MSTR_SIZE977 * to: VME RANGE: VME_A32_MSTR_BUS - VME_A32_MSTR_BUS +978 * VME_A32_MSTR_SIZE979 *980 * NOTE:981 * - VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE must not exceed982 * VME_A24_MSTR_LOCAL (no overlap of A32 and A24 address spaces)

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983 * - for local memory sizes greater than 256 MB, set VME_A32_MSTR_LOCAL equal984 * to the memory size.985 */986 # define VME_A32_MSTR_LOCAL0x10000000987 # define VAL_LSI1_BS_VALUE(VME_A32_MSTR_LOCAL)988 # if ((VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE) > VME_A24_MSTR_LOCAL)989 # error VME A32 space extends into VME A24 space990 # endif991 #endif992 # if ((VME_A32_MSTR_BUS + VME_A32_MSTR_SIZE) > VME_A32_REG_BASE) && \993 (VME_A32_MSTR_BUS < (VME_A32_REG_BASE + VME_A32_REG_SPACE))994 # warning VME A32 space overlaps VME LM/SEM (MAILBOX) REG space995 # endif996997 #define VAL_LSI1_BS(VAL_LSI1_BS_VALUE)998 #define VAL_LSI1_BD(VAL_LSI1_BS + VME_A32_MSTR_SIZE)999 #define VAL_LSI1_TO(VME_A32_MSTR_BUS - VAL_LSI1_BS) /* LSI1_CTL_WP | */1000 #define VAL_LSI1_CTL( LSI1_CTL_EN | LSI1_CTL_WP |\1001 LSI1_CTL_D64 | LSI1_CTL_A32 |\1002 LSI1_CTL_DATA | LSI1_CTL_USR |\1003 LSI1_CTL_SINGLE | LSI1_CTL_PCI_MEM )10041005 /*1006 * VME MASTER WINDOW FOR A16 SPACE1007 *1008 * Universe PCI slave (VME master) window 31009 */10101011 #ifndef EXTENDED_VME1012 /*1013 * Map access to A16 VMEbus - 64K MAP FOR STANDARD vxWorks1014 * This maps: MPU RANGE: 0xefff0000 - 0xefffffff1015 * to: PCI RANGE: 0x2fff0000 - 0x2fffffff1016 * to: VME RANGE: 0xffff0000 - 0xffffffff1017 */1018 #define VME_A16_MSTR_LOCAL0xefff00001019 #define VAL_LSI3_BS_VALUE(VME_A16_MSTR_LOCAL - CPU_PCI_ISA_MEM_ADRS)1020 #else1021 /*1022 * Map access to A16 VMEbus - 64K MAP FOR EXTENDED VME vxWorks1023 * This maps: MPU RANGE: 0xfbff0000 - 0xfbffffff1024 * to: PCI RANGE: 0xfbff0000 - 0xfbffffff1025 * to: VME RANGE: 0xfbff0000 - 0xfbffffff1026 */1027 # define VME_A16_MSTR_LOCAL0xfbff00001028 # define VAL_LSI3_BS_VALUE(VME_A16_MSTR_LOCAL)1029 #endif1030 # if (VME_A16_MSTR_SIZE > 0x00010000)1031 # error Maximum VME_A16_MSTR_SIZE cannot exceed 64 KB1032 # endif1033 #defineVME_A16_MSTR_BUS0x00000000/* must be 0 */1034 #define VAL_LSI3_BS(VAL_LSI3_BS_VALUE)

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1035 #define VAL_LSI3_BD(VAL_LSI3_BS + VME_A16_MSTR_SIZE)1036 #define VAL_LSI3_TO(0xffff0000 + VME_A16_MSTR_BUS - VAL_LSI3_BS)1037 #define VAL_LSI3_CTL( LSI3_CTL_EN | LSI3_CTL_WP |\1038 LSI3_CTL_D64 | LSI3_CTL_A16 |\1039 LSI3_CTL_DATA | LSI3_CTL_USR |\1040 LSI3_CTL_SINGLE | LSI3_CTL_PCI_MEM )10411042 /*1043 * VME MASTER MEMORY WINDOW LIMITS1044 *1045 * These values are strictly defined by the base memory addresses and window1046 * sizes of the spaces defined above. These values must be correct for the1047 * sysBusProbe() memory range checks of the VME bus to work properly.1048 */10491050 #ifndef EXTENDED_VME1051 # define VME_MSTR_LO_ADRS (VME_A32_MSTR_LOCAL)1052 # define VME_MSTR_HI_ADRS (CPU_VME_WINDOW_REG_BASE + VME_A32_REG_SPACE)1053 #else1054 # define VME_MSTR_LO_ADRS (VME_A32_MSTR_LOCAL)1055 # define VME_MSTR_HI_ADRS (VME_A16_MSTR_LOCAL + VME_A16_MSTR_SIZE)1056 #endif /* EXTENDED_VME */10571058 /*1059 * VME SLAVE WINDOW FOR REG SPACE1060 *1061 * Universe VME slave window 0.1062 *1063 * Setup to access the node’s VME LM/SEM Regs via1064 * A32 space on VMEbus (4KB)1065 * This range needs to be unique for each target board.1066 */10671068 #ifndef EXTENDED_VME1069 /*1070 * MAP FOR STANDARD vxWorks1071 * This maps: VME RANGE: (0x40000000 + (0x1000 * ProcNum)) -1072

* (0x40000fff + (0x1000 * ProcNum))1073 * to: PCI RANGE: 0x00001000 - 0x00001fff - ISA I/O Space1074 */1075 #define VAL_VSI0_TO_VALUE(0xc0001000 - (sysProcNumGet() * \1076 VME_A32_REG_SIZE))1077 #else1078 /*1079 * MAP FOR EXTENDED VME vxWorks1080 * This maps: VME RANGE: (0xfb000000 + (0x1000 * ProcNum)) -1081

* (0xfb000fff + (0x1000 * ProcNum))1082 * to: PCI RANGE: 0x00001000 - 0x00001fff1083 */1084 #define VAL_VSI0_TO_VALUE(0x05001000 - (sysProcNumGet() * \1085 VME_A32_REG_SIZE))1086 #endif

E-23

10871088 #define VAL_VSI0_BS(VME_A32_REG_BASE + (sysProcNumGet() * \1089 VME_A32_REG_SIZE))1090 #define VAL_VSI0_BD(VME_A32_REG_BASE + ((sysProcNumGet() + 1) * \1091 VME_A32_REG_SIZE))1092 #define VAL_VSI0_TO(VAL_VSI0_TO_VALUE)1093 #define VAL_VSI0_CTL(VSI0_CTL_EN | \1094 VSI0_CTL_AM_DATA | VSI0_CTL_AM_PGM |\1095 VSI0_CTL_AM_SUPER | VSI0_CTL_AM_USER |\1096 VSI0_CTL_VAS_A32 | VSI0_CTL_LAS_IO )10971098 /*1099 * VME SLAVE WINDOW FOR A32 SPACE1100 *1101 * Universe VME slave window 11102 *1103 * VME bus A32 window to access the master node’s local memory.1104 * This VME Slave window is only used by the master node.1105 */11061107 #ifndef EXTENDED_VME1108 /*1109 * MAP FOR STANDARD vxWorks1110 * This maps: VME RANGE: 0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)1111 * to: PCI RANGE: 0x80000000 - 0x80000000 + VME_A32_SLV_SIZE-11112 * to: MPU RANGE: 0x00000000 - VME_A32_SLV_SIZE-11113 */1114 # define PCI2DRAM_BASE_ADRS0x80000000 /* local memory seen from PCI bus */1115 #else1116 /*1117 * MAP FOR EXTENDED VME vxWorks1118 * This maps: VME RANGE: 0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)1119 * to: PCI RANGE: 0x00000000 - VME_A32_SLV_SIZE-11120 * to: MPU RANGE: 0x00000000 - VME_A32_SLV_SIZE-11121 */1122 # define PCI2DRAM_BASE_ADRS0x00000000 /* local memory seen from PCI bus */1123 #endif11241125 #define VAL_VSI1_BS(VME_A32_SLV_BUS)1126 #define VAL_VSI1_BD(VAL_VSI1_BS + VME_A32_SLV_SIZE)1127 #define VAL_VSI1_TO(PCI2DRAM_BASE_ADRS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)1128 #define VAL_VSI1_CTL( VSI1_CTL_EN | VSI1_CTL_PREN | \1129 VSI1_CTL_AM_DATA | VSI1_CTL_AM_PGM | \1130 VSI1_CTL_AM_SUPER | VSI1_CTL_AM_USER | \1131 VSI1_CTL_VAS_A32 | VSI1_CTL_LAS_MEM | \1132 VSI1_CTL_LD64EN )11331134 /*1135 * VME SLAVE WINDOW FOR A24 SPACE1136 *1137 * Universe VME A24 Slave window, does not exist. (Could use window 2.)1138 */

E-24

11391140 #define VME_A24_SLV_BUS 0x01141 #define VME_A24_SLV_SIZE 0x0/* 0, window is disabled */1142 #define VME_A24_SLV_LOCAL 0x011431144 /*1145 * VME SLAVE WINDOW FOR A16 SPACE1146 *1147 * Universe VME A16 Slave window, does not exist. (Could use window 3.)1148 */11491150 #define VME_A16_SLV_BUS0x01151 #define VME_A16_SLV_SIZE0x0/* 0, window is disabled */1152 #define VME_A16_SLV_LOCAL0x0115311541155 /* VME Registers as seen from CPU */11561157 #define CPU_VME_HW_REGS_BASE( CPU_PCI_ISA_IO_ADRS + 0x1000 )1158 #define CPU_SIG_LM_CONTROL_REG( CPU_PCI_ISA_IO_ADRS + 0x1000 )1159 #define CPU_SIG_LM_STATUS_REG( CPU_PCI_ISA_IO_ADRS + 0x1001 )1160 #define CPU_VME_LM_UBA( CPU_PCI_ISA_IO_ADRS + 0x1002 )1161 #define CPU_VME_LM_LBA( CPU_PCI_ISA_IO_ADRS + 0x1003 )1162 #define CPU_VME_SEM_REG1( CPU_PCI_ISA_IO_ADRS + 0x1004 )1163 #define CPU_VME_SEM_REG2( CPU_PCI_ISA_IO_ADRS + 0x1005 )1164 #define CPU_VME_GEOG_STAT( CPU_PCI_ISA_IO_ADRS + 0x1006 )1165 #define CPU_VME_HW_REGS_SZ711661167 /* INTERRUPT DEFINES */11681169 #define ISA_INTERRUPT_BASE0x001170 #define EXT_INTERRUPT_BASE0x101171 #define TIMER_INTERRUPT_BASE0x201172 #define IPI_INTERRUPT_BASE0x241173 #define ERR_INTERRUPT_BASE0x281174 #defineESCC_INTERRUPT_BASE0x0011751176 /* interrupt Level definitions */11771178 #ifdef INCLUDE_MPIC11791180 /* PIB (8259) interrupt connection */11811182 #define PIB_INT_LVL( 0x00 + EXT_INTERRUPT_BASE )11831184 /* ISA interrupt defines (NOTE: these are int. NUMBERS, not levels) */11851186 /* programable timer interrup level */1187 #define PIT_INT_LVL( 0x00 + ISA_INTERRUPT_BASE )11881189 /* keyboard interrupt level ( currently not supported ) */1190 #define KBD_INT_LVL( 0x01 + ISA_INTERRUPT_BASE )

E-25

11911192 /* com port 2 interrupt level */1193 #define COM2_INT_LVL( 0x03 + ISA_INTERRUPT_BASE )11941195 /* com port 1 interrupt level */1196 #define COM1_INT_LVL( 0x04 + ISA_INTERRUPT_BASE )11971198 /* floppy interrupt ( currently not supported ) */1199 #define FLOPPY_INT_LVL( 0x06 + ISA_INTERRUPT_BASE )12001201 /* parallel port interrupt level */1202 #define PP_INT_LVL( 0x07 + ISA_INTERRUPT_BASE )12031204 /* z8536 timer interrupt level */1205 #define Z8536_INT_LVL( 0x09 + ISA_INTERRUPT_BASE )12061207 /* z85230 ESCC interrupt level (shared with z8536) */1208 #define Z85230_INT_LVL( 0x09 + ISA_INTERRUPT_BASE )12091210 /* mouse interrupt ( currently not supported ) */1211 #define MOUSE_INT_LVL( 0x0c + ISA_INTERRUPT_BASE )12121213 /* PCI interrupt levels */12141215 /* Falcon-ECC error interrupt */1216 #define ECC_INT_LVL( 0x01 + EXT_INTERRUPT_BASE )12171218 /* ethernet interrupt level */1219 #define LN_INT_LVL( 0x02 + EXT_INTERRUPT_BASE )12201221 /* SCSI interrupt level */1222 #define SCSI_INT_LVL( 0x03 + EXT_INTERRUPT_BASE )12231224 /* Graphics interrupt level ( not currently used ) */1225 #define GRPH_INT_LVL( 0x04 + EXT_INTERRUPT_BASE )12261227 /* Universe LINT#0 interrupt level ( used for the UNIVERSE chip )*/1228 #define UNIV_INT_LVL0( 0x05 + EXT_INTERRUPT_BASE )12291230 /* Universe LINT#1 interrupt level */1231 #define UNIV_LINT_LVL1( 0x06 + EXT_INTERRUPT_BASE )12321233 /* Universe LINT#2 interrupt level */1234 #define UNIV_INT_LVL2( 0x07 + EXT_INTERRUPT_BASE )12351236 /* Universe LINT#3 interrupt level */1237 #define UNIV_INT_LVL3( 0x08 + EXT_INTERRUPT_BASE )12381239 /* PMC1 INTA#, PMC2 INTD# */1240 #define PMC_INT_LVL1( 0x09 + EXT_INTERRUPT_BASE )12411242 /* PMC1 INTB#, PMC2 INTC# */

E-26

1243 #define PMC_INT_LVL2( 0x0a + EXT_INTERRUPT_BASE )12441245 /* PMC1 INTC#, PMC2 INTB# */1246 #define PMC_INT_LVL3( 0x0b + EXT_INTERRUPT_BASE )12471248 /* PMC1 INTD#, PMC2 INTA# */1249 #define PMC_INT_LVL4( 0x0c + EXT_INTERRUPT_BASE )1250 1251 /* Location Monitor/SIG interrupt 0 */1252 #define LM_SIG_INT_LVL0( 0x0d + EXT_INTERRUPT_BASE )12531254 /* Location Monitor/SIG interrupt 1 ( used for the mailbox intr. ) */1255 #define LM_SIG_INT_LVL1( 0x0e + EXT_INTERRUPT_BASE )12561257 #define LM_SIG_INT_LVLLM_SIG_INT_LVL1 /* used for mailbox intr */1258 #define UNIV_INT_LVLUNIV_INT_LVL0 /* universe int level */12591260 #else12611262 #define PIT_INT_LVL0x00/* programable timer interrup level */1263 #define KBD_INT_LVL0x01/* keyboard interrupt level */1264 #define COM2_INT_LVL0x03/* com port 2 interrupt level */1265 #define COM1_INT_LVL0x04/* com port 1 interrupt level */1266 #define LM_SIG_INT_LVL0x05/* used for mailbox intr */1267 #define PP_INT_LVL0x07/* parallel port interrupt level */1268 #define Z8536_INT_LVL0x09/* z8536 timer interrupt level*/1269 #define Z85230_INT_LVL0x09/* z85230 ESCC interrupt level */1270 #define LN_INT_LVL0x0a/* ethernet interrupt level */1271 #define UNIV_INT_LVL0x0b/* universe int level */1272 #define SCSI_INT_LVL0x0e/* scsi interrupt level */1273 #define PMC_INT_LVL10x0a/* PCI INTA */1274 #define PMC_INT_LVL20x0b/* PCI INTB */1275 #define PMC_INT_LVL30x0e/* PCI INTC */1276 #define PMC_INT_LVL40x0f/* PCI INTD */12771278 #endif /* INCLUDE_MPIC */12791280 /* interrupt vector definitions */12811282 #define INT_VEC_IRQ00x00/* vector for IRQ0 */12831284 /* ISA interrupt vectors */12851286 #define PIT_INT_VECINT_VEC_IRQ0 + PIT_INT_LVL1287 #define KBD_INT_VECINT_VEC_IRQ0 + KBD_INT_LVL1288 #define PP_INT_VECINT_VEC_IRQ0 + PP_INT_LVL1289 #define COM1_INT_VEC INT_VEC_IRQ0 + COM1_INT_LVL1290 #define COM2_INT_VEC INT_VEC_IRQ0 + COM2_INT_LVL1291 #define Z8536_INT_VECINT_VEC_IRQ0 + Z8536_INT_LVL1292 #define Z85230_INT_VECINT_VEC_IRQ0 + Z85230_INT_LVL12931294 /* PCI/MPIC interrupt vectors */

E-27

12951296 #define LN_INT_VECINT_VEC_IRQ0 + LN_INT_LVL1297 #define SCSI_INT_VECINT_VEC_IRQ0 + SCSI_INT_LVL1298 #define UNIV_INT_VECINT_VEC_IRQ0 + UNIV_INT_LVL1299 #define LN2_INT_VEC INT_VEC_IRQ0 + PMC_INT_LVL21300 #define SCSI_INT_VEC2 INT_VEC_IRQ0 + PMC_INT_LVL31301 #define PIB_INT_VECINT_VEC_IRQ0 + PIB_INT_LVL1302 #definePCI_PRI_INTA_VECINT_VEC_IRQ0 + PMC_INT_LVL11303 #definePCI_PRI_INTB_VECINT_VEC_IRQ0 + PMC_INT_LVL21304 #definePCI_PRI_INTC_VECINT_VEC_IRQ0 + PMC_INT_LVL31305 #definePCI_PRI_INTD_VECINT_VEC_IRQ0 + PMC_INT_LVL413061307 /* UNIVERSE chip interrupt vector defines */13081309 #define UNIV_DMA_INT_VEC0x561310 #define UNIV_VME_SW_IACK_INT_VEC 0x571311 #define UNIV_PCI_SW_INT_VEC0x581312 #define UNIV_VOWN_INT_VEC0x591313 #define UNIV_LERR_INT_VEC0x5a1314 #define UNIV_VERR_INT_VEC0x5c1315 #define UNIV_SYSFAIL_INT_VEC0x5d1316 #define UNIV_ACFAIL_INT_VEC0x5f13171318 /*1319 * Address range definitions for VME and PCI buses.1320 *1321 * Used with vxMemProbe() hook sysBusProbe().1322 */13231324 #define IS_VME_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)VME_MSTR_LO_ADRS) && \1325 ((UINT32)(adrs) < (UINT32)VME_MSTR_HI_ADRS))13261327 #define IS_PCI_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)PCI_MSTR_LO_ADRS) && \1328 ((UINT32)(adrs) < (UINT32)PCI_MSTR_HI_ADRS))13291330 /* VME Interrupt Bit definitions */13311332 #define SIG1_INTR_SET0x801333 #define SIG0_INTR_SET0x401334 #define LM1_INTR_SET0x201335 #define LM0_INTR_SET0x101336 #define SIG1_INTR_CLEAR0x081337 #define SIG0_INTR_CLEAR0x041338 #define LM1_INTR_CLEAR0x021339 #define LM0_INTR_CLEAR0x0113401341 #define SIG1_INTR_ENABL0x801342 #define SIG0_INTR_ENABL0x401343 #define LM1_INTR_ENABL0x201344 #define LM0_INTR_ENABL0x101345 #define SIG1_INTR_STATUS0x081346 #define SIG0_INTR_STATUS0x04

E-28

1347 #define LM1_INTR_STATUS0x021348 #define LM0_INTR_STATUS0x0113491350 #define MV2600_SIOP_HW_REGS {0,0,0,0,0,1,0,0,0,0,0}13511352 /* PCI bus number for primary PCI bus */13531354 #define PCI_PRIMARY_BUS 013551356 /* Fixed PMC Span (PCI-to-PCI Bridge) configuration parameters */13571358 #define P2P_CLR_STATUS 0xFFFF00001359 #define P2P_SEC_BUS_RESET (0x0040 << 16)1360 #define P2P_CLK_ENABLE 0x00 /* enable clocks on all slots */1361 #define P2P_PMC_DISABLE 01362 #define P2P_PMC_ENABLE 713631364 #ifndef _ASMLANGUAGE13651366 /* PMC Span (DEC21150 PCI-to-PCI Bridge) Configuration Parameter Structure */13671368 typedef struct pmc_span_parm/* PMC_SPAN */1369 {1370 UINT16 parmOffset;/* offset into configuration header */1371 UINT16 parmSize;/* parmValue size (1, 2 or 4 bytes) */1372 UINT32 parmValue;/* parameter value placed at this offset */1373 } PMC_SPAN;13741375 #endif /* _ASMLANGUAGE */13761377 #define SEC_CLR_STATUS 0xFFFF00001378 #define SEC_CACHE_LINE_SIZE (0x08)1379 #define SEC_PRIM_LATENCY 01380 #define SEC_IO_SPACE_BASE_ADRS (0x01)1381 #define SEC_IO_SPACE_LIMIT_ADRS (0xF1 << 8)1382 #define SEC_MEM_SPACE_BASE_ADRS ((PCI_MEM_ADRS + PMC_SPAN_MEM_BASE) >> 16)1383 #define SEC_MEM_SPACE_LIMIT_ADRS ((PCI_MEM_ADRS + PMC_SPAN_MEM_BASE + \1384 PMC_SPAN_MEM_SIZE - 1) & 0xFFFF)1385 #define SEC_MEM_MAP_IO_BASE_ADRS (0x7F00)1386 #define SEC_MEM_MAP_IO_LIMIT_ADRS (0x7000 << 16)1387 #defineSEC_IO_32SPACE_BASE_ADRS ((PCI_IO_ADRS + PMC_SPAN_IO_BASE) >> 16)1388 #defineSEC_IO_32SPACE_LIMIT_ADRS ((PCI_IO_ADRS + PMC_SPAN_IO_BASE + \1389 PMC_SPAN_IO_SIZE - 1) & 0xFFFF)1390 #define SEC_ISA_BUS (0x0000 << 16) /* 0 = none, 4 = ISA */1391 #define SEC_PMC_DISABLE (0x00)1392 #define SEC_PMC_ENABLE (0x07)139313941395 #ifdef __cplusplus1396 }1397 #endif1398

E-29

1399 #endif /* INCmv260xh */


Appendix - F

config.h

F-2

mv2600.h

1 /* config.h - Motorola PowerPlus board configuration header */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 /* Copyright 1996 Motorola, Inc. */56 /*7 modification history8 --------------------9 01w,03oct97,mas assigned non-zero MPIC priorities to all PCI ints (SPR 9388).10 01v,18sep97,dds added macro SCSI_WIDE_ENABLE.11 01u,14aug97,mas Extended VME addressing is now default; no slave VME A24 space12 (for cumulative patch release 9/97; BSP_REV 4).13 01t,24jul97,mas added MPIC priority scheme (SPR 8956).14 01s,20jul97,dat REV 3 for jumbo patch 2, chg’d SM_ANCHOR_ADRS (SPR 9019).15 01r,17jul97,mas added undef of LOCAL_MEM_AUTOSIZE, refined definition of16 VME_A32_SLV_SIZE (SPR 8824).17 01q,09jul97,mas NCR810_DELAY_MULT now defined in mv2600.h (SPR 8842).18 01p,17jun97,mas merged w/SENS version of BSP.19 01o,05jun97,mas added support for serial ports 3 & 4 (Z85230 ESCC). (SPR 8566)20 01n,29may97,srr Added comments about shared memory setup (MCG MR #74)21 01m,12may97,dat moving things between config.h and mv2600.h22 01l,09may97,mas added extended VME addressing (SPR 8410).23 added NCR810_DELAY_MULT (SPR 8430).24 01k,28apr97,gnn Added documentation for END_OVERRIDE and INCLUDE_END25 01j,25apr97,map BSP_REV is 2. Added SENS support.26 01i,23apr97,mas added MPIC support from Motorola (SPR 8170).27 01h,11apr97,dat moved macros around, user changeable macros are here,28 not-changeable ones are in mv2600.h29 01g,10apr97,mas added PCI I/O function defines and PMC Span support (SPR 8226).30 01f,01apr97,dat new VME window configuration macros, SPR 827131 01e,18feb97,mas added undef of INCLUDE_TIMESTAMP (SPR 7772, 7811).32 01d,03jan97,mas BSP_REV set to “/0”.33 01c,02jan97,dat default does not include SCSI, fixed mod history34 01b,19oct96,srr Replaced CPU_SPEED with MEMORY_BUS_SPEED to be compatible35 with change made by Wind River.36 01a,01oct96,mot written. (from ver 01q, mv1600/config.h)37 */3839 /*40 This file contains the configuration parameters for the41 Motorola PowerPlus architecture42 */4344 #ifndefINCconfigh45 #defineINCconfigh4647 #ifdef __cplusplus48 extern “C” {49 #endif

F-3

5051 /* The following defines must precede configAll.h */5253 /* BSP version/revision identification */5455 #define BSP_VER_1_1 156 #define BSP_VERSION “1.1”57 #define BSP_REV “/4”/* 0 for first revision */5859 /* PRIMARY INCLUDES */6061 #include “configAll.h”6263 /* defines */6465 #if (CPU == PPC603)66 # define DEFAULT_BOOT_LINE \67 “dc(0,0)host:/tornado/mv2603/vxWorks h=90.0.0.1 e=90.0.0.2 u=vxworks”68 # define WRONG_CPU_MSG “A PPC603 VxWorks image cannot run on a PPC604!\n”;6970 #elif (CPU == PPC604)71 72 # define DEFAULT_BOOT_LINE \73 “dc(0,0)host:/tornado/mv2604/vxWorks h=90.0.0.1 e=90.0.0.2 u=vxworks”74 # define WRONG_CPU_MSG “A PPC604 VxWorks image cannot run on a PPC603!\n”;75 #endif/* (CPU == PPC604) */767778 /*79 * Default board configurations80 *81 * If a supported feature is desired,82 * change to: #define83 * If a feature is not desired or not supported84 * change to: #undef85 *86 * NOTE: Not all functionality is supported on all boards87 */8889 #ifdef MV260090 # defineINCLUDE_CACHE_L2/* L2 cache support */91 # defineINCLUDE_I8250_SIO /* COM1 and COM2 via i8250 */92 # defineINCLUDE_Z85230_SIO /* serial ports 3 & 4 via Z85230 */93 # defineINCLUDE_PRIMARY_ENET/* DEC 21140 */94 # undefINCLUDE_SECONDARY_ENET/* [NOT AVAILABLE] */95 # defineINCLUDE_PRIMARY_SCSI/* NCR 825 */96 # undefINCLUDE_SECONDARY_SCSI/* [NOT AVAILABLE] */97 # defineINCLUDE_AUXCLK/* Z 8536 */98 #endif99 100 #ifdef MV3600101 # defineINCLUDE_CACHE_L2/* L2 cache support */

F-4

102 # defineINCLUDE_I8250_SIO /* COM1 and COM2 via i8250 */103 # defineINCLUDE_Z85230_SIO /* serial ports 3 & 4 via Z85230 */104 # defineINCLUDE_PRIMARY_ENET/* DEC 21140 */105 # defineINCLUDE_SECONDARY_ENET/* DEC 21040 */106 # defineINCLUDE_PRIMARY_SCSI/* NCR 825 */107 # defineINCLUDE_SECONDARY_SCSI/* NCR 825 */108 # defineINCLUDE_AUXCLK/* Z 8536 */109 #endif110111 #ifdef MV2300112 # undefINCLUDE_CACHE_L2/* [NOT AVAILABLE] */113 # defineINCLUDE_I8250_SIO /* Debug port via i8250 */114 # undefINCLUDE_Z85230_SIO /* [NOT AVAILABLE] */115 # defineINCLUDE_PRIMARY_ENET/* DEC 21140 */116 # undefINCLUDE_SECONDARY_ENET/* [NOT AVAILABLE] */117 # undefINCLUDE_PRIMARY_SCSI/* [NOT AVAILABLE] */118 # undefINCLUDE_SECONDARY_SCSI/* [NOT AVAILABLE] */119 # undefINCLUDE_AUXCLK/* [NOT AVAILABLE] */120 #endif121122 /* MMU and Cache options */123124 #defineINCLUDE_MMU_BASIC /* bundled mmu support */125 #undefUSER_D_CACHE_MODE126 #defineUSER_D_CACHE_MODE (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)127128 #ifdef INCLUDE_CACHE_L2129 # define USER_L2_CACHE_ENABLE/* enable the L2 cache */130 #endif /* INCLUDE_CACHE_L2 */131132 /* timestamp option not included by default; #define to include it */133134 #undef INCLUDE_TIMESTAMP135136 /* De-select unused (default) network drivers selected in configAll.h */137138 #undef INCLUDE_EX /* include Excelan Ethernet interface */139 #undef INCLUDE_ENP /* include CMC Ethernet interface*/140141 /* De-select unused advanced network driver support */142143 #undefINCLUDE_END/* Enhanced Network Driver (see configNet.h) */144 #undefEND_OVERRIDE/* define if you are using old boot ROMs. */145146 /*147 * Primary Ethernet = DEC21140 = device unit #0148 *149 * The dec21140 driver can handle up to 4 devices.150 * Currently, it is only possible to boot from unit #0.151 */152153 #ifdef INCLUDE_PRIMARY_ENET

F-5

154 #define INCLUDE_DC155 #define DC_POOL_ADRS (RAM_LOW_ADRS - DC_POOL_SIZE) /* memory pooladrs */156 #define DC_POOL_SIZE 0x0000C000 /* memory pool size */157 #define DC_MODE 0x08 /* Dec21140 */158 #endif /* INCLUDE_PRIMARY_ENET */159160 /* Secondary Ethernet = DEC21040 = device unit #1 */161162 #ifdef INCLUDE_SECONDARY_ENET163 #define DC1_POOL_ADRS NONE /* memory pooladrs */164 #define DC1_POOL_SIZE NONE /* memory pool size */165 #define DC1_MODE NONE /* Default: dec21040 */166 #endif /* INCLUDE_SECONDARY_ENET */167168 /* Primary SCSI support */169170 #define INCLUDE_SCSI2/* Use SCSI2 library, not SCSI1 */171172 #ifdef INCLUDE_PRIMARY_SCSI173 #define INCLUDE_SCSI174 #define INCLUDE_SCSI_BOOT/* include ability to boot from SCSI */175 #define INCLUDE_DOSFS/* file system to be used */176 #undefSCSI_AUTO_CONFIG/* scan bus on startup */177 #undefSCSI_WIDE_ENABLE/* enable wide SCSI on MVME761-011 only */178 #defineSYS_SCSI_CONFIG/* call sysScsiConfig in sysScsi.c */179 #endif /* INCLUDE_PRIMARY_SCSI */180181 /* PCI bus numbers for secondary and subordinate buses */182183 #define PCI_SECONDARY_BUS 1184 #define PCI_SUBORD_BUS 1185 #define PCI_MAX_BUS 2 /* Max. number of PCI buses in system */186187 /* PMC Span (PCI Bridge) configuration parameters */188189 #undefINCLUDE_PMC_SPAN /* PMC Span support not included by default */190191 /* PMC Span configuration values */192193 #defineP2P_IO_BASE 0x01060000/* PCI I/O window */194 #defineP2P_IO_SIZE 0x00040000195 #defineP2P_PREF_MEM_BASE 0x02000000/* PCI prefetch mem window */196 #defineP2P_PREF_MEM_SIZE 0x01000000197 #defineP2P_PREF_HI32_BASE 0x00000000/* hi 32 bits of address */198 #defineP2P_NONPREF_MEM_BASE 0x03000000/* PCI non-prefech mem window */199 #define P2P_NONPREF_MEM_SIZE 0x01000000200 #define P2P_CACHE_LINE_SIZE 8/* cache line size */201 #define P2P_PRIM_LATENCY 0/* latency */202203 /* serial parameters */204205 #undefNUM_TTY

F-6

206 #defineNUM_TTY N_SIO_CHANNELS207208 /*209 * Auxiliary Clock support is an optional feature that is not supported210 * by all BSPs.211 */212213 #ifdef INCLUDE_AUXCLK214 # define INCLUDE_Z8536_AUXCLK /* specify aux clock device */215 #else216 # undef INCLUDE_SPY217 #endif /* INCLUDE_AUXCLK */218219 /* Shared-memory Backplane Network parameters */220221 /*222 * INCLUDE_SM_NET and INCLUDE_SM_SEQ_ADDR are the shared memory backplane223 * driver and the auto address setup which are defined in configAll.h. To224 * excluded them uncomment the following lines:225 *226 * #undef INCLUDE_SM_NET227 * #undef INCLUDE_SM_SEQ_ADDR228 */229230 #define SM_OFF_BOARDFALSE231232 #undef SM_ANCHOR_ADRS233 #define SM_ANCHOR_ADRS ((sysProcNumGet() == 0) ? \234 ((char*) (LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET)) : \235 ((char*) (VME_A32_MSTR_LOCAL + SM_ANCHOR_OFFSET)))236237 #define SM_INT_TYPESM_INT_MAILBOX_1 /* or SM_INT_NONE */238239 /*240 * The following defines are only used by the master.241 * The slave only uses the “Anchor” address.242 */243244 #define SM_MEM_ADRS0x00010000245 #define SM_MEM_SIZE0x00020000246 #define SM_OBJ_MEM_ADRS(SM_MEM_ADRS+SM_MEM_SIZE) /* SM Objects pool */247 #define SM_OBJ_MEM_SIZE0x00010000248249 #defineINCLUDE_VME/* undef to exclude VME support */250251 /*252 * Local Memory definitions253 *254 * By default, the available DRAM memory is sized at bootup (LOCAL_MEM_AUTOSIZE255 * is defined). If auto-sizing is not selected, make certain that256 * LOCAL_MEM_SIZE is set to the actual amount of memory on the board.257 * By default, it is set to the minimum memory configuration: 16 MB.

F-7

258 * Failure to do so can cause unpredictable system behavior!259 */260261 #defineLOCAL_MEM_AUTOSIZE/* undef for fixed size */262 #define LOCAL_MEM_LOCAL_ADRS0x00000000/* fixed at zero */263 #define LOCAL_MEM_SIZE0x01000000/* Default: Min memory: 16MB */264265 #define RAM_HIGH_ADRS0x00200000 /* RAM address for ROM boot */266 #define RAM_LOW_ADRS0x00100000/* RAM address for kernel */267268 /* user reserved memory, see sysMemTop() */269270 #define USER_RESERVED_MEM(0)/* number of reserved bytes */271272 /*273 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_LOW_ADRS and RAM_HIGH_ADRS274 * are defined in config.h, Makefile .275 * All definitions for these constants must be identical.276 */277278 #undef INCLUDE_MOT_BUG_ROM/* define this to use */279280 #ifdef INCLUDE_MOT_BUG_ROM281 # defineROM_BASE_ADRS(LOCAL_MEM_SIZE)282 # defineROM_TEXT_ADRSROM_BASE_ADRS283 #else284 # defineROM_BASE_ADRS0xfff00000/* base address of ROM */285 # defineROM_TEXT_ADRS(ROM_BASE_ADRS + 0x100)286 #endif /* INCLUDE_MOT_BUG_ROM */287288 #defineROM_SIZE0x00080000/* 512K ROM space */289290 /* Extended VME A32 space; enabled by default, #undef disables it */291292 #defineEXTENDED_VME293294 /*295 * VME A32 master window,296 *297 * The standard window size (as shipped) is 128 MB. This is the largest298 * size recommended for use with TLBs and is the largest size allowed with299 * extended VME addressing disabled. Use of only BAT registers can increase300 * the size to 1 GB. For larger sizes, TLBs and BATs must be used together.301 *302 * Memory address granularity is 64 KB for TLBs while BATs are restricted to303 * the following fixed sizes: 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB,304 * 16 MB, 32 MB, 64 MB, 128 MB or 256 MB each. Because there are only 4 BATs305 * for data address translation, a maximum of 4 x 256 MB = 1 GB can be306 * mapped this way.307 *308 * Memory usage by TLBs is costly. For each 128 MB of memory to be mapped,309 * 1 MB of memory is used by TLBs. A TLB array for 1 GB would require 8 MB!

F-8

310 */311312 /* VME Master access windows, set size to 0 to disable a window */313314 #defineVME_A32_MSTR_BUS0x08000000315 #define VME_A32_MSTR_SIZE0x08000000/* Base VME address */316317 /* VME A24 master window, (16MB) */318319 #defineVME_A24_MSTR_BUS0x00000000/* Base VME address */320 #define VME_A24_MSTR_SIZE0x01000000/* 0 to 16MB, mult of 64K */321322 /* VME A16 Master window (64KB) */323324 #define VME_A16_MSTR_SIZE0x00010000/* either 0 or 64KB, only */325326 /* Setup VME slave windows, set size to 0 to disable a window */327328 /*329 * VME A32 slave window, default is to map all local memory to VMEbus.330 * The window size is set to LOCAL_MEM_SIZE. This will reduce the window331 * size if LOCAL_MEM_SIZE does not reflect the actual amount of memory.332 * Hence, if all of physical memory is to be addressed in the A32 window,333 * the actual board memory size should be set in LOCAL_MEM_SIZE.334 */335336 #define VME_A32_SLV_LOCALLOCAL_MEM_LOCAL_ADRS337 #define VME_A32_SLV_BUSVME_A32_MSTR_BUS338 #ifdef LOCAL_MEM_AUTOSIZE339 # define VME_A32_SLV_SIZE((ULONG)sysPhysMemTop())340 #else341 # define VME_A32_SLV_SIZE(LOCAL_MEM_SIZE)342 #endif343344 /* VME A24 slave window, no default support */345346 /* VME A16 slave window, no default support */347348349 /* Include MPIC support by default */350351 #defineINCLUDE_MPIC352353 /*354 * These defines are used to initialize the External Source355 * Vector/Priority registers in the MPIC. The following can356 * be defined: interrupt sensitivity, polarity and interrupt priority.357 *358 * Note: by default a 0 into the sense bit(22) will setup for level359 * sensitive, and a 0 into the polarity bit(23) will setup for low360 * polarity.361 *

F-9

362 * At initialization all external interrupt sources are disabled363 * except for the 8259 input, which is enabled in the MPIC driver.364 *365 * All currently unused interrupt sources are set to a priority of366 * 0, which will not allow them to be enabled. If any one of these367 * levels is to be used, the priority value must be changed here.368 */369370 #define INIT_EXT_SRC0 ( INT_MASK_BIT | HIGH_POLARITY | LEVEL_SENSE |\371 PRIORITY_LVL8 ) /* PIB (8259) */372373 #define INIT_EXT_SRC1 ( INT_MASK_BIT | PRIORITY_LVL0 ) /* Falcon ECC*/374375 #define INIT_EXT_SRC2 ( INT_MASK_BIT | LEVEL_SENSE |\376 PRIORITY_LVL14 ) /* primary ethernet */377378 #define INIT_EXT_SRC3 ( INT_MASK_BIT | LEVEL_SENSE |\379 PRIORITY_LVL3 ) /* primary SCSI */380381 #define INIT_EXT_SRC4 ( INT_MASK_BIT | LEVEL_SENSE |\382 PRIORITY_LVL0 ) /* graphics */383384 #define INIT_EXT_SRC5 ( INT_MASK_BIT | LEVEL_SENSE |\385 PRIORITY_LVL10 ) /* Universe LINT0 */386387 #define INIT_EXT_SRC6 ( INT_MASK_BIT | LEVEL_SENSE |\388 PRIORITY_LVL0 ) /* Universe LINT1 */389390 #define INIT_EXT_SRC7 ( INT_MASK_BIT | LEVEL_SENSE |\391 PRIORITY_LVL0 ) /* Universe LINT2 */392393 #define INIT_EXT_SRC8 ( INT_MASK_BIT | LEVEL_SENSE |\394 PRIORITY_LVL0 ) /* Universe LINT3 */395396 #define INIT_EXT_SRC9 ( INT_MASK_BIT | LEVEL_SENSE |\397 PRIORITY_LVL7 ) /* PCI PMC1/PMC2 INTA */398399 #ifdef INCLUDE_SECONDARY_ENET400 # define INIT_EXT_SRC10 ( INT_MASK_BIT | LEVEL_SENSE |\401 PRIORITY_LVL13 ) /* PCI INTB/sec ethernet */402 #else403 # define INIT_EXT_SRC10 ( INT_MASK_BIT | LEVEL_SENSE |\404 PRIORITY_LVL6 ) /* PCI INTB */405 #endif /* INCLUDE_SECONDARY_ENET */406407 #ifdef INCLUDE_SECONDARY_SCSI408 # define INIT_EXT_SRC11 ( INT_MASK_BIT | LEVEL_SENSE |\409 PRIORITY_LVL2 ) /* PCI INTC/sec SCSI */410 #else411 # define INIT_EXT_SRC11 ( INT_MASK_BIT | LEVEL_SENSE |\412 PRIORITY_LVL5 ) /* PCI INTC */413 #endif /* INCLUDE_SECONDARY_SCSI */

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414415 #define INIT_EXT_SRC12 ( INT_MASK_BIT | LEVEL_SENSE |\416 PRIORITY_LVL4 ) /* PCI PMC1/PMC2 INTD */417418 #define INIT_EXT_SRC13 ( INT_MASK_BIT | LEVEL_SENSE |\419 PRIORITY_LVL0 ) /* LM/SIG int 0 */420421 #define INIT_EXT_SRC14 ( INT_MASK_BIT | LEVEL_SENSE |\422 PRIORITY_LVL15 ) /* LM/SIG int 0/mailbox */423424 #define INIT_EXT_SRC15 ( INT_MASK_BIT | LEVEL_SENSE |\425 PRIORITY_LVL0 ) /* NOT USED */426427428 /* BSP-specific includes */429430 #include “mv2600.h”431432433 #ifdef __cplusplus434 }435 #endif436437 #endif/* INCconfigh */438


Appendix - G

Serial Driver Code

G-2

sysSerial.c

1 /* sysSerial.c - MVME260x/360x BSP serial device initialization */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 #include “copyright_wrs.h”56 /*7 modification history8 --------------------9 01d,10jun97,mas added support for serial ports 3 & 4 (Z85230 ESCC). (SPR 8566)10 01c,02jan97,wlf doc: cleanup.11 01b,02jan97,dat documentation, mod history fix12 01a,01sep96,mot written (from mv1603/sysSerial.c, ver 01b)13 */1415 /*16 The sysSerial.c file is normally included as part of the sysLib.c file.17 This code segment configures the serial ports for the BSP.1819 This BSP can support a single I8250 DUSART and the onboard SCC channels20 of the Z85230 ESCC. Either, both, or none may be configured into the21 system.22 */2324 #include “vxWorks.h”25 #include “iv.h”26 #include “intLib.h”27 #include “config.h”28 #include “sysLib.h”29 #include “drv/sio/i8250Sio.h”30 #include “drv/sio/z8530Sio.h”3132 /* externals */3334 IMPORT UCHARsysInByte(ULONG);35 IMPORT voidsysOutByte(ULONG, UCHAR);36 IMPORT intintEnable (int intLevel);3738 /* device initialization structures */3940 #ifdef INCLUDE_I8250_SIO41 typedef struct42 {43 USHORT vector;/* Interrupt vector */44 ULONG baseAdrs;/* Register base address */45 USHORT regSpace;/* Address Interval */46 USHORT intLevel;/* Interrupt level */47 } I8250_CHAN_PARAS;48 #endif /*INCLUDE_I8250_SIO*/49

G-3

50 /* Local data structures */5152 #ifdef INCLUDE_I8250_SIO53 static I8250_CHAN i8250Chan[N_UART_CHANNELS];5455 static I8250_CHAN_PARAS devParas[] =56 {57 {COM1_INT_VEC, COM1_BASE_ADR, UART_REG_ADDR_INTERVAL, COM1_INT_LVL},58 {COM2_INT_VEC, COM2_BASE_ADR, UART_REG_ADDR_INTERVAL, COM2_INT_LVL}59 };60 #endif /*INCLUDE_I8250_SIO*/6162 #define UART_REG(reg,chan) \63 (devParas[chan].baseAdrs + reg * devParas[chan].regSpace)6465 #ifdef INCLUDE_Z85230_SIO66 static Z8530_DUSART z85230Escc;67 #endif /*INCLUDE_Z85230_SIO*/6869 /* globals */7071 /*72 * sysSioChans - Array of pointers to all serial channels configured in system.73 *74 * Channel pointer position in this table determines the device name75 * under vxWorks. The first pointer points to the device for /tyCo/0,76 * the second to /tyCo/1, etc. See sysSerialChanGet().77 */7879 SIO_CHAN * sysSioChans [N_SIO_CHANNELS] =80 {81 #ifdef INCLUDE_I8250_SIO82 (SIO_CHAN *)&i8250Chan[0].pDrvFuncs,/* /tyCo/0 */83 (SIO_CHAN *)&i8250Chan[1].pDrvFuncs,/* /tyCo/1 */84 #endif /*INCLUDE_I8250_SIO*/8586 #ifdef INCLUDE_Z85230_SIO87 (SIO_CHAN *)&z85230Escc.portA.pDrvFuncs,/* /tyCo/2 -or- /tyCo/0 */88 (SIO_CHAN *)&z85230Escc.portB.pDrvFuncs,/* /tyCo/3 -or- /tyCo/1 */89 #endif /*INCLUDE_Z85230_SIO*/90 };919293 /

******************************************************************************94 *95 * sysSerialHwInit - initialize the BSP serial devices to a quiescent state96 *97 * This routine initializes the BSP serial device descriptors and puts the98 * devices in a quiescent state. It is called from sysHwInit() with99 * interrupts locked. Polled mode serial operations are possible, but not100 * interrupt mode operations which are enabled by sysSerialHwInit2().

G-4

101 *102 * RETURNS: N/A103 *104 * SEE ALSO: sysHwInit(), sysSerialHwInit2()105 */106107 void sysSerialHwInit (void)108 {109 #ifdef INCLUDE_I8250_SIO110 int i;111112 for (i = 0; i < N_UART_CHANNELS; i++)113 {114 i8250Chan[i].int_vec = devParas[i].vector;115 i8250Chan[i].channelMode = 0;116 i8250Chan[i].lcr = UART_REG(UART_LCR, i);117 i8250Chan[i].data = UART_REG(UART_RDR, i);118 i8250Chan[i].brdl = UART_REG(UART_BRDL, i);119 i8250Chan[i].brdh = UART_REG(UART_BRDH, i);120 i8250Chan[i].ier = UART_REG(UART_IER, i);121 i8250Chan[i].iid = UART_REG(UART_IID, i);122 i8250Chan[i].mdc = UART_REG(UART_MDC, i);123 i8250Chan[i].lst = UART_REG(UART_LST, i);124 i8250Chan[i].msr = UART_REG(UART_MSR, i);125 i8250Chan[i].outByte = (void (*) (int, char)) sysOutByte;126 i8250Chan[i].inByte = (UINT8 (*) ()) sysInByte;127128 i8250HrdInit (&i8250Chan[i]);129 }130 #endif /*INCLUDE_I8250_SIO*/131132 #ifdef INCLUDE_Z85230_SIO133 /* intialize the chips device descriptors */134135 z85230Escc.portA.cr = (char *) z85230_PORTA_CTRL;136 z85230Escc.portA.dr = (char *) z85230_PORTA_DATA;137 z85230Escc.portA.baudFreq = BAUD_CLK_FREQ;138 z85230Escc.portA.writeReg11 = SCC_WR11_RX_BR_GEN | SCC_WR11_TX_BR_GEN |139 SCC_WR11_OUT_BR_GEN;140 z85230Escc.portA.writeReg14 = SCC_WR14_BR_EN | SCC_WR14_BR_SRC |141 SCC_WR14_SRC_BR;142 z85230Escc.portA.intType = SCC_WR9_VIS;143 z85230Escc.portA.intVec = ESCC_INTERRUPT_BASE;144145 z85230Escc.portB.cr = (char *) z85230_PORTB_CTRL;146 z85230Escc.portB.dr = (char *) z85230_PORTB_DATA;147 z85230Escc.portB.baudFreq = BAUD_CLK_FREQ;148 z85230Escc.portB.writeReg11 = SCC_WR11_RX_BR_GEN | SCC_WR11_TX_BR_GEN |149 SCC_WR11_OUT_BR_GEN;150 z85230Escc.portB.writeReg14 = SCC_WR14_BR_EN | SCC_WR14_BR_SRC |151 SCC_WR14_SRC_BR;152 z85230Escc.portB.intType = SCC_WR9_VIS;

G-5

153 z85230Escc.portB.intVec = ESCC_INTERRUPT_BASE;154155 /* reset the chip */156157 z8530DevInit (&z85230Escc);158 #endif /*INCLUDE_Z85230_SIO*/159 }160161 /

******************************************************************************162 *163 * sysSerialHwInit2 - connect BSP serial device interrupts164 *165 * This routine connects the BSP serial device interrupts. It is called from166 * sysHwInit2().167 *168 * Serial device interrupts cannot be connected in sysSerialHwInit() because169 * the kernel memory allocator is not initialized at that point, and170 * intConnect() calls malloc().171 *172 * RETURNS: N/A173 *174 * SEE ALSO: sysHwInit2()175 */176177 void sysSerialHwInit2 (void)178 {179 #ifdef INCLUDE_I8250_SIO180 int i;181182 /* connect serial interrupts */183184 for (i = 0; i < N_UART_CHANNELS; i++)185 if (i8250Chan[i].int_vec)186 {187 (void) intConnect (INUM_TO_IVEC ((int)i8250Chan[i].int_vec),188 i8250Int, (int)&i8250Chan[i] );189190 intEnable (devParas[i].intLevel);191 }192 #endif /*INCLUDE_I8250_SIO*/193194 #ifdef INCLUDE_Z85230_SIO195 (void)intConnect ((VOIDFUNCPTR *)(Z85230_INT_VEC), z8530Int,196 (int)&z85230Escc);197 intEnable (Z85230_INT_LVL);198 #endif /*INCLUDE_Z85230_SIO*/199 }200201202 /

******************************************************************************

G-6

203 *204 * sysSerialChanGet - get the SIO_CHAN device associated with a serial channel205 *206 * This routine returns a pointer to the SIO_CHAN device associated207 * with a specified serial channel. It is called by usrRoot() to obtain208 * pointers when creating the system serial devices, `/tyCo/x’. It209 * is also used by the WDB agent to locate its serial channel.210 *211 * RETURNS: A pointer to the SIO_CHAN structure for the channel, or ERROR212 * if the channel is invalid.213 */214215 SIO_CHAN * sysSerialChanGet216 (217 int channel/* serial channel */218 )219 {220 if (channel < 0 || channel >= NELEMENTS(sysSioChans))221 return (SIO_CHAN *)ERROR;222223 return sysSioChans[channel];224 }225226 /

******************************************************************************227 *228 * sysSerialReset - reset all serial devices to a quiescent state229 *230 * This routine resets all serial devices to a quiescent state. It is called231 * by sysToMonitor().232 *233 * RETURNS: N/A234 *235 * SEE ALSO: sysToMonitor()236 */237238 void sysSerialReset (void)239 {240 #ifdef INCLUDE_I8250_SIO241 int i;242243 for (i = 0; i < N_UART_CHANNELS; i++)244 i8250HrdInit (&i8250Chan[i]);245 #endif /*INCLUDE_I8250_SIO*/246247 #ifdef INCLUDE_Z85230_SIO248 z8530DevInit (&z85230Escc);249 #endif /*INCLUDE_Z85230_SIO*/250

G-7

sioLib.h

1 /* z8530Sio.h - header file for binary interface z8530 driver */23 /* Copyright 1984-1994 Wind River Systems, Inc. */45 /*6 modification history7 --------------------8 01d,20may97,db added element options to Z8530_CHAN structure to9 implement hardware options & modem control(SPR #1037).10 01c,13oct95,ms added comments for what fields need to be set by the BSP11 01b,15jun95,ms updated for new driver structure12 01a,20dec94,ms written (from z8530Serial.h).13 */1415 #ifndef __INCwdbz8530h16 #define __INCwdbz8530h1718 #include “sioLib.h”1920 #ifdef __cplusplus21 extern “C” {22 #endif2324 /* device and channel structures */2526 /* The BSP must initilize all Z8530_CHAN fields which say “BSP:” */2728 /* The BSP must initilize all Z8530_CHAN fields which say “BSP:” */2930 typedef struct /* Z8530_CHAN */31 {32 /* always goes first */3334 SIO_DRV_FUNCS * pDrvFuncs; /* driver functions */3536 /* callbacks */3738 STATUS (*getTxChar) (); /* pointer to xmitr function */39 STATUS (*putRcvChar) (); /* pointer to rcvr functione */40 void * getTxArg;41 void * putRcvArg;4243 /* control and data register addresses */4445 volatile char * cr; /* BSP: control register I/O address */46 volatile char * dr; /* BSP: data port I/O address */47

G-8

48 /* misc values */4950 int baudFreq; /* BSP: baud clock frequency */51 int baudRate; /* baud rate */52 int options; /* hardware options */53 char writeReg5; /* BSP: write register 5 value */54 char writeReg11; /* BSP: write register 11 value */55 char writeReg14; /* BSP: write register 14 value */5657 /* interrupt/polled mode configuration info */5859 uint_t mode; /* SIO_MODE_[INT | POLL] */60 char intVec; /* BSP: interrupt vector address */61 char intType; /* BSP: type of vector to supply from 8530 */62 uint_t channel; /* channel number (0 or 1) */63 } Z8530_CHAN;6465 typedef struct66 {67 Z8530_CHAN portA; /* port A device descriptor */68 Z8530_CHAN portB; /* port B device descriptor */69 } Z8530_DUSART;7071 /* channels */7273 #define SCC_CHANNEL_A 074 #define SCC_CHANNEL_B 17576 /* bit values for write register 0 */77 /* command register */7879 ....

G-9

templateSio.c

1 /* templateSio.c - template serial driver */23 /* Copyright 1984-1997 Wind River Systems, Inc. */45 /*6 modification history7 --------------------8 TODO - Remove the template modification history and begin a new history9 starting with version 01a and growing the history upward with10 each revision.1112 01i,23sep97,dat added TEMPLATE_REG_READ, TEMPLATE_REG_WRITE13 01h,10sep97,dat added opt declarations for SIO_HUP, SIO_OPEN14 01g,10aug97,dat fixed bugs in ver 01f15 01f,01jul97,db added ioctl commands used in modem control(SPR 7637,1037).16 01e,16apr97,dat fixed baud rate calc for SIO_BAUD_GET, SPR 8405.17 01d,06mar97,dat doc cleanup18 01c,16dec96,dat added templateOptSet() hardware options template19 01b,16oct96,dat added templateDevInit2(), and templateIntrMode variable.20 01a,01aug95,ms written.21 */2223 ....2425 #include “vxWorks.h”26 #include “sioLib.h”27 #include “intLib.h”28 #include “errno.h”29 #include “drv/sio/templateSio.h”3031 #define TEMPLATE_BAUD_MIN 7532 #define TEMPLATE_BAUD_MAX 384003334 /* Hardware abstraction macros */3536 #ifndef TEMPLATE_REG_READ37 # define TEMPLATE_REG_READ(pChan, reg, result) \38 ((result) = *(UCHAR *)(pChan->reg))39 #endif /*TEMPLATE_REG_READ*/4041 #ifndef TEMPLATE_REG_WRITE42 # define TEMPLATE_REG_WRITE(pChan, reg, data) \43 (*(UCHAR *)(pChan->reg) = data)44 #endif /*TEMPLATE_REG_WRITE*/4546 /* for backward compatibility */47

G-10

48 #ifndef SIO_HUP49 # define SIO_OPEN 0x100A /* open channel, raise DTR, RTS */50 # define SIO_HUP 0x100B /* hang-up, lower DTR, RTS */51 #endif5253 /* forward static declarations */5455 LOCAL int templateTxStartup (SIO_CHAN * pSioChan);56 LOCAL int templateCallbackInstall (SIO_CHAN *pSioChan, int callbackType ,57 STATUS (*callback)(), void *callbackArg);58 LOCAL int templatePollOutput (SIO_CHAN *pSioChan, char outChar);59 LOCAL int templatePollInput (SIO_CHAN *pSioChan, char *thisChar);60 LOCAL int templateIoctl (SIO_CHAN *pSioChan, int request, void *arg);61 LOCAL STATUSdummyCallback (void);6263 /* local variables */6465 LOCAL SIO_DRV_FUNCS templateSioDrvFuncs =66 {67 templateIoctl,68 templateTxStartup,69 templateCallbackInstall,70 templatePollInput,71 templatePollOutput72 };7374 LOCAL BOOL templateIntrMode = FALSE; /* interrupt mode allowed flag */7576 /

******************************************************************************77 *78 * templateDevInit - initialize a TEMPLATE_DUSART79 *80 * This routine initializes the driver81 * function pointers and then resets the chip in a quiescent state.82 * The BSP must have already initialized all the device addresses and the83 * baudFreq fields in the TEMPLATE_DUSART structure before passing it to84 * this routine.85 *86 * RETURNS: N/A87 */8889 void templateDevInit90 (91 TEMPLATE_DUSART * pDusart92 )93 {94 /* initialize each channel’s driver function pointers */9596 pDusart->portA.sio.pDrvFuncs = &templateSioDrvFuncs;97 pDusart->portB.sio.pDrvFuncs = &templateSioDrvFuncs;98

G-11

99 /* install dummy driver callbacks */100101 pDusart->portA.getTxChar = dummyCallback;102 pDusart->portA.putRcvChar = dummyCallback;103 pDusart->portB.getTxChar = dummyCallback;104 pDusart->portB.putRcvChar = dummyCallback;105106 /* reset the chip */107108 TEMPLATE_REG_WRITE(pDusart, masterCr,109 TEMPLATE_RESET_CHIP);110111 /* setting polled mode is one way to make the device quiet */112113 templateIoctl ((SIO_CHAN *)&pDusart->portA, SIO_MODE_SET,114 (void *)SIO_MODE_POLL);115 templateIoctl ((SIO_CHAN *)&pDusart->portB, SIO_MODE_SET,116 (void *)SIO_MODE_POLL);117 }118119 /

******************************************************************************120121 ....122123 /

*******************************************************************************

124 *125 * templatePollOutput - output a character in polled mode126 *127 * RETURNS: OK if a character arrived, EIO on device error, EAGAIN128 * if the output buffer if full. ENOSYS if the device is129 * interrupt-only.130 */131132 LOCAL int templatePollOutput133 (134 SIO_CHAN * pSioChan,135 char outChar136 )137 {138 TEMPLATE_CHAN * pChan = (TEMPLATE_CHAN *)pSioChan;139 UINT8 status;140141 /* is the transmitter ready to accept a character? */142143 TEMPLATE_REG_READ(pChan, sr, status);144 if ((status & TEMPLATE_TX_READY) == 0x00)145 return (EAGAIN);146147 /* write out the character */

G-12

148149 TEMPLATE_REG_WRITE(pChan, dr, outChar);150151 return (OK);152 }153154 /

******************************************************************************155 *156 * templatePollInput - poll the device for input157 *158 * RETURNS: OK if a character arrived, EIO on device error, EAGAIN159 * if the input buffer if empty, ENOSYS if the device is160 * interrupt-only.161 */162163 LOCAL int templatePollInput164 (165 SIO_CHAN * pSioChan,166 char * thisChar167 )168 {169 TEMPLATE_CHAN * pChan = (TEMPLATE_CHAN *)pSioChan;170 UINT8 status;171172 TEMPLATE_REG_READ(pChan, sr, status);173 if ((status & TEMPLATE_RX_AVAIL) == 0x00)174 return (EAGAIN); /* no input available at this time */175176 /* got a character */177178 TEMPLATE_REG_READ(pChan, dr, *thisChar);179180 return (OK);181 }182183 ....184185 /***************************************************************************186 *187 * templateIoctl - special device control188 *189 * This routine handles the IOCTL messages from the user. It supports commands190 * to get/set baud rate, mode(INT,POLL), hardware options(parity, number of191 * data bits) and modem control(RTS/CTS and DTR/DSR handshakes).192 * The ioctl commands SIO_HUP and SIO_OPEN are used to implement the HUPCL(hang193 * up on last close) function.194 *195 * RETURNS: OK on success, ENOSYS on unsupported request, EIO on failed196 * request.197 */198

G-13

199 LOCAL int templateIoctl200 (201 SIO_CHAN * pSioChan, /* device to control */202 int request, /* request code */203 void * someArg /* some argument */204 )205 {206 TEMPLATE_CHAN *pChan = (TEMPLATE_CHAN *) pSioChan;207 int oldlevel; /* current interrupt level mask */208 short baudConstant;209 int arg = (int)someArg;210 UINT8 temp;211212 switch (request)213 {214 case SIO_BAUD_SET:215216 /*217 * Set the baud rate. Return EIO for an invalid baud rate, or218 * OK on success.219 */220221 if (arg < TEMPLATE_BAUD_MIN || arg > TEMPLATE_BAUD_MAX)222 {223 return (EIO);224 }225226 /* Calculate the baud rate constant for the new baud rate */227228 baudConstant = pChan->baudFreq / arg / 16;229230 /* disable interrupts during chip access */231232 oldlevel= intLock ();233 TEMPLATE_REG_WRITE(pChan, br, (short)baudConstant);234 intUnlock (oldlevel);235236 return (OK);237238 case SIO_BAUD_GET:239240 /* Get the baud rate and return OK */241242 TEMPLATE_REG_READ(pChan, br, temp);243 *(int *)arg = pChan->baudFreq / temp / 16;244 return (OK);245246 case SIO_MODE_SET:247248 /*249 * Set the mode (e.g., to interrupt or polled). Return OK250 * or EIO for an unknown or unsupported mode.

G-14

251 */252253 return (templateModeSet (pChan, arg));254255 case SIO_MODE_GET:256257 /* Get the current mode and return OK. */258259 *(int *)arg = pChan->mode;260 return (OK);261262 case SIO_AVAIL_MODES_GET:263264 /* Get the available modes and return OK. */265266 *(int *)arg = SIO_MODE_INT | SIO_MODE_POLL;267 return (OK);268269 case SIO_HW_OPTS_SET:270271 /*272 * Optional command to set the hardware options (as defined273 * in sioLib.h).274 * Return OK, or ENOSYS if this command is not implemented.275 * Note: several hardware options are specified at once.276 * This routine should set as many as it can and then return277 * OK. The SIO_HW_OPTS_GET is used to find out which options278 * were actually set.279 */280281 return (templateOptSet (pChan, arg));282283 case SIO_HW_OPTS_GET:284285 /*286 * Optional command to get the hardware options (as defined287 * in sioLib.h). Return OK or ENOSYS if this command is not288 * implemented. Note: if this command is unimplemented, it289 * will be assumed that the driver options are CREAD | CS8290 * (e.g., eight data bits, one stop bit, no parity, ints enabled).291 */292293 *(int *)arg = pChan->options;294 return (OK);295296 case SIO_HUP:297298 /* check if hupcl option is enabled */299300 if (pChan->options & HUPCL)301 return (templateHup (pChan));302 return (OK);

G-15

303304 case SIO_OPEN:305306 /* check if hupcl option is enabled */307308 if (pChan->options & HUPCL)309 return (templateOpen (pChan));310 return (OK);311312 default:313 return (ENOSYS);314 }315 }

G-16

templateSio.h

1 /* templateSio.h - header file for template serial driver */23 /* Copyright 1984-1997 Wind River Systems, Inc. */45 /*6 modification history7 --------------------8 01d,01jul97,db added registers and defines for modem control.9 01c,24feb97,dat used SIO_CHAN as first structure element,10 instead of SIO_DRV_FUNCS *.11 01b,17dec96,dat added ‘options’to chan structure.12 01a,02aug95,ms written.13 */1415 #ifndef __INCtemplateSioh16 #define __INCtemplateSioh1718 #include “sioLib.h”1920 /* device and channel structures */2122 typedef struct23 {24 /* must be first */2526 SIO_CHAN sio; /* standard SIO_CHAN element */2728 /* callbacks */2930 STATUS (*getTxChar) ();31 STATUS (*putRcvChar) ();32 void * getTxArg;33 void * putRcvArg;3435 /* register addresses */3637 volatile char * cr; /* channel control register */38 volatile char * dr; /* channel data register */39 volatile char * sr; /* channel status register */40 volatile char * ms; /* channel modem status register */41 volatile char * mc; /* channel modem control register */42 volatile short * br; /* channel baud constant register */4344 /* misc */4546 int mode; /* current mode (interrupt or poll) */47 int baudFreq; /* input clock frequency */

G-17

48 int options; /* Hardware options */49 } TEMPLATE_CHAN;5051 typedef struct52 {53 TEMPLATE_CHAN portA; /* DUSRAT has two channels */54 TEMPLATE_CHAN portB;55 volatile char * masterCr; /* master control register */56 } TEMPLATE_DUSART;5758 /* definitions */5960 /* master control register definitions */6162 #define TEMPLATE_RESET_CHIP 0x16364 /* channel control register definitions */6566 #define TEMPLATE_RESET_TX 0x1 /* reset the transmitter */67 #define TEMPLATE_RESET_ERR 0x2 /* reset error condition */68 #define TEMPLATE_RESET_INT 0x4 /* acknoledge the interrupt */69 #define TEMPLATE_INT_ENABLE 0x8 /* enable interrupts */7071 /* channel status register definitions */7273 #define TEMPLATE_TX_READY 0x1 /* txmitter ready for another char */74 #define TEMPLATE_RX_AVAIL 0x2 /* character has arrived */7576 /* channel modem status register definitions */7778 #define TEMPLATE_MS_RTS 0x1 /* RTS signal asserted */79 #define TEMPLATE_MS_DTR 0x2 /* DTR signal asserted */8081 /* channel modem control register definitions */8283 #define TEMPLATE_MC_RTS 0x1 /* enable RTS */84 #define TEMPLATE_MC_DTR 0x2 /* enable DTR */8586 /* function prototypes */8788 #if defined(__STDC__)8990 extern void templateDevInit (TEMPLATE_DUSART *pDusart);91 extern void templateIntRcv (TEMPLATE_CHAN *pChan);92 extern void templateIntTx (TEMPLATE_CHAN *pChan);93 extern void templateIntErr (TEMPLATE_CHAN *pChan);9495 #else /* __STDC__ */9697 extern void templateDevInit ();98 extern void templateIntRcv ();99 extern void templateIntTx ();

G-18

100 extern void templateIntErr ();101102 #endif /* __STDC__ */103104 #endif /* __INCtemplateSioh */105


Appendix - H

Interrupt ControllerLibrary

H-2

ravenMpic .c

1 /* ravenMpic.c - Raven Interrupt Controller driver */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 /* Copyright 1996 Motorola, Inc. */5 #include “copyright_wrs.h”67 /*8 modification history9 --------------------10 01h,23oct97,dat, removed IACK loop from sysMpicIntHandler() (SPR 9389).11 mas12 01g,20jul97,dat implemented dave’s second revision + some code cleanup13 01f,11jun97,dmw MPIC handler cleanup.14 01e,06may97,dat added IBC updates from sl82565 controller.15 01d,30apr97,dat added WindView instrumentation SPR 843416 01c,29apr97,dat Fixed Motorola MR #62, moved MPIC_EOI17 01b,23apr97,mas merged with sl82565IntrCtl.c (SPR 8170).18 01a,11nov96,rhk created by Motorola.19 */2021 /*22 DESCRIPTION23 This module implements the Raven Mpic and the Winbond W83C553 PCI-ISA Bridge24 (PIB) drivers. (The W83C553 PIB was formerly known as the Motorola sl82565 ISA25 Bridge Controller (IBC).2627 These merged drivers provide support for initializing their respective devices28 and handling interrupts from them.29 */303132 /* includes */3334 #include “ravenMpic .h”353637 /* defines */3839 #defineMPIC_EOIsysPciWrite32(MPIC_ADDR(MPIC_CPU0_EOI_REG),0)40 #define IBC_INT_PENDING0x804142 /* globals */4344 IMPORT STATUS (*_func_intConnectRtn) (VOIDFUNCPTR *, VOIDFUNCPTR, int);45 IMPORT int (*_func_intEnableRtn) (int);46 IMPORT int (*_func_intDisableRtn) (int);47 IMPORT voidsysOutByte (ULONG, UCHAR);48 IMPORT UCHARsysInByte (ULONG);49 IMPORT voidsysPciRead32 (UINT32, UINT32 *);

H-3

50 IMPORT voidsysPciWrite32 (UINT32, UINT32);51 IMPORT STATUSexcIntConnect (VOIDFUNCPTR *, VOIDFUNCPTR);52 void sysIbcIntEnable (int);53 void sysIbcIntDisable (int);54 void sysIbcIntHandler (void);55 void sysMpicIntHandler (void);5657 IMPORT UINTsysVectorIRQ0; /* vector for IRQ0 */58 INT_HANDLER_DESC * sysIntTbl [256];/* system interrupt table */59 int tpr;6061 #ifdef INCLUDE_INSTRUMENTATION62 IMPORTint evtTimeStamp;63 #endif6465 /* forward declarations */6667 LOCAL int getMpicVecOffset (int);68 LOCAL STATUSsysMpicIntConnect (VOIDFUNCPTR * vector, VOIDFUNCPTR routine,69 int parameter);70 LOCAL intsysMpicIntEnable (int);71 LOCAL intsysMpicIntDisable (int);7273 LOCAL voidsysIbcMpicConnect (void);74 LOCAL voidsysIbcEndOfInt (int);75 LOCAL voidsysIbcIntLevelSet (int);7677 /* Mask values are the currently disabled sources */7879 LOCAL UINT8sysPicMask1 = 0xfb;/* all levels disabled */80 LOCAL UINT8sysPicMask2 = 0xff;8182 /* Level values are the interrupt level masks */8384 LOCAL UINT8sysPicLevel1;85 LOCAL UINT8sysPicLevel2;86 LOCAL UINT8sysPicLevelCur;/* current priority level, 0 to 16 */8788 /* level values by real priority */8990 LOCAL UCHAR sysPicPriMask1[17] = {0xFB,0xFA,0xF8,0xF8,0xF0,0xE0,0xC0,0x80,91 0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0x0};92 LOCAL UCHAR sysPicPriMask2[17] = {0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,93 0xFF,0xFE,0xFC,0xF8,0xF0,0xE0,0xC0,0x80,0x0};949596 /* Hardware access methods */9798 #ifndef IBC_BYTE_OUT99 # define IBC_BYTE_OUT(reg,data) \100 (sysOutByte (reg,data))101 #endif

H-4

102103 #ifndef IBC_BYTE_IN104 # define IBC_BYTE_IN(reg,pData) \105 (*pData = sysInByte(reg))106 #endif107108 #ifndef CPU_INT_LOCK109 # define CPU_INT_LOCK(x) \110 (*x = intLock ())111 #endif112113 #ifndef CPU_INT_UNLOCK114 # define CPU_INT_UNLOCK(data) \115 (intUnlock (data))116 #endif117118 /

*******************************************************************************

119 *120 * sysMpicInit - initialize the MPIC in the Raven121 *122 * This function initializes the Multi-Processor Interrupt Controller (MPIC)123 * contained in the Raven chip.124 *125 * It first initializes the system vector table, connects the MPIC interrupt126 * handler to the PPC external interrupt and attaches the local MPIC routines127 * for interrupt connecting, enabling and disabling to the corresponding system128 * routine pointers.129 *130 * It then initializes the MPIC registers, clears any pending MPIC interrupts,131 * enables interrupt handling by the MPIC and enables external ISA interrupts132 * (from the W83C553).133 *134 * RETURNS: OK always135 */136 STATUS sysMpicInit (void)137 {138 int i;139 UINT32timerReg;140 UINT32ipiReg;141 UINT32destReg;142 LOCAL_INT_DATAinit;143144145 /* Initialize the interrupt table */146147 for (i = 0; i < 256; i++)148 sysIntTbl[i] = NULL;149150 /* Connect the interrupt demultiplexer to the PowerPC external interrupt */151

H-5

152 excIntConnect ((VOIDFUNCPTR *) _EXC_OFF_INTR, sysMpicIntHandler);153154 /*155 * Set up the BSP specific routines156 * Attach the local routines to the vxWorks system calls157 */158159 _func_intConnectRtn = sysMpicIntConnect;160 _func_intEnableRtn = sysMpicIntEnable ;161 _func_intDisableRtn = sysMpicIntDisable ;162163 /* Initialize the MPIC */164165 /* generate a PCI IACK to clear any pending interrupts */166167 sysPciRead32( MPIC_ADDR(MPIC_CPU0_IACK_REG), &init.temp );168169 /* inhibit the timer and IPI regs. and clear the counter regs. */170171 timerReg = MPIC_TIMER0_BASE_CT_REG;172 ipiReg = MPIC_IPI0_VEC_PRI_REG;173 for (i=0; i<4; i++)174 {175 sysPciWrite32( MPIC_ADDR(ipiReg), IPI_INHIBIT );176 ipiReg += REG_OFFSET;177 sysPciWrite32( MPIC_ADDR(timerReg), TIMER_INHIBIT );178 timerReg += REG_OFFSET;179 sysPciWrite32( MPIC_ADDR(timerReg), TIMER_INHIBIT );180 timerReg += (REG_OFFSET * 3);181 }182183 /* setup the external source vector/priority registers */184185 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC0_VEC_PRI_REG), INIT_EXT_SRC0 );186 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC1_VEC_PRI_REG), INIT_EXT_SRC1 );187 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC2_VEC_PRI_REG), INIT_EXT_SRC2 );188 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC3_VEC_PRI_REG), INIT_EXT_SRC3 );189 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC4_VEC_PRI_REG), INIT_EXT_SRC4 );190 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC5_VEC_PRI_REG), INIT_EXT_SRC5 );191 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC6_VEC_PRI_REG), INIT_EXT_SRC6 );192 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC7_VEC_PRI_REG), INIT_EXT_SRC7 );193 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC8_VEC_PRI_REG), INIT_EXT_SRC8 );194 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC9_VEC_PRI_REG), INIT_EXT_SRC9 );195 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC10_VEC_PRI_REG), INIT_EXT_SRC10 );196 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC11_VEC_PRI_REG), INIT_EXT_SRC11 );197 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC12_VEC_PRI_REG), INIT_EXT_SRC12 );198 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC13_VEC_PRI_REG), INIT_EXT_SRC13 );199 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC14_VEC_PRI_REG), INIT_EXT_SRC14 );200 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC15_VEC_PRI_REG), INIT_EXT_SRC15 );201202 destReg = MPIC_EXT_SRC0_DEST_REG;203 for (i=0; i<=15; i++)

H-6

204 {205 sysPciWrite32( MPIC_ADDR(destReg), DESTINATION_CPU0 );206 destReg += (REG_OFFSET*2);207 }208209 /* setup the Ext source 0 reg (8259 input) for normal operation */210211 sysPciRead32( MPIC_ADDR(MPIC_EXT_SRC0_VEC_PRI_REG), &init.regVal );212 init.regVal |= PIB_INT_VEC;213 init.regVal &= (~INT_MASK_BIT);214 sysPciWrite32( MPIC_ADDR(MPIC_EXT_SRC0_VEC_PRI_REG), init.regVal );215216 /* enable interrupts for this processor */217218 sysPciWrite32( MPIC_ADDR(MPIC_CPU0_CUR_TASK_PRI_REG), 1 );219220 /* setup the MPIC to process the 8259 interrupts ( mixed mode ) */221222 sysPciWrite32( MPIC_ADDR(MPIC_GLOBAL_CONFIG_REG), SET_MIXED_MODE );223224 return (OK);225 }226227 /

******************************************************************************228 *229 * sysMpicIntConnect - connect an interrupt handler to the system vector table230 *231 * This function connects an interrupt handler to the system vector table.232 *233 * RETURNS: OK/ERROR.234 */235236 LOCAL STATUSsysMpicIntConnect237 (238 VOIDFUNCPTR * vector, /* interrupt vector to attach */239 VOIDFUNCPTR routine, /* routine to be called */240 int parameter /* parameter to be passed to routine */241 )242 {243 INT_HANDLER_DESC * newHandler;244 INT_HANDLER_DESC * currHandler;245 LOCAL_INT_DATA connect;246 static BOOLfirstTime = TRUE;247248 if (((int)vector < 0) || ((int)vector > 0xff)) /* Out of Range? */249 return (ERROR);250251 if (firstTime)252 {253254 /* connect the PIB to MPIC, before any other connections */

H-7

255256 firstTime = FALSE;257 sysIbcMpicConnect (); /* calls this rtn, recursively */258 }259260 /* create a new interrupt handler */261262 if ((newHandler = (INT_HANDLER_DESC *)calloc (1, sizeof

(INT_HANDLER_DESC)))263 == NULL)264 return (ERROR);265266 /* initialize the new handler */267268 newHandler->vec = routine;269 newHandler->arg = parameter;270 newHandler->next = NULL;271272 /* install the handler in the system interrupt table */273274 if (sysIntTbl[(int) vector] == NULL)275 sysIntTbl [(int ) vector] = newHandler; /* single int. handler case */276 else277 {278 currHandler = sysIntTbl[(int) vector]; /* multiple int. handler case */279 while (currHandler->next != NULL)280 {281 currHandler = currHandler->next;282 }283 currHandler->next = newHandler;284 }285286 /*287 * if the connect is for an MPIC interrupt,288 * then store the vector into the appropriate MPIC vector register289 */290291 connect.regAddr = getMpicVecOffset( (int)vector );292 if ( connect.regAddr > 0 )293 {294 /* read the vector register */295296 sysPciRead32( MPIC_ADDR(connect.regAddr), &connect.regVal );297298 /* store the interrupt vector number */299300 connect.regVal |= (int)vector;301302 /* write the contents of the vector register back */303304 sysPciWrite32( MPIC_ADDR(connect.regAddr), connect.regVal );305 }

H-8

306307 return (OK);308 }309310311 /

*******************************************************************************

312 *313 * sysMpicIntEnable - enable an Mpic interrupt level314 *315 * This routine enables a specified Mpic interrupt level.316 *317 * RETURNS: OK or ERROR if interrupt level not supported318 */319320 LOCAL int sysMpicIntEnable321 (322 int intLevel /* interrupt level to enable */323 )324 {325 LOCAL_INT_DATAenable;326327 /*328 * if the int. level is not for ISA or MPIC, then it is not supported.329 * If not supported, just return.330 */331332 if ((intLevel < 0) || (intLevel> ERR_INTERRUPT_BASE))333 return (ERROR);334335 /* If ISA interrupt level,call the IBC driver enable routine, */336337 if ( intLevel < EXT_INTERRUPT_BASE )338 sysIbcIntEnable( intLevel);339340 enable.regAddr = getMpicVecOffset( intLevel );341342 if ( enable.regAddr > 0 )343 {344 /* read the vector register */345346 sysPciRead32( MPIC_ADDR(enable.regAddr), &enable.regVal );347348 /* enable the interrupt */349350 enable.regVal &= (~INT_MASK_BIT);351352 /* write the contents of the vector register back */353354 sysPciWrite32( MPIC_ADDR(enable.regAddr), enable.regVal );355 }

H-9

356357 return (OK);358 }359360361 /

*******************************************************************************

362 *363 * sysMpicIntDisable - disable an Mpic interrupt level364 *365 * This routine disables a specified Mpic interrupt level.366 *367 * RETURNS: OK or ERROR if interrupt level not supported368 */369370 LOCAL int sysMpicIntDisable371 (372 int intLevel /* interrupt level to disable */373 )374 {375 LOCAL_INT_DATA disable;376377 /*378 * if the int. level is not for ISA or MPIC, then it is not supported.379 * If not supported, just return.380 */381382 if ((intLevel < 0) || (intLevel> ERR_INTERRUPT_BASE))383 return (ERROR);384385 /* If ISA interrupt level, call the IBC driver disable routine,*/386387 if ( intLevel < EXT_INTERRUPT_BASE )388 sysIbcIntDisable ( intLevel );389390 /* else, it is an MPIC interrupt level */391 else392 {393 /* get the vector reg. offset value */394 disable.regAddr = getMpicVecOffset( intLevel );395396 if ( disable.regAddr > 0 )397 {398 /* read the vector register */399400 sysPciRead32( MPIC_ADDR(disable.regAddr), &disable.regVal );401402 /* disable the interrupt */403404 disable.regVal |= INT_MASK_BIT;405

H-10

406 /* write the contents of the vector register back */407408 sysPciWrite32( MPIC_ADDR(disable.regAddr), disable.regVal );409 }410 }411412 return (OK);413 }414415416 /

******************************************************************************417 *418 * sysMpicIntHandler - handle an interrupt received at the Mpic419 *420 * This routine will process interrupts received from PCI or ISA devices as421 * these interrupts arrive via the MPIC. This routine supports MPIC interrupt422 * nesting.423 *424 * RETURNS: N/A425 */426427 void sysMpicIntHandler (void)428 {429 INT_HANDLER_DESC * currHandler;430 UINT32vecNum;431 int dontCare;432433 /* get the vector from the MPIC IACK reg. */434435 sysPciRead32 (MPIC_ADDR (MPIC_CPU0_IACK_REG), &vecNum);436 vecNum &= VECTOR_MASK;437438 /* Ignore spurious interrupts */439440 if (vecNum == 0xFF)441 {442 logMsg (“MPIC Spurious Interrupt!\n”, 0,0,0,0,0,0);443 return;444 }445446 /*447 * Allow maskable interrupts to the CPU. MPIC will hold off448 * lower and equal interrupts until MPIC_EOI is performed.449 */450451 CPU_INT_UNLOCK(_PPC_MSR_EE);452453 #ifdef INCLUDE_INSTRUMENTATION454 if (evtLogTIsOn)455 (* _func_evtLogT1_noTS) (EVENT_INT_ENT((int)vecNum),456 evtTimeStamp);

H-11

457 #endif458459 /* call the necessary interrupt handlers */460461 if ((currHandler = sysIntTbl [vecNum]) == NULL)462 {463 logMsg (“uninitialized MPIC interrupt %d\r\n”, vecNum, 0,0,0,0,0);464 }465 else466 {467 /* Call EACH respective chained interrupt handler */468469 while (currHandler != NULL)470 {471 currHandler->vec (currHandler->arg);472 currHandler = currHandler->next;473 }474 }475476 /* issue an end-of-interrupt to the MPIC */477478 MPIC_EOI;479480 CPU_INT_LOCK (&dontCare);481482 return;483 }484485486 /

*******************************************************************************

487 *488 * getMpicVecOffset - get the vector offset value of an MPIC register489 *490 * This routine calculates the appropriate MPIC register offset based on the491 * specified MPIC interrupt level.492 *493 * RETURNS: MPIC register offset or zero if not a supported level.494 */495496 LOCAL int getMpicVecOffset497 (498 int intLevel499 )500 {501 int offset = 0;502503 /* check for external interrupt level */504505 if ((intLevel >= EXT_INTERRUPT_BASE) && (intLevel < TIMER_INTERRUPT_BASE))506 {

H-12

507 offset = intLevel - EXT_INTERRUPT_BASE;508 offset = MPIC_EXT_SRC0_VEC_PRI_REG + ( offset * REG_OFFSET * 2 );509 }510511 /* check for a timer interrupt level */512513 if ((intLevel >= TIMER_INTERRUPT_BASE) && (intLevel < IPI_INTERRUPT_BASE))514 {515 offset = intLevel - TIMER_INTERRUPT_BASE;516 offset = MPIC_TIMER0_VEC_PRI_REG + ( offset * REG_OFFSET * 4 );517 }518519 /* check for an IPI interrupt level */520521 if ((intLevel >= IPI_INTERRUPT_BASE) && (intLevel < ERR_INTERRUPT_BASE))522 {523 offset = intLevel - IPI_INTERRUPT_BASE;524 offset = MPIC_IPI0_VEC_PRI_REG + ( offset * REG_OFFSET );525 }526 /* check for the Raven internal error interrupt */527528 if (intLevel == ERR_INTERRUPT_BASE )529 {530 offset = MPIC_ERR_VEC_PRI_REG;531 }532533 return (offset);534 }535536537 /

*******************************************************************************

538 *539 * sysIbcInit - Initialize the IBC540 *541 * This routine initializes the non-PCI Header configuration registers of the542 * IBC within the W83C553 PIB.543 *544 * RETURNS: OK always545 */546547 STATUS sysIbcInit (void)548 {549 UCHARintVec;550551552 /* Initialize the Interrupt Controller #1 */553554 IBC_BYTE_OUT (PIC_port1 (PIC1_BASE_ADR),0x11); /* ICW1 */555 IBC_BYTE_OUT (PIC_port2 (PIC1_BASE_ADR),sysVectorIRQ0); /* ICW2 */556 IBC_BYTE_OUT (PIC_port2 (PIC1_BASE_ADR),0x04);/* ICW3 */

H-13

557 IBC_BYTE_OUT (PIC_port2 (PIC1_BASE_ADR),0x01);/* ICW4 */558559 /*560 *Mask interrupts IRQ 0, 1, and 3-7 by writing to OCW1 register561 *IRQ 2 is the cascade input562 */563564 IBC_BYTE_OUT (PIC_IMASK (PIC1_BASE_ADR),0xfb);565566 /* Make IRQ 5 level sensitive */567568 IBC_BYTE_OUT (SL82565_INT1_ELC, 0x20);569570 /* Initialize the Interrupt Controller #2 */571572 IBC_BYTE_OUT (PIC_port1 (PIC2_BASE_ADR),0x11);/* ICW1 */573 IBC_BYTE_OUT (PIC_port2 (PIC2_BASE_ADR),sysVectorIRQ0+8); /* ICW2 */574 IBC_BYTE_OUT (PIC_port2 (PIC2_BASE_ADR),0x02);/* ICW3 */575 IBC_BYTE_OUT (PIC_port2 (PIC2_BASE_ADR),0x01);/* ICW4 */576577 /* Mask interrupts IRQ 8-15 by writing to OCW1 register */578579 IBC_BYTE_OUT (PIC_IMASK (PIC2_BASE_ADR),0xff);580581 /* Make IRQ 15, 14, 11, 10, and 9 level sensitive */582583 IBC_BYTE_OUT (SL82565_INT2_ELC, 0x80 | 0x40 | 0x08 | 0x04 | 0x02);584585 /* Permanently turn off ISA refresh by never completing init steps */586587 IBC_BYTE_OUT (SL82565_TMR1_CMOD, 0x74);588589 /*Perform the PCI Interrupt Ack cycle */590591 IBC_BYTE_IN (RAVEN_BASE_ADRS + 0x30, &intVec);592593 /* Perform the end of interrupt procedure */594595 sysIbcEndOfInt (15);596597 sysIbcIntLevelSet (16);598599 return (OK);600 }601602603 /

*******************************************************************************

604 *605 * sysIbcIntEnable - enable a IBC interrupt level606 *

H-14

607 * This routine enables a specified IBC interrupt level.608 *609 * RETURNS: N/A610 */611612 void sysIbcIntEnable613 (614 int intNum /* interrupt level to enable */615 )616 {617 if (intNum < 8)618 {619 sysPicMask1 &= ~(1 << intNum);620 IBC_BYTE_OUT (PIC_IMASK (PIC1_BASE_ADR), sysPicMask1 | sysPicLevel1);621 }622 else623 {624 sysPicMask2 &= ~(1 << (intNum - 8));625 IBC_BYTE_OUT (PIC_IMASK (PIC2_BASE_ADR), sysPicMask2 | sysPicLevel2);626 }627 }628629630 /

*******************************************************************************

631 *632 * sysIbcIntDisable - disable a IBC interrupt level633 *634 * This routine disables a specified IBC interrupt level.635 *636 * RETURNS: N/A637 */638639 void sysIbcIntDisable640 (641 int intNum /* interrupt level to disable */642 )643 {644 if (intNum < 8)645 {646 sysPicMask1 |= (1 << intNum);647 IBC_BYTE_OUT (PIC_IMASK (PIC1_BASE_ADR), sysPicMask1 | sysPicLevel1 );648 }649 else650 {651 sysPicMask2 |= (1 << (intNum - 8));652 IBC_BYTE_OUT (PIC_IMASK (PIC2_BASE_ADR), sysPicMask2 | sysPicLevel2);653 }654 }655

H-15

656 /******************************************************************************

657 *658 * sysIbcIntHandler - handler of the sl82565 IBC interrupt.659 *660 * This routine handles interrupts originating from the W83C553 PIB ISA Bus661 * Controller (IBC). This device implements the functional equivalent of two662 * cascaded 8259 PICs.663 *664 * This routine is entered with CPU external interrupts enabled.665 *666 * Because the ISA bus is only accessible via the PCI bus, this driver first667 * initiates a PCI interrupt acknowledge cycle to read the interrupt number668 * (vector) coming from the IBC.669 *670 * This routine then processes the interrupt by calling all interrupt service671 * routines chained to the vector.672 *673 * Finally, this routine re-arms the interrupt at the IBC by performing a674 * IBC EOI.675 *676 * RETURNS: N/A677 */678679 void sysIbcIntHandler (void)680 {681 UCHARintNum;682 INT_HANDLER_DESC *currHandler;683684 IBC_BYTE_IN (RAVEN_BASE_ADRS + 0x30, &intNum);685686 /* Check for cascade from IBC2. If so get IBC2 interrupt. */687688 if (intNum == 0x02)689 {690 IBC_BYTE_IN (PIC_IACK (PIC2_BASE_ADR), &intNum);691 if (intNum & IBC_INT_PENDING)692 {693 intNum &= 0x7;694 intNum += 8;695 }696 else697 {698 logMsg (“non-pending IBC interrupt level %x\r\n”, intNum,699 0,0,0,0,0);700 sysIbcEndOfInt (intNum);701 return;702 }703 }704705 if ((currHandler = sysIntTbl [intNum]) == NULL)706 {

H-16

707 logMsg (“uninitialized IBC interrupt level %x\r\n”, intNum, 0,0,0,0,0);708 }709 else710 {711 /* Call EACH respective chained interrupt handler */712713 while (currHandler != NULL)714 {715 currHandler->vec (currHandler->arg);716 currHandler = currHandler->next;717 }718 }719720 /* Re-arm (enable) the interrupt on the IBC */721722 sysIbcEndOfInt (intNum);723 }724725 /

*******************************************************************************

726 *727 * sysIbcEndOfInt - send EOI (end of interrupt) signal.728 *729 * This routine is called at the end of the interrupt handler to730 * send a non-specific end of interrupt (EOI) signal.731 *732 * The second PIC is acked only if the interrupt came from that PIC.733 * The first PIC is always acked.734 */735736 LOCAL void sysIbcEndOfInt737 (738 int intNum739 )740 {741 if (intNum > 7)742 {743 IBC_BYTE_OUT (PIC_IACK (PIC2_BASE_ADR), 0x20);744 }745 IBC_BYTE_OUT (PIC_IACK (PIC1_BASE_ADR), 0x20);746 }747748 /

*******************************************************************************

749 *750 * sysIbcIntLevelSet - set the interrupt priority level751 *752 * This routine masks interrupts with real priority equal to or lower than753 * <intNum>. The special754 * value 16 indicates all interrupts are enabled. Individual interrupt

H-17

755 * numbers have to be specifically enabled by sysIbcIntEnable () before they756 * are ever enabled by setting the interrupt level value.757 *758 * Note because of the IBM cascade scheme, the actual priority order for759 * interrupt numbers is (high to low) 0, 1, 8, 9, 10, 11, 12, 13, 14, 15,760 * 3, 4, 5, 6, 7, 16 (all enabled)761 *762 * INTERNAL: It is possible that we need to determine if we are raising763 * or lowering our priority level. It may be that the order of loading the764 * two mask registers is dependent upon raising or lowering the priority.765 *766 * RETURNS: N/A767 */768769 void sysIbcIntLevelSet770 (771 int intNum/* interrupt level to implement */772 )773 {774 if (intNum > 16)775 intNum = 16;776777 sysPicLevelCur = intNum;778779 if (sysPicLevel2 != sysPicPriMask2[intNum])780 {781 sysPicLevel2 = sysPicPriMask2[intNum];782 IBC_BYTE_OUT (PIC_IMASK (PIC2_BASE_ADR), sysPicMask2 | sysPicLevel2);783 }784785 if (sysPicLevel1 != sysPicPriMask1[intNum])786 {787 sysPicLevel1 = sysPicPriMask1[intNum];788 IBC_BYTE_OUT (PIC_IMASK (PIC1_BASE_ADR), sysPicMask1 | sysPicLevel1);789 }790 }791792 /

*******************************************************************************

793 *794 * sysIbcMpicConnect - routine to connect IBC interrupts to MPIC795 *796 * This function is called from sysHwInit2 and sets the IBC interrupt797 * handler into the MPIC interrupt vector table.798 *799 * RETURNS: N/A800 */801802 LOCAL void sysIbcMpicConnect (void)803 {804 intConnect (INUM_TO_IVEC(PIB_INT_VEC), sysIbcIntHandler, 0);

H-18

805 intEnable (PIB_INT_LVL);806 }

H-19

ravenMpic .h

1 /* ravenMpic.h - Raven MPIC register definitions */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 /* Copyright 1996 Motorola, Inc. */56 /*7 modification history8 --------------------9 01c,29apr97,dat replaced pci.h with pciIomapLib.h10 01b,23apr97,mas merged with sl82565IntrCtl.h (SPR 8170).11 01a,30oct96,rhk created by Motorola.12 */13 14 /*15 Description:1617 Contains structure typedefs and device-specific defines for the Motorola MPIC18 and Winbond PIB chips.19 */202122 #ifndefINCravenMpich23 #defineINCravenMpich2425 #ifdef __cplusplus26 extern “C” {27 #endif2829 /* includes */3031 #include “drv/pci/pciIomapLib.h”3233 /* structures */34 typedef struct intHandlerDesc /* interrupt handler desciption */35 {36 VOIDFUNCPTR vec; /* interrupt vector */37 int arg; /* interrupt handler argument */38 struct intHandlerDesc * next; /* next interrupt handler & argument */39 } INT_HANDLER_DESC;4041 typedef struct localIntData42 {43 UCHARmpicVec;44 UCHARibcVec;45 INT8 cpuCtrlReg;46 int temp;47 UINT32regAddr;48 UINT32regVal;49 } LOCAL_INT_DATA;

H-20

5051 /* macros */5253 #define MPIC_ADDR(reg) (MPIC_BASE_ADRS + reg)5455 /*56 * Raven MPIC bit masks and settings for the registers57 */5859 #define SET_MIXED_MODE0x2000000060 #define TIMER_INHIBIT0x8000000061 #define IPI_INHIBIT0x8000000062 #define INT_MASK_BIT0x8000000063 #define RESET_CNTRLR0x8000000064 #define HIGH_POLARITY0x0080000065 #define LEVEL_SENSE0x0040000066 #define VECTOR_MASK0x000000ff67 #define DESTINATION_CPU00x000000016869 #define PRIORITY_MASK0x000f000070 #define PRIORITY_LVL00x0000000071 #define PRIORITY_LVL10x0001000072 #define PRIORITY_LVL2 0x0002000073 #define PRIORITY_LVL3 0x0003000074 #define PRIORITY_LVL4 0x0004000075 #define PRIORITY_LVL5 0x0005000076 #define PRIORITY_LVL6 0x0006000077 #define PRIORITY_LVL7 0x0007000078 #define PRIORITY_LVL8 0x0008000079 #define PRIORITY_LVL9 0x0009000080 #define PRIORITY_LVL10 0x000a000081 #define PRIORITY_LVL11 0x000b000082 #define PRIORITY_LVL12 0x000c000083 #define PRIORITY_LVL13 0x000d000084 #define PRIORITY_LVL14 0x000e000085 #define PRIORITY_LVL15 0x000f00008687 /* miscellaneous defines */8889 #define REG_OFFSET0x109091 /*92 * Raven MPIC register definitions93 */9495 /* feature reporting register */96 #define MPIC_FEATURE_REG0x010009798 /* global configuration register */99 #define MPIC_GLOBAL_CONFIG_REG0x01020100101 /* vendor identification register */

H-21

102 #define MPIC_VENDOR_ID_REG0x01080103104 /* processor init register */105 #define MPIC_PROCESSOR_INIT_REG 0x01090106107 /* IPI vector/priority registers 0-3 */108 #define MPIC_IPI0_VEC_PRI_REG0x010a0109 #define MPIC_IPI1_VEC_PRI_REG 0x010b0110 #define MPIC_IPI2_VEC_PRI_REG 0x010c0111 #define MPIC_IPI3_VEC_PRI_REG 0x010d0112113 /* spurious vector register */114 #define MPIC_SPUR_VEC_REG0x010e0115116 /* timer frequency register */117 #define MPIC_TIMER_FREQ_REG0x010f0118119 /*120 * timer registers 0-3121 * - current count register122 * - base count register123 * - vector/priority register124 * - destination register125 */126 #define MPIC_TIMER0_CUR_CNT_REG 0x01100127 #define MPIC_TIMER0_BASE_CT_REG 0x01110128 #define MPIC_TIMER0_VEC_PRI_REG 0x01120129 #define MPIC_TIMER0_DEST_REG0x01130130131 #define MPIC_TIMER1_CUR_CNT_REG 0x01140132 #define MPIC_TIMER1_BASE_CT_REG 0x01150133 #define MPIC_TIMER1_VEC_PRI_REG 0x01160134 #define MPIC_TIMER1_DEST_REG 0x01170135136 #define MPIC_TIMER2_CUR_CNT_REG 0x01180137 #define MPIC_TIMER2_BASE_CT_REG 0x01190138 #define MPIC_TIMER2_VEC_PRI_REG 0x011a0139 #define MPIC_TIMER2_DEST_REG 0x011b0140141 #define MPIC_TIMER3_CUR_CNT_REG 0x011c0142 #define MPIC_TIMER3_BASE_CT_REG 0x011d0143 #define MPIC_TIMER3_VEC_PRI_REG 0x011e0144 #define MPIC_TIMER3_DEST_REG 0x011f0145146 /*147 * external source registers 0-15148 * - vector/priority register149 * - destination register150 */151 #define MPIC_EXT_SRC0_VEC_PRI_REG 0x10000152 #define MPIC_EXT_SRC0_DEST_REG 0x10010153

H-22

154 #define MPIC_EXT_SRC1_VEC_PRI_REG 0x10020155 #define MPIC_EXT_SRC1_DEST_REG 0x10030156157 #define MPIC_EXT_SRC2_VEC_PRI_REG 0x10040158 #define MPIC_EXT_SRC2_DEST_REG 0x10050159160 #define MPIC_EXT_SRC3_VEC_PRI_REG 0x10060161 #define MPIC_EXT_SRC3_DEST_REG 0x10070162163 #define MPIC_EXT_SRC4_VEC_PRI_REG 0x10080164 #define MPIC_EXT_SRC4_DEST_REG 0x10090165166 #define MPIC_EXT_SRC5_VEC_PRI_REG 0x100a0167 #define MPIC_EXT_SRC5_DEST_REG 0x100b0168169 #define MPIC_EXT_SRC6_VEC_PRI_REG 0x100c0170 #define MPIC_EXT_SRC6_DEST_REG 0x100d0171172 #define MPIC_EXT_SRC7_VEC_PRI_REG 0x100e0173 #define MPIC_EXT_SRC7_DEST_REG 0x100f0174175 #define MPIC_EXT_SRC8_VEC_PRI_REG 0x10100176 #define MPIC_EXT_SRC8_DEST_REG 0x10110177178 #define MPIC_EXT_SRC9_VEC_PRI_REG 0x10120179 #define MPIC_EXT_SRC9_DEST_REG 0x10130180181 #define MPIC_EXT_SRC10_VEC_PRI_REG 0x10140182 #define MPIC_EXT_SRC10_DEST_REG 0x10150183184 #define MPIC_EXT_SRC11_VEC_PRI_REG 0x10160185 #define MPIC_EXT_SRC11_DEST_REG 0x10170186187 #define MPIC_EXT_SRC12_VEC_PRI_REG 0x10180188 #define MPIC_EXT_SRC12_DEST_REG 0x10190189190 #define MPIC_EXT_SRC13_VEC_PRI_REG 0x101a0191 #define MPIC_EXT_SRC13_DEST_REG 0x101b0192193 #define MPIC_EXT_SRC14_VEC_PRI_REG 0x101c0194 #define MPIC_EXT_SRC14_DEST_REG 0x101d0195196 #define MPIC_EXT_SRC15_VEC_PRI_REG 0x101e0197 #define MPIC_EXT_SRC15_DEST_REG 0x101f0198199 /* raven detected error registers */200 #define MPIC_ERR_VEC_PRI_REG0x10200201 #define MPIC_ERR_DEST_REG0x10210202203 /* interprocessor interrupt dispatch registers for cpu 0 */204 #define MPIC_CPU0_IPI0_DISP_REG 0x20040205 #define MPIC_CPU0_IPI1_DISP_REG 0x20050

H-23

206 #define MPIC_CPU0_IPI2_DISP_REG 0x20060207 #define MPIC_CPU0_IPI3_DISP_REG 0x20070208 /* interrupt task priority register for cpu 0 */209 #define MPIC_CPU0_CUR_TASK_PRI_REG 0x20080210211 /* cpu 0 interrupt acknowledge register */212 #define MPIC_CPU0_IACK_REG0x200a0213 /* cpu 0 end-of-interrupt register */214 #define MPIC_CPU0_EOI_REG0x200b0215216 /* interprocessor interrupt dispatch registers for cpu 1 */217 #define MPIC_CPU1_IPI0_DISP_REG 0x21040218 #define MPIC_CPU1_IPI1_DISP_REG 0x21050219 #define MPIC_CPU1_IPI2_DISP_REG 0x21060220 #define MPIC_CPU1_IPI3_DISP_REG 0x21070221 /* interrupt task priority register for cpu 1 */222 #define MPIC_CPU1_CUR_TASK_PRI_REG 0x21080223224 /* cpu 1 interrupt acknowledge register */225 #define MPIC_CPU1_IACK_REG 0x210a0226 /* cpu 1 end-of-interrupt register */227 #define MPIC_CPU1_EOI_REG 0x210b0228229230231 /*232 * IBC Extensions to Standard PCI Config Header register offsets233 */234 #define PCI_CFG_IBC_INTR_ROUTE0x44235236237 /* default definitions */238239 #defineCAST240241 #define PIC_ADRS(base,reg) (CAST (base+(reg*PIC_REG_ADDR_INTERVAL)))242243 /* register definitions */244245 #define PIC_port1(base)PIC_ADRS(base,0x00)/* port 1. */246 #define PIC_port2(base)PIC_ADRS(base,0x01)/* port 2. */247248 /* alias */249250 #define PIC_IMASK(base)PIC_port2(base)/* Interrupt mask. */251 #define PIC_IACK(base)PIC_port1(base)/* Interrupt acknowledge. */252253 #define PIC_ISR_MASK(base) PIC_port1(base)/* in-service register mask */254 #define PIC_IRR_MASK(base) PIC_port1(base) /* interrupt request reg */255256 /*257 * Non-PCI Config Header register definitions

H-24

258 *259 * These are mapped to ISA I/O Space260 */261 #define SL82565_INT1_CTRL (CPU_PCI_ISA_IO_ADRS + 0x0020) /* PIC1 */262 #define SL82565_INT1_MASK (CPU_PCI_ISA_IO_ADRS + 0x0021)263 #define SL82565_INT1_ELC (CPU_PCI_ISA_IO_ADRS + 0x04d0)264 #define SL82565_INT2_CTRL (CPU_PCI_ISA_IO_ADRS + 0x00a0) /* PIC2 */265 #define SL82565_INT2_MASK (CPU_PCI_ISA_IO_ADRS + 0x00a1)266 #define SL82565_INT2_ELC (CPU_PCI_ISA_IO_ADRS + 0x04d1)267 #define SL82565_TMR1_CNT0 (CPU_PCI_ISA_IO_ADRS + 0x0040)268 #define SL82565_TMR1_CNT1 (CPU_PCI_ISA_IO_ADRS + 0x0041)269 #define SL82565_TMR1_CNT2 (CPU_PCI_ISA_IO_ADRS + 0x0042)270 #define SL82565_TMR1_CMOD (CPU_PCI_ISA_IO_ADRS + 0x0043)271 #define SL82565_RST_IRQ12 (CPU_PCI_ISA_IO_ADRS + 0x0060)272 #define SL82565_NMI_SCTRL (CPU_PCI_ISA_IO_ADRS + 0x0061)273 #define SL82565_PCOP (CPU_PCI_ISA_IO_ADRS + 0x0c04)274 #define SL82565_TMCP (CPU_PCI_ISA_IO_ADRS + 0x0c01)275276 /* programmable interrupt controller (PIC) */277278 #define PIC1_BASE_ADR SL82565_INT1_CTRL279 #define PIC2_BASE_ADR SL82565_INT2_CTRL280281282 #ifdef __cplusplus283 }284 #endif285286 #endif/* INCravenMpich */287


Appendix - I

Timer Library

I-2

ppcDecTimer.c

1 /* ppcDecTimer.c - PowerPC decrementer timer library */23 /* Copyright 1984-1997 Wind River Systems, Inc. */4 #include “copyright_wrs.h”56 /*7 modification history8 --------------------9 01n,04nov96,tam renamed MEMORY_BUS_SPEED to DEC_CLOCK_FREQ, BUS_CLK_TO_INC10 to DEC_CLK_TO_INC and DEFAULT_BUS_SPEED to DEFAULT_DEC_CLK_FREQ11 (spr #7423).12 01m,29oct96,wlf doc: cleanup.13 01l,31jul96,dat added PPC_TMR_RATE_SET_ADJUST14 01k,22jul96,tam cleanup. added timestamp support. Changed CPU_SPEED macro to15 MEMORY_BUS_SPEED.16 01j,17jun96,tpr optimized sysClkInt() assembly code.17 01i,14may96,tam fixed drift in sysClkInt. Changed DEFAULT_CPU_SPEED to18 33333333 (33.33 Mhz)19 01h,11mar96,ms fixed roundoff in sysClkInt.20 01g,12feb96,tpr reworked.21 01f,23oct95,kvk cleanup.22 01e,22may95,caf added conditional compile for PowerPC 601.23 01d,02may95,caf cleanup.24 01c,27apr95,caf removed vxDecEnable() and PPC60x_TIMER_INT_VECTOR,25 changed name to ppcDecTimer.c.26 01b,25jan95,vin cleanup.27 01a,20jan95,kvk written.28 */2930 /*31 DESCRIPTION32 This library provides PowerPC decrementer timer routines.33 This library handles both the system clock and the auxiliary clock plus34 and timestamp functions. However, the auxiliary clock functions have no35 effect.3637 The macro DEC_CLOCK_FREQ (frequency of the decrementer input clock) should be38 defined before using this module. The macro DEC_CLK_TO_INC (ratio between the39 number of decrementer input clock cycles and one counter increment) can be40 redefined prior to #including this file into sysLib.c.41 The macros SYS_CLK_RATE_MIN and SYS_CLK_RATE_MAX must be defined to provide42 parameter checking for sysClkRateSet().4344 To include the timestamp timer facility, the macro INCLUDE_TIMESTAMP must be45 defined. Note that changing the system clock rate will affect the timestamp46 timer period, which can be read by calling sysTimestampPeriod().4748 If dynamic bus clock speed calculation is needed, the BSP can define the49 macro PPC_TMR_RATE_SET_ADJUST to be a call to the needed routine.

I-3

50 This macro, if defined, will be executed during each call to sysClkRateSet().51 PPC_TMR_RATE_SET_ADJUST is usually not defined.5253 e.g. Assuming sysClkRateAdjust can compute a correct value54 for sysDecClkFrequency.5556 #define PPC_TMR_RATE_SET_ADJUST \57 sysClkRateAdjust (&sysDecClkFrequency)58596061 INCLUDE FILES: ppcDecTimer.h6263 SEE ALSO:64 .pG “Configuration”65 */6667 /* includes */6869 #include “arch/ppc/vxPpcLib.h”70 #include “drv/timer/ppcDecTimer.h”71 #include “drv/timer/timestampDev.h”7273 /* local defines */7475 #ifndef DEC_CLK_TO_INC76 #define DEC_CLK_TO_INC 4 /* # bus clks per increment */77 #endif7879 #define DEFAULT_DEC_CLK_FREQ 33333333 /* 33.33 Mhz default */8081 #if (CPU == PPC601)82 # define DEC_SHIFT 7 /* 7 low-order bits aren’t used */83 #else84 # define DEC_SHIFT 085 #endif /* CPU == PPC601 */8687 /* extern declarations */8889 IMPORT STATUS excIntConnect (VOIDFUNCPTR *, VOIDFUNCPTR);9091 /* Locals */92 LOCAL int sysClkTicksPerSecond = 60; /* default 60 ticks/second */93 LOCAL FUNCPTR sysClkRoutine = NULL;94 LOCAL int sysClkArg = NULL;95 LOCAL BOOL sysClkConnectFirstTime = TRUE;96 LOCAL int decCountVal = 10000000; /* default dec value */97 LOCAL BOOL sysClkRunning = FALSE;98 LOCAL int sysDecClkFrequency = DEFAULT_DEC_CLK_FREQ/DEC_CLK_TO_INC;99100 #ifdef INCLUDE_TIMESTAMP101 LOCAL BOOL sysTimestampRunning = FALSE; /* timestamp running flag */

I-4

102 #endif /* INCLUDE_TIMESTAMP */103104 /

*******************************************************************************

105 *106 * sysClkInt - clock interrupt handler107 *108 * This routine handles the clock interrupt on the PowerPC architecture. It is109 * attached to the decrementer vector by the routine sysClkConnect().110 *111 * RETURNS : N/A112 */113114 LOCAL void sysClkInt (void)115 {116 /*117 * The PowerPC decrementer doesn’t reload the value by itself. The reload118 * need to be performed in this handler. The reload value should be119 * adjusted each time because the time spent between the exception120 * generation and the moment the register is reloaded changes.121 * By reading the decrementer we obtain the time spent between the122 * two events and can adjust the value to reload. This is done in assembly123 * language in order to minimize time spent between reading and writing124 * to the decrementer register in order to maximize system clock accuracy.125 */126127 __asm__ (“128 mfdec 3129 sysClkIntLoop:130 add. 3, %0, 3131 ble sysClkIntLoop /* check if we missed tick(s) */132 mtdec 3”133 : /* no output operands */134 : “r” (decCountVal) /* input operand, %0 = decCountVal */135 : “3”, “cc” /* side-effects: r3 clobbered, ‘condition code’is clobbered */136 );137138 /* execute the system clock routine */139140 if (sysClkRunning && (sysClkRoutine != NULL))141 (*(FUNCPTR) sysClkRoutine) (sysClkArg);142143 }144145 /

*******************************************************************************

146 *147 * sysClkConnect - connect a routine to the system clock interrupt148 *149 * This routine specifies the interrupt service routine to be called at each

I-5

150 * clock interrupt. Normally, it is called from usrRoot() in usrConfig.c to151 * connect usrClock() to the system clock interrupt.152 *153 * RETURNS: OK, or ERROR if the routine cannot be connected to the interrupt.154 *155 * SEE ALSO: intConnect(), usrClock(), sysClkEnable()156 */157158 STATUS sysClkConnect159 (160 FUNCPTR routine, /* routine to connect */161 int arg /* argument for the routine */162 )163 {164165 if (sysClkConnectFirstTime)166 {167 sysHwInit2();168 sysClkConnectFirstTime = FALSE;169 }170171 #ifdef DEC_CLOCK_FREQ172 sysDecClkFrequency = DEC_CLOCK_FREQ / DEC_CLK_TO_INC;173 #endif /* DEC_CLOCK_FREQ */174175 /* connect the routine to the decrementer exception */176177 excIntConnect ((VOIDFUNCPTR *) _EXC_OFF_DECR, (VOIDFUNCPTR) sysClkInt);178179 sysClkRoutine = routine;180 sysClkArg = arg;181182 return (OK);183 }184185 /

******************************************************************************186 *187 * sysClkEnable - turn on system clock interrupts188 *189 * This routine enables system clock interrupts.190 *191 * RETURNS: N/A192 *193 * SEE ALSO: sysClkConnect(), sysClkDisable(), sysClkRateSet()194 */195196 void sysClkEnable (void)197 {198 if (!sysClkRunning)199 {200 sysClkRunning = TRUE;

I-6

201 vxDecSet (decCountVal);202 }203 }204205 /

******************************************************************************206 *207 * sysClkDisable - turn off system clock interrupts208 *209 * This routine disables system clock interrupts.210 *211 * RETURNS: N/A212 *213 * SEE ALSO: sysClkEnable()214 */215216 void sysClkDisable (void)217 {218 if (sysClkRunning)219 sysClkRunning = FALSE;220 }221222 /

******************************************************************************223 *224 * sysClkRateGet - get the system clock rate225 *226 * This routine returns the system clock rate.227 *228 * RETURNS: The number of ticks per second of the system clock.229 *230 * SEE ALSO: sysClkEnable(), sysClkRateSet()231 */232233 int sysClkRateGet (void)234 {235 return (sysClkTicksPerSecond);236 }237238 /

******************************************************************************239 *240 * sysClkRateSet - set the system clock rate241 *242 * This routine sets the interrupt rate of the system clock. It is called243 * by usrRoot() in usrConfig.c.244 *245 * RETURNS: OK, or ERROR if the tick rate is invalid or the timer cannot be set.246 *247 * SEE ALSO: sysClkEnable(), sysClkRateGet()248 */249

I-7

250 STATUS sysClkRateSet251 (252 int ticksPerSecond /* number of clock interrupts per second */253 )254 {255 if (ticksPerSecond < SYS_CLK_RATE_MIN || ticksPerSecond > SYS_CLK_RATE_MAX)256 return (ERROR);257258 /* save the clock speed */259260 sysClkTicksPerSecond = ticksPerSecond;261262 /* Calibrate the clock, if needed. */263264 #ifdef PPC_TMR_RATE_SET_ADJUST265 PPC_TMR_RATE_SET_ADJUST;266 #endif267268 /*269 * compute the value to load in the decrementer. The new value will be270 * load in the decrementer after the end of the current period271 */272273 decCountVal = sysDecClkFrequency / ticksPerSecond;274275 return (OK);276 }277278279 #ifdef INCLUDE_TIMESTAMP280281 ....


Appendix - J

bootConfig.c - CoreFunctions

J-2

usrRoot()

1 * usrRoot - user-defined root task2 *3 * The root task performs any initialization that should be done4 * subsequent to the kernel initialization.5 *6 * It initializes the I/O system, install drivers, create devices,7 * sets up the network, etc., as necessary for the particular configuration.8 * It may also create the system symbol table if one is to be included.9 * Finally, it spawns the boot command loop task.10 *11 * NOMANUAL12 */1314 void usrRoot15 (16 char * pMemPoolStart, /* start of system memory partition */17 unsigned memPoolSize /* initial size of mem pool */18 )1920 {21 char tyName [20];22 int ix;2324 /* Initialize the memory pool before initializing any other package.25 * The memory associated with the root task will be reclaimed at the26 * completion of its activities.27 */2829 memInit (pMemPoolStart, memPoolSize);/* XXX select between memPartLibInit

*/3031 /* set up system timer */3233 sysClkConnect ((FUNCPTR) usrClock, 0); /* connect clock interrupt routine */34 sysClkRateSet (60); /* set system clock rate */35 sysClkEnable (); /* start it */3637 /* initialize I/O and file system */3839 iosInit (NUM_DRIVERS, NUM_FILES, “/null”);40 consoleFd = NONE;4142 /* install driver for on-board serial ports and make devices */4344 #ifdef INCLUDE_TYCODRV_5_245 #ifdef INCLUDE_TTY_DEV46 if (NUM_TTY > 0)47 {48 tyCoDrv (); /* install console driver */

J-3

4950 for (ix = 0; ix < NUM_TTY; ix++) /* create serial devices */51 {52 sprintf (tyName, “%s%d”, “/tyCo/”, ix);5354 (void) tyCoDevCreate (tyName, ix, 512, 512);5556 if (ix == CONSOLE_TTY)57 strcpy (consoleName, tyName); /* store console name */58 }5960 consoleFd = open (consoleName, O_RDWR, 0);6162 /* set baud rate */6364 (void) ioctl (consoleFd, FIOBAUDRATE, CONSOLE_BAUD_RATE);65 (void) ioctl (consoleFd, FIOSETOPTIONS,66 OPT_ECHO | OPT_CRMOD | OPT_TANDEM | OPT_7_BIT);67 }68 #endif /* INCLUDE_TTY_DEV */6970 #else /* !INCLUDE_TYCODRV_5_2 */71 #ifdef INCLUDE_TTY_DEV72 if (NUM_TTY > 0)73 {74 ttyDrv(); /* install console driver */7576 for (ix = 0; ix < NUM_TTY; ix++) /* create serial devices */77 {78 sprintf (tyName, “%s%d”, “/tyCo/”, ix);79 (void) ttyDevCreate (tyName, sysSerialChanGet(ix), 512, 512);8081 if (ix == CONSOLE_TTY) /* init the tty console */82 {83 strcpy (consoleName, tyName);84 consoleFd = open (consoleName, O_RDWR, 0);85 (void) ioctl (consoleFd, FIOBAUDRATE, CONSOLE_BAUD_RATE);86 (void) ioctl (consoleFd, FIOSETOPTIONS,87 OPT_ECHO | OPT_CRMOD | OPT_TANDEM | OPT_7_BIT);88 }89 }90 }91 #endif /* INCLUDE_TTY_DEV */929394 #ifdef INCLUDE_PC_CONSOLE95 pcConDrv ();96 for (ix = 0; ix < N_VIRTUAL_CONSOLES; ix++)97 {98 sprintf (tyName, “%s%d”, “/pcConsole/”, ix);99 (void) pcConDevCreate (tyName,ix, 512, 512);100 if (ix == PC_CONSOLE) /* init the console device */

J-4

101 {102 strcpy (consoleName, tyName);103 consoleFd = open (consoleName, O_RDWR, 0);104 (void) ioctl (consoleFd, FIOBAUDRATE, CONSOLE_BAUD_RATE);105 (void) ioctl (consoleFd, FIOSETOPTIONS,106 OPT_ECHO | OPT_CRMOD | OPT_TANDEM | OPT_7_BIT);107 }108 }109 #endif /* INCLUDE_PC_CONSOLE */110111 #endif /* !INCLUDE_TYCODRV_5_2 */112113 ioGlobalStdSet (STD_IN, consoleFd);114 ioGlobalStdSet (STD_OUT, consoleFd);115 ioGlobalStdSet (STD_ERR, consoleFd);116117 pipeDrv (); /* install pipe driver */118 excInit (); /* init exception handling */119 excHookAdd ((FUNCPTR) bootExcHandler); /* install exc handler */120 logInit (consoleFd, 5); /* initialize logging */121122 #ifdef INCLUDE_DOSFS123 hashLibInit (); /* hashLib used by dosFS */124 #endif125126 /* initialize object module loader */127128 #if defined(INCLUDE_AOUT)129 bootAoutInit (); /* use a.out format */130 #else /* coff or ecoff */131 #if defined(INCLUDE_ECOFF)132 bootEcoffInit (); /* use ecoff format */133 #else /* coff */134 #if defined(INCLUDE_COFF)135 bootCoffInit (); /* use coff format */136 #else /* coff */137 #if defined(INCLUDE_ELF)138 bootElfInit (); /* use elf format */139 #endif140 #endif /* mips cpp no elif */141 #endif142 #endif143144 taskSpawn (“tBoot”, bootCmdTaskPriority, bootCmdTaskOptions,145 bootCmdTaskStackSize, (FUNCPTR) bootCmdLoop,146 0,0,0,0,0,0,0,0,0,0);147 }

J-5

bootCmdLoop()

1 * bootCmdLoop - read and execute user commands forever (until boot)2 */34 LOCAL void bootCmdLoop (void)56 {7 BOOT_PARAMS params;8 char line [MAX_LINE];9 char *pLine;10 int nwords;11 int nbytes;12 int value;13 int adr;14 int adr2;15 FUNCPTR entry;16 char key = 0;1718 /* flush standard input to get rid of any garbage;19 * E.g. the Heurikon HKV2F gets junk in USART if no terminal connected.20 */2122 (void) ioctl (STD_IN, FIOFLUSH, 0 /*XXX*/);2324 if (sysStartType & BOOT_CLEAR)25 printBootLogo ();2627 usrBootLineInit (sysStartType);282930 /* print out any new exception message -31

* the first byte is zeroed after printing so that we won’t print32 * it again automatically. However, ‘e’command will still print out33 * the remainder. */3435 printExcMsg (sysExcMsg);36 *sysExcMsg = EOS; /* indicate exception message is old */373839 /* start autoboot, unless no-autoboot specified */4041 bootStringToStruct (BOOT_LINE_ADRS, &params);42 sysFlags = params.flags;4344 if (!(sysStartType & BOOT_NO_AUTOBOOT) &&45 !(sysFlags & SYSFLG_NO_AUTOBOOT))46 {47 int timeout = TIMEOUT;4849 if ((sysStartType & BOOT_QUICK_AUTOBOOT) ||

J-6

50 (sysFlags & SYSFLG_QUICK_AUTOBOOT))51 {52 timeout = 1;53 }5455 key = autoboot (timeout); /* doesn’t return if successful */56 }575859 /* If we’re here, either we aren’t auto-booting, or we got an error60 * auto-booting, or the auto-booting was stopped. */6162 /* put console in line mode */6364 (void) ioctl (consoleFd, FIOSETOPTIONS, OPT_TERMINAL);6566 /* read and execute the ROM commands */6768 printf (“\n”);6970 FOREVER71 {72 if ((key == ‘!’) || (key == ‘@’))73 {74 line [0] = key;75 line [1] = EOS;76 key = 0;77 }78 else79 {80 printf (“[VxWorks Boot]: “);81 fioRdString (STD_IN, line, sizeof (line));82 }8384 adr = adr2 = 0;85 nwords = 0;8687 /* take blanks off end of line */8889 pLine = line + strlen (line) - 1; /* point at last char */90 while ((pLine >= line) && (*pLine == ‘‘))91 {92 *pLine = EOS;93 pLine--;94 }9596 pLine = line;97 skipSpace (&pLine);9899 switch (*(pLine++))100 {101 case EOS: /* blank line */

J-7

102 break;103104 case ‘d’: /* display */105 if ((getArg (&pLine, &adr, HEX, OPT) == OK) &&106 (getArg (&pLine, &nwords, DEC, OPT) == OK))107 d ((char *) adr, nwords);108 break;109110 case ‘e’: /* exception */111 printExcMsg (sysExcMsg + 1);112 break;113114 case ‘f’: /* fill */115 if ((getArg (&pLine, &adr, HEX, !OPT) == OK) &&116 (getArg (&pLine, &nbytes, DEC, !OPT) == OK) &&117 (getArg (&pLine, &value, DEC, !OPT) == OK))118 {119 bfillBytes ((char *) adr, nbytes, value);120 }121122 break;123124 case ‘t’: /* transpose(?) (running out of letters!) */125 if ((getArg (&pLine, &adr, HEX, !OPT) == OK) &&126 (getArg (&pLine, &adr2, HEX, !OPT) == OK) &&127 (getArg (&pLine, &nbytes, HEX, !OPT) == OK))128 {129 bcopy ((char *) adr, (char *) adr2, nbytes);130 }131 break;132133 case ‘m’: /* modify */134 if (getArg (&pLine, &adr, HEX, !OPT) == OK)135 m ((char *) adr);136 break;137138 #ifdef TARGET_HK_V2F139 case ‘s’: /* system controller */140 {141 extern ULONG sysBCLSet ();142143 if (getArg (&pLine, &value, DEC, !OPT) == OK)144 {145 if (value != 0)146 {147 (void) sysBCLSet ((ULONG)HK_BCL_SYS_CONTROLLER,148 (ULONG)HK_BCL_SYS_CONTROLLER);149 printf (“System controller on.\n”);150 }151 else152 {153 (void) sysBCLSet ((ULONG)HK_BCL_SYS_CONTROLLER,

J-8

154 (ULONG)0);155 printf (“System controller off.\n”);156 }157 }158 break;159 }160 #endif /* TARGET_HK_V2F */161162 #if defined(TARGET_FRC_30) || defined(TARGET_FRC_31) || defined(TARGET_FRC_33)163 case ‘s’: /* system controller */164 if (getArg (&pLine, &value, DEC, !OPT) == OK)165 {166 if (value != 0)167 {168 *FGA_CTL1 |= FGA_CTL1_SCON;169 printf (“System controller on.\n”);170 }171 else172 {173 *FGA_CTL1 &= ~FGA_CTL1_SCON;174 printf (“System controller off.\n”);175 }176 }177 break;178 #endif /* TARGET_FRC_30 || TARGET_FRC_31 || TARGET_FRC_33 */179180 case ‘p’: /* print boot params */181 bootParamsShow (BOOT_LINE_ADRS);182 break;183184 case ‘c’: /* change boot params */185 bootParamsPrompt (BOOT_LINE_ADRS);186 (void) sysNvRamSet (BOOT_LINE_ADRS,187 strlen (BOOT_LINE_ADRS) + 1, 0);188 break;189190 case ‘g’: /* go */191 if (getArg (&pLine, (int *) &entry, HEX, !OPT) == OK)192 go (entry);193 break;194195 #ifdef INCLUDE_NETWORK196 case ‘n’:197 netifAdrsPrint (pLine);198 break;199200 #ifdef ETHERNET_ADR_SET201 case ‘N’:202 mEnet ();203 break;204 #endif /* ETHERNET_ADR_SET */205 #endif /* INCLUDE_NETWORK */

J-9

206207 case ‘?’: /* help */208 case ‘h’: /* help */209 bootHelp ();210 break;211212 case ‘@’: /* load and go with internalparams */213 case ‘$’: /* load and go with internalparams */214215 if (bootLoad (pLine, &entry) == OK)216 {217 go (entry);218 }219 else220 {221 taskDelay (sysClkRateGet ()); /* pause a second */222 reboot (BOOT_NO_AUTOBOOT); /* something is awry */223 }224 break;225226 case ‘l’: /* load with internalparams */227228 if (bootLoad (pLine, &entry) == OK)229 {230 printf (“entry = 0x%x\n”, (int) entry);231 }232 else233 {234 taskDelay (sysClkRateGet ()); /* pause a second */235 reboot (BOOT_NO_AUTOBOOT); /* something is awry */236 }237 break;238239240 default:241 printf (“Unrecognized command. Type ‘?’for help.\n”);242 break;243244 } /* switch */245 } /* FOREVER */246 }

J-10

autoboot()

1 * autoboot - do automatic boot sequence2 *3 * RETURNS: Doesn’t return if successful (starts execution of booted system).4 */56 LOCAL char autoboot7 (8 int timeout /* timeout time in seconds */9 )10 {11 int autoBootTime;12 int timeLeft;13 UINT timeMarker;14 int bytesRead = 0;15 FUNCPTR entry;16 char key;1718 if (timeout > 0)19 {20 printf (“\nPress any key to stop auto-boot...\n”);2122 /* Loop looking for a char, or timeout after specified seconds */2324 autoBootTime = tickGet () + sysClkRateGet () * timeout;25 timeMarker = tickGet () + sysClkRateGet ();26 timeLeft = timeout;2728 printf (“%2d\r”, timeLeft);2930 while ((tickGet () < autoBootTime) && (bytesRead == 0))31 {32 (void) ioctl (consoleFd, FIONREAD, (int) &bytesRead);3334 if (tickGet () == timeMarker)35 {36 timeMarker = tickGet () + sysClkRateGet ();37 printf (“%2d\r”, --timeLeft);38 }39 }40 }4142 if (bytesRead == 0) /* nothing typed so auto-boot */43 {44 /* put the console back in line mode so it echoes (so’s you can bang45 * on it to see if it’s still alive) */4647 (void) ioctl (consoleFd, FIOSETOPTIONS, OPT_TERMINAL);4849 printf (“\nauto-booting...\n\n”);

J-11

5051 if (bootLoad (BOOT_LINE_ADRS, &entry) == OK)52 go (entry); /* ... and never return */53 else54 {55 printf (“Can’t load boot file!!\n”);56 taskDelay (sysClkRateGet ()); /* pause a second */57 reboot (BOOT_NO_AUTOBOOT); /* something is awry */58 }59 }60 else61 {62 /* read the key that stopped autoboot */6364 read (consoleFd, &key, 1);65 return (key & 0x7f); /* mask off parity in raw mode */66 }6768 return (ERROR); /* for lint - can’t really get here */69 }70

J-12

bootLoad()1 * bootLoad - load a module into memory2 *3 * RETURNS: OK or ERROR4 */56 LOCAL STATUS bootLoad7 (8 char * bootString,9 FUNCPTR *pEntry10 )11 {12 BOOT_PARAMS params;13 #ifdef INCLUDE_SCSI_BOOT14 #ifdef INCLUDE_SCSI215 SCSI_OPTIONS options;16 UINT which;17 int devBusId;18 #endif /* INCLUDE_SCSI2 */19 #endif /* INCLUDE_SCSI_BOOT */20 #ifdef INCLUDE_NETWORK21 char nad [20]; /* host’s network internet addr */22 int netmask = 0; /* temporary storage */23 char mask [30]; /* string mask */24 char netDev [BOOT_DEV_LEN + 1];25 char bootDev [BOOT_DEV_LEN];26 BOOL backplaneBoot;27 char * pBootAddr;28 #endif /* INCLUDE_NETWORK */2930 /* copy bootString to low mem address, if specified */3132 if ((bootString != NULL) && (*bootString != EOS))33 strcpy (BOOT_LINE_ADRS, bootString);3435 /* interpret boot command */3637 if (usrBootLineCrack (BOOT_LINE_ADRS, &params) != OK)38 return (ERROR);3940 /* Display boot parameters */4142 bootParamsShow (BOOT_LINE_ADRS);4344 /* set our processor number: may establish vme access, etc. */4546 sysFlags = params.flags;47 sysProcNumSet (params.procNum);4849 #ifdef INCLUDE_SCSI_BOOT

J-13

5051 /*52 * initialize either the SCSI1 or SCSI2 interface; initialize SCSI2 when53 * the SCSI2 interface is available.5455 #ifndef INCLUDE_SCSI256 scsi1IfInit ();57 #else58 scsi2IfInit ();59 #endif6061 if (strncmp (params.bootDev, “scsi”, 4) == 0)62 {63 int bootDevId = NONE;64 int bootDevLUN = NONE;6566 #ifdef INCLUDE_SCSI267 /* Set all devices to asynchronous data transfer */6869 which = SCSI_SET_OPT_XFER_PARAMS;70 options.maxOffset = 0;71 options.minPeriod = SCSI_SYNC_XFER_MIN_PERIOD;7273 for (devBusId = 0; devBusId < 8; devBusId++)74 {75 scsiTargetOptionsSet (pSysScsiCtrl, devBusId, &options, which);76 }77 #endif /* INCLUDE_SCSI2 */7879 /* check for absence of bus ID and LUN, in which case80 * auto-configure and display results81 */8283 if (strlen (params.bootDev) == 4)84 {85 if (!scsiInitialized)86 {87 if (sysScsiInit () == ERROR)88 {89 printErr (“Could not initialize SCSI.\n”);90 return (ERROR);91 }92 scsiInitialized = TRUE;93 }9495 scsiAutoConfig (pSysScsiCtrl);96 scsiShow (pSysScsiCtrl);9798 /* return ERROR to indicate that no file was loaded */99 return (ERROR);100 }101

J-14

102 sscanf (params.bootDev, “%*4s%*c%d%*c%d”, &bootDevId, &bootDevLUN);103104 if (scsiLoad (bootDevId, bootDevLUN, params.bootFile, pEntry) != OK)105 {106 printErr (“\nError loading file: errno = 0x%x.\n”, errno);107 return (ERROR);108 }109110 return (OK);111 }112113 #endif /* INCLUDE_SCSI_BOOT */114115 #ifdef INCLUDE_FD116117 if (strncmp (params.bootDev, “fd”, 2) == 0)118 {119 int type = 0;120 int drive = 0;121122 if (strlen (params.bootDev) == 2)123 return (ERROR);124 else125 sscanf (params.bootDev, “%*2s%*c%d%*c%d”, &drive, &type);126127 if (fdLoad (drive, type, params.bootFile, pEntry) != OK)128 {129 printErr (“\nError loading file: errno = 0x%x.\n”, errno);130 return (ERROR);131 }132133 return (OK);134 }135136 #endif /* INCLUDE_FD */137138 #ifdef INCLUDE_IDE139140 if (strncmp (params.bootDev, “ide”, 3) == 0)141 {142 int type = 0;143 int drive = 0;144145 if (strlen (params.bootDev) == 3)146 return (ERROR);147 else148 sscanf (params.bootDev, “%*3s%*c%d%*c%d”, &drive, &type);149150 if (ideLoad (drive, type, params.bootFile , pEntry) != OK)151 {152 printErr (“\nError loading file: errno = 0x%x.\n”, errno);153 return (ERROR);

J-15

154 }155156 return (OK);157 }158159 #endif /* INCLUDE_IDE */160161 #ifdef INCLUDE_ATA162163 if (strncmp (params.bootDev, “ata”, 3) == 0)164 {165 int ctrl = 0;166 int drive = 0;167168 if (strlen (params.bootDev) == 3)169 return (ERROR);170 else171 sscanf (params.bootDev, “%*3s%*c%d%*c%d”, &ctrl, &drive);172173 if (ataLoad (ctrl, drive, params.bootFile, pEntry) != OK)174 {175 printErr (“\nError loading file: errno = 0x%x.\n”, errno);176 return (ERROR);177 }178179 return (OK);180 }181182 #endif /* INCLUDE_ATA */183184 #ifdef INCLUDE_PCMCIA185186 pcmciaInit (); /* init PCMCIA Lib */187188 if (strncmp (params.bootDev, “pcmcia”, 6) == 0)189 {190 int sock = NONE;191192 if (strlen (params.bootDev) == 6)193 return (ERROR);194 else195 sscanf (params.bootDev, “%*6s%*c%d”, &sock);196197 if (pcmciaLoad (sock, params.bootFile , pEntry) == OK)198 return (OK);199200 /* fall through if the PC card is not a block device.201 * let’s try to boot it from an ethernet device.202 */203 }204205 #endif /* INCLUDE_PCMCIA */

J-16

206207 #ifndef INCLUDE_NETWORK208209 printf (“\nError loading file: networking code not present.\n”);210 return (ERROR);211 }212213 #else /* INCLUDE_NETWORK */214215 /* start the network */216217 /* initialize the generic socket library */218219 if (sockLibInit (NUM_FILES) == ERROR)220 return (ERROR);221222 #if defined(INCLUDE_STREAMS) || defined(INCLUDE_STREAMS_ALL)223 if (usrStrmInit() == ERROR) /* init Streams subsystem */224 return (ERROR);225 #endif226227 #if defined(INCLUDE_BSD) || defined(INCLUDE_BSD_SOCKET)228229 /* install default socket library interface */230231 #ifndef DEFAULT_STREAMS_SOCKET232 if (sockLibAdd ((FUNCPTR) bsdSockLibInit , AF_INET, AF_INET) == ERROR)233 return (ERROR);234 #endif /* DEFAULT_STREAMS_SOCKET */235236 hostTblInit (); /* initialize host table */237 netLibInit ();238239 #ifdef INCLUDE_PPP240 #ifdef INCLUDE_PPP_CRYPT241 cryptRtnInit (&pppCryptRtn); /* install crypt() routine */242 #endif /* INCLUDE_PPP_CRYPT */243 #endif /* INCLUDE_PPP */244245 /* attach and configure boot interface */246247 if (strncmp (params.bootDev, “ppp”, 3) == 0)248 {249 /* booting via ppp */250251 if (usrPPPInit (params.bootDev, params.ead, ((params.gad[0] == EOS)?252 params.had : params.gad)) == ERROR)253 return (ERROR);254 }255 else if (strncmp (params.bootDev, “sl”, 2) == 0)256 {257 if (usrSlipInit (params.bootDev, params.ead, ((params.gad[0] == EOS)?

J-17

258 params.had : params.gad)) == ERROR)259 return (ERROR);260 }261 else262 {263 strncpy (bootDev, params.bootDev, sizeof (bootDev));264265 if ((strncmp (params.bootDev, “bp”, 2) != 0) &&266 (strncmp (params.bootDev, “sm”, 2) != 0))267 {268 pBootAddr = params.ead;269 backplaneBoot = FALSE;270 }271 else272 {273 if (sysProcNumGet () == 0)274 {275 printf (276 “Error: processor number must be non-zero to boot from bp\n”);277 return (ERROR);278 }279280 if (usrBpInit (bootDev, 0) == ERROR)281 return (ERROR);282283 pBootAddr = params.bad;284 backplaneBoot = TRUE;285 }286287 netmask = 0;288 bootNetmaskExtract (pBootAddr, &netmask);289290 if (usrNetIfAttach (bootDev, pBootAddr) != OK)291 return (ERROR);292293 (void) sprintf (netDev, “%s%d”, bootDev, 0);294295 if ((sysFlags & SYSFLG_BOOTP) || (sysFlags & SYSFLG_PROXY) ||296 (netmask == 0))297 {298 struct ifnet * pIf;299300 /* Initialize the boot device */301302 if ((pIf = ifunit (netDev)) == NULL)303 {304 printf (“invalid device \”%s\”\n”, netDev);305 return (ERROR); /* device not attached */306 }307308 if (pIf->if_init != NULL)309

J-18

310 if ((*pIf->if_init) (pIf->if_unit) != 0)311 {312 printf (“initialization failed for device \”%s\”\n”,netDev);313 return (ERROR);314 }315 }316 }317318 #ifdef INCLUDE_SM_NET319 if (backplaneBoot)320 {321 if ((params.bad [0] == EOS) &&322 (strncmp (bootDev, “sm”, 2) == 0) &&323 (smNetInetGet (netDev, params.bad, NONE) == OK))324 printf (“Backplane inet address: %s\n”, params.bad);325326 if (params.bad [0] == EOS)327 {328 printf (“no backplane address specified\n”);329 return (ERROR);330 }331332 if ((sysFlags & SYSFLG_BOOTP) && !(sysFlags & SYSFLG_PROXY))333 {334 printf (“BOOTP over backplane only with proxy arp\n”);335 return (ERROR);336 }337338 if (sysFlags & SYSFLG_PROXY)339 {340 #ifdef INCLUDE_PROXY_CLIENT341 printf (“registering proxy client: %s”, params.bad);342343 if (proxyReg (netDev, params.bad) == ERROR)344 {345 printf (“client registered failed %x\n”, errno);346 return (ERROR);347 }348 printf (“done.\n”);349350 #else /* INCLUDE_PROXY_CLIENT */351 printf (“proxy client referenced but not included.\n”);352 return (ERROR);353 #endif /* INCLUDE_PROXY_CLIENT */354 }355 }356 #endif /* INCLUDE_SM_NET */357358 /* get boot parameters via bootp */359360 if (sysFlags & SYSFLG_BOOTP)361 {

J-19

362 if (bootpGet (netDev, pBootAddr, params.bootFile , params.had,363 &netmask, params.gad) == ERROR)364 return (ERROR);365 }366367 if (netmask == 0)368 {369 (void) icmpMaskGet (netDev, pBootAddr , backplaneBoot ?370 NULL : params.had, &netmask);371 if (netmask != 0)372 printf (“Subnet Mask: 0x%x\n”, netmask);373 }374375 /* configure the device */376377 if (usrNetIfConfig (bootDev, pBootAddr , (char *) NULL, netmask) != OK)378 return (ERROR);379380 /* get gateway address */381382 #ifdef INCLUDE_SM_NET383384 if (netmask != 0) /* reconstruct address with mask */385 {386 sprintf (mask, “:%x”, netmask);387 strcat (pBootAddr, mask);388 }389390 /* in case boot string changed */391392 bootStructToString (BOOT_LINE_ADRS, &params);393 }394395 usrNetIfAttach (“lo”, “127.0.0.1”);396 usrNetIfConfig (“lo”, “127.0.0.1”, “localhost”, 0);397398 /* if a gateway was specified, extract the network part of the host’s399 * address and add a route to this network400 */401402 if (params.gad[0] != EOS)403 {404 inet_netof_string (params.had, nad);405 routeAdd (nad, params.gad);406 }407408 /* associate hostName with the specified host address */409410 hostAdd (params.hostName, params.had);411412 /* load specified file */413

J-20

414 if (netLoad (params.had, params.bootFile , params.usr,415 params.passwd, pEntry) != OK)416 {417 printf (“\nError loading file:errno = 0x%x.\n”, errno);418 return (ERROR);419 }420421 return (OK);422 }

J-21

go()

1 * go - start at specified address2 */34 LOCAL void go5 (6 FUNCPTR entry7 )8 {9 printf (“Starting at 0x%x...\n\n”, (int) entry);1011 taskDelay (sysClkRateGet ()); /* give the network a moment to close */1213 #ifdef INCLUDE_NETWORK14 ifreset (); /* reset network to avoid interrupts */15 #endif /* INCLUDE_NETWORK */1617 #if (CPU_FAMILY == PPC)18 cacheTextUpdate ((void *) (LOCAL_MEM_LOCAL_ADRS), /* cache coherency */19 (size_t) (sysMemTop() - LOCAL_MEM_LOCAL_ADRS));20 #else21 cacheClear (DATA_CACHE, NULL, ENTIRE_CACHE); /* push cache to mem */22 #endif /* (CPU_FAMILY == PPC) */2324 (entry) (); /* go to entry point - never to return */25 }26


Appendix - K

PCI Bus

K-2

PCI BusOverview

PCI Bus Operational Essentials

PCI Bus Configuration

PCI Bus And The BSP

PCI Bus

K-3

• Appendix designed to provide basic information about the PCI bus which BSP developer should be aware:• Review of (or introduction to) BSP relevant PCI bus features.• Discussion WRS PCI bus support and BSP responsibilities.

• For more complete information see the relevant PCI bus specifications for your target environment:• PCI Bus specification.• PCI-to-PCI bridge specification.• BIOS specification.• PCI System Design Guide.• etc.

Overview

K-4

• Principle PCI features (revision 2.1)• Processor independent.• Support for up to 256 PCI devices per bus.• Peer-to-peer bus access.• Low power consumption and pin count.• Support for expansion cards (variable sizes).• High bus speed.• Standardized peripheral detection/configuration.

• PCI bus designed to prevent marketplace from becoming overpopulated with various permutation of local bus architectures:• Facilitates plug-and-play design strategy.

PCI Features

K-5

• Typical device consist of a peripheral adapter encapsulated in a PCI package.

• Each physical PCI package supports up to 8 PCI functions. Examples of functions:• LAN interface.• SCSI adaptor.

• Package may also be a PCI-to-PCI bus bridge.• Bus uses time-multiplexed address/data lines:

• Transactions are phased.• Timing supplied by PCI clock signal.

• PCI bus uses little-endian byte ordering.

Basic PCI BUS Properties

K-6

Overview



PCI Bus And The BSP

PCI Bus

K-7

• This section is a presentation of PCI bus operational essentials needed for BSP development.

• Features discussed:• Three PCI address spaces:

- Configuration- I/O- Memory

• PCI bus topology.• Bus operation basics.• PCI interrupts.

PCI BUS Operational Essentials

K-8

• Configuration space is used to access device configuration registers:• Each physical PCI device has set of configuration registers.• Each logical PCI device has a device configuration header

providing software interface to physical configuration registers, and PCI specific info.

• Geographic addressing (device location specified by bus number, device ID, and function).

• I/O space used by PCI bus masters to access I/O device registers:• Device control/status registers mapped to I/O space• Logically addressed.

PCI Address Spaces

K-9

• Memory space used by PCI bus masters to access memory mapped device registers, control structures, and data. Example:• Network link buffers mapped to memory space.

• Memory and I/O space use a Base Address Register to:• Define where the space begins.• Specific properties of the space.

• BSP developer may want to provide Memory Base Address Register for mapping device registers:• Some processors not capable of performing I/O transactions.• I/O is densely populated.

PCI Address Spaces - cont.

K-10

• Terminology:• WRS refers to the complete (logical) PCI bus as “the PCI bus”.• The physical components of the PCI bus are referred to as “PCI

bus segments”.• PCI specification currently does not have term for PCI physical

components.• A PCI bus can support up to 256 PCI bus segments.• For systems with multiple PCI bus segments:

• Each bus segment has a unique bus segment number.• Bus segments are connected by PCI-to-PCI bridges.

PCI Bus Topology

K-11

• PCI bus terminology:• Downstream - When transaction is passed through one or more

bridges flowing away from the host bridge, transaction is movingdownstream.

• Upstream - When transaction is passed through oneor more bridges flowing toward the host bridge, transaction is moving upstream.

• Primary bus segment - Bus on upstream side of bridge.• Secondary bus segment - Bus on downstream side of bridge.• Subordinate bus segment - Highest numbered bus segment on

downstream side of bridge.

PCI Bus Topology - cont.

K-12

• At start-up PCI configuration software only aware of bus segment zero:• Walks PCI bus segment zero looking for other PCI-to- PCI

bridges.• When bridge is discovered, secondary bus segment is walked

attempting to find another bridge.• As bridges are discovered they are assigned bus segment numbers,

and subordinate bus segment numbers for upstream bridges are updated.

• After tree branch is configured, return to first bus segment andsearch for other bridges.

• Tree is then walked again scanning for and configuring PCI devices.


K-13

• PCI specification does not dictate order of bus segment numbers, but requires that bus segment number for each bus behind a bridge:• Be greater than current bridge’s primary bus segment number.• Be less than or equal to than its own subordinate bus segment

number.• PCI bus capable of supporting up to ten electrical loads:

• Each bridge is one load.• Bridges embedded in bus or on add-in card installed in PCI

expansion connector.• Loading constraint on a per bus segment basis (controlled by

power supply).


K-14

• Transactions involve master and target:• Master initiates transaction.• Target is device currently addressed by master.• PCI master and target devices are commonly referred to as agents.

• All PCI transactions are synchronized to PCI clock signal:• Clock may be set between 0 - 66 MHz. (See PCI specification for

operations in the range of 34 - 66 MHz.)• All PCI devices must support operation in the 0 - 33 MHz range.• Clock rate may be modified dynamically.

Bus Operation Basics

K-15

• All transactions consist of phases:• An address phase followed by one or more data phases.• Address phase is one PCI clock period.• Each data phase is a minimum of one PCI clock period (wait states

inserted to round-up).

• During address phase master:• Identifies target device.• Identifies type of transaction.

• During data phase:• Data object is transferred between master and target.• Number of data bytes transferred dictated by master.

Bus Operation Basics - cont.

K-16

• All read and write transfers over PCI bus are burst transfers:• Length of the burst is negotiated between master and target devices.• Bursts can be of any length.• Number of data bytes transferred controlled by Command/Byte Enable

signals asserted by master.• Target latches start address in address counter and is responsible for

incrementing address from data phase to data phase.

• If no wait states are inserted in data phases transfer rate of 132 Mbytes/sec (33MHz X 4Bytes) may be obtained:• Higher rates for 64-bit and/or 66Mhz.


K-17

• After data phase PCI bus is returned to idle state:• Master indicates when last data transfer is in progress.• After last transfer, bus will be returned to another bus master which had

previously been granted the bus by the arbiter.• Preempted bus master can regain control of the bus after detecting bus

has returned to idle state.

• System has single bus arbiter which grants the bus to requesting bus masters:• Typically host/PCI bridge or PCI/expansion bus bridge.• Grants bus to master by asserting the devices grant signal (GNT#).


K-18

• PCI specification does not define scheme dictating who gets bus when multiple masters request it simultaneously.

• PCI specification states that arbitration scheme is required to implement a fairness algorithm to avoid deadlocks:• Can be based on fixed or rotational priority.• Ideally bus arbiter should be programmable.

• Device priorities hard-wired in PCI device maximum latency configuration register:• Allowed values in increments of 250ns.• Smaller values have higher priority.


K-19

• A PCI device may implement up to 4 interrupt pins on a package: INTA#, INTB#, INTC#, INTD#.• No inherent interrupt priority levels.

• If package has one pin it must be called INTA#. If it implements two pins they must be INTA# and INTB#, etc.

• A package containing eight functions could bond interrupt request signals as follows:• All eight to INTA# pin.• Four to INTA# and four to INTB#.• Two each to INTA#, INTB#, INTC#, and INTD#.• etc.

PCI Interrupts

K-20

• Target board designer dictates how PCI interrupt pins on PCI packages residing on bus segment zero are mapped to interrupt controller. Examples:• All tied to single trace on board and hard-wired to one input on interrupt

controller.• Each tied to separate traces on board and hard-wired to separate input on

interrupt controller.• All tied to separate board traces and routed to separate inputs of

programmable interrupt controller.• All INTA# pins tied to single trace, all INTB# pins tied to single trace,

etc. Each board trace wired to separate inputs of interrupt controller (programmable or not).

PCI Interrupts - cont.

K-21

• Interrupt priority levels for PCI devices controlled by interrupt controller:• May be hard-wired.• May be configurable.

• For progammable interrupt controller:• PCI interrupt pins wired to controller pins (IRQs).• Controller pins (IRQs) can be mapped to interrupt levels in software.

• Controller will have demultiplexer ISR:• Obtains interrupt vector from controller.• Interrupt vector identifies PCI package(s).• Continue demultiplexing to device service.

PCI Interrupts - cont.

K-22

Overview



PCI Bus And The BSP

PCI Bus

K-23

• PCI configuration performed with configuration transactions:• Reads and writes to configuration registers.

• A physical PCI package can contain up to 8 (logical) PCI devices(functions). PCI package needs to know:• It’s a target for a configuration read/write.• Identity of target function within it.• Configuration register within function.

• PCI package can be a single function or a multi-function device:• Bit of a configuration register identifies if device is multi-functional or

not.


K-24

• Each (logical) PCI device has a configuration control structure called a configuration header:• Contains all configuration registers for device.• 64 bytes (16 blocks of 4 bytes each).• Type one - for PCI-to-PCI bridges.• Type zero - non PCI-to-PCI bridge devices.

• Some configuration registers are mandatory for all PCI devices, some are mandatory for specific devices.Mandatory registers:• Identify the device.• Control device’s PCI functions.• Sense PCI status in a generic fashion.

PCI Configuration - cont.

K-25

PCI Configuration Header (Type 0)

Device ID Vendor ID

Status Register Command Register

Class Code Rev. ID

3 2 1 0

00

03

01

04

05

06

02

07

#

BIST Header Lat. Timer CLS

Base Address 0

Base Address 1

Base Address 2

Base Address 3

Byte

K-26

PCI Configuration Header (Type 0)

3 2 1 0

08

11

09

12

13

14

10

15

#

Reserved

Base Address 4

Byte

Base Address 5

CardBus CIS Pointer

Sub. Vendor IDSubsystem ID

Expansion ROM Base Address

Reserved

Max_Lat Min_Gnt Int. Pin Int. Line

K-27

• Vendor ID - Identifies device manufacturer (read-only).• Device ID - Assigned by device manufacturer to identify type of

device.• Command Register - Provides control for device’s ability to respond

to and/or perform PCI access:• I/O access enable.• Memory access enable.• Parity error response.• Wait cycle control.• etc.• See PCI specification for details and register bit assignments.

PCI Configuration Registers

K-28

• Status Register - Tracks status of PCI bus events.• Parity error detected.• 66 MHz capable.• See PCI specification for details.

• Revision ID - Assigned by device manufacturer to identify revision number of device.

• Class Code - Read only, divided into three sub registers:• Basic class type (e.g. network controller- class code 2)• Sub-class type (e.g. ATM controller)• Programming interface

• Header Type - Specifies format for configuration header (PCI-to-PCI), and single/multi-function device.

PCI Configuration Registers - cont.

K-29

• Remaining configuration registers may be mandatory for some devices and not for others:• Interrupt Pin Register - Required if PCI device generates

interrupts. Defines which of the four PCI interrupts (INTA# -INTD#) a device is connected to.

• Base Address Registers - Required if device implements decoders. Used to assign start address to address decoder.

• For more information:• See PCI specification for more details on configuration registers

(type 0 and type 1).• See device documentation for more information on mandatory and

optional PCI features.

PCI Configuration Registers - cont.

K-30

• Many popular architectures can not perform configuration read/write transactions (x86, PowerPC, etc.).• I/O and memory read/writes transactions used to configure

devices.• Host/PCI bridge designed to recognize certain I/O or memory

accesses as configuration transactions.• Two methods to stimulate host/PCI bridge to generate configuration

transactions:• Configuration mechanism one - Must be provided by all current

and future host bridges.• Configuration mechanism two - Provided for backward

compatibility.

Configuration Mechanisms

K-31

• Configuration mechanism one uses two I/O space ports:• 32-bit configuration address port at 0x0cf8.• 32-bit configuration data port at 0x0cfc.

• Configuration transaction requires two steps:• Write target bus number, physical device number, function

number and “doubleword” number to configuration address port.• Perform I/O read/write to configuration data port.

• If bit 31 of address port is set, read/write to data port is translated into a configuration transaction. If not it is passed to the PCI bus as an I/O transaction.

Configuration Mechanism One

K-32

• Configuration mechanism two uses two single byte I/O ports.:• Configuration Space Enable (CSE) register at 0xcf8.• Forward register as 0x0cfa.

• To generate a configuration transaction:• Write target bus number to forward register.• Write 8 bit pattern to CSE register which will enable configuration

transactions and specify the PCI functional device.• Perform a 1,2, or 4 byte read/write transaction in the I/O range

0x000 and 0xfff.• This transaction mechanism supplied for backward• compatibility. Type one is preferred mechanism.

Configuration Mechanism Two

K-33

Overview



PCI Bus And The BSP

PCI Bus

K-34

• BSP is responsible for supplying PCI support for:• Bridge/memory controllers.• Configuration.• Managing interrupts.

• BSP developer must provide bridge/memory controller code.• WRS supplies library pciIomapLib for PowerPC and x86 based

targets:• Routines for configuration.• PCI interrupt management.• I/O address space access.

• WRS support is revision 2.1 compliant.

PCI BUS and BSP

K-35

• PCI configuration software must:• Scan (walk) the PCI bus for devices.• Determine what devices exist.• Determine device configuration requirements.• Initialize device configuration registers.

• These PCI initialization and configuration transactions performed insysHwInit().

• pciIomapLib provides support for configuration transactions:• Type zero configuration read/write transactions only.

Configuration Overview

K-36

• Code in pciIomapLib.c and pciIomapLib.h provides support routines to:• Initialize configuration access method.• Locate device by device ID and vendor ID, or locate device by

class code.• Access configuration registers.• Connect/disconnect PCI interrupt handlers.• Dispatch shared PCI interrupts.

• Library pciIomapShow is provided to supply show routines for devices and bridges on a PCI bus.

• Support for targets with PowerPC and x86 processors.

pciIomapLib

K-37

STATUS pciIomapLibInit (mechanism,addr0, addr1, addr2)

mechanism Configuration mechanism 1 or 2. Variabletype: int.

addr0 CAR (mechanism 1), CSE register(mechanism 2). Variable type: int.

addr1 CDR (mechanism 1), FR (mechanism 2).Variable type: int.

addr2 Not used (mechanism 1), Base Address(mechanism 2). Variable type: int.

• Routine initializes access method and I/O addresses:• Supports configuration mechanism 1 or 2.

Access Method Initialization

K-38

STATUS pciFindDevice (vendorId,deviceId, index, pBusNo, pDeviceNo,

pFuncNo)vendorId Vendor ID. Variable type: int.deviceId Device ID. Variable type: int.index Desired instance of device. Variable

type: int.pBusNo Bus segment # ptr. Variable type: int *.pDeviceNo Device number ptr. Variable type: int *.pFuncNo Function number ptr. Variable type: int*.

• Routine finds the nth (index) instance of device specified by device and vendor ID’s.

Find Device

K-39

STATUS pciFindClass (classCode, index,pBusNo, pDeviceNo, pFuncNo)

classCode Class code. Variable type: int.index Desired instance of device. Variable type:

int.pBusNo Bus segment # ptr. Variable type: int *.pDeviceNo Device number ptr. Variable type: int *.pFuncNo Function number ptr. Variable type: int*.

• Routine finds the nth (index) instance of devicespecified by class code.

Find Device - cont.

K-40

STATUS pciDevConfig (pciBusNo,pciDevNo, pciFuncNo, devIoBaseAdrs,

devMemBaseAdrs, command)pciBusNo Bus segment #. Variable type: FUNCPTR.pciDevNo Device number. Variable type: int.pciFuncNo Function number. Variable type: int.devIoBaseAdrs I/O base. Variable type: unsigned long.devMemBaseAdrs Memory base. Variable type: unsigned

long.command Command. Variable type: unsigned long.

• Routine configures a device on PCI bus by writing tothe configuration header for device (type 0 only).

Device Configuration

K-41

• First three arguments, bus, device, and function numbers, obtained using pciFindX().

• PCI I/O and base addresses are defined in <target>.h.• PCI commands defined in ../h/drv/pci/pciIomapLib.h:

• PCI_CMD_IO_ENABLE• PCI_CMD_MEM_ENABLE• etc.

• Routine not designed to configure all PCI devices:• One memory base address.• One I/O base address.• If more are needed, build routine to configure appropriate base

address registers.

Device Configuration - cont

K-42

• Configuration of devices on the PCI bus is performed in sysHwInit():• First pciIomapLibInit() is called to specify configuration

mechanism 1 or 2.• Each device is then located by vender and device Ids (or class

code) using pciFindDevice() (or pciFindClass()). Bus, device, and function numbers returned by reference.

• Each device is then configured with pciDevConfig() and using the bus, device, and function numbers previously obtained.

• Some PCI devices power-up with their configuration header initialized. Above steps not required.

• Non-PCI device configuration may also be required.

PCI Device Configuration

K-43

• PCI library pciIomapLib provides routines to connect and disconnect PCI interrupt handlers to PCI interrupt lines (INTA# - INTD#).• Useful for targets without interrupt controllers.

• For targets with interrupt controllers:• Interrupt controller will map PCI interrupt lines to interrupt vectors.• Interrupt vectors may be programmable in software.

• pciIomapLib uses a link list for multiple interrupt handlers connected to single interrupt line:• Library also provides interrupt dispatcher to walk linked list and check

device interrupt status.

PCI Interrupts

K-44

• PCI device drivers may define routines (or macro routines) to perform PCI address management:• PCI address translations.• PCI read/write transactions to device registers.• Endian swapping.• etc.

• Example to map memory address to (physical) PCI address: #define MEM_TO_PCI_PHYS(memAdrs) \

((memAdrs) + (pDrvCtrl->pciMemBase))

• pDevControl is a pointer to a device driver control structure.

Device PCI Transactions

K-45

• PCI bus provides standardization for embedded systems:• Allows plug-and-play design strategy.

• WRS supplies support for PCI specification revision 2.1.• BSP developer responsible for initializing PCI device configuration

headers in sysHwInit() using pciIomapLib facilities:• Initialize configuration mechanism (1 or 2) with

pciIomapLibInit().• Locate PCI devices with pciFindX().• Perform configuration transactions with pciDevConfig().

Summary


Appendix - L

Memory Maps

L-2

sysPhysMemDesc[]

1 PHYS_MEM_DESC sysPhysMemDesc [] =2 {3 {4 /*5 * Vector Table and Interrupt Stack6 */7 (void *) LOCAL_MEM_LOCAL_ADRS,8 (void *) LOCAL_MEM_LOCAL_ADRS,9 RAM_LOW_ADRS,10 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,11 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT12 },1314 {15 /*16 * Local DRAM17 */18 (void *) RAM_LOW_ADRS,19 (void *) RAM_LOW_ADRS,20 LOCAL_MEM_SIZE - RAM_LOW_ADRS,21 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,22 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE23 },2425 {26 (void *) CPU_PCI_ISA_IO_ADRS,27 (void *) CPU_PCI_ISA_IO_ADRS,28 CPU_PCI_ISA_IO_SIZE,29 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,30 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT31 },3233 {34 (void *) CPU_PCI_IO_ADRS,35 (void *) CPU_PCI_IO_ADRS,36 CPU_PCI_IO_SIZE,37 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,38 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT39 },4041 {42 (void *) CPU_PCI_IACK_ADRS,43 (void *) CPU_PCI_IACK_ADRS,44 CPU_PCI_IACK_SIZE,45 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,46 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT47 },4849 {

L-3

50 (void *) CPU_PCI_MEM_ADRS,51 (void *) CPU_PCI_MEM_ADRS,52 CPU_PCI_MEM_SIZE,53 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,54 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT55 },5657 {58 (void *) CPU_PCI_ISA_MEM_ADRS,59 (void *) CPU_PCI_ISA_MEM_ADRS,60 CPU_PCI_ISA_MEM_SIZE,61 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,62 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT63 },6465 {66 (void *) CPU_VME_WINDOW_A32_BASE,67 (void *) CPU_VME_WINDOW_A32_BASE,68 CPU_VME_WINDOW_A32_SIZE,69 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,70 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT71 },7273 {74 (void *) CPU_VME_WINDOW_A24_BASE,75 (void *) CPU_VME_WINDOW_A24_BASE,76 CPU_VME_WINDOW_A24_SIZE,77 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,78 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT79 },8081 {82 (void *) CPU_VME_WINDOW_A16_BASE,83 (void *) CPU_VME_WINDOW_A16_BASE,84 CPU_VME_WINDOW_A16_SIZE,85 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,86 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT87 },8889 {90 /*91 * Off-board VME LM/SIG/Semaphore Regs92 */93 (void *) CPU_VME_WINDOW_REG_BASE,94 (void *) CPU_VME_WINDOW_REG_BASE,95 CPU_VME_WINDOW_REG_SIZE,96 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,97 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT98 },99100 {101 (void *) FALCON_BASE_ADRS,

L-4

102 (void *) FALCON_BASE_ADRS,103 FALCON_REG_SIZE,104 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,105 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT106 },107108 {109 (void *) RAVEN_BASE_ADRS,110 (void *) RAVEN_BASE_ADRS,111 RAVEN_REG_SIZE,112 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,113 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT114 },115116 {117 (void *) FLASH_BASE_ADRS,118 (void *) FLASH_BASE_ADRS,119 FLASH_MEM_SIZE,120 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,121 VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT122 }123 };

L-5

Memory MapLOCAL_MEM_LOCAL_ADRS (0x0)

RAM_LOW_ADRS

CPU_PCI_IACK_ADRS

CPU_VME_WINDOW_A32_BASE



CPU_VME_WINDOW_REG_BASE

RAVEN_BASE_ADRS

CPU_PCI_MEM_ADRS

CPU_PCI_IO_ADRS

FALCON_BASE_ADRS

FLASH_BASE_ADRS

0xffffffff

L-6

sysBusProbe ()

1 /****************************************************************************23 * sysBusProbe - probe a bus address based on bus type.4 *5 * This routine is a function hook into vxMemProbe. It determines which bus,6 * VME, PCI or local is being probed based on the address to be probed.7 * If the VME bus is being probed, the sysVmeProbe() routine is called to do8 * the special VME probing. If the PCI bus is being probed, the sysPciProbe()9 * routine is called to do the special PCI probing. If the local bus is being10 * probed, the routine returns ERROR which indicates that the default local11 * bus probe in vxMemProbe() should be used.12 *13 * RETURNS: ERROR if local bus is being probed, OK if VME or PCI bus.14 */1516 STATUS sysBusProbe17 (18 char * adrs, /* address to be probed */19 int mode, /* VX_READ or VX_WRITE */20 int length, /* 1, 2 or 4 byte probe */21 char * pVal /* address of value to write OR */22 /* address of location to place value read */23 )24 {25 STATUS status;2627 /* Clear any existing errors/exceptions */2829 sysProbeErrClr ();3031 /* Handle VME bus in special manner */3233 if (IS_VME_ADDRESS(adrs))34 status = sysVmeProbe (adrs, mode, length, pVal);3536 /* Handle PCI bus in special manner */3738 else if (IS_PCI_ADDRESS(adrs))39 status = sysPciProbe (adrs, mode, length, pVal);4041 /* Handle local bus in architecture-specific manner */4243 else44 status = vxMemArchProbe (adrs, mode, length, pVal);4546 /* Clear any errors/exceptions before exiting */47

L-7

48 sysProbeErrClr ();4950 return (status);51 }

Tornado BSP Manual2

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