Tiva C Series TM4C1292NCPDT Microcontroller Data Sheet · TableofContents RevisionHistory.....44

Tiva™ TM4C1292NCPDT Microcontroller

DATA SHEET

Copyr ight © 2007-2013Texas Instruments Incorporated

DS-TM4C1292NCPDT-15638.2711SPMS431

TEXAS INSTRUMENTS-ADVANCE INFORMATION

CopyrightCopyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb areregistered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

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December 12, 20132Texas Instruments-Advance Information

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 44About This Document .................................................................................................................... 45Audience .............................................................................................................................................. 45About This Manual ................................................................................................................................ 45Related Documents ............................................................................................................................... 45Documentation Conventions .................................................................................................................. 46

1 Architectural Overview .......................................................................................... 481.1 Tiva™ C Series Overview .............................................................................................. 481.2 TM4C1292NCPDT Microcontroller Overview .................................................................. 491.3 TM4C1292NCPDT Microcontroller Features ................................................................... 521.3.1 ARM Cortex-M4F Processor Core .................................................................................. 521.3.2 On-Chip Memory ........................................................................................................... 541.3.3 External Peripheral Interface ......................................................................................... 561.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 581.3.5 Serial Communications Peripherals ................................................................................ 581.3.6 System Integration ........................................................................................................ 641.3.7 Advanced Motion Control ............................................................................................... 711.3.8 Analog .......................................................................................................................... 731.3.9 JTAG and ARM Serial Wire Debug ................................................................................ 741.3.10 Packaging and Temperature .......................................................................................... 751.4 TM4C1292NCPDT Microcontroller Hardware Details ....................................................... 751.5 Kits .............................................................................................................................. 761.6 Support Information ....................................................................................................... 76

2 The Cortex-M4F Processor ................................................................................... 772.1 Block Diagram .............................................................................................................. 782.2 Overview ...................................................................................................................... 792.2.1 System-Level Interface .................................................................................................. 792.2.2 Integrated Configurable Debug ...................................................................................... 792.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 802.2.4 Cortex-M4F System Component Details ......................................................................... 802.3 Programming Model ...................................................................................................... 812.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 812.3.2 Stacks .......................................................................................................................... 822.3.3 Register Map ................................................................................................................ 822.3.4 Register Descriptions .................................................................................................... 842.3.5 Exceptions and Interrupts ............................................................................................ 1002.3.6 Data Types ................................................................................................................. 1002.4 Memory Model ............................................................................................................ 1002.4.1 Memory Regions, Types and Attributes ......................................................................... 1042.4.2 Memory System Ordering of Memory Accesses ............................................................ 1042.4.3 Behavior of Memory Accesses ..................................................................................... 1042.4.4 Software Ordering of Memory Accesses ....................................................................... 1052.4.5 Bit-Banding ................................................................................................................. 1062.4.6 Data Storage .............................................................................................................. 1082.4.7 Synchronization Primitives ........................................................................................... 109

3December 12, 2013Texas Instruments-Advance Information


2.5 Exception Model ......................................................................................................... 1102.5.1 Exception States ......................................................................................................... 1112.5.2 Exception Types .......................................................................................................... 1112.5.3 Exception Handlers ..................................................................................................... 1162.5.4 Vector Table ................................................................................................................ 1162.5.5 Exception Priorities ...................................................................................................... 1172.5.6 Interrupt Priority Grouping ............................................................................................ 1172.5.7 Exception Entry and Return ......................................................................................... 1172.6 Fault Handling ............................................................................................................. 1202.6.1 Fault Types ................................................................................................................. 1212.6.2 Fault Escalation and Hard Faults .................................................................................. 1212.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1222.6.4 Lockup ....................................................................................................................... 1222.7 Power Management .................................................................................................... 1232.7.1 Entering Sleep Modes ................................................................................................. 1232.7.2 Wake Up from Sleep Mode .......................................................................................... 1232.8 Instruction Set Summary .............................................................................................. 124

3 Cortex-M4 Peripherals ......................................................................................... 1313.1 Functional Description ................................................................................................. 1313.1.1 System Timer (SysTick) ............................................................................................... 1323.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1333.1.3 System Control Block (SCB) ........................................................................................ 1343.1.4 Memory Protection Unit (MPU) ..................................................................................... 1343.1.5 Floating-Point Unit (FPU) ............................................................................................. 1393.2 Register Map .............................................................................................................. 1433.3 System Timer (SysTick) Register Descriptions .............................................................. 1463.4 NVIC Register Descriptions .......................................................................................... 1503.5 System Control Block (SCB) Register Descriptions ........................................................ 1603.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1893.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 198

4 JTAG Interface ...................................................................................................... 2044.1 Block Diagram ............................................................................................................ 2054.2 Signal Description ....................................................................................................... 2054.3 Functional Description ................................................................................................. 2064.3.1 JTAG Interface Pins ..................................................................................................... 2064.3.2 JTAG TAP Controller ................................................................................................... 2084.3.3 Shift Registers ............................................................................................................ 2094.3.4 Operational Considerations .......................................................................................... 2094.4 Initialization and Configuration ..................................................................................... 2124.5 Register Descriptions .................................................................................................. 2124.5.1 Instruction Register (IR) ............................................................................................... 2134.5.2 Data Registers ............................................................................................................ 214

5 System Control ..................................................................................................... 2175.1 Signal Description ....................................................................................................... 2175.2 Functional Description ................................................................................................. 2175.2.1 Device Identification .................................................................................................... 2175.2.2 Reset Control .............................................................................................................. 2185.2.3 Non-Maskable Interrupt ............................................................................................... 225


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5.2.4 Power Control ............................................................................................................. 2265.2.5 Clock Control .............................................................................................................. 2275.2.6 System Control ........................................................................................................... 2365.3 Initialization and Configuration ..................................................................................... 2435.4 Register Map .............................................................................................................. 2445.5 System Control Register Descriptions (System Control Offset) ....................................... 251

6 Processor Support and Exception Module ........................................................ 5126.1 Functional Description ................................................................................................. 5126.2 Register Map .............................................................................................................. 5126.3 Register Descriptions .................................................................................................. 512

7 Hibernation Module .............................................................................................. 5207.1 Block Diagram ............................................................................................................ 5227.2 Signal Description ....................................................................................................... 5227.3 Functional Description ................................................................................................. 5237.3.1 Register Access Timing ............................................................................................... 5247.3.2 Hibernation Clock Source ............................................................................................ 5247.3.3 System Implementation ............................................................................................... 5277.3.4 Battery Management ................................................................................................... 5287.3.5 Real-Time Clock .......................................................................................................... 5287.3.6 Tamper ....................................................................................................................... 5317.3.7 Battery-Backed Memory .............................................................................................. 5347.3.8 Power Control Using HIB ............................................................................................. 5347.3.9 Power Control Using VDD3ON Mode ........................................................................... 5357.3.10 Initiating Hibernate ...................................................................................................... 5357.3.11 Waking from Hibernate ................................................................................................ 5357.3.12 Arbitrary Power Removal ............................................................................................. 5367.3.13 Interrupts and Status ................................................................................................... 5377.4 Initialization and Configuration ..................................................................................... 5377.4.1 Initialization ................................................................................................................. 5377.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5387.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5387.4.4 External Wake-Up from Hibernation .............................................................................. 5397.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5407.4.6 Tamper Initialization ..................................................................................................... 5407.5 Register Map .............................................................................................................. 5407.6 Register Descriptions .................................................................................................. 542

8 Internal Memory ................................................................................................... 5898.1 Block Diagram ............................................................................................................ 5898.2 Functional Description ................................................................................................. 5918.2.1 SRAM ........................................................................................................................ 5918.2.2 ROM .......................................................................................................................... 5918.2.3 Flash Memory ............................................................................................................. 5938.2.4 EEPROM .................................................................................................................... 6048.2.5 Bus Matrix Memory Accesses ...................................................................................... 6098.3 Register Map .............................................................................................................. 6108.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 6128.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 6388.6 Memory Register Descriptions (System Control Offset) .................................................. 655



9 Micro Direct Memory Access (μDMA) ................................................................ 6669.1 Block Diagram ............................................................................................................ 6679.2 Functional Description ................................................................................................. 6679.2.1 Channel Assignments .................................................................................................. 6689.2.2 Priority ........................................................................................................................ 6699.2.3 Arbitration Size ............................................................................................................ 6709.2.4 Request Types ............................................................................................................ 6709.2.5 Channel Configuration ................................................................................................. 6719.2.6 Transfer Modes ........................................................................................................... 6739.2.7 Transfer Size and Increment ........................................................................................ 6819.2.8 Peripheral Interface ..................................................................................................... 6819.2.9 Software Request ........................................................................................................ 6829.2.10 Interrupts and Errors .................................................................................................... 6829.3 Initialization and Configuration ..................................................................................... 6829.3.1 Module Initialization ..................................................................................................... 6829.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6839.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6849.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6869.3.5 Configuring Channel Assignments ................................................................................ 6899.4 Register Map .............................................................................................................. 6899.5 μDMA Channel Control Structure ................................................................................. 6909.6 μDMA Register Descriptions ........................................................................................ 697

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 73010.1 Signal Description ....................................................................................................... 73110.2 Pad Capabilities .......................................................................................................... 73410.3 Functional Description ................................................................................................. 73510.3.1 Data Control ............................................................................................................... 73610.3.2 Interrupt Control .......................................................................................................... 73810.3.3 Mode Control .............................................................................................................. 73910.3.4 Commit Control ........................................................................................................... 74010.3.5 Pad Control ................................................................................................................. 74010.3.6 Identification ............................................................................................................... 74110.4 Initialization and Configuration ..................................................................................... 74110.5 Register Map .............................................................................................................. 74310.6 Register Descriptions .................................................................................................. 745

11 External Peripheral Interface (EPI) ..................................................................... 80211.1 EPI Block Diagram ...................................................................................................... 80311.2 Signal Description ....................................................................................................... 80411.3 Functional Description ................................................................................................. 80511.3.1 Master Access to EPI .................................................................................................. 80611.3.2 Non-Blocking Reads .................................................................................................... 80611.3.3 DMA Operation ........................................................................................................... 80711.4 Initialization and Configuration ..................................................................................... 80811.4.1 EPI Interface Options .................................................................................................. 80911.4.2 SDRAM Mode ............................................................................................................. 80911.4.3 Host Bus Mode ........................................................................................................... 81311.4.4 General-Purpose Mode ............................................................................................... 83411.5 Register Map .............................................................................................................. 841


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11.6 Register Descriptions .................................................................................................. 843

12 Cyclical Redundancy Check (CRC) .................................................................... 93312.1 Functional Description ................................................................................................. 93312.1.1 CRC Support .............................................................................................................. 93312.2 Initialization and Configuration ..................................................................................... 93512.2.1 CRC Initialization and Configuration ............................................................................. 93512.3 Register Map .............................................................................................................. 93612.4 CRC Module Register Descriptions .............................................................................. 936

13 General-Purpose Timers ...................................................................................... 94213.1 Block Diagram ............................................................................................................ 94313.2 Signal Description ....................................................................................................... 94413.3 Functional Description ................................................................................................. 94513.3.1 GPTM Reset Conditions .............................................................................................. 94613.3.2 Timer Clock Source ..................................................................................................... 94613.3.3 Timer Modes ............................................................................................................... 94613.3.4 Wait-for-Trigger Mode .................................................................................................. 95513.3.5 Synchronizing GP Timer Blocks ................................................................................... 95613.3.6 DMA Operation ........................................................................................................... 95713.3.7 ADC Operation ............................................................................................................ 95713.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 95713.4 Initialization and Configuration ..................................................................................... 95813.4.1 One-Shot/Periodic Timer Mode .................................................................................... 95813.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 95913.4.3 Input Edge-Count Mode ............................................................................................... 95913.4.4 Input Edge Time Mode ................................................................................................. 96013.4.5 PWM Mode ................................................................................................................. 96013.5 Register Map .............................................................................................................. 96113.6 Register Descriptions .................................................................................................. 962

14 Watchdog Timers ............................................................................................... 101414.1 Block Diagram ........................................................................................................... 101514.2 Functional Description ............................................................................................... 101514.2.1 Register Access Timing ............................................................................................. 101614.3 Initialization and Configuration .................................................................................... 101614.4 Register Map ............................................................................................................ 101614.5 Register Descriptions ................................................................................................. 1017

15 Analog-to-Digital Converter (ADC) ................................................................... 103915.1 Block Diagram ........................................................................................................... 104015.2 Signal Description ..................................................................................................... 104115.3 Functional Description ............................................................................................... 104215.3.1 Sample Sequencers .................................................................................................. 104215.3.2 Module Control .......................................................................................................... 104315.3.3 Hardware Sample Averaging Circuit ........................................................................... 104815.3.4 Analog-to-Digital Converter ........................................................................................ 104915.3.5 Differential Sampling .................................................................................................. 105215.3.6 Internal Temperature Sensor ...................................................................................... 105415.3.7 Digital Comparator Unit .............................................................................................. 105515.4 Initialization and Configuration .................................................................................... 1059



15.4.1 Module Initialization ................................................................................................... 105915.4.2 Sample Sequencer Configuration ............................................................................... 106015.5 Register Map ............................................................................................................ 106015.6 Register Descriptions ................................................................................................. 1063

16 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 114816.1 Block Diagram ........................................................................................................... 114916.2 Signal Description ..................................................................................................... 114916.3 Functional Description ............................................................................................... 115116.3.1 Transmit/Receive Logic .............................................................................................. 115116.3.2 Baud-Rate Generation ............................................................................................... 115216.3.3 Data Transmission ..................................................................................................... 115316.3.4 Serial IR (SIR) ........................................................................................................... 115316.3.5 ISO 7816 Support ...................................................................................................... 115416.3.6 Modem Handshake Support ....................................................................................... 115516.3.7 9-Bit UART Mode ...................................................................................................... 115616.3.8 FIFO Operation ......................................................................................................... 115616.3.9 Interrupts .................................................................................................................. 115716.3.10 Loopback Operation .................................................................................................. 115816.3.11 DMA Operation ......................................................................................................... 115816.4 Initialization and Configuration .................................................................................... 115816.5 Register Map ............................................................................................................ 116016.6 Register Descriptions ................................................................................................. 1161

17 Quad Synchronous Serial Interface (QSSI) ..................................................... 121317.1 Block Diagram ........................................................................................................... 121317.2 Signal Description ..................................................................................................... 121417.3 Functional Description ............................................................................................... 121617.3.1 Bit Rate Generation ................................................................................................... 121617.3.2 FIFO Operation ......................................................................................................... 121617.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 121717.3.4 SSInFSS Function ..................................................................................................... 121817.3.5 High Speed Clock Operation ...................................................................................... 121917.3.6 Interrupts .................................................................................................................. 121917.3.7 Frame Formats ......................................................................................................... 122017.3.8 DMA Operation ......................................................................................................... 122717.4 Initialization and Configuration .................................................................................... 122717.4.1 Enhanced Mode Configuration ................................................................................... 122917.5 Register Map ............................................................................................................ 122917.6 Register Descriptions ................................................................................................. 1230

18 Inter-Integrated Circuit (I2C) Interface .............................................................. 126218.1 Block Diagram ........................................................................................................... 126318.2 Signal Description ..................................................................................................... 126418.3 Functional Description ............................................................................................... 126518.3.1 I2C Bus Functional Overview ...................................................................................... 126518.3.2 Available Speed Modes ............................................................................................. 127118.3.3 Interrupts .................................................................................................................. 127318.3.4 Loopback Operation .................................................................................................. 127418.3.5 FIFO and µDMA Operation ........................................................................................ 127418.3.6 Command Sequence Flow Charts .............................................................................. 1276


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18.4 Initialization and Configuration .................................................................................... 128418.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 128418.4.2 Configure the I2C Master to High Speed Mode ............................................................ 128518.5 Register Map ............................................................................................................ 128618.6 Register Descriptions (I2C Master) .............................................................................. 128818.7 Register Descriptions (I2C Slave) ............................................................................... 131718.8 Register Descriptions (I2C Status and Control) ............................................................ 1334

19 Controller Area Network (CAN) Module ........................................................... 134319.1 Block Diagram ........................................................................................................... 134419.2 Signal Description ..................................................................................................... 134419.3 Functional Description ............................................................................................... 134519.3.1 Initialization ............................................................................................................... 134619.3.2 Operation .................................................................................................................. 134619.3.3 Transmitting Message Objects ................................................................................... 134719.3.4 Configuring a Transmit Message Object ...................................................................... 134819.3.5 Updating a Transmit Message Object ......................................................................... 134919.3.6 Accepting Received Message Objects ........................................................................ 134919.3.7 Receiving a Data Frame ............................................................................................ 135019.3.8 Receiving a Remote Frame ........................................................................................ 135019.3.9 Receive/Transmit Priority ........................................................................................... 135019.3.10 Configuring a Receive Message Object ...................................................................... 135119.3.11 Handling of Received Message Objects ...................................................................... 135219.3.12 Handling of Interrupts ................................................................................................ 135419.3.13 Test Mode ................................................................................................................. 135519.3.14 Bit Timing Configuration Error Considerations ............................................................. 135719.3.15 Bit Time and Bit Rate ................................................................................................. 135719.3.16 Calculating the Bit Timing Parameters ........................................................................ 135919.4 Register Map ............................................................................................................ 136219.5 CAN Register Descriptions ......................................................................................... 1363

20 Ethernet Controller ............................................................................................ 139420.1 Block Diagram ........................................................................................................... 139520.2 Signal Description ..................................................................................................... 139520.3 Functional Description ............................................................................................... 139620.3.1 Ethernet Clock Control ............................................................................................... 139620.3.2 MII/RMII Interface Signals .......................................................................................... 139820.3.3 DMA Controller ......................................................................................................... 139920.3.4 Descriptors ............................................................................................................... 141220.3.5 TX/RX Controller ....................................................................................................... 143120.3.6 MAC Operation ......................................................................................................... 143520.3.7 IEEE 1588 and Advanced Timestamp Function ........................................................... 143820.3.8 Frame Filtering .......................................................................................................... 144620.3.9 Source Address, VLAN, and CRC Insertion, Replacement or Deletion .......................... 144720.3.10 Checksum Offload Engine .......................................................................................... 144920.3.11 MAC Management Counters ...................................................................................... 145020.3.12 Power Management Module ....................................................................................... 145020.3.13 Serial Management Interface ..................................................................................... 145320.3.14 Reduced Media Independent Interface (RMII) ............................................................. 145320.3.15 Interrupt Configuration ............................................................................................... 1454



20.4 EMAC Initialization and Configuration ......................................................................... 145420.5 Register Map ............................................................................................................ 145520.6 Ethernet MAC Register Descriptions ........................................................................... 1458

21 Universal Serial Bus (USB) Controller ............................................................. 157821.1 Block Diagram ........................................................................................................... 157921.2 Signal Description ..................................................................................................... 157921.3 Register Map ............................................................................................................ 1580

22 Analog Comparators .......................................................................................... 158722.1 Block Diagram ........................................................................................................... 158822.2 Signal Description ..................................................................................................... 158822.3 Functional Description ............................................................................................... 158922.3.1 Internal Reference Programming ................................................................................ 159022.4 Initialization and Configuration .................................................................................... 159222.5 Register Map ............................................................................................................ 159322.6 Register Descriptions ................................................................................................. 1593

23 Pulse Width Modulator (PWM) .......................................................................... 160323.1 Block Diagram ........................................................................................................... 160423.2 Signal Description ..................................................................................................... 160623.3 Functional Description ............................................................................................... 160623.3.1 Clock Configuration ................................................................................................... 160623.3.2 PWM Timer ............................................................................................................... 160623.3.3 PWM Comparators .................................................................................................... 160723.3.4 PWM Signal Generator .............................................................................................. 160823.3.5 Dead-Band Generator ............................................................................................... 160923.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 160923.3.7 Synchronization Methods .......................................................................................... 161023.3.8 Fault Conditions ........................................................................................................ 161123.3.9 Output Control Block .................................................................................................. 161223.4 Initialization and Configuration .................................................................................... 161223.5 Register Map ............................................................................................................ 161323.6 Register Descriptions ................................................................................................. 1616

24 Quadrature Encoder Interface (QEI) ................................................................. 168224.1 Block Diagram ........................................................................................................... 168224.2 Signal Description ..................................................................................................... 168424.3 Functional Description ............................................................................................... 168424.4 Initialization and Configuration .................................................................................... 168724.5 Register Map ............................................................................................................ 168724.6 Register Descriptions ................................................................................................. 1688

25 Pin Diagram ........................................................................................................ 170526 Signal Tables ...................................................................................................... 170626.1 Signals by Pin Number .............................................................................................. 170726.2 Signals by Signal Name ............................................................................................. 172026.3 Signals by Function, Except for GPIO ......................................................................... 173226.4 GPIO Pins and Alternate Functions ............................................................................ 174426.5 Possible Pin Assignments for Alternate Functions ....................................................... 174826.6 Connections for Unused Signals ................................................................................. 1753


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27 Electrical Characteristics .................................................................................. 175527.1 Maximum Ratings ...................................................................................................... 175527.2 Operating Characteristics ........................................................................................... 175627.3 Recommended Operating Conditions ......................................................................... 175727.3.1 DC Operating Conditions ........................................................................................... 175727.3.2 Recommended GPIO Operating Characteristics .......................................................... 175727.4 Load Conditions ........................................................................................................ 175927.5 JTAG and Boundary Scan .......................................................................................... 176027.6 Power and Brown-Out ............................................................................................... 176127.6.1 VDDA Levels .............................................................................................................. 176227.6.2 VDD Levels ................................................................................................................ 176327.6.3 VDDC Levels .............................................................................................................. 176427.6.4 Response ................................................................................................................. 176527.7 Reset ........................................................................................................................ 176627.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 176827.9 Clocks ...................................................................................................................... 176927.9.1 PLL Specifications ..................................................................................................... 176927.9.2 PIOSC Specifications ................................................................................................ 177127.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 177127.9.4 Hibernation Clock Source Specifications ..................................................................... 177127.9.5 Main Oscillator Specifications ..................................................................................... 177227.9.6 System Clock Specification with ADC Operation .......................................................... 177627.9.7 System Clock Specification with USB Operation .......................................................... 177627.10 Sleep Modes ............................................................................................................. 177627.11 Hibernation Module ................................................................................................... 177727.12 Flash Memory ........................................................................................................... 177827.13 EEPROM .................................................................................................................. 177927.14 Input/Output Pin Characteristics ................................................................................. 178027.14.1 Types of I/O Pins and ESD Protection ......................................................................... 178227.15 External Peripheral Interface (EPI) .............................................................................. 178327.16 Analog-to-Digital Converter (ADC) .............................................................................. 179027.17 Synchronous Serial Interface (SSI) ............................................................................. 179627.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 179927.19 Ethernet Controller .................................................................................................... 180027.19.1 Clock Characteristics ................................................................................................. 180027.19.2 AC Characteristics ..................................................................................................... 180127.20 Universal Serial Bus (USB) Controller ......................................................................... 180427.21 Analog Comparator ................................................................................................... 180527.22 Current Consumption ................................................................................................. 1807

A Package Information .......................................................................................... 1810A.1 Orderable Devices ..................................................................................................... 1810A.2 Part Markings ............................................................................................................ 1811A.3 Packaging Diagram ................................................................................................... 1812A.4 Packaging Materials .................................................................................................. 1813



List of FiguresFigure 1-1. Tiva™ TM4C1292NCPDT Microcontroller High-Level Block Diagram ....................... 51Figure 2-1. CPU Block Diagram ............................................................................................. 79Figure 2-2. TPIU Block Diagram ............................................................................................ 80Figure 2-3. Cortex-M4F Register Set ...................................................................................... 83Figure 2-4. Bit-Band Mapping .............................................................................................. 108Figure 2-5. Data Storage ..................................................................................................... 109Figure 2-6. Vector Table ...................................................................................................... 116Figure 2-7. Exception Stack Frame ...................................................................................... 119Figure 3-1. SRD Use Example ............................................................................................. 137Figure 3-2. FPU Register Bank ............................................................................................ 140Figure 4-1. JTAG Module Block Diagram .............................................................................. 205Figure 4-2. Test Access Port State Machine ......................................................................... 209Figure 4-3. IDCODE Register Format ................................................................................... 215Figure 4-4. BYPASS Register Format ................................................................................... 215Figure 4-5. Boundary Scan Register Format ......................................................................... 215Figure 5-1. Basic RST Configuration .................................................................................... 221Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 221Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 221Figure 5-4. Power Architecture ............................................................................................ 226Figure 5-5. Main Clock Tree ................................................................................................ 230Figure 5-6. Module Clock Selection ...................................................................................... 239Figure 7-1. Hibernation Module Block Diagram ..................................................................... 522Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 526Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 526Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 527Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 531Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 531Figure 7-7. Tamper Block Diagram ....................................................................................... 531Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 532Figure 8-1. Internal Memory Block Diagram .......................................................................... 590Figure 8-2. Flash Memory Configuration ............................................................................... 594Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 595Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 595Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 596Figure 8-6. Prefetch Fills from Flash ..................................................................................... 597Figure 8-7. Mirror Mode Function ......................................................................................... 598Figure 9-1. μDMA Block Diagram ......................................................................................... 667Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 674Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 676Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 677Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 679Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 680Figure 10-1. Digital I/O Pads ................................................................................................. 735Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 736Figure 10-3. GPIODATA Write Example ................................................................................. 737


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Figure 10-4. GPIODATA Read Example ................................................................................. 737Figure 11-1. EPI Block Diagram ............................................................................................. 804Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 811Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 812Figure 11-4. SDRAM Write Cycle ........................................................................................... 813Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 823Figure 11-6. iRDY Signal Connection ..................................................................................... 823Figure 11-7. PSRAM Burst Read ........................................................................................... 826Figure 11-8. PSRAM Burst Write ........................................................................................... 826Figure 11-9. Read Delay During Refresh Event ...................................................................... 827Figure 11-10. Write Delay During Refresh Event ....................................................................... 828Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 829Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 832Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 832Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 833Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or

Quad CSn ......................................................................................................... 833Figure 11-16. Continuous Read Mode Accesses ...................................................................... 833Figure 11-17. Write Followed by Read to External FIFO ............................................................ 834Figure 11-18. Two-Entry FIFO ................................................................................................. 834Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 837Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 838Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 838Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 839Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 839Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 839Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 839Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 840Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 840Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 840Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 841Figure 13-1. GPTM Module Block Diagram ............................................................................ 943Figure 13-2. Input Edge-Count Mode Example, Counting Down ............................................... 951Figure 13-3. 16-Bit Input Edge-Time Mode Example ............................................................... 952Figure 13-4. 16-Bit PWM Mode Example ................................................................................ 954Figure 13-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 954Figure 13-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 955Figure 13-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 955Figure 13-8. Timer Daisy Chain ............................................................................................. 956Figure 14-1. WDT Module Block Diagram ............................................................................. 1015Figure 15-1. Implementation of Two ADC Blocks .................................................................. 1040Figure 15-2. ADC Module Block Diagram ............................................................................. 1041Figure 15-3. ADC Sample Phases ....................................................................................... 1046Figure 15-4. Doubling the ADC Sample Rate ........................................................................ 1046Figure 15-5. Skewed Sampling ............................................................................................ 1047Figure 15-6. Sample Averaging Example .............................................................................. 1049Figure 15-7. ADC Input Equivalency Diagram ....................................................................... 1050



Figure 15-8. ADC Voltage Reference ................................................................................... 1051Figure 15-9. ADC Conversion Result ................................................................................... 1052Figure 15-10. Differential Voltage Representation ................................................................... 1054Figure 15-11. Internal Temperature Sensor Characteristic ....................................................... 1055Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1057Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1058Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1059Figure 16-1. UART Module Block Diagram ........................................................................... 1149Figure 16-2. UART Character Frame .................................................................................... 1152Figure 16-3. IrDA Data Modulation ....................................................................................... 1154Figure 17-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1214Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1221Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1222Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1223Figure 17-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1223Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1224Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1225Figure 17-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1225Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1226Figure 18-1. I2C Block Diagram ........................................................................................... 1263Figure 18-2. I2C Bus Configuration ....................................................................................... 1265Figure 18-3. START and STOP Conditions ........................................................................... 1266Figure 18-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1266Figure 18-5. R/S Bit in First Byte .......................................................................................... 1267Figure 18-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1267Figure 18-7. High-Speed Data Format .................................................................................. 1273Figure 18-8. Master Single TRANSMIT ................................................................................ 1277Figure 18-9. Master Single RECEIVE ................................................................................... 1278Figure 18-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1279Figure 18-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1280Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1281Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1282Figure 18-14. Standard High Speed Mode Master Transmit ..................................................... 1283Figure 18-15. Slave Command Sequence .............................................................................. 1284Figure 19-1. CAN Controller Block Diagram .......................................................................... 1344Figure 19-2. CAN Data/Remote Frame ................................................................................. 1345Figure 19-3. Message Objects in a FIFO Buffer .................................................................... 1354Figure 19-4. CAN Bit Time ................................................................................................... 1358Figure 20-1. Ethernet MAC ................................................................................................. 1395Figure 20-2. MII Clock Structure .......................................................................................... 1397Figure 20-3. RMII Clock Structure ........................................................................................ 1398Figure 20-4. TX DMA Default Operation Using Normal Descriptors ........................................ 1404Figure 20-5. TX DMA OSF Mode Operation Using Normal Descriptors ................................... 1406Figure 20-6. RX DMA Operation Flow .................................................................................. 1409Figure 20-7. Normal Receive and Transmit Descriptor Configuration ...................................... 1412Figure 20-8. Enhanced Transmit Descriptor Structure ........................................................... 1421Figure 20-9. Enhanced Receive Descriptor Structure ............................................................ 1426Figure 20-10. Networked Time Synchronization ...................................................................... 1438


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Figure 20-11. System Time Update Using Fine Correction Method .......................................... 1440Figure 20-12. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path

Correction ....................................................................................................... 1443Figure 20-13. Wake-Up Frame Filter Register Bank ................................................................ 1451Figure 21-1. USB Module Block Diagram ............................................................................. 1579Figure 22-1. Analog Comparator Module Block Diagram ....................................................... 1588Figure 22-2. Structure of Comparator Unit ............................................................................ 1589Figure 22-3. Comparator Internal Reference Structure .......................................................... 1590Figure 23-1. PWM Module Diagram ..................................................................................... 1605Figure 23-2. PWM Generator Block Diagram ........................................................................ 1605Figure 23-3. PWM Count-Down Mode .................................................................................. 1608Figure 23-4. PWM Count-Up/Down Mode ............................................................................. 1608Figure 23-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1609Figure 23-6. PWM Dead-Band Generator ............................................................................. 1609Figure 24-1. QEI Block Diagram .......................................................................................... 1683Figure 24-2. QEI Input Signal Logic ...................................................................................... 1684Figure 24-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1686Figure 25-1. 128-Pin TQFP Package Pin Diagram ................................................................ 1705Figure 27-1. Load Conditions ............................................................................................... 1759Figure 27-2. JTAG Test Clock Input Timing ........................................................................... 1761Figure 27-3. JTAG Test Access Port (TAP) Timing ................................................................ 1761Figure 27-4. Power and Brown-Out Assertions vs VDDA Levels .............................................. 1763Figure 27-5. Power and Brown-Out Assertions vs VDD Levels ................................................ 1764Figure 27-6. POK Assertion vs VDDC ................................................................................... 1765Figure 27-7. POR-BOR VDD Glitch Response ....................................................................... 1765Figure 27-8. POR-BOR VDD Droop Response ...................................................................... 1766Figure 27-9. Digital Power-On Reset Timing ......................................................................... 1767Figure 27-10. Brown-Out Reset Timing .................................................................................. 1767Figure 27-11. External Reset Timing (RST) ............................................................................ 1767Figure 27-12. Software Reset Timing ..................................................................................... 1768Figure 27-13. Watchdog Reset Timing ................................................................................... 1768Figure 27-14. MOSC Failure Reset Timing ............................................................................. 1768Figure 27-15. Hibernation Module Timing ............................................................................... 1778Figure 27-16. ESD Protection ................................................................................................ 1782Figure 27-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1783Figure 27-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1784Figure 27-19. SDRAM Read Timing ....................................................................................... 1785Figure 27-20. SDRAM Write Timing ....................................................................................... 1785Figure 27-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1786Figure 27-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1786Figure 27-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1787Figure 27-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1787Figure 27-25. General-Purpose Mode Read and Write Timing ................................................. 1788Figure 27-26. PSRAM Single Burst Read ............................................................................... 1789Figure 27-27. PSRAM Single Burst Write ............................................................................... 1790Figure 27-28. ADC External Reference Filtering ..................................................................... 1796Figure 27-29. ADC Input Equivalency Diagram ....................................................................... 1796



Figure 27-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer TimingMeasurement .................................................................................................. 1797

Figure 27-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1798Figure 27-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1798Figure 27-33. I2C Timing ....................................................................................................... 1800Figure 27-34. MOSC Crystal Characteristics for Ethernet ........................................................ 1800Figure 27-35. Single-Ended MOSC Characteristics for Ethernet .............................................. 1801Figure 27-36. EN0RREF_CLK 50-MHz Oscillator Characteristics ............................................ 1801Figure 27-37. Station Management Write and Read Timing ..................................................... 1802Figure 27-38. 100 Mb/s MII Transmit Timing ........................................................................... 1802Figure 27-39. 100 Mb/s MII Receive Timing ............................................................................ 1803Figure 27-40. 10 Mb/s MII Transmit Timing ............................................................................. 1803Figure 27-41. 10 Mb/s MII Receive Timing ............................................................................. 1803Figure 27-42. RMII Transmit Timing ....................................................................................... 1804Figure 27-43. RMII Receive Timing ........................................................................................ 1804Figure 27-44. ULPI Interface Timing Diagram ......................................................................... 1805Figure A-1. Key to Part Numbers ........................................................................................ 1810Figure A-2. TM4C1292NCPDT 128-Pin TQFP Package Diagram ......................................... 1812Figure A-3. 128-Pin TQFP PDT Package Carrier Tape ......................................................... 1813Figure A-4. 128-Pin TQFP PDT Package Plastic Reel ......................................................... 1814Figure A-5. 128-Pin TQFP PDT Package Tape and Reel Box ............................................... 1815


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List of TablesTable 1. Revision History .................................................................................................. 44Table 2. Documentation Conventions ................................................................................ 46Table 1-1. TM4C1292NCPDT Microcontroller Features .......................................................... 49Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 82Table 2-2. Processor Register Map ....................................................................................... 83Table 2-3. PSR Register Combinations ................................................................................. 89Table 2-4. Memory Map ..................................................................................................... 100Table 2-5. Memory Access Behavior ................................................................................... 104Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 106Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 107Table 2-8. Exception Types ................................................................................................ 112Table 2-9. Interrupts .......................................................................................................... 113Table 2-10. Exception Return Behavior ................................................................................. 120Table 2-11. Faults ............................................................................................................... 121Table 2-12. Fault Status and Fault Address Registers ............................................................ 122Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 124Table 3-1. Core Peripheral Register Regions ....................................................................... 131Table 3-2. Memory Attributes Summary .............................................................................. 135Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 137Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 138Table 3-5. AP Bit Field Encoding ........................................................................................ 138Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 139Table 3-7. QNaN and SNaN Handling ................................................................................. 142Table 3-8. Peripherals Register Map ................................................................................... 143Table 3-9. Interrupt Priority Levels ...................................................................................... 168Table 3-10. Example SIZE Field Values ................................................................................ 196Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 205Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 207Table 4-3. JTAG Instruction Register Commands ................................................................. 213Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 217Table 5-2. Reset Sources ................................................................................................... 218Table 5-3. Clock Source Options ........................................................................................ 228Table 5-4. Clock Source State Following POR ..................................................................... 228Table 5-5. System Clock Frequency ................................................................................... 233Table 5-6. System Divisor Factors for fvco=480 MHz ............................................................ 235Table 5-7. Actual PLL Frequency ........................................................................................ 235Table 5-8. Peripheral Memory Power Control ...................................................................... 240Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 241Table 5-10. MOSC Configurations ........................................................................................ 244Table 5-11. System Control Register Map ............................................................................. 245Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 274Table 5-13. MOSC Configurations ........................................................................................ 278Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 297Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 300Table 5-16. Module Power Control ........................................................................................ 444Table 5-17. Module Power Control ........................................................................................ 446



Table 5-18. Module Power Control ........................................................................................ 449Table 5-19. Module Power Control ........................................................................................ 454Table 5-20. Module Power Control ........................................................................................ 456Table 5-21. Module Power Control ........................................................................................ 458Table 5-22. Module Power Control ........................................................................................ 460Table 5-23. Module Power Control ........................................................................................ 463Table 5-24. Module Power Control ........................................................................................ 465Table 5-25. Module Power Control ........................................................................................ 469Table 5-26. Module Power Control ........................................................................................ 471Table 5-27. Module Power Control ........................................................................................ 473Table 5-28. Module Power Control ........................................................................................ 475Table 5-29. Module Power Control ........................................................................................ 477Table 5-30. Module Power Control ........................................................................................ 479Table 5-31. Module Power Control ........................................................................................ 481Table 5-32. Module Power Control ........................................................................................ 483Table 5-33. Module Power Control ........................................................................................ 485Table 6-1. System Exception Register Map ......................................................................... 512Table 7-1. Hibernate Signals (128TQFP) ............................................

Tiva C Series TM4C1292NCPDT Microcontroller Data Sheet · TableofContents RevisionHistory.....44

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Transcript of Tiva C Series TM4C1292NCPDT Microcontroller Data Sheet · TableofContents RevisionHistory.....44