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Stellaris® LM3S1R21 Microcontroller

DATA SHEET

Copyr ight © 2007-2010Texas Instruments Incorporated

DS-LM3S1R21-8832

TEXAS INSTRUMENTS-ADVANCE INFORMATION

CopyrightCopyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas InstrumentsIncorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as theproperty of others.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specificationsare subject to change without notice.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductorproducts and disclaimers thereto appears at the end of this data sheet.

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December 02, 20102Texas Instruments-Advance Information

Table of ContentsRevision History ............................................................................................................................. 27About This Document .................................................................................................................... 34Audience .............................................................................................................................................. 34About This Manual ................................................................................................................................ 34Related Documents ............................................................................................................................... 34Documentation Conventions .................................................................................................................. 35

1 Architectural Overview .......................................................................................... 371.1 Functional Overview ...................................................................................................... 391.1.1 ARM Cortex™-M3 ......................................................................................................... 391.1.2 On-Chip Memory ........................................................................................................... 411.1.3 External Peripheral Interface ......................................................................................... 421.1.4 Serial Communications Peripherals ................................................................................ 431.1.5 System Integration ........................................................................................................ 461.1.6 Analog .......................................................................................................................... 521.1.7 JTAG and ARM Serial Wire Debug ................................................................................ 531.1.8 Packaging and Temperature .......................................................................................... 541.2 Target Applications ........................................................................................................ 541.3 High-Level Block Diagram ............................................................................................. 551.4 Hardware Details .......................................................................................................... 57

2 The Cortex-M3 Processor ...................................................................................... 582.1 Block Diagram .............................................................................................................. 592.2 Overview ...................................................................................................................... 602.2.1 System-Level Interface .................................................................................................. 602.2.2 Integrated Configurable Debug ...................................................................................... 602.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 612.2.4 Cortex-M3 System Component Details ........................................................................... 612.3 Programming Model ...................................................................................................... 622.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 622.3.2 Stacks .......................................................................................................................... 622.3.3 Register Map ................................................................................................................ 632.3.4 Register Descriptions .................................................................................................... 642.3.5 Exceptions and Interrupts .............................................................................................. 772.3.6 Data Types ................................................................................................................... 772.4 Memory Model .............................................................................................................. 772.4.1 Memory Regions, Types and Attributes ........................................................................... 792.4.2 Memory System Ordering of Memory Accesses .............................................................. 792.4.3 Behavior of Memory Accesses ....................................................................................... 802.4.4 Software Ordering of Memory Accesses ......................................................................... 802.4.5 Bit-Banding ................................................................................................................... 822.4.6 Data Storage ................................................................................................................ 842.4.7 Synchronization Primitives ............................................................................................. 842.5 Exception Model ........................................................................................................... 852.5.1 Exception States ........................................................................................................... 862.5.2 Exception Types ............................................................................................................ 862.5.3 Exception Handlers ....................................................................................................... 89

3December 02, 2010Texas Instruments-Advance Information


2.5.4 Vector Table .................................................................................................................. 892.5.5 Exception Priorities ....................................................................................................... 902.5.6 Interrupt Priority Grouping .............................................................................................. 912.5.7 Exception Entry and Return ........................................................................................... 912.6 Fault Handling .............................................................................................................. 932.6.1 Fault Types ................................................................................................................... 932.6.2 Fault Escalation and Hard Faults .................................................................................... 942.6.3 Fault Status Registers and Fault Address Registers ........................................................ 952.6.4 Lockup ......................................................................................................................... 952.7 Power Management ...................................................................................................... 952.7.1 Entering Sleep Modes ................................................................................................... 962.7.2 Wake Up from Sleep Mode ............................................................................................ 962.8 Instruction Set Summary ............................................................................................... 97

3 Cortex-M3 Peripherals ......................................................................................... 1003.1 Functional Description ................................................................................................. 1003.1.1 System Timer (SysTick) ............................................................................................... 1003.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1013.1.3 System Control Block (SCB) ........................................................................................ 1033.1.4 Memory Protection Unit (MPU) ..................................................................................... 1033.2 Register Map .............................................................................................................. 1083.3 System Timer (SysTick) Register Descriptions .............................................................. 1103.4 NVIC Register Descriptions .......................................................................................... 1143.5 System Control Block (SCB) Register Descriptions ........................................................ 1273.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 156

4 JTAG Interface ...................................................................................................... 1664.1 Block Diagram ............................................................................................................ 1674.2 Signal Description ....................................................................................................... 1674.3 Functional Description ................................................................................................. 1684.3.1 JTAG Interface Pins ..................................................................................................... 1684.3.2 JTAG TAP Controller ................................................................................................... 1704.3.3 Shift Registers ............................................................................................................ 1704.3.4 Operational Considerations .......................................................................................... 1714.4 Initialization and Configuration ..................................................................................... 1734.5 Register Descriptions .................................................................................................. 1744.5.1 Instruction Register (IR) ............................................................................................... 1744.5.2 Data Registers ............................................................................................................ 176

5 System Control ..................................................................................................... 1785.1 Signal Description ....................................................................................................... 1785.2 Functional Description ................................................................................................. 1785.2.1 Device Identification .................................................................................................... 1795.2.2 Reset Control .............................................................................................................. 1795.2.3 Non-Maskable Interrupt ............................................................................................... 1865.2.4 Power Control ............................................................................................................. 1875.2.5 Clock Control .............................................................................................................. 1875.2.6 System Control ........................................................................................................... 1945.3 Initialization and Configuration ..................................................................................... 1965.4 Register Map .............................................................................................................. 1965.5 Register Descriptions .................................................................................................. 198


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6 Hibernation Module .............................................................................................. 2736.1 Block Diagram ............................................................................................................ 2746.2 Signal Description ....................................................................................................... 2746.3 Functional Description ................................................................................................. 2756.3.1 Register Access Timing ............................................................................................... 2766.3.2 Hibernation Clock Source ............................................................................................ 2766.3.3 Battery Management ................................................................................................... 2786.3.4 Real-Time Clock .......................................................................................................... 2786.3.5 Non-Volatile Memory ................................................................................................... 2796.3.6 Power Control Using HIB ............................................................................................. 2796.3.7 Power Control Using VDD3ON Mode ........................................................................... 2796.3.8 Initiating Hibernate ...................................................................................................... 2796.3.9 Interrupts and Status ................................................................................................... 2806.4 Initialization and Configuration ..................................................................................... 2806.4.1 Initialization ................................................................................................................. 2806.4.2 RTC Match Functionality (No Hibernation) .................................................................... 2816.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 2816.4.4 External Wake-Up from Hibernation .............................................................................. 2826.4.5 RTC or External Wake-Up from Hibernation .................................................................. 2826.4.6 Register Reset ............................................................................................................ 2826.5 Register Map .............................................................................................................. 2836.6 Register Descriptions .................................................................................................. 283

7 Internal Memory ................................................................................................... 3007.1 Block Diagram ............................................................................................................ 3007.2 Functional Description ................................................................................................. 3007.2.1 SRAM ........................................................................................................................ 3017.2.2 ROM .......................................................................................................................... 3017.2.3 Flash Memory ............................................................................................................. 3037.3 Flash Memory Initialization and Configuration ............................................................... 3057.3.1 Flash Memory Programming ........................................................................................ 3057.3.2 32-Word Flash Memory Write Buffer ............................................................................. 3067.3.3 Nonvolatile Register Programming ............................................................................... 3077.4 Register Map .............................................................................................................. 3087.5 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 3097.6 Memory Register Descriptions (System Control Offset) .................................................. 321

8 Micro Direct Memory Access (μDMA) ................................................................ 3378.1 Block Diagram ............................................................................................................ 3388.2 Functional Description ................................................................................................. 3388.2.1 Channel Assignments .................................................................................................. 3398.2.2 Priority ........................................................................................................................ 3408.2.3 Arbitration Size ............................................................................................................ 3408.2.4 Request Types ............................................................................................................ 3408.2.5 Channel Configuration ................................................................................................. 3418.2.6 Transfer Modes ........................................................................................................... 3438.2.7 Transfer Size and Increment ........................................................................................ 3518.2.8 Peripheral Interface ..................................................................................................... 3518.2.9 Software Request ........................................................................................................ 3518.2.10 Interrupts and Errors .................................................................................................... 352



8.3 Initialization and Configuration ..................................................................................... 3528.3.1 Module Initialization ..................................................................................................... 3528.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 3528.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 3548.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 3558.3.5 Configuring Channel Assignments ................................................................................ 3588.4 Register Map .............................................................................................................. 3588.5 μDMA Channel Control Structure ................................................................................. 3598.6 μDMA Register Descriptions ........................................................................................ 366

9 General-Purpose Input/Outputs (GPIOs) ........................................................... 3959.1 Signal Description ....................................................................................................... 3959.2 Functional Description ................................................................................................. 4009.2.1 Data Control ............................................................................................................... 4019.2.2 Interrupt Control .......................................................................................................... 4029.2.3 Mode Control .............................................................................................................. 4039.2.4 Commit Control ........................................................................................................... 4039.2.5 Pad Control ................................................................................................................. 4049.2.6 Identification ............................................................................................................... 4049.3 Initialization and Configuration ..................................................................................... 4049.4 Register Map .............................................................................................................. 4059.5 Register Descriptions .................................................................................................. 408

10 External Peripheral Interface (EPI) ..................................................................... 45110.1 EPI Block Diagram ...................................................................................................... 45210.2 Signal Description ....................................................................................................... 45310.3 Functional Description ................................................................................................. 45510.3.1 Non-Blocking Reads .................................................................................................... 45610.3.2 DMA Operation ........................................................................................................... 45710.4 Initialization and Configuration ..................................................................................... 45710.4.1 SDRAM Mode ............................................................................................................. 45810.4.2 Host Bus Mode ........................................................................................................... 46210.4.3 General-Purpose Mode ............................................................................................... 47110.5 Register Map .............................................................................................................. 47910.6 Register Descriptions .................................................................................................. 480

11 General-Purpose Timers ...................................................................................... 52211.1 Block Diagram ............................................................................................................ 52211.2 Signal Description ....................................................................................................... 52311.3 Functional Description ................................................................................................. 52611.3.1 GPTM Reset Conditions .............................................................................................. 52711.3.2 Timer Modes ............................................................................................................... 52711.3.3 DMA Operation ........................................................................................................... 53211.3.4 Accessing Concatenated Register Values ..................................................................... 53311.4 Initialization and Configuration ..................................................................................... 53311.4.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 53311.4.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 53411.4.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 53411.4.4 Input Edge-Count Mode ............................................................................................... 53511.4.5 16-Bit Input Edge Timing Mode .................................................................................... 53611.4.6 16-Bit PWM Mode ....................................................................................................... 536


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11.5 Register Map .............................................................................................................. 53711.6 Register Descriptions .................................................................................................. 538

12 Watchdog Timers ................................................................................................. 56912.1 Block Diagram ............................................................................................................ 57012.2 Functional Description ................................................................................................. 57012.2.1 Register Access Timing ............................................................................................... 57112.3 Initialization and Configuration ..................................................................................... 57112.4 Register Map .............................................................................................................. 57112.5 Register Descriptions .................................................................................................. 572

13 Analog-to-Digital Converter (ADC) ..................................................................... 59413.1 Block Diagram ............................................................................................................ 59513.2 Signal Description ....................................................................................................... 59513.3 Functional Description ................................................................................................. 59613.3.1 Sample Sequencers .................................................................................................... 59613.3.2 Module Control ............................................................................................................ 59713.3.3 Hardware Sample Averaging Circuit ............................................................................. 59913.3.4 Analog-to-Digital Converter .......................................................................................... 59913.3.5 Differential Sampling ................................................................................................... 60113.3.6 Internal Temperature Sensor ........................................................................................ 60413.3.7 Digital Comparator Unit ............................................................................................... 60413.4 Initialization and Configuration ..................................................................................... 60913.4.1 Module Initialization ..................................................................................................... 60913.4.2 Sample Sequencer Configuration ................................................................................. 61013.5 Register Map .............................................................................................................. 61013.6 Register Descriptions .................................................................................................. 612

14 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 66714.1 Block Diagram ............................................................................................................ 66814.2 Signal Description ....................................................................................................... 66814.3 Functional Description ................................................................................................. 67014.3.1 Transmit/Receive Logic ............................................................................................... 67014.3.2 Baud-Rate Generation ................................................................................................. 67114.3.3 Data Transmission ...................................................................................................... 67214.3.4 Serial IR (SIR) ............................................................................................................. 67214.3.5 ISO 7816 Support ....................................................................................................... 67314.3.6 Modem Handshake Support ......................................................................................... 67314.3.7 LIN Support ................................................................................................................ 67514.3.8 FIFO Operation ........................................................................................................... 67614.3.9 Interrupts .................................................................................................................... 67614.3.10 Loopback Operation .................................................................................................... 67714.3.11 DMA Operation ........................................................................................................... 67714.4 Initialization and Configuration ..................................................................................... 67814.5 Register Map .............................................................................................................. 67914.6 Register Descriptions .................................................................................................. 680

15 Synchronous Serial Interface (SSI) .................................................................... 72815.1 Block Diagram ............................................................................................................ 72915.2 Signal Description ....................................................................................................... 72915.3 Functional Description ................................................................................................. 730



15.3.1 Bit Rate Generation ..................................................................................................... 73115.3.2 FIFO Operation ........................................................................................................... 73115.3.3 Interrupts .................................................................................................................... 73115.3.4 Frame Formats ........................................................................................................... 73215.3.5 DMA Operation ........................................................................................................... 74015.4 Initialization and Configuration ..................................................................................... 74015.5 Register Map .............................................................................................................. 74215.6 Register Descriptions .................................................................................................. 743

16 Inter-Integrated Circuit (I2C) Interface ................................................................ 77116.1 Block Diagram ............................................................................................................ 77216.2 Signal Description ....................................................................................................... 77216.3 Functional Description ................................................................................................. 77316.3.1 I2C Bus Functional Overview ........................................................................................ 77316.3.2 Available Speed Modes ............................................................................................... 77516.3.3 Interrupts .................................................................................................................... 77616.3.4 Loopback Operation .................................................................................................... 77716.3.5 Command Sequence Flow Charts ................................................................................ 77716.4 Initialization and Configuration ..................................................................................... 78416.5 Register Map .............................................................................................................. 78516.6 Register Descriptions (I2C Master) ............................................................................... 78616.7 Register Descriptions (I2C Slave) ................................................................................. 798

17 Analog Comparators ............................................................................................ 80717.1 Block Diagram ............................................................................................................ 80717.2 Signal Description ....................................................................................................... 80817.3 Functional Description ................................................................................................. 80917.3.1 Internal Reference Programming .................................................................................. 80917.4 Initialization and Configuration ..................................................................................... 81117.5 Register Map .............................................................................................................. 81117.6 Register Descriptions .................................................................................................. 811

18 Pin Diagram .......................................................................................................... 81919 Signal Tables ........................................................................................................ 82119.1 100-Pin LQFP Package Pin Tables ............................................................................... 82219.2 108-Pin BGA Package Pin Tables ................................................................................ 84719.3 Connections for Unused Signals ................................................................................... 873

20 Operating Characteristics ................................................................................... 87521 Electrical Characteristics .................................................................................... 87621.1 DC Characteristics ...................................................................................................... 87621.1.1 Maximum Ratings ....................................................................................................... 87621.1.2 Recommended DC Operating Conditions ...................................................................... 87621.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 87721.1.4 Hibernation Module Characteristics .............................................................................. 87721.1.5 Flash Memory Characteristics ...................................................................................... 87721.1.6 GPIO Module Characteristics ....................................................................................... 87821.1.7 Current Specifications .................................................................................................. 87821.2 AC Characteristics ....................................................................................................... 87921.2.1 Load Conditions .......................................................................................................... 87921.2.2 Clocks ........................................................................................................................ 879


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21.2.3 JTAG and Boundary Scan ............................................................................................ 88221.2.4 Reset ......................................................................................................................... 88321.2.5 Sleep Modes ............................................................................................................... 88521.2.6 Hibernation Module ..................................................................................................... 88521.2.7 General-Purpose I/O (GPIO) ........................................................................................ 88721.2.8 External Peripheral Interface (EPI) ............................................................................... 88721.2.9 Analog-to-Digital Converter (ADC) ................................................................................ 89321.2.10 Synchronous Serial Interface (SSI) ............................................................................... 89421.2.11 Inter-Integrated Circuit (I2C) Interface ........................................................................... 89621.2.12 Analog Comparator ..................................................................................................... 897

A Register Quick Reference ................................................................................... 898B Ordering and Contact Information ..................................................................... 924B.1 Ordering Information .................................................................................................... 924B.2 Part Markings .............................................................................................................. 924B.3 Kits ............................................................................................................................. 925B.4 Support Information ..................................................................................................... 925

C Package Information ............................................................................................ 926C.1 100-Pin LQFP Package ............................................................................................... 926C.1.1 Package Dimensions ................................................................................................... 926C.1.2 Tray Dimensions ......................................................................................................... 928C.1.3 Tape and Reel Dimensions .......................................................................................... 928C.2 108-Ball BGA Package ................................................................................................ 930C.2.1 Package Dimensions ................................................................................................... 930C.2.2 Tray Dimensions ......................................................................................................... 932C.2.3 Tape and Reel Dimensions .......................................................................................... 933



List of FiguresFigure 1-1. Stellaris LM3S1R21 Microcontroller High-Level Block Diagram .............................. 56Figure 2-1. CPU Block Diagram ............................................................................................. 60Figure 2-2. TPIU Block Diagram ............................................................................................ 61Figure 2-3. Cortex-M3 Register Set ........................................................................................ 63Figure 2-4. Bit-Band Mapping ................................................................................................ 83Figure 2-5. Data Storage ....................................................................................................... 84Figure 2-6. Vector table ......................................................................................................... 90Figure 2-7. Exception Stack Frame ........................................................................................ 92Figure 3-1. SRD Use Example ............................................................................................. 106Figure 4-1. JTAG Module Block Diagram .............................................................................. 167Figure 4-2. Test Access Port State Machine ......................................................................... 170Figure 4-3. IDCODE Register Format ................................................................................... 176Figure 4-4. BYPASS Register Format ................................................................................... 176Figure 4-5. Boundary Scan Register Format ......................................................................... 177Figure 5-1. Basic RST Configuration .................................................................................... 181Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 181Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 182Figure 5-4. Power Architecture ............................................................................................ 187Figure 5-5. Main Clock Tree ................................................................................................ 190Figure 6-1. Hibernation Module Block Diagram ..................................................................... 274Figure 6-2. Using a Crystal as the Hibernation Clock Source ................................................. 277Figure 6-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 277Figure 7-1. Internal Memory Block Diagram .......................................................................... 300Figure 8-1. μDMA Block Diagram ......................................................................................... 338Figure 8-2. Example of Ping-Pong μDMA Transaction ........................................................... 344Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 346Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 347Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 349Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 350Figure 9-1. Digital I/O Pads ................................................................................................. 400Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 401Figure 9-3. GPIODATA Write Example ................................................................................. 402Figure 9-4. GPIODATA Read Example ................................................................................. 402Figure 10-1. EPI Block Diagram ............................................................................................. 453Figure 10-2. SDRAM Non-Blocking Read Cycle ...................................................................... 460Figure 10-3. SDRAM Normal Read Cycle ............................................................................... 461Figure 10-4. SDRAM Write Cycle ........................................................................................... 462Figure 10-5. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 469Figure 10-6. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 469Figure 10-7. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 1, RDHIGH = 1 ............................................................................................... 470Figure 10-8. Continuous Read Mode Accesses ...................................................................... 470Figure 10-9. Write Followed by Read to External FIFO ............................................................ 471Figure 10-10. Two-Entry FIFO ................................................................................................. 471Figure 10-11. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 475


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Figure 10-12. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,WRCYC=1 ........................................................................................................ 475

Figure 10-13. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 476Figure 10-14. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 476Figure 10-15. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 476Figure 10-16. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 477Figure 10-17. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 477Figure 10-18. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 477Figure 10-19. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 477Figure 10-20. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 478Figure 10-21. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 478Figure 10-22. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 479Figure 11-1. GPTM Module Block Diagram ............................................................................ 523Figure 11-2. Timer Daisy Chain ............................................................................................. 529Figure 11-3. Input Edge-Count Mode Example ....................................................................... 530Figure 11-4. 16-Bit Input Edge-Time Mode Example ............................................................... 531Figure 11-5. 16-Bit PWM Mode Example ................................................................................ 532Figure 12-1. WDT Module Block Diagram .............................................................................. 570Figure 13-1. ADC Module Block Diagram ............................................................................... 595Figure 13-2. ADC Sample Phases ......................................................................................... 599Figure 13-3. Internal Voltage Conversion Result ..................................................................... 600Figure 13-4. External Voltage Conversion Result .................................................................... 601Figure 13-5. Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 602Figure 13-6. Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 603Figure 13-7. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 603Figure 13-8. Internal Temperature Sensor Characteristic ......................................................... 604Figure 13-9. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 607Figure 13-10. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 608Figure 13-11. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 609Figure 14-1. UART Module Block Diagram ............................................................................. 668Figure 14-2. UART Character Frame ..................................................................................... 671Figure 14-3. IrDA Data Modulation ......................................................................................... 673Figure 14-4. LIN Message ..................................................................................................... 675Figure 14-5. LIN Synchronization Field ................................................................................... 676Figure 15-1. SSI Module Block Diagram ................................................................................. 729Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 733Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 734Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 734Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 735Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 736Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 736Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 737Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 738Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 738Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 739Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 740Figure 16-1. I2C Block Diagram ............................................................................................. 772Figure 16-2. I2C Bus Configuration ........................................................................................ 773



Figure 16-3. START and STOP Conditions ............................................................................. 774Figure 16-4. Complete Data Transfer with a 7-Bit Address ....................................................... 774Figure 16-5. R/S Bit in First Byte ............................................................................................ 774Figure 16-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 775Figure 16-7. Master Single TRANSMIT .................................................................................. 778Figure 16-8. Master Single RECEIVE ..................................................................................... 779Figure 16-9. Master TRANSMIT with Repeated START ........................................................... 780Figure 16-10. Master RECEIVE with Repeated START ............................................................. 781Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated

START .............................................................................................................. 782Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated

START .............................................................................................................. 783Figure 16-13. Slave Command Sequence ................................................................................ 784Figure 17-1. Analog Comparator Module Block Diagram ......................................................... 807Figure 17-2. Structure of Comparator Unit .............................................................................. 809Figure 17-3. Comparator Internal Reference Structure ............................................................ 810Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 819Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 820Figure 21-1. Load Conditions ................................................................................................ 879Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 882Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 883Figure 21-4. Power-On Reset and Voltage Parameters ........................................................... 884Figure 21-5. External Reset Timing (RST) .............................................................................. 884Figure 21-6. Power-On Reset Timing ..................................................................................... 884Figure 21-7. Brown-Out Reset Timing .................................................................................... 884Figure 21-8. Software Reset Timing ....................................................................................... 885Figure 21-9. Watchdog Reset Timing ..................................................................................... 885Figure 21-10. MOSC Failure Reset Timing ............................................................................... 885Figure 21-11. Hibernation Module Timing with Internal Oscillator Running in Hibernation ............ 886Figure 21-12. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation ............ 886Figure 21-13. VDD Ramp when Waking from Hibernation ......................................................... 887Figure 21-14. SDRAM Initialization and Load Mode Register Timing .......................................... 888Figure 21-15. SDRAM Read Timing ......................................................................................... 888Figure 21-16. SDRAM Write Timing ......................................................................................... 889Figure 21-17. Host-Bus 8/16 Mode Read Timing ...................................................................... 890Figure 21-18. Host-Bus 8/16 Mode Write Timing ....................................................................... 890Figure 21-19. Host-Bus 8/16 Mode Muxed Read Timing ............................................................ 891Figure 21-20. Host-Bus 8/16 Mode Muxed Write Timing ............................................................ 891Figure 21-21. General-Purpose Mode Read and Write Timing ................................................... 892Figure 21-22. General-Purpose Mode iRDY Timing .................................................................. 892Figure 21-23. ADC Input Equivalency Diagram ......................................................................... 894Figure 21-24. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................... 895Figure 21-25. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 895Figure 21-26. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 896Figure 21-27. I2C Timing ......................................................................................................... 897Figure C-1. 100-Pin LQFP Package Dimensions ................................................................... 926Figure C-2. 100-Pin LQFP Tray Dimensions .......................................................................... 928


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Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 929Figure C-4. 108-Ball BGA Package Dimensions .................................................................... 930Figure C-5. 108-Ball BGA Tray Dimensions ........................................................................... 932Figure C-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 933



List of TablesTable 1. Revision History .................................................................................................. 27Table 2. Documentation Conventions ................................................................................ 35Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 63Table 2-2. Processor Register Map ....................................................................................... 64Table 2-3. PSR Register Combinations ................................................................................. 69Table 2-4. Memory Map ....................................................................................................... 77Table 2-5. Memory Access Behavior ..................................................................................... 80Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 82Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 82Table 2-8. Exception Types .................................................................................................. 88Table 2-9. Interrupts ............................................................................................................ 88Table 2-10. Exception Return Behavior ................................................................................... 93Table 2-11. Faults ................................................................................................................. 94Table 2-12. Fault Status and Fault Address Registers .............................................................. 95Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 97Table 3-1. Core Peripheral Register Regions ....................................................................... 100Table 3-2. Memory Attributes Summary .............................................................................. 103Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 106Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 107Table 3-5. AP Bit Field Encoding ........................................................................................ 107Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 107Table 3-7. Peripherals Register Map ................................................................................... 108Table 3-8. Interrupt Priority Levels ...................................................................................... 135Table 3-9. Example SIZE Field Values ................................................................................ 163Table 4-1. Signals for JTAG_SWD_SWO (100LQFP) ........................................................... 167Table 4-2. Signals for JTAG_SWD_SWO (108BGA) ............................................................ 168Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 169Table 4-4. JTAG Instruction Register Commands ................................................................. 174Table 5-1. Signals for System Control & Clocks (100LQFP) .................................................. 178Table 5-2. Signals for System Control & Clocks (108BGA) ................................................... 178Table 5-3. Reset Sources ................................................................................................... 179Table 5-4. Clock Source Options ........................................................................................ 188Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ............................... 191Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 191Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 192Table 5-8. System Control Register Map ............................................................................. 196Table 5-9. RCC2 Fields that Override RCC Fields ............................................................... 217Table 6-1. Signals for Hibernate (100LQFP) ........................................................................ 274Table 6-2. Signals for Hibernate (108BGA) .......................................................................... 275Table 6-3. Hibernation Module Clock Operation ................................................................... 281Table 6-4. Hibernation Module Register Map ....................................................................... 283Table 7-1. Flash Memory Protection Policy Combinations .................................................... 304Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 307Table 7-3. Flash Register Map ............................................................................................ 308Table 8-1. μDMA Channel Assignments .............................................................................. 339Table 8-2. Request Type Support ....................................................................................... 341


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Table 8-3. Control Structure Memory Map ........................................................................... 342Table 8-4. Channel Control Structure .................................................................................. 342Table 8-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 351Table 8-6. μDMA Interrupt Assignments .............................................................................. 352Table 8-7. Channel Control Structure Offsets for Channel 30 ................................................ 353Table 8-8. Channel Control Word Configuration for Memory Transfer Example ...................... 353Table 8-9. Channel Control Structure Offsets for Channel 7 .................................................. 354Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 355Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 356Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 357Table 8-13. μDMA Register Map .......................................................................................... 358Table 9-1. GPIO Pins With Non-Zero Reset Values .............................................................. 396Table 9-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 396Table 9-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 398Table 9-4. GPIO Pad Configuration Examples ..................................................................... 404Table 9-5. GPIO Interrupt Configuration Example ................................................................ 405Table 9-6. GPIO Pins With Non-Zero Reset Values .............................................................. 406Table 9-7. GPIO Register Map ........................................................................................... 406Table 9-8. GPIO Pins With Non-Zero Reset Values .............................................................. 419Table 9-9. GPIO Pins With Non-Zero Reset Values .............................................................. 425Table 9-10. GPIO Pins With Non-Zero Reset Values .............................................................. 427Table 9-11. GPIO Pins With Non-Zero Reset Values .............................................................. 430Table 9-12. GPIO Pins With Non-Zero Reset Values .............................................................. 437Table 10-1. Signals for External Peripheral Interface (100LQFP) ............................................ 453Table 10-2. Signals for External Peripheral Interface (108BGA) .............................................. 454Table 10-3. EPI SDRAM Signal Connections ......................................................................... 459Table 10-4. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 463Table 10-5. EPI Host-Bus 8 Signal Connections .................................................................... 464Table 10-6. EPI Host-Bus 16 Signal Connections .................................................................. 465Table 10-7. EPI General Purpose Signal Connections ........................................................... 473Table 10-8. External Peripheral Interface (EPI) Register Map ................................................. 479Table 11-1. Available CCP Pins ............................................................................................ 523Table 11-2. Signals for General-Purpose Timers (100LQFP) .................................................. 524Table 11-3. Signals for General-Purpose Timers (108BGA) .................................................... 525Table 11-4. General-Purpose Timer Capabilities .................................................................... 526Table 11-5. 16-Bit Timer With Prescaler Configurations ......................................................... 528Table 11-6. Timers Register Map .......................................................................................... 537Table 12-1. Watchdog Timers Register Map .......................................................................... 572Table 13-1. Signals for ADC (100LQFP) ............................................................................... 595Table 13-2. Signals for ADC (108BGA) ................................................................................. 596Table 13-3. Samples and FIFO Depth of Sequencers ............................................................ 597Table 13-4. Differential Sampling Pairs ................................................................................. 601Table 13-5. ADC Register Map ............................................................................................. 610Table 14-1. Signals for UART (100LQFP) ............................................................................. 669Table 14-2. Signals for UART (108BGA) ............................................................................... 669Table 14-3. Flow Control Mode ............................................................................................. 674Table 14-4. UART Register Map ........................................................................................... 679



Table 15-1. Signals for SSI (100LQFP) ................................................................................. 730Table 15-2. Signals for SSI (108BGA) ................................................................................... 730Table 15-3. SSI Register Map .............................................................................................. 742Table 16-1. Signals for I2C (100LQFP) ................................................................................. 772Table 16-2. Signals for I2C (108BGA) ................................................................................... 772Table 16-3. Examples of I2C Master Timer Period versus Speed Mode ................................... 776Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 785Table 16-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 790Table 17-1. Signals for Analog Comparators (100LQFP) ........................................................ 808Table 17-2. Signals for Analog Comparators (108BGA) .......................................................... 808Table 17-3. Internal Reference Voltage and ACREFCTL Field Values ..................................... 810Table 17-4. Analog Comparators Register Map ..................................................................... 811Table 19-1. GPIO Pins With Default Alternate Functions ........................................................ 821Table 19-2. Signals by Pin Number ....................................................................................... 822Table 19-3. Signals by Signal Name ..................................................................................... 830Table 19-4. Signals by Function, Except for GPIO ................................................................. 837Table 19-5. GPIO Pins and Alternate Functions ..................................................................... 843Table 19-6. Possible Pin Assignments for Alternate Functions ................................................ 845Table 19-7. Signals by Pin Number ....................................................................................... 847Table 19-8. Signals by Signal Name ..................................................................................... 855Table 19-9. Signals by Function, Except for GPIO ................................................................. 863Table 19-10. GPIO Pins and Alternate Functions ..................................................................... 869Table 19-11. Possible Pin Assignments for Alternate Functions ................................................ 871Table 19-12. Connections for Unused Signals (100-pin LQFP) ................................................. 873Table 19-13. Connections for Unused Signals, 108-pin BGA .................................................... 873Table 20-1. Temperature Characteristics ............................................................................... 875Table 20-2. Thermal Characteristics ..................................................................................... 875Table 20-3. ESD Absolute Maximum Ratings ........................................................................ 875Table 21-1. Maximum Ratings .............................................................................................. 876Table 21-2. Recommended DC Operating Conditions ............................................................ 876Table 21-3. LDO Regulator Characteristics ........................................................................... 877Table 21-4. Hibernation Module DC Characteristics ............................................................... 877Table 21-5. Flash Memory Characteristics ............................................................................ 877Table 21-6. GPIO Module DC Characteristics ........................................................................ 878Table 21-7. Preliminary Current Consumption ....................................................................... 878Table 21-8. Phase Locked Loop (PLL) Characteristics ........................................................... 879Table 21-9. Actual PLL Frequency ........................................................................................ 880Table 21-10. PIOSC Clock Characteristics .............................................................................. 880Table 21-11. 30-kHz Clock Characteristics .............................................................................. 880Table 21-12. Hibernation Clock Characteristics ....................................................................... 880Table 21-13. HIB Oscillator Input Characteristics ..................................................................... 881Table 21-14. Main Oscillator Clock Characteristics .................................................................. 881Table 21-15. MOSC Oscillator Input Characteristics ................................................................ 881Table 21-16. System Clock Characteristics with ADC Operation ............................................... 881Table 21-17. JTAG Characteristics ......................................................................................... 882Table 21-18. Reset Characteristics ......................................................................................... 883Table 21-19. Sleep Modes AC Characteristics ......................................................................... 885Table 21-20. Hibernation Module AC Characteristics ............................................................... 886


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Table 21-21. GPIO Characteristics ......................................................................................... 887Table 21-22. EPI SDRAM Characteristics ............................................................................... 887Table 21-23. EPI SDRAM Interface Characteristics ................................................................. 887Table 21-24. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ................................... 889Table 21-25. EPI General-Purpose Interface Characteristics .................................................... 891Table 21-26. ADC Characteristics ........................................................................................... 893Table 21-27. ADC Module External Reference Characteristics ................................................. 894Table 21-28. ADC Module Internal Reference Characteristics .................................................. 894Table 21-29. SSI Characteristics ............................................................................................ 894Table 21-30. I2C Characteristics ............................................................................................. 896Table 21-31. Analog Comparator Characteristics ..................................................................... 897Table 21-32. Analog Comparator Voltage Reference Characteristics ........................................ 897Table B-1. Part Ordering Information ................................................................................... 924



List of RegistersThe Cortex-M3 Processor ............................................................................................................. 58Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 65Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 65Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 65Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 65Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 65Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 65Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 65Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 65Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 65Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 65Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 65Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 65Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 65Register 14: Stack Pointer (SP) ........................................................................................................... 66Register 15: Link Register (LR) ............................................................................................................ 67Register 16: Program Counter (PC) ..................................................................................................... 68Register 17: Program Status Register (PSR) ........................................................................................ 69Register 18: Priority Mask Register (PRIMASK) .................................................................................... 73Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 74Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 75Register 21: Control Register (CONTROL) ........................................................................................... 76

Cortex-M3 Peripherals ................................................................................................................. 100Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 111Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 113Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 114Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 115Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 116Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 117Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 118Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 119Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 120Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 121Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 122Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 123Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 124Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 125Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 125Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 125Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 125Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 125Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 125Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 125Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 125Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 125


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Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 125Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 125Register 25: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 125Register 26: Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 125Register 27: Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 125Register 28: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 127Register 29: Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 128Register 30: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 130Register 31: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 131Register 32: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 134Register 33: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 135Register 34: System Control (SYSCTRL), offset 0xD10 ....................................................................... 137Register 35: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 139Register 36: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 141Register 37: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 142Register 38: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 143Register 39: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 144Register 40: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 148Register 41: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 154Register 42: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 155Register 43: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 156Register 44: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 157Register 45: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 158Register 46: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 160Register 47: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 161Register 48: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 161Register 49: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 161Register 50: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 161Register 51: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 163Register 52: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 163Register 53: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 163Register 54: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 163

System Control ............................................................................................................................ 178Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 199Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 201Register 3: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 202Register 4: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 204Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 206Register 6: Reset Cause (RESC), offset 0x05C ................................................................................ 208Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 210Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 214Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 215Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 217Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 220Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 221Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 223Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 225Register 15: Device Identification 1 (DID1), offset 0x004 ..................................................................... 226



Register 16: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 228Register 17: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 229Register 18: Device Capabilities 2 (DC2), offset 0x014 ....................

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