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This document contains information on a new product. Specifications and information herein are subject to change without notice.

© MOTOROLA INC., 1995, 1997

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68HC11EA9MC68HC711EA9

Technical Summary

8-Bit Microcontrollers

1 Introduction

The MC68HC11EA9 and MC68HC711EA9 microcontroller units (MCUs) are high-performance mem-bers of the M68HC11 family of MCUs. The MC68HC(7)11EA9 MCUs have a multiplexed external ad-dress and data bus and are characterized by high speed and low power consumption. Their fully staticdesign allows operation at frequencies from 3 MHz to dc. The addition of a phase-locked loop (PLL)frequency synthesizer to the timer circuitry further enhances low-power operation and allows the use oflower frequency crystals while maintaining a clock speed of up to 3 MHz.

This document contains information concerning standard and custom-ROM devices. Standard devicesare those with ROM or with EPROM replacing ROM (MC68HC711EA9). Custom-ROM devices have aROM array that is programmed at the factory to customer specifications. Where information in this doc-ument refers to both the ROM and EPROM versions, the device is referred to as MC68HC(7)11EA9.

1.1 Features

• M68HC11 CPU• 512 Bytes RAM (Data Retained During Standby, by use of V

STBY

)• 12 Kbytes Mask-Programmed ROM or EPROM• 512 Bytes Electrically Erasable Programmable ROM (EEPROM)• PROG Mode Allows Use of Standard EPROM Programmer (27C256 Footprint)• Multiplexed Address and Data Buses Reduce Pin Count• Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler

— Three Input Capture (IC) Channels— Four Output Compare (OC) Channels— One Additional Channel, Selectable as Fourth IC or Fifth OC

• 8-Bit Pulse Accumulator• Phase-Locked Loop (PLL) Frequency Synthesizer for Reduced Power Consumption• Power Saving STOP and WAIT Modes• Real-Time Interrupt Circuit• Computer Operating Properly (COP) Watchdog Timer• Clock Monitor Circuit• Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)• Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter • Five Input/Output (I/O) Ports (34 Pins)

— Four Bidirectional I/O Ports (26 Pins)— One Fixed Input-Only Port (8 Pins)

• Two Alternate, Fixed Input-Only Pins (XIRQ pin/XPIN bit and IRQ pin/IPIN bit)• Available in 52-Pin Plastic Leaded Chip Carrier (PLCC), 52-Pin Windowed Ceramic Leaded Chip

Carrier (CLCC), and 56-Pin SDIP (0.070” Lead Spacing)

Section Page

MOTOROLA MC68HC11EA92 MC68HC11EA9TS/D

1 Introduction

1

1.1 Features ......................................................................................................................................1

2 Device Package Options and Ordering Information

5

2.1 Available Device Packages .........................................................................................................52.2 Ordering Information ...................................................................................................................7

3 Central Processing Unit

8

3.1 Programming Model ....................................................................................................................83.2 CPU Registers .............................................................................................................................83.2.1 Accumulators A, B, and D ................................................................................................83.2.2 Index Register X (IX) .......................................................................................................83.2.3 Index Register Y (IY) .......................................................................................................93.2.4 Stack Pointer (SP) ............................................................................................................93.2.5 Program Counter (PC) ......................................................................................................93.2.6 Condition Code Register (CCR) .......................................................................................93.2.7 Addressing Modes ............................................................................................................9

4 Operating Modes and On-Chip Memory

10

4.1 Single-Chip Mode ......................................................................................................................104.2 Expanded Mode ........................................................................................................................104.3 Test Mode .................................................................................................................................114.4 Bootstrap Mode .........................................................................................................................114.5 Mode Selection ..........................................................................................................................114.6 RAM ..........................................................................................................................................124.7 Bootstrap ROM ..........................................................................................................................124.8 Memory Map and Register Block ..............................................................................................124.9 ROM/EPROM/OTPROM ...........................................................................................................154.9.1 EPROM Emulation Mode ...............................................................................................154.9.2 Programming an Individual EPROM Address ................................................................164.9.3 Programming EPROM with Downloaded Data ...............................................................174.10 EEPROM ...................................................................................................................................184.10.1 Programming and Erasing EEPROM .............................................................................184.10.2 CONFIG Register ...........................................................................................................204.10.3 EEPROM Security ..........................................................................................................21

5 Resets and Interrupts

22

6 Parallel Input/Output

26

7 Timing System

31

7.1 Phase-Locked Loop Synthesizer ...............................................................................................327.2 Main Timer ................................................................................................................................347.3 Real-Time Interrupt ...................................................................................................................427.4 Pulse Accumulator ....................................................................................................................43

8 Serial Communications Interface

47

9 Analog-to-Digital Converter

54

TABLE OF CONTENTS

MC68HC11EA9 MOTOROLA

MC68HC11EA9TS/D 3

Register Index

ADCTL . . . . . . . . . A/D Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1030 . . . . . . . . . . . . . . 62ADR1–ADR4 . . . . A/D Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1031–$1034 . . . . . . . . 63BPROT . . . . . . . . . EEPROM Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . .$1035 . . . . . . . . . . . . . . 21CFORC . . . . . . . . . Timer Compare Force . . . . . . . . . . . . . . . . . . . . . . . . . . .$100B . . . . . . . . . . . . . . 41CONFIG . . . . . . . . Security, COP, ROM/EPROM/EEPROM Enables . . . . . .$103F . . . . . . . . . . . 23, 28COPRST . . . . . . . . Arm/Reset COP Timer Circuitry . . . . . . . . . . . . . . . . . . . .$103A . . . . . . . . . . . . . . 27DDRA . . . . . . . . . . Port A Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1001 . . . . . . . . . . . . . . 32DDRB . . . . . . . . . . Port B Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1006 . . . . . . . . . . . . . . 32DDRC . . . . . . . . . . Port C Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1007 . . . . . . . . . . . . . . 33DDRD . . . . . . . . . . Port D Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1009 . . . . . . . . . . . . . . 34HPRIO . . . . . . . . . Highest Priority I-bit Interrupt and Miscellaneous. . . . . . .$103C . . . . . . . . . . . 12, 27INIT . . . . . . . . . . . . RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . .$103D . . . . . . . . . . . . . . 14OC1D . . . . . . . . . . Output Compare 1 Data . . . . . . . . . . . . . . . . . . . . . . . . . .$100D . . . . . . . . . . . . . . 41OC1M . . . . . . . . . . Output Compare 1 Mask . . . . . . . . . . . . . . . . . . . . . . . . .$100C . . . . . . . . . . . . . . 41OPTION . . . . . . . . System Configuration Options . . . . . . . . . . . . . . . . . . . . .$1039 . . . . . . . . 26, 47, 63PACNT . . . . . . . . . Pulse Accumulator Counter . . . . . . . . . . . . . . . . . . . . . . .$1027 . . . . . . . . . . . . . . 51PACTL . . . . . . . . . Pulse Accumulator Control. . . . . . . . . . . . . . . . . . . . . . . .$1026 . . . . . . . . 46, 49, 50PPROG . . . . . . . . . EPROM and EEPROM Programming Control Register. .$103B . . . . . . . . . . . 19, 22PIOC . . . . . . . . . . . Port I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1002 . . . . . . . . . . . . . . 30PLLCR . . . . . . . . . PLL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1036 . . . . . . . . . . . . . . 37PORTA . . . . . . . . . Port A Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1000 . . . . . . . . . . . . . . 31PORTB . . . . . . . . . Port B Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1004 . . . . . . . . . . . . . . 32PORTC . . . . . . . . . Port C Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1003 . . . . . . . . . . . . . . 32PORTCL . . . . . . . . Port C Latched Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1005 . . . . . . . . . . . . . . 33PORTD . . . . . . . . . Port D Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1008 . . . . . . . . . . . . . . 33PORTE . . . . . . . . . Port E Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$100A . . . . . . . . . . . . . . . 34SCBDH/L . . . . . . . SCI Baud Rate Select High/Low . . . . . . . . . . . . . . . . . . .$1028, $1029 . . . . . . . . 56SCCR1 . . . . . . . . . SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .$102A . . . . . . . . . . . . . . 57SCCR2 . . . . . . . . . SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .$102B . . . . . . . . . . . . . . 57SCDRH/L . . . . . . . SCI Data High, SCI Data Low . . . . . . . . . . . . . . . . . . . . .$102E, $102F . . . . . . . . 59SCSR1 . . . . . . . . . SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .$102C . . . . . . . . . . . . . . 58SCSR2 . . . . . . . . . SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .$102D . . . . . . . . . . . . . . 59SYNR . . . . . . . . . . Frequency Synthesizer Control . . . . . . . . . . . . . . . . . . . .$1037 . . . . . . . . . . . . . . 38TCNT . . . . . . . . . . Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$100E–$100F . . . . . . . . 41TCTL1 . . . . . . . . . . Timer Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1020 . . . . . . . . . . . . . . 43TCTL2 . . . . . . . . . . Timer Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1021 . . . . . . . . . . . . . . 43TFLG1 . . . . . . . . . Timer Interrupt Flag 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .$1023 . . . . . . . . . . . . . . 44TFLG2 . . . . . . . . . Timer Interrupt Flag 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .$1025 . . . . . . . . 45, 48, 52TI4/O5 . . . . . . . . . . Timer Input Capture 4/Output Compare 5 . . . . . . . . . . . .$101E–$101F . . . . . . . . 42TIC1–TIC3 . . . . . . Timer Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1010–$1015 . . . . . . . . 42TMSK1 . . . . . . . . . Timer Interrupt Mask 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .$1022 . . . . . . . . . . . . . . 43TMSK2 . . . . . . . . . Timer Interrupt Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .$1024 . . . . . . . . . . . 44, 51TOC1–TOC4 . . . . . Timer Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . .$1016–$101D . . . . . . . . 42


Figure 1 MC68HC(7)11EA9 Block Diagram

CONTROL

EA9 BLOCK

PC7/

ADD

R7/

DAT

A7PC

6/AD

DR

6/D

ATA6

PC5/

ADD

R5/

DAT

A5PC

4/AD

DR

4/D

ATA4

PC3/

ADD

R3/

DAT

A3PC

2/AD

DR

2/D

ATA2

PC1/

ADD

R1/

DAT

A1PC

0/AD

DR

0/D

ATA0

MODE CONTROLOSC

CLOCK LOGICINTERRUPT

LOGIC

512 BYTES EEPROM

512 BYTES RAM

SERIALCOMMUNICATION

INTERFACESCI

M68HC11 CPU

CONTROL

PORT D PORT E

PE7/

AN7

TxD

RxD

PD0/

RxD

STR

A/AS

STR

B/R

/W

ADDRESS/DATABUS EXPANSIONADDRESS AS

STROBE AND HANDSHAKEPARALLEL I/O ST

RB

STR

A

CONTROL

PORT CPORT B

PB7/

ADD

R15

PORT A

PA7/

PAI

TIMERSYSTEMC

OP

PULS

E AC

CU

MU

LATO

R

OC

2O

C3

OC

4O

C5/

IC4/

OC

1IC

1IC

2IC

3

PAI

PER

IOD

IC IN

TER

RU

PT

MODA/LIR

MODB/VSTBY XTAL EXTAL E

IRQ/VPPEE RESET

PD1/

TxD

R/W

PA6/

OC

2/O

C1

PA5/

OC

3/O

C1

PA4/

OC

4/O

C1

PA3/

OC

5/IC

4/O

C1

PA2/

IC1

PA1/

IC2

PA0/

IC3

PB6/

ADD

R14

PB5/

ADD

R13

PB4/

ADD

R12

PB3/

ADD

R11

PB2/

ADD

R10

PB1/

ADD

R9

PB0/

ADD

R8

PE6/

AN6

PE5/

AN5

PE4/

AN4

PE3/

AN3

PE2/

AN2

PE1/

AN1

PE0/

AN0

VDDVSS

VRHVRL

XIRQ/VPPE*

* VPPE APPLIES ONLY TO DEVICES WITH EPROM/OTPROM.

12 KBYTES ROM/EPROM

A/D CONVERTER

CONTROL

PLL

XFCVDDSYN

IPIN XPIN

2 Device Package Options and Ordering Information

2.1 Available Device Packages

The MC68HC(7)11EA9 MCUs are available in a 52-pin plastic leaded chip carrier (PLCC) and a 52-pinceramic leaded chip carrier (CLCC). Refer to Figure 2. A plastic 56-pin shrink DIP (SDIP) package isalso available. Refer to Figure 3.

The EPROM-based MC68HC711EA9 is available in a windowed 52-pin ceramic leaded chip carrier(CLCC). A one-time-programmable (OTP) version of the MC68HC711EA9 is available by ordering thedevice in a non-windowed package. Refer to Table 1.

Figure 2 MC68HC(7)11EA9 PLCC/CLCC Pin Assignments

EA9 52-PIN PLCC

PE4/AN4

PE0/AN0

PB0/ADDR8

PB1/ADDR9

PB2/ADDR10

PB3/ADDR11

PB4/ADDR12

PB5/ADDR13

PB6/ADDR14

PB7/ADDR15

PA0/IC3

EXTA

L

STR

B/R

/W

E STR

A/AS

MO

DA/

LIR

V DD

V SS

V RH

V RL

PE7/

AN7

PE3/

AN3

XTAL

PC0/ADDR0/DATA0

PC1/ADDR1/DATA1

PC2/ADDR2/DATA2

PC3/ADDR3/DATA3

PC4/ADDR4/DATA4

PC5/ADDR5/DATA5

PC6/ADDR6/DATA6

PC7/ADDR7/DATA7

RESET

XIRQ/VPPE

PD1/

TxD

MO

DB/

V STB

Y

V DD

SYN

XFC

V SS

V DD

PA7/

PAI/O

C1

PA6/

OC

2/O

C1

PA5/

OC

3/O

C1

PA4/

OC

4/O

C1

PA3/

OC

5/IC

4/O

C1

MC68HC(7)11EA9

8

9

10

11

12

13

14

15

16

17

44

43

42

41

40

39

38

37

36

35

34

21 22 23 24 25 26 27 28 29 30 31

7 6 5 4 3

1

2 52 51 50 49

IRQ/VPPEE

18

PD0/RxD

19

PA2/

IC1

32

PA1/

IC2

33

PE6/

AN6

48

PE2/

AN2

47

PE1/AN145

PE5/AN546

20

*

* VPPE APPLIES ONLY TO DEVICES WITH EPROM/OTPROM.

MC68HC11EA9 MOTOROLAMC68HC11EA9TS/D 5

Figure 3 MC68HC(7)11EA9 56-Pin SDIP Pin Assignments

EA9 56-PIN DIP* VPPE APPLIES ONLY TO MC68HC711EA9.

PC0/ADDR0/DATA0

PC1/ADDR1/DATA1

PC2/ADDR2/DATA2

PC3/ADDR3/DATA3

PC4/ADDR4/DATA4

PC5/ADDR5/DATA5

PC6/ADDR6/DATA6

PC7/ADDR7/DATA7

RESET

XIRQ/VPPE

MC68HC(7)11EA9

(0.070" SPACING)

9

10

11

12

13

14

15

16

17

18

IRQ/VPPEE

19

20

21

*

22

PD1/TxD 23

MODB/VSTBY 24

VDDSYN25

XFC 26

VSS27

VDD 28

XTAL 8

NC 7

STRB/R/W

6

E

5

STRA/AS

4

3

2

VDD 1

PE0/AN0

PB0/ADDR8

PB1/ADDR9

PB2/ADDR10

PB3/ADDR11

PB4/ADDR12

PB5/ADDR13

PB6/ADDR14

PB7/ADDR15

NC

PA1/IC2

46

45

44

43

42

41

40

39

38

37

36

PE4/AN447

PE1/AN148

PA2/IC1

35

PA3/OC5/IC4/OC1

34

PA4/OC4/OC1

33

PA5/OC3/OC1

32

PA6/OC2/OC1

31

PA7/PAI/OC1

30

29

PE5/AN549

PE2/AN250

PE6/AN651

PE3/AN352

PE7/AN753

VRL54

VRH55

VSS56

PD0/RxDVSS

MODA/LIR

EXTAL

NC

PA0/IC3


2.2 Ordering Information

The MC68HC(7)11EA9 MCUs are available in a combination of packages, speeds, and temperatureranges. Refer to Table 1.

Table 1 Device Ordering Information

Description Package Temperature Frequency MC Order Number

Buffalo ROM 52-Pin PLCC – 40° to + 85° C 2 MHz MC68HC11EA9BCFN2

12 Kbytes ROM, 2 MHz MC68HC11EA9CFN2

512 Bytes RAM 3 MHz MC68HC11EA9CFN3

– 40° to + 105° C 2 MHz MC68HC11EA9VFN2

3 MHz MC68HC11EA9VFN3

– 40° to + 125° C 2 MHz MC68HC11EA9MFN2

3 MHz MC68HC11EA9MFN3

56-PIN SDIP – 40° to + 85° C 2 MHz MC68HC11EA9CP2

(.070” Spacing) 3 MHz MC68HC11EA9CP3

– 40° to + 105° C 2 MHz MC68HC11EA9VP2

3 MHz MC68HC11EA9VP3

– 40° to + 125° C 2 MHz MC68HC11EA9MP2

3 MHz MC68HC11EA9MP3

12 Kbytes OTPROM, 52-Pin PLCC – 40° to + 85° C 2 MHz MC68HC711EA9CFN2

512 Bytes RAM 3 MHz MC68HC711EA9CFN3

– 40° to + 105° C 2 MHz MC68HC711EA9VFN2

3 MHz MC68HC711EA9VFN3

– 40° to + 125° C 2 MHz MC68HC711EA9MFN2

3 MHz MC68HC711EA9MFN3

56-PIN SDIP – 40° to + 85° C 2 MHz MC68HC711EA9CP2

(.070” Spacing) 3 MHz MC68HC711EA9CP3

– 40° to + 105° C 2 MHz MC68HC711EA9VP2

3 MHz MC68HC711EA9VP3

– 40° to + 125° C 2 MHz MC68HC711EA9MP2

3 MHz MC68HC711EA9MP3

12 Kbytes EPROM, 52-PIN CLCC – 40° to + 85° C 2 MHz MC68HC711EA9CFS2

512 Bytes RAM (Windowed) 3 MHz MC68HC711EA9CFS3

– 40° to + 105° C 2 MHz MC68HC711EA9VFS2

3 MHz MC68HC711EA9VFS3

– 40° to + 125° C 2 MHz MC68HC711EA9MFS2

3 MHz MC68HC711EA9MFS3


3 Central Processing UnitA full description of the CPU and instruction set of M68HC11 MCUs is beyond the scope of this sum-mary. The programming model for the M68HC11 CPU and a brief description of the CPU registers isprovided here. For more detailed information refer to the M68HC11 Reference Manual (M68HC11RM/AD) or the programming reference guide or technical data book for the appropriate device.

3.1 Programming Model

Figure 4 shows a graphic representation of the internal registers of the M68HC11 CPU.

Figure 4 M68HC11 Programming Model

3.2 CPU Registers

M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memorylocations. The seven registers, discussed briefly in the following paragraphs, are shown in Figure 4.For a complete description of the CPU registers, addressing modes, and instruction set refer to theM68HC11 Reference Manual (M68HC11RM/AD).

3.2.1 Accumulators A, B, and D

Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmeticcalculations or data manipulations. For some instructions, these two accumulators are treated as a sin-gle double-byte (16-bit) accumulator called accumulator D. Most instructions can use accumulators Aor B interchangeably, however some exceptions apply.

3.2.2 Index Register X (IX)

The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an in-struction to create an effective address. The IX register can also be used as a counter or as a temporarystorage register.

HC11 PROG MODEL

7

15

15

15

15

15

0 7 0

0

0

0

0

0

ACCUMULATOR A ACCUMULATOR B

DOUBLE ACCUMULATOR D

INDEX REGISTER X

INDEX REGISTER Y

STACK POINTER

PROGRAM COUNTER

CONDITION CODE REGISTER S X H I N Z V C CCR

A:B

D

IX

IY

SP

PC

CARRY

OVERFLOW

ZERO

NEGATIVE

I INTERRUPT MASK

HALF CARRY (FROM BIT 3)

X INTERRUPT MASK

STOP DISABLE


3.2.3 Index Register Y (IY)

The 16-bit IY register performs an indexed mode function similar to that of the IX register. However,most instructions using the IY register require an extra byte of machine code and an extra cycle of ex-ecution time because of the way the opcode map is implemented.

3.2.4 Stack Pointer (SP)

The M68HC11 CPU has an automatic program stack. This stack can be located anywhere in the ad-dress space and can be any size up to the amount of memory available in the system. Normally the SPis initialized by one of the first instructions in an application program. The stack is configured as a datastructure that grows downward from high memory to low memory. Each time a new byte is pushed ontothe stack, the SP is decremented. Each time a byte is pulled from the stack, the SP is incremented. Atany given time, the SP holds the 16-bit address of the next free location in the stack.

3.2.5 Program Counter (PC)

The program counter, a 16-bit register, contains the address of the next instruction to be executed. Afterreset, the program counter is initialized from one of six possible vectors, depending on operating modeand the cause of reset.

3.2.6 Condition Code Register (CCR)

This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two interrupt masking bits,(IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 CPU, condition codes are automaticallyupdated by most instructions. For example, load accumulator A (LDAA) and store accumulator A(STAA) instructions automatically set or clear the N, Z, and V condition code flags.

3.2.7 Addressing Modes

Six addressing modes can be used to access memory: immediate, direct, extended, indexed, inherent,and relative. These modes are not detailed in this manual. For a complete description of the CPU reg-isters, addressing modes, and instruction set refer to the M68HC11 Reference Manual (M68HC11RM/AD).


4 Operating Modes and On-Chip Memory

4.1 Single-Chip Mode

In single-chip mode, ports B and C are available for general-purpose parallel I/O. Strobe pins A (STRA)and B (STRB) can be used to control handshaking of parallel I/O on ports B and C. In this mode, allsoftware needed to control the MCU is contained in internal resources. ROM/EPROM (if present) willalways be enabled out of reset, ensuring that the reset and interrupt vectors will be available at locations$FFC0–$FFFF.

4.2 Expanded Mode

In expanded operating mode, the MCU can access the full 64-Kbyte address space. The space includesthe same on-chip memory addresses used for single-chip mode as well as addresses for external pe-ripherals and memory devices. The expansion bus is made up of ports B and C, and control signals ASand R/W. R/W (read/write) and AS (address strobe) allow the low-order address and the 8-bit data busto be multiplexed on the same pins. During the first half of each bus cycle address information ispresent. During the second half of each bus cycle the pins become the bidirectional data bus. AS is anactive-high latch enable signal for an external address latch. Address information is allowed through thetransparent latch while AS is high and is latched when AS drives low. Figure 5 shows an example ofaddress and data demultiplexing.

Figure 5 Address/Data Demultiplexing

ADDR/DATA DEMUX

R/W

E

WE

MC

54/7

4HC

373

AS

MCU

PB7PB6PB5PB4PB3PB2PB1PB0

PC7PC6PC5PC4PC3PC2PC1PC0

ADDR15ADDR14ADDR13ADDR12ADDR11ADDR10ADDR9ADDR8

ADDR7ADDR6ADDR5ADDR4ADDR3ADDR2ADDR1ADDR0

DATA1DATA2DATA3DATA4DATA5DATA6DATA7DATA8

LE

DATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0

Q1Q2Q3Q4Q5Q6Q7Q8

Q0


4.3 Test Mode

Test mode, a variation of the expanded mode, is primarily used during Motorola's internal productiontesting; however, it is accessible for programming the CONFIG register, programming calibration datainto EEPROM, and supporting emulation and debugging during development. Refer to Figure 6.

4.4 Bootstrap Mode

Bootstrap mode is a special variation of the single-chip mode. Bootstrap mode allows special-purposeprograms to be entered into internal RAM. When boot mode is selected at reset, a small bootstrap ROMbecomes present in the memory map. Reset and interrupt vectors are located in this ROM at $BFC0–$BFFF. The bootstrap ROM contains a small program which initializes the SCI and allows the user todownload a program into on-chip RAM. The size of the downloaded program can be as large as the sizeof the on-chip RAM. After a four-character delay, or after receiving the character for the highest addressin RAM, control passes to the loaded program at $0000. Refer to Figure 6.

4.5 Mode Selection

The four mode variations are selected by the logic levels present on the MODA and MODB pins duringreset. The MODA and MODB logic levels determine the logic state of SMOD and the MDA control bitsin the highest priority I-bit interrupt and miscellaneous (HPRIO) register. See Table 2 for further infor-mation.

After reset is released, the mode select pins no longer influence the MCU operating mode. In single-chip operating mode, the MODA pin is connected to a logic level zero. In expanded mode, MODA isnormally connected to VDD through a pull-up resistor of 4.7 kΩ. The MODA pin also functions as theload instruction register (LIR) pin when the MCU is not in reset. The LIR signal is useful during programdebugging. The open-drain active low LIR output pin drives low during the first E cycle of each instruc-tion. The MODB pin also functions as standby power input (VSTBY), which allows RAM contents to bemaintained in absence of VDD.

*The reset values of RBOOT, SMOD, and MDA depend on the mode selected at power up.

RBOOT — Read Bootstrap ROM/EPROMValid only when SMOD is set (bootstrap or special test mode). Can only be written in special modes.

0 = Bootstrap ROM disabled and not in map1 = Bootstrap ROM enabled and in map at $BF00–$BFFF

SMOD and MDA — Special Mode Select and Mode Select AThese two bits can be read at any time. They can be written anytime in special modes. MDA can onlybe written once in normal modes. SMOD cannot be set once it has been cleared.

HPRIO — Highest Priority I-bit Interrupt and Miscellaneous $103C

BIT 7 6 5 4 3 2 1 BIT 0RBOOT* SMOD* MDA* IRVNE PSEL3 PSEL2 PSEL1 PSEL0

RESET: 0 0 0 0 0 0 0 0

Table 2 Operating Mode Selection

InputsMode

Latched at Reset

MODA MODB MDA SMOD

0 1 Single Chip 0 0

1 1 Expanded 1 0

0 0 Bootstrap 0 1

1 0 Special Test 1 1


IRV(NE) — Internal Read Visibility(Not E) IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV is on oroff. In special test mode, IRVNE is reset to one. In all other modes, IRVNE is reset to zero.

0 = No internal read visibility on external bus1 = Data from internal reads is driven out the external data bus.

In single-chip modes this bit determines whether the E clock drives out from the chip. 0 = E is driven out from the chip.1 = E pin is driven low. Refer to the following table.

PSEL[3:0] — Priority Select Bits [3:0]Refer to 5 Resets and Interrupts

4.6 RAM

In all modes RAM is enabled and present at locations $0000–$01FF. The RAM can be mapped to any1-Kbyte boundary by writing an appropriate value to the INIT register. The INIT register must be writtenduring the first 64 cycles after reset in expanded and single-chip modes. If RAM and the register blockare placed at the same 1-Kbyte boundary, the first 64 bytes of RAM are inaccessible. This is due to anon-chip hardware priority scheme which eliminates conflicts which could arise from multiple resourcessharing address locations. Figure 6 shows the location of the RAM array.

4.7 Bootstrap ROM

When operating in normal modes (SMOD = 0), the bootstrap ROM is disabled and removed from thememory map. In bootstrap and special test modes, bootstrap ROM is present at $BF00–$BFFF. Boot-strap ROM cannot be remapped to other locations. Figure 6 shows the location of the bootstrap ROMarray.

The bootstrap ROM contains a small program that allows program code to be downloaded into on-chipRAM. When the MC68HC(7)11EA9 enters bootstrap mode, bootloader firmware residing in bootstrapROM begins the downloading procedure by initializing the SCI system and transmitting a break out theSCI TxD pin. The SCI then waits for the first character to be received. After the first character is receivedon the RxD pin of the SCI, bootloader firmware begins counting the number of bytes received. Whenan idle time of four characters or the character for address $01FF is received, the bootloader programterminates the download and control is passed to the loaded program at $0000. For a detailed descrip-tion of the M68HC11 bootstrap mode, refer to application note M68HC11 Bootstrap Mode (AN1060/D).

4.8 Memory Map and Register Block

The operating mode determines memory mapping and whether external addresses can be accessed.Memory locations for on-chip resources are the same for both expanded and single-chip modes. Con-trol bits in the CONFIG register allow ROM/EPROM and EEPROM to be disabled from the memorymap. The RAM is mapped to $0000 after reset. It can be placed at any 4 Kbyte boundary ($x000) bywriting an appropriate value to the INIT register. The 64-byte register block is mapped to $1000 afterreset and can also be placed at any 4 Kbyte boundary ($x000) by writing an appropriate value to theINIT register. If RAM and registers are mapped to the same boundary, the first 64 bytes of RAM will beinaccessible. Table 4 shows the arrangement of control registers and bits within the register block.

Table 3 IRVNE Control vs. Operating Mode

OperatingMode

IRVNE BitOut of Reset

E ClockOut of Reset

IRV FunctionOut of Reset

IRVNE Bit Affects Only

Single Chip 0 On Off E

Expanded 0 On Off IRV

Bootstrap 0 On Off E

Special Test 1 On On IRV


Figure 6 MC68HC(7)11EA9 Memory Map

RAM[3:0] — RAM Map PositionThese four bits, which specify the upper hexadecimal digit of the RAM address, control position of RAMin the memory map. RAM can be positioned at the beginning of any 4 Kbyte page in the memory map.It is initialized to address $0000 out of reset.

REG[3:0] — 64-Byte Register Block PositionThese four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal reg-isters. The register block, positioned at the beginning of any 4 Kbyte page in the memory map, is initial-ized to address $1000 out of reset.

INIT — RAM and I/O Mapping Register $103D

BIT 7 6 5 4 3 2 1 BIT 0RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0

RESET: 0 0 0 0 0 0 0 1

EA9 MEM MAP

AAAA

FFC0

FFFF

NORMAL MODESINTERRUPTVECTORS

64-BYTE REGISTER BLOCK

512 BYTES RAM

SINGLECHIP

BOOTSTRAP SPECIALTEST

EXT

AAAA

AAAA

AAAA

AAAA

$0000

$1000

$B600

$D000

$FFFF

0000

1000

103F

BF00

EXPANDED

D000

FFFF

BFFF

BFC0

BFFF

SPECIAL MODESINTERRUPTVECTORS

B600

B7FF

512 BYTES EEPROM

12 KBYTES ROM/EPROM

BOOTROM

EXT

EXT EXT

EXTEXT

01FF

AAAA

AAAA


Table 4 MC68HC(7)11EA9 Registers (Sheet 1 of 2)

BIT 7 6 5 4 3 2 1 BIT 0$1000 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA$1001 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA$1002 STAF STAI CWOM HNDS OIN PLS EGA INVB PIOC$1003 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTC$1004 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB$1005 PCL7 PCL6 PCL5 PCL4 PCL3 PCL2 PCL1 PCL0 PORTCL$1006 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB$1007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC$1008 XPIN IPIN 0 0 0 0 PD1 PD0 PORTD$1009 DISX DISI 0 0 0 0 DDD1 DDD0 DDRD$100A PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTE$100B FOC1 FOC2 FOC3 FOC4 FOC5 0 0 0 CFORC$100C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 0 0 0 OC1M$100D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 0 0 0 OC1D$100E Bit 15 14 13 12 11 10 9 Bit 8 TCNT (HI)$100F Bit 7 6 5 4 3 2 1 Bit 0 TCNT (LO)$1010 Bit 15 14 13 12 11 10 9 Bit 8 TIC1 (HI)$1011 Bit 7 6 5 4 3 2 1 Bit 0 TIC1 (LO)$1012 Bit 15 14 13 12 11 10 9 Bit 8 TIC2 (HI)$1013 Bit 7 6 5 4 3 2 1 Bit 0 TIC2 (LO)$1014 Bit 15 14 13 12 11 10 9 Bit 8 TIC3 (HI)$1015 Bit 7 6 5 4 3 2 1 Bit 0 TIC3 (LO)$1016 Bit 15 14 13 12 11 10 9 Bit 8 TOC1 (HI)$1017 Bit 7 6 5 4 3 2 1 Bit 0 TOC1 (LO)$1018 Bit 15 14 13 12 11 10 9 Bit 8 TOC2 (HI)$1019 Bit 7 6 5 4 3 2 1 Bit 0 TOC2 (LO)$101A Bit 15 14 13 12 11 10 9 Bit 8 TOC3 (HI)$101B Bit 7 6 5 4 3 2 1 Bit 0 TOC3 (LO)$101C Bit 15 14 13 12 11 10 9 Bit 8 TOC4 (HI)$101D Bit 7 6 5 4 3 2 1 Bit 0 TOC4 (LO)$101E Bit 15 14 13 12 11 10 9 Bit 8 TI4/O5 (HI)$101F Bit 7 6 5 4 3 2 1 Bit 0 TI4/O5

(LO)$1020 OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5 TCTL1$1021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A TCTL2$1022 OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I TMSK1$1023 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F TFLG1$1024 TOI RTII PAOVI PAII 0 0 PR1 PR0 TMSK2$1025 TOF RTIF PAOVF PAIF 0 0 0 0 TFLG2$1026 0 PAEN PAMOD PEDGE 0 I4/O5 RTR1 RTR0 PACTL$1027 Bit 7 6 5 4 3 2 1 Bit 0 PACNT$1028 BTST BSPL BRST SBR12 SBR11 SBR10 SBR9 SBR8 SCBDH$1029 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SCBDL$102A LOOPS WOMS 0 M WAKE ILT PE PT SCCR1$102B TIE TCIE RIE ILIE TE RE RWU SBK SCCR2$102C TDRE TC RDRF IDLE OR NF FE PF SCSR1$102D 0 0 0 0 0 0 0 RAF SCSR2$102E R8 T8 0 0 0 0 0 0 SCDRH


4.9 ROM/EPROM/OTPROM

The MC68HC11EA9 contains 12 Kbytes of mask-programmed ROM. The ROM array is programmedat the factory to customer specifications and cannot be altered. The ROM array can be disabled byclearing the ROMON bit in the CONFIG register.

The MC68HC711EA9 MCU contains 12 Kbytes of on-chip EPROM/OTPROM. When theMC68HC711EA9 is packaged in a windowed CLCC, the 12 Kbytes of EPROM may be erased by ex-posing the device to ultraviolet light. An MC68HC711EA9 MCU packaged in a non-windowed case con-tains 12 Kbytes of one-time-programmable ROM (OTPROM).

Using the on-chip EPROM/OTPROM programming feature requires an external 12.25-volt power sup-ply (VPPE). Normal programming is accomplished using the EPROM/OTPROM programming register(PPROG). PPROG is the combined EPROM/OTPROM and EEPROM programming register(MC68HC711EA9 only). For the MC68HC11EA9, PPROG is used for programming EEPROM only.There are three possible methods of programming and verifying EPROM.

4.9.1 EPROM Emulation Mode

The EPROM emulation (PROG) mode allows the on-chip EPROM/OTPROM to be programmed as astandard EPROM by adapting the MCU footprint to that of the 27256-type EPROM, as shown in Figure7. Grounding the RESET, MODA, and MODB pins places the MCU in PROG mode. An appropriateEPROM programmer can then be used to enter data into the on-chip EPROM. Figure 7 shows the MCUpin functions while the device is in PROG mode.

If the MCU is operating with programming voltage present on the XIRQ/VPPE pin, the IRQ pin (CE pinin PROG mode) must be pulled high before the address and data are changed to program the next lo-cation.

NOTEPROG mode is disabled in devices having the security feature.

$102F R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 SCDRL$1030 CCF 0 SCAN MULT CD CC CB CA ADCTL$1031 Bit 7 6 5 4 3 2 1 Bit 0 ADR1$1032 Bit 7 6 5 4 3 2 1 Bit 0 ADR2$1033 Bit 7 6 5 4 3 2 1 Bit 0 ADR3$1034 Bit 7 6 5 4 3 2 1 Bit 0 ADR4$1035 0 0 0 PTCON BPRT3 BPRT2 BPRT1 BPRT0 BPROT$1036 PLLON BCS AUTO BWC VCOT MCS LCK WEN PLLCR$1037 SYNX1 SYNX0 SYNY5 SYNY4 SYNY3 SYNY2 SYNY1 SYNY0 SYNR$1038 Reserved

$1039 ADPU CSEL IRQE DLY CME 0 CR1 CR0 OPTION$103A Bit 7 6 5 4 3 2 1 Bit 0 COPRST$103B ODD EVEN ELAT1 BYTE ROW ERASE EELAT PGM PPROG

$103C RBOOT SMOD MDA IRVNE PSEL3 PSEL2 PSEL1 PSEL0 HPRIO$103D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 INIT$103E — — — — — — — — TEST12

$103F 0 0 0 0 NOSEC NOCOP ROMON EEON CONFIGNotes:

1. MC68HC711EA9 only.2. Factory test only.

Table 4 MC68HC(7)11EA9 Registers (Sheet 2 of 2)

BIT 7 6 5 4 3 2 1 BIT 0


Figure 7 MC68HC711EA9 PROG Mode Connections

4.9.2 Programming an Individual EPROM Address

In the second method, the MCU programs its own EPROM by controlling the PPROG register. Use thefollowing procedure to program the EPROM through the MCU with the ROMON bit set in the CONFIGregister. The 12 volt nominal programming voltage must be present on the XIRQ/VPPE pin. Any operat-ing mode can be used.

1. Write to PPROG to set the ELAT bit.2. Write the data to the desired address.3. Write to PPROG to set both the ELAT and PGM bits.4. Delay for 10 ms or more, as appropriate.

7EA9 PROG CONN

A4

A5

A6

A1

A2

A3

A7

A12

A8

A9

A10

A11

A0

NC

EXTAL

PA4/OC4/OC1

PA5/OC3/OC1

PC4/ADDR4/DATA4

PC5/ADDR5/DATA5

PC6/ADDR6/DATA6

PC1/ADDR1/DATA1

PC2/ADDR2/DATA2

PC3/ADDR3/DATA3

PC7/ADDR7/DATA7

PB4/ADDR12

PB0/ADDR8

PB1/ADDR9

PB2/ADDR10

PB3/ADDR11

PC0/ADDR0/DATA0

STRB/R/W

STRA/AS

PA5/OC3/OC1

PA4/OC4/OC1

PA3/OC5/IC4/OC1

PA2/IC1

PD1/TxD

PD0/RxD

O7

O6

O5

O1

O2

O4

O3

O0

A4

A5

A6

A1

A2

A3

A7

A12

A8

A9

A10

A11

A0

A14

GND

NOTE 1

O7

O6

O5

O1

O2

O4

O3

O0

INTERNAL 12-KBYTEEPROM

EPROMPIN FUNCTIONS

MCU PIN FUNCTIONS

EPROM MODE PIN CONNECTIONS

MC68HC711EA9

NOTES:1. UNUSED INPUTS — GROUNDING IS RECOMMENDED.2. UNUSED OUTPUTS — THESE PINS SHOULD BE LEFT UNTERMINATED.3. THESE PINS MUST BE GROUNDED FOR PROG MODE OPERATION.

VSS

VDD

IRQ

XIRQ

PB7/ADDR15

GND

VCC

CE

VPP

OE

GND

VCE

VOE

PP

CC

EXTAL

PA1/IC2

PA0/IC3

PB6/ADDR14

GND

GND

GND

GND

NOTE 3

PB5/ADDR13 A13

RESETMODB/VSTBY

MODA/LIR

GND

GND

NC

NCNOTE 2

A13

NC

NCGND

GND PE0/AN0

PE6/AN6

GND PE1/AN1GND PE2/AN2GND PE3/AN3GND PE4/AN4GND PE5/AN5

GND PE7/AN7

GNDRHRL

GND VV

GND VDDSYNGND XFC

PA7/PAI/OC1GNDPA6/OC2/OC1GND


5. Clear the PGM bit to turn off the VPPE voltage.6. Clear all bits in the PPROG register to reconfigure the EPROM address and data buses for nor-

mal operation.

NOTEPROG mode is initiated when RESET, MODA, and MODB pins are pulled low (thepin state required to enter bootstrap mode). This means that if these three pins arepulled low and VPPE is present on the XIRQ pin, the EPROM will be programmed.To prevent this, place a pull-up resistor on the IRQ pin (CE pin in PROG mode).When the device goes into reset, the PGM bit is forced to the voltage disable state(EPGM = 0) before the address/data latches are enabled to the external input lines.Only after this occurs is voltage control returned to the IRQ pin.

4.9.3 Programming EPROM with Downloaded Data

When using this method, the EPROM is programmed by software while in the special test or bootstrapmodes. User-developed software can be uploaded through the SCI, or a ROM resident EPROM pro-gramming utility can be used. To use the resident utility, bootload a three-byte program consisting of asingle jump instruction to $BF00. $BF00 is the starting address of a resident EPROM programming util-ity. The utility program sets the X and Y index registers to default values, then receives programmingdata from an external host and puts it in EPROM. The value in IX determines programming delay time.The value in IY is a pointer to the first address in EPROM to be programmed (default = $D000).

When the utility program is ready to receive programming data, it sends the host the $FF character.Then it waits. When the host sees the $FF character, the EPROM programming data is sent, startingwith the first location in the EPROM array. After the last byte to be programmed is sent and the corre-sponding verification data is returned, the programming operation is terminated by resetting the MCU.

* MC68HC711EA9 only.

ODD — Program Odd Rows in Half of EEPROM (TEST)Refer to 4.10 EEPROM.

EVEN — Program Even Rows in Half of EEPROM (TEST)Refer to 4.10 EEPROM.

ELAT — EPROM/OTPROM Latch ControlWhen ELAT = 1, writes to EPROM cause address and data to be latched and the EPROM/OTPROMcannot be read. ELAT can be read any time. ELAT can be written any time except when EPGM = 1;then the write to ELAT is disabled. For MC68HC711EA9, EPGM enables the high voltage necessaryfor both EPROM/OTPROM and EEPROM programming. For MC68HC711EA9 ELAT and EELAT aremutually exclusive and cannot both equal one.

0 = EPROM address and data bus configured for normal reads1 = EPROM address and data bus configured for programming

BYTE — Byte/Other EEPROM Erase ModeRefer to 4.10 EEPROM.

ROW — Row/All EEPROM Erase ModeRefer to 4.10 EEPROM.

PPROG — EPROM and EEPROM Programming Control Register $103B

BIT 7 6 5 4 3 2 1 BIT 0ODD EVEN ELAT* BYTE ROW ERASE EELAT PGM

RESET: 0 0 0 0 0 0 0 1


ERASE — Erase/Normal Control for EEPROMRefer to 4.10 EEPROM.

EELAT — EEPROM Latch Control0 = EEPROM address and data bus configured for normal reads1 = EEPROM address and data bus configured for programming or erasing

PGM — EPROM/OTPROM/EEPROM Programming Voltage Enable0 = Programming voltage to EPROM/OTPROM/EEPROM array disconnected1 = Programming voltage to EPROM/OTPROM/EEPROM array connected

PGM can be read any time and can only be written when ELAT = 1 (for EPROM/OTPROM program-ming) or when EELAT = 1 (for EEPROM programming).

4.10 EEPROM

MC68HC(7)11EA9 MCUs contain 512 bytes of EEPROM. The 512-byte EEPROM is initially located at$B600 after reset, assuming EEPROM is enabled in the memory map by the EEON bit in the CONFIGregister. EEPROM can be placed at any 4 Kbyte boundary ($x600) by writing appropriate values to theINIT register. Note that EEPROM can be mapped such that it contains the vector space. See Figure 6.

4.10.1 Programming and Erasing EEPROM

Programming and erasing the EEPROM is controlled by the PPROG register, and is dependent uponthe block protect (BPROT) register value. The erased state of an EEPROM bit is one. During a readoperation, bit lines are precharged to one. The floating gate devices of programmed bits conduct andpull the bit lines to zero. Unprogrammed bits remain at the precharged level and are read as ones. Pro-gramming a bit to one causes no change. Programming a bit to zero changes the bit so that subsequentreads return zero.

When appropriate bits in the BPROT register are cleared, the PPROG register controls programmingand erasing of the EEPROM. The PPROG register can be read or written at any time, but logic enforcesdefined programming and erasing sequences to prevent unintentional changes to data in EEPROM.When the EELAT bit in the PPROG register is cleared, the EEPROM can be read as if it were a ROM.

The on-chip charge pump that generates the EEPROM programming voltage from VDD uses MOS ca-pacitors, which are relatively small in value. The efficiency of this charge pump and its drive capabilityare affected by the level of VDD and the frequency of the driving clock. The clock source driving thecharge pump is software selectable. When the clock select (CSEL) bit in the OPTION register is zero,the E clock is used; when CSEL is one, an on-chip resistor-capacitor (RC) oscillator is used. The RCoscillator should be used when E < 1 MHz. This RC oscillator will drive the A/D circuitry as well as theEEPROM charge pump when CSEL = 1.

The EEPROM programming voltage connection to the EEPROM array is not enabled until there hasbeen a write to PPROG with EELAT set and PGM cleared. This must be followed by a write to a validEEPROM location or to the CONFIG address, and then a write to PPROG with both EELAT and PGMset. Any attempt to set both EELAT and PGM during the same write operation results in neither bit beingset.

The erased state of an EEPROM byte is $FF (all ones).

To erase the EEPROM, ensure that the proper bits of the BPROT register are cleared, then completethe following steps using the PPROG register:

1. Set the ERASE, EELAT, and appropriate BYTE and ROW bits in PPROG register.2. Write to the appropriate EEPROM address with any data. Row erase only requires a write to

any location in the row. Bulk erase is done by writing to any location in the array.3. Set the ERASE, EELAT, EEPGM, and appropriate BYTE and ROW bits in PPROG register.


4. Delay for 10 ms or more, as appropriate.5. Clear the EEPGM bit in PPROG to turn off the programming voltage.6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal op-

eration.

To program the EEPROM, ensure the proper bits of the BPROT register are cleared and use the PROGregister to complete the following steps:

1. Set the EELAT bit in PPROG register.2. Write data to the desired address.3. Set EEPGM bit in PPROG.4. Delay for 10 ms or more, as appropriate.5. Clear the EEPGM bit in PPROG to turn off the programming voltage.6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal op-

eration.

CAUTIONSince it is possible to perform other operations while the EEPROM programming/erase operation is in progress, it is common to start the operation then return to themain program until the 10 ms is completed. When the EELAT bit is set at the be-ginning of a program/erase operation, the EEPROM is electronically removed fromthe memory map; thus, it is not accessible during the program/erase cycle. Caremust be taken to ensure that EEPROM resources will not be needed by any rou-tines in the code during the 10 ms program/erase time.

Active bits in BPROT reset to ones in all modes and can only be cleared during the first 64 cycles outof reset. Bits can be set only once in normal modes. In special modes, bits can be set and cleared re-peatedly.

Bits [7:5] — Not implementedAlways read zero

PTCON — Protect CONFIG Register0 = CONFIG register can be programmed or erased normally1 = CONFIG register cannot be programmed or erased

BPRT[3:0] — Block Protect Bits for EEPROMWhen set, these bits protect a block of EEPROM from being programmed or electronically erased. Ul-traviolet light, however can erase the entire EEPROM contents regardless of BPRT[3:0] (windowedpackages only). When cleared, they allow programming and erasure of the associated block.

BPROT — EEPROM Block Protect $1035

BIT 7 6 5 4 3 2 1 BIT 0— — — PTCON BPRT3 BPRT2 BPRT1 BPRT0

RESET: 0 0 0 1 1 1 1 1

Table 5 EEPROM Block Protect

Bit Name Block Protected Block Size

BPRT0 $B600–$B61F 32 Bytes

BPRT1 $B620–$B65F 64 Bytes

BPRT2 $B660–$B6DF 128 Bytes

BPRT3 $B6E0–$B7FF 288 Bytes


* MC68HC711EA9 only.

ODD — Program Odd Rows in Half of EEPROM (TEST)

EVEN — Program Even Rows in Half of EEPROM (TEST)

ELAT — EPROM/OTPROM Latch ControlMC68HC711EA9 only. Refer to 4.9.3 Programming EPROM with Downloaded Data.

BYTE — Byte/Other EEPROM Erase Mode0 = Row or bulk erase mode used1 = Erase only one byte of EEPROM

ROW — Row/All EEPROM Erase Mode (only valid when BYTE = 0)0 = All 512 bytes of EEPROM erased1 = Erase only one 16-byte row of EEPROM

ERASE — Erase/Normal Control for EEPROM0 = Normal read or program mode1 = Erase mode

EELAT — EEPROM Latch Control0 = EEPROM address and data bus configured for normal reads1 = EEPROM address and data bus configured for programming or erasing

PGM — EPROM/OTPROM/EEPROM Programming Voltage Enable0 = Programming voltage to EPROM/OTPROM/EEPROM array disconnected1 = Programming voltage to EPROM/OTPROM/EEPROM array connected

PGM can be read any time and can only be written when ELAT = 1 (for EPROM/OTPROM program-ming) or when EELAT = 1 (for EEPROM programming).

4.10.2 CONFIG Register

The CONFIG register consists of an EEPROM byte and static latches that control the start-up configu-ration of the MCU. The contents of the EEPROM byte are transferred into static working latches duringreset sequences. The operation of the MCU is controlled directly by these latches and not by CONFIGitself. Although the byte is not included in the 512-byte EEPROM array, programming the CONFIG reg-ister requires the same procedure as any byte in the array. In normal modes, changes to CONFIG donot affect operation of the MCU until after the next reset sequence. When programming, the CONFIGregister itself is accessed. When the CONFIG register is read, the static latches are accessed.

PPROG — EPROM and EEPROM Programming Control Register $103B

BIT 7 6 5 4 3 2 1 BIT 0ODD EVEN ELAT* BYTE ROW ERASE EELAT PGM

RESET: 0 0 0 0 0 0 0 1

Table 6 BYTE/ROW Control Bits

BYTE ROW Action

0 0 Bulk Erase (All 512 Bytes)

0 1 Row Erase (16 Bytes)

1 0 Byte Erase

1 1 Byte Erase


U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in thelatch prior to reset (unchanged), but the function of COP is controlled by DISR bit in TEST1 register.

Bits [7:4] — Not ImplementedAlways read zero

NOSEC — Security DisableNOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If se-curity mask option is omitted NOSEC always reads one. The security feature protects the contents ofRAM and EEPROM.

0 = Security enabled1 = Security disabled

NOCOP — COP System DisableRefer to 5 Resets and Interrupts.

ROMON — ROM/EPROM/OTPROM EnableWhen this bit is zero, the ROM or EPROM/OTPROM is disabled and that memory space becomes ex-ternally addressed. In single-chip mode, ROMON is forced to one to enable ROM/EPROM/OTPROMregardless of the state of the ROMON bit.

0 = ROM/EPROM/OTPROM disabled from the memory map1 = ROM/EPROM/OTPROM present in the memory map

EEON — EEPROM EnableWhen this bit is zero, the EEPROM is disabled and that memory space becomes externally addressed.

0 = EEPROM removed from the memory map1 = EEPROM present in the memory map

4.10.3 EEPROM Security

The optional security feature, available only on ROM-based MCUs, protects the EEPROM and RAMcontents from unauthorized access. A program, or a key portion of a program, can be protected againstunauthorized duplication. To accomplish this, the protection mechanism restricts operation of protecteddevices to the single-chip modes. This prevents the memory locations from being monitored externallybecause single-chip modes do not allow visibility of the internal address and data buses. Resident pro-grams, however, have unlimited access to the internal EEPROM and RAM and can read, write, or trans-fer the contents of these memories.

CONFIG — Security, COP, ROM/EPROM, and EEPROM Enables $103F

BIT 7 6 5 4 3 2 1 BIT 0— — — — NOSEC NOCOP ROMON EEON

RESETS:S. Chip: 0 0 0 0 U U 1 U

Boot: 0 0 0 0 U U(L) U UExp.: 0 0 0 0 1 U U UTest: 0 0 0 0 1 U(L) U U


5 Resets and InterruptsAll M68HC11 MCUs have three reset vectors and 18 interrupt vectors. The reset vectors are as follows:

• RESET, or Power-On Reset• Clock Monitor Fail• COP Failure

The 18 interrupt vectors service 22 interrupt sources (3 non-maskable, 19 maskable). The 3 non-maskable interrupt sources are as follows:

• Illegal Opcode Trap• Software Interrupt• XIRQ Pin (X Interrupt)

On-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter-rupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized accord-ing to a default arrangement; however, any one source can be elevated to the highest maskable priorityposition by a software-accessible control register (HPRIO). The HPRIO register can be written at anytime, provided bit I in the CCR is set.

Eighteen interrupt sources in the MC68HC(7)11EA9 MCUs are subject to masking by the global inter-rupt mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the externalinterrupt (IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in theM68HC11 have separate interrupt vectors; therefore, there is usually no need for software to poll controlregisters to determine the cause of an interrupt.

For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during thenormal course of responding to the interrupt requests. For example, the RDRF flag in the SCI systemis cleared by the automatic clearing mechanism invoked by a read of the SCI status register while RDRFis set, followed by a read of the SCI data register. The normal response to an RDRF interrupt requestwould be to read the SCI status register to check for receive errors, then to read the received data fromthe SCI data register. These two steps satisfy the automatic clearing mechanism without requiring anyspecial instructions.

The computer operating properly (COP) watchdog and the clock monitor are both circuits that force areset sequence when a malfunctioning clock is encountered. The COP function forces a reset when atimeout occurs. The timeout period is determined by programming CR[1:0] in OPTION register. Theclock monitor circuit forces a reset sequence whenever the clock is slow or absent. The CME bit in theOPTION register enables the clock monitor circuit. To use STOP mode the clock monitor must be dis-abled before the STOP instruction is executed or a reset sequence will occur.

Refer to the following table for a list of interrupt and reset vector assignments.

Table 7 Interrupt and Reset Vector Assignments

Vector Address Interrupt Source CCR Mask Local Mask Priority(1 = High)

FFC0, C1 — FFD4, D5 Reserved — — —

FFD6, D7 SCI Serial System Bit I 18

• SCI Receive Data Register Full RIE

• SCI Receiver Overrun RIE

• SCI Transmit Data Register Empty TIE

• SCI Transmit Complete TCIE

• SCI Idle Line Detect ILIE

FFD8, D9 Reserved — — —


ADPU — A/D Converter Power upRefer to 9 Analog-to-Digital Converter

CSEL — Clock SelectRefer to 4.10 EEPROM.

IRQE — IRQ Select Edge-Sensitive Only0 = IRQ input is active-low1 = IRQ input recognizes falling edges only

DLY — Enable Oscillator Start-up Delay0 = No stabilization delay on exit from STOP mode.1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU exits STOP mode.

CME — Clock Monitor Enable0 = Clock monitor disabled; slow clock can be used.1 = Slow or stopped clocks cause COP failure reset.

Bit 2 — Not implementedAlways reads zero

CR[1:0] — COP Timer Rate SelectRefer to the following table of COP timer rates.

FFDA, DB Pulse Accumulator Input Edge Bit I PAII 17

FFDC, DD Pulse Accumulator Overflow Bit I PAOVI 16

FFDE, DF Timer Overflow Bit I TOI 15

FFE0, E1 Timer Input Capture 4/Output Compare 5 Bit I I4/O5I 14

FFE2, E3 Timer Output Compare 4 Bit I OC4I 13




FFEA, EB Timer Input Capture 3 Bit I IC3I 9

FFEC, ED Timer Input Capture 2 Bit I IC2I 8

FFEE, EF Timer Input Capture 1 Bit I IC1I 7

FFF0, F1 Real-Time Interrupt Bit I RTII 6

FFF2, F3 IRQ (External Pin) Bit I None 5

FFF4, F5 XIRQ Pin Bit X None 4

FFF6, F7 Software Interrupt None None *

FFF8, F9 Illegal Opcode Trap None None *

FFFA, FB COP Failure None NOCOP 3

FFFC, FD Clock Monitor Fail None CME 2

FFFE, FF RESET None None 1

* Same level as an instruction

OPTION — System Configuration Options $1039

BIT 7 6 5 4 3 2 1 BIT 0ADPU CSEL IRQE* DLY* CME — CR1* CR0*

RESET: 0 0 0 1 0 0 0 0* Can be written only once in first 64 cycles after reset in normal modes, or at any time in special modes.

Table 7 Interrupt and Reset Vector Assignments


Write $55 to COPRST to arm COP watchdog circuit. Write $AA to COPRST to reset COP watchdogcircuit.

*RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written inspecial mode.

RBOOT — Read Bootstrap ROMRefer to 4.4 Bootstrap Mode

SMOD — Special Mode SelectRefer to 4.5 Mode Selection

MDA — Mode Select ARefer to 4.5 Mode Selection

IRVNE — Internal Read Visibility/Not ERefer to 4.5 Mode Selection

PSEL[3:0] — Priority Select Bit 4 through Bit 0Can be written only while the I-bit in the CCR is set (interrupts disabled). These bits select one interruptsource to be elevated above all other I-bit related sources.

Table 8 COP Timer Rate Selection

Rate Period Length

CR[1:0] Selected E = 1.0 MHz E = 2.0 MHz E = 3.0 MHz

0 0 215 ÷ E 32.768 ms 16.384 ms 10.923 ms

0 1 217 ÷ E 131.072 ms 65.536 ms 43.691 ms

1 0 219 ÷ E 524.288 ms 262.140 ms 174.76 ms

1 1 221 ÷ E 2.097 s 1.049 s 699.05 ms

COPRST — Arm/Reset COP Timer Circuitry $103A

BIT 7 6 5 4 3 2 1 BIT 07 6 5 4 3 2 1 0

RESET: 0 0 0 1 0 0 0 0

HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous $103C

BIT 7 6 5 4 3 2 1 BIT 0RBOOT* SMOD* MDA* IRVNE PSEL3 PSEL2 PSEL1 PSEL0

RESET: — — — 0 0 1 0 1



NOSEC — EEPROM Security Mode DisableRefer to 4.10.3 EEPROM Security

NOCOP — COP System Disable0 = COP system enabled (forces reset on timeout)1 = COP system disabled

ROMON — ROM/EPROM EnableRefer to 4 Operating Modes and On-Chip Memory.

EEON — EEPROM EnableRefer to 4.10 EEPROM

Table 9 Highest I-Bit Interrupt Source Selection

PSEL3 PSEL2 PSEL1 PSEL0 Interrupt Source Promoted

0 0 0 0 Timer Overflow

0 0 0 1 Pulse Accumulator Overflow

0 0 1 0 Pulse Accumulator Input Edge

0 0 1 1 Reserved (Default to IRQ)

0 1 0 0 SCI Serial System

0 1 0 1 Reserved (Default to IRQ)

0 1 1 0 IRQ (External Pin)

0 1 1 1 Real-Time Interrupt

1 0 0 0 Timer Input Capture 1



1 0 1 1 Timer Output Compare 1




1 1 1 1 Timer IC4/OC5

PSEL[3:0] reset to %0101, making IRQ the highest priority I-bit related interrupt source.

CONFIG — Security, COP, ROM/EPROM, and EEPROM Enables $103F

BIT 7 6 5 4 3 2 1 BIT 0— — — — NOSEC NOCOP ROMON EEON

RESET: — — — 0 0 1 0 1


6 Parallel Input/OutputThe MC68HC(7)11EA9 has up to 36 input/output lines, depending on the operating mode. Table 10shows the configuration and features of each port.

Simple and full handshake input and output functions are available on ports B and C lines in single-chipmode. The following is a description of the handshake functions.

In simple strobed mode, port B is a strobed output port and port C is a latching input port. The two ac-tivities are available simultaneously.

The STRB output is pulsed for two E-clock periods each time there is a write to the PORTB register.The INVB bit in the PIOC register controls the polarity of STRB pulses. Port C levels are latched intothe alternate port C latch (PORTCL) register on each assertion of the STRA input. STRA edge select,flag, and interrupt enable bits are located in the PIOC register. Any or all of the port C lines can still beused as general-purpose I/O while in strobed input mode.

Full handshake modes involve port C pins and the STRA and STRB lines. Input and output handshakemodes are supported, and output handshake mode has a three-stated variation. STRA is an edge de-tecting input, and STRB is a handshake output. Control and enable bits are located in the PIOC register.

In full input handshake mode, the MCU uses STRB as a ready line to an external system. Port C logiclevels are latched into PORTCL when the STRA line is asserted by the external system. The MCU thennegates STRB. The MCU reasserts STRB after the PORTCL register is read. A mix of latched inputs,static inputs, and static outputs is allowed on port C, differentiated by the data direction bits and use ofthe PORTC and PORTCL registers.

In full output handshake mode, the MCU writes data to PORTCL which, in turn, asserts the STRB outputto indicate that data is ready. The external system reads port C and asserts the STRA input to acknowl-edge that data has been received.

In the three-state variation of output handshake mode, lines intended as three-state handshake outputsare configured as inputs by clearing the corresponding DDRC bits. The MCU writes data to PORTCLand asserts STRB. The external system responds by activating the STRA input, which forces the MCUto drive the data in PORTCL out on all of the port C lines. The mode variation does not allow part of portC to be used for static inputs while other port C pins are being used for handshake outputs. Refer toPIOC register description for further information.

Table 10 I/O Port Configuration

Port InputPins

OutputPins

BidirectionalPins

Shared Functions

A — — 8 Timer

B — — 8 High Order Address

C — — 8 Multiplexed Low Order Address/Data

D — — 2 SCI/PLL Test

E 8 — — A/D Converter

— 1 — — XPIN (XIRQ pin configured for data input)

— 1 — — IPIN (IRQ pin configured for data input)


STAF — Strobe A Interrupt Status FlagThis bit is set when a selected edge occurs on Strobe A. Clearing it depends on the state of the HNDSand OIN bits. In simple strobed mode or in full handshake mode, STAF is cleared by a read of the PIOCregister followed by a read of PORTCL register. In output handshake mode, STAF is cleared by readingthe PIOC register followed by a write to PORTCL register.

0 = No edge detected on strobe A1 = The selected edge (rising or falling) has been detected on strobe A

STAI — Strobe A Interrupt EnableWhen bit I in the condition code register is clear and STAI is set, STAF (when set) will request an inter-rupt.

0 = STAF will not generate an interrupt when set.1 = STAF will generate an interrupt when set.

CWOM — Port C Wire-OR ModeCWOM affects all eight port A pins.

0 = Port C outputs are normal CMOS outputs1 = Port C outputs act as open-drain outputs

HNDS — Handshake ModeWhen clear, strobe A acts as a simple input strobe to latch data into PORTCL, and strobe B acts as asimple output strobe which pulses after a write to port B. When set, a handshake protocol involving portC, STRA, and STRB is selected (see the definition for the OIN bit).

0 = Simple strobe mode1 = Full input or output handshake mode

OIN — Output or Input HandshakingThis bit has no meaning or effect when HNDS = 0.

0 = Input handshake1 = Output handshake

PLS — Pulse/Interlocked Handshake OperationThis bit has no meaning if HNDS = 0. When interlocked handshake operation is selected, strobe B, onceactivated, stays active until the selected edge of strobe A is detected. When pulsed handshake opera-tion is selected, strobe B is pulsed for two E cycles.

0 = Interlocked handshake selected1 = Pulsed handshake selected

EGA — Active Edge for Strobe A0 = Falling edge of strobe A selected. When output handshake is selected, port C lines obey the

data direction register while STRA is low, but port C is forced to output when STRA is high. 1 = Rising edge of strobe A selected. When output handshake is selected, port C lines obey the

data direction register while STRA is high, but port C is forced to output when STRA is low.

INVB — Invert Strobe B0 = Active level is logic zero1 = Active level is logic one

PIOC — Port I/O Control $1002

BIT 7 6 5 4 3 2 1 BIT 0STAF STAI CWOM HNDS OIN PLS EGA INVB

RESET: 0 0 0 0 0 0 0 0


Table 11 Strobed and Handshake Parallel I/O Control Bit Summary

Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin atreset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of thecorresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-tions, an "I" indicates this condition. Port pins that are driven to a known logic level during reset areshown with a value of either one or zero. Some control bits are unaffected by reset. Reset states forthese bits are indicated with a "U".

NOTEThe timer forces the I/O state to output for each port A line associated with an en-abled output compare. In these cases the data direction bits will not be changed,but have no effect on these lines. The DDRA will revert to controlling data directionwhen the associated timer compare is disabled. Input captures do not force eitherthe I/O state of the pin or the state of DDRA. To enable PA3 as fourth input capture,set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth out-put compare out of reset, with bit I4/O5 being cleared. If the DDA3 bit in DDRA isset (configuring PA3 as an output), and IC4 is enabled, writes to PA3 cause edgeson the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4. PA7 drives the pulse accumulator input but also canbe configured for general-purpose I/O or output compare. DDA7 bit in DDRA reg-ister configures PA7 for either input or output. Note that even when PA7 is config-ured as an output, the pin still drives the pulse accumulator input.

PORTA — Port A Data $1000

BIT 7 6 5 4 3 2 1 BIT 0PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

RESET: I I I I I I I IAlt. PinFunc.:

PAI OC2 OC3 OC4 IC4/OC5 IC1 IC2 IC3

And/or OC1 OC1 OC1 OC1 OC1 — — —

1

0

0

1

0

1Port CDriven

STRAActive EdgeFollow

DDRCFollowDDRC

Simplestrobedmode

Fullinput

handshakemode

Fulloutput

handshakemode

0

1

1

X

0

1

X

0 = STRBactive level

Read PIOCwith STAF = 1

then read PORTCL


then read PORTCL


then write PORTCL

1 = STRBactive pulse

0 = STRBactive level

1 = STRBactive pulse

STAFClearing

Sequence HNDS OIN PLS EGA

Inputs latchedinto PORTCL

on anyactive edgeon STRA

Driven as outputs if STRA at activelevel; follows

DDRC if STRA notat active level

STRB pulses on writes to

PORTB

Normal outputport, unaffectedin handshake

modes

Normal output port, unaffected in handshake

modes

Port CPort B

Inputs latchedinto PORTCL

on anyactive edgeon STRA


DDA[7:0] — Data Direction for Port A0 = Corresponding pin configured for input1 = Corresponding pin configured for output

DDB[7:0] — Data Direction for Port B0 = Corresponding pin configured for input1 = Corresponding pin configured for output

PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin,port C data is latched into the PORTCL register. Reads of this register return the last value latched intoPORTCL and clear STAF flag (following a read of PIOC with STAF set).

DDC[7:0] — Data Direction for Port C0 = Corresponding pin configured for input1 = Corresponding pin configured for output

DDRA — Port A Data Direction $1001

BIT 7 6 5 4 3 2 1 BIT 0DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0

RESET: 0 0 0 0 0 0 0 0

PORTB — Port B Data $1004

BIT 7 6 5 4 3 2 1 BIT 0PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

RESET: 0 0 0 0 0 0 0 0Alt. PinFunc.: ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8

DDRB — Port B Data Direction $1006

BIT 7 6 5 4 3 2 1 BIT 0DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0

RESET: 0 0 0 0 0 0 0 0

PORTC — Port C Data $1003

BIT 7 6 5 4 3 2 1 BIT 0PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

RESET: 0 0 0 0 0 0 0 0Alt. PinFunc.: ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

Or: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

PORTCL — Port C Latched Data $1005

BIT 7 6 5 4 3 2 1 BIT 0PCL7 PCL6 PCL5 PCL4 PCL3 PCL2 PCL1 PCL0

RESET: 0 0 0 0 0 0 0 0

DDRC — Port C Data Direction $1007

BIT 7 6 5 4 3 2 1 BIT 0DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0

RESET: 0 0 0 0 0 0 0 0


XPIN — XIRQ Interrupt Pin Status FlagThis is a read-only bit. XPIN reflects the logic level present on the XIRQ pin.

0 = XIRQ pin low.1 = XIRQ pin high.

IPIN — IRQ Interrupt Pin Status FlagThis is a read-only bit. IPIN reflects the logic level present on the IRQ pin.

0 = IRQ pin low.1 = IRQ pin high.

XPIN and IPIN are read-only status bits that reflect the logic levels present on the XIRQ and IRQ pins.XPIN and IPIN provide the data bits that allow the XIRQ and IRQ pins to be used as general-purposeinputs. However, to use XIRQ and IRQ as data inputs, the interrupts normally generated by these twopins must be disabled with the DISX and DISI bits in the DDRD register.

After reset PD[1:0] are configured as high-impedance inputs. PD[1:0] share functions with the SCI sys-tem. 8 Serial Communications Interface details information regarding port D SCI functions.

DISX — Disable XIRQ Pin InterruptsCan be read anytime. Can be written only once. Any write to the DDRD register will prevent modificationof this bit. This bit must be set to use the XIRQ pin as a data input.

0 = Interrupts generated by the XIRQ pin function are enabled1 = Interrupts generated by the XIRQ pin function are disabled

DISI — Disable IRQ Pin InterruptsCan be read anytime. Can be written only once. Any write to the DDRD register will prevent modificationof this bit. This bit must be set to use the IRQ pin as a data input.

0 = Interrupts generated by the IRQ pin function are enabled1 = Interrupts generated by the IRQ pin function are disabled

DDD[1:0] — Data Direction for PD[1:0]0 = Corresponding port D pin configured for input1 = Corresponding port D pin configured for output

Port E has eight general-purpose input pins and shares functions with the A/D converter system. Whenany port E pins are being used as A/D inputs, PORTE should not be read during the sample portion ofan A/D conversion. Refer to 9 Analog-to-Digital Converter for more information.

PORTD — Port D Data $1008

BIT 7 6 5 4 3 2 1 BIT 0XPIN IPIN — — — — PD1 PD0

RESET: 0 0 0 0 0 0 0 0Alt. PinFunc.:

— — — — — — TxD RxD

DDRD — Port D Data Direction $1009

BIT 7 6 5 4 3 2 1 BIT 0DISX DISI — — — — DDD1 DDD0

RESET: 0 0 0 0 0 0 0 0

PORTE — Port E Data $100A

BIT 7 6 5 4 3 2 1 BIT 0PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

RESET: I I I I I I I I


7 Timing SystemThe timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler.A timer overflow function allows software to extend the system’s timing capability beyond the counter's16-bit range. The main timer consists of the timer prescaler, the 16-bit free-running counter, and thecapture/compare unit. 7.2 Main Timer details this portion of the timing system.

The free-running counter can be driven by either the EXTAL signal, as in other M68HC11 derivativesor it can be driven by a software-controlled phase-locked loop (PLL) frequency synthesizer which hasbeen added to the MC68HC(7)11EA9 MCUs. The PLL allows the MCU to operate in WAIT mode withextremely low power requirements. Refer to 7.1 Phase-Locked Loop Synthesizer.

In addition, the timing system includes pulse accumulator and real-time interrupt (RTI) functions, as wellas a clock monitor function, which can be used to detect clock failures that are not detected by the COPsystem. Refer to the appropriate paragraphs within this section for information regarding these func-tions. Table 12 shows a summary of the crystal-related frequencies and periods.

Table 12 Timer Summary

Control Bits Common System Frequencies Definition

4.0 MHz 8.0 MHz 12.0 MHz XTAL

1.0 MHz 2.0 MHz 3.0 MHz E

PR[1:0] Main Timer Count Rate (Period Length)

0 0

1 count — 1000 ns 500 ns 333 ns 1/E

overflow — 65.536 ms 32.768 ms 21.845 ms 216/E

0 1

1 count — 4.0 µs 2.0 µs 1.333 µs 4/E


1 0

1 count — 8.0 µs 4.0 µs 2.667 µs 8/E


1 1

1 count — 16.0 µs 8.0 µs 5.333 µs 16/E

overflow — 1.049 s 524.29 ms 349.52 ms 220/E

RTR[1:0] Periodic (RTI) Interrupt Rates (Period Length)

0 0 8.192 ms 4.096 ms 2.731 ms 213/E

0 1 16.384 ms 8.192 ms 5.461 ms 214/E

1 0 32.768 ms 16.384 ms 10.923 ms 215/E

1 1 65.536 ms 32.768 ms 21.845 ms 216/E

CR[1:0] COP Watchdog Timeout Rates (Period Length)

0 0 32.768 ms 16.384 ms 10.923 ms 215/E

0 1 131.072 ms 65.536 ms 43.691 ms 217/E

1 0 524.288 ms 262.14 ms 174.76 ms 219/E

1 1 2.098 s 1.049 s 699.05 ms 221/E

Time-out Tolerance(–0 ms/+...) 32.8 ms 16.4 ms 10.9 ms 215/E


7.1 Phase-Locked Loop Synthesizer

The phase-locked loop synthesizer (PLL) generates clocks for the CPU, bus circuitry, and A/D convert-er. The clocks for the SCI and timers are derived directly from the EXTAL clock. The EXTAL clock alsoprovides the reference for the synthesizer which generates a frequency that is a multiple of the EXTALclock frequency. Values written to the SYNR register determine the factor by which the EXTAL clock isscaled. Refer to Figure 8.

The PLL has two frequency bandwidths which are automatically selected whenever AUTO = 1 in thePLLCR register. When the PLL is first enabled, the wide bandwidth is selected to provide a fast ramptime. When the desired frequency is nearly reached, the low bandwidth is selected to provide greaterstability. Manual control of bandwidth can be accomplished by clearing the AUTO bit.

Figure 8 Phase-Locked Loop Synthesizer Block Diagram

EA9 PLL BLOCK

CRYSTALOSCILLATOR

SYNR

LOOP FILTER VCO

BUSCLOCK SELECT

EXTAL

4XCLKFOR CPU

AND MEMORIES

MODULECLOCKSELECT

PLLMOFOR SCI

AND TIMER

MCS

VDDSYN

÷2

SCICLOCK

÷4SYNCHRONIZE

WITH PH2

TIMERCLOCK

TO TIMERPRESCALER

PLLTO

÷4 PH2

E

EXTALPIN

0 = EXTAL1 = 4XCLK

BCS

0 = EXTAL1 = VCOUT

VCOUT

2(Y + 1)•(2X)Y = SYNY[1:0]X = SYNX[5:0]

XFCPIN

XTALPIN

FREQUENCYDIVIDER

PHASEDETECT

VCOUTPCOMPEXTAL

TO SCI MODULUSBAUD GENERATOR

SCI BAUD CLOCK

PHASE-LOCKEDLOOP SYNTHESIZER

EXTERNALCRYSTAL

VDDSYNPIN

XFC


PLLON — PLL System EnableThis bit activates the PLL synthesizer circuit without connecting its output to the control circuit. This al-lows the synthesizer to stabilize before it can drive the CPU clocks. This bit resets to one, allowing thesynthesizer to stabilize as the device is being powered up.

0 = PLL is off1 = PLL is on

BCS — Bus Clock SelectThis bit determines which signal drives the clock circuitry generating the bus clocks. Refer to Figure 8.Once BCS has been changed, up to 1.5 EXTAL cycles + 1.5 PLLOUT cycles may be required for thetransition. During the transition, all CPU activity will cease. BCS is cleared by a STOP or WAIT instruc-tion or when VDDSYN falls to the VSS level.

0 = EXTAL drives the clock circuit1 = VCOUT drives the clock circuit

NOTE PLLON and BCS have built-in protection such that the PLL cannot be selected todrive any clocks if the PLL is off. Similarly, the PLL cannot be turned off if it hasbeen selected as a clock source. Turning the PLL on and selecting its output as aclock source require two separate writes to the PLLCR register.

AUTO — Automatic/Manual Loop Filter Bandwidth ControlThis bit selects between automatic bandwidth control circuits within the phase detect block and manualbandwidth control. Refer to Table 13.

0 = Automatic bandwidth control is selected1 = Bandwidth control is manual

BWC — Loop Filter Bandwidth Control/StatusBandwidth control is manual only when AUTO = 0. Since the low bandwidth driver is always enabled,BWC determines if the high bandwidth driver is enabled. When AUTO = 1, BWC is a read-only statusbit that indicates which mode has been selected by the internal circuit. During PLL start-up in automaticmode, the high bandwidth driver is enabled by internal circuitry until the PLL is near the selected fre-quency. The high bandwidth driver is then disabled and BWC is cleared. Refer to Table 13.

0 = Only the low bandwidth driver is enabled1 = Both low and high bandwidth drivers are selected

VCOT — Voltage Controlled Oscillator (VCO) TestThis bit is used to isolate the loop filter from the VCO to aid in factory testing of the PLL. VCOT is alwaysset when AUTO = 1 (automatic bandwidth control mode). This bit can be written only in special testmode.

0 = Loop filter low bandwidth mode is disabled (factory test only)1 = Loop filter operates according to values of AUTO and BWC control bits

PLLCR — PLL Control $1036

BIT 7 6 5 4 3 2 1 BIT 0PLLON BCS AUTO BWC VCOT MCS LCK WEN

RESET: 1 0 1 1 1 0 0 0

Table 13 Loop Filter Bandwidth Driver Control

AUTO BWC VCOT High Bandwidth Driver Low Bandwidth Driver

0 0 0 Off Off

0 0 1 Off On

0 1 0 On Off

0 1 1 On On

1 X 1 Automatic On


MCS — Module Clock SelectThis bit determines which clock signal drives the SCI and timer.

0 = EXTAL is the clock source for SCI and timer divider chains1 = 4XCLK is the clock source for the SCI and timer divider chains

LCK— Synthesizer Lock Detect FlagThis is a read-only status bit that indicates when the PLL has stabilized. BCS cannot be set (selectingVCOUT as a clock source) until LCK is set.

0 = The PLL is not stable1 = The PLL has stabilized

WEN — WAIT EnableThis bit determines whether the EXTAL signal will be used to drive the CPU clocks while the device isin WAIT mode. When this feature is enabled, entering wait mode clears BCS (selecting EXTAL as thesource for CPU clocks) and reduces the PLL frequency to the lowest value, modulus 1. Any interrupt orreset or the assertion of the RAF bit within the SCI (if the receiver is enabled by RE = 1) will allow thePLL to resume operation at the frequency selected in SYNR register. Then the user must set BCS toselect VCOUT as the source for CPU clocks.

0 = VCOUT remains connected to the 4XCLK circuit during operation in WAIT mode. 1 = After stacking prior to entering WAIT mode, BCS is cleared and the PLL is maintained at the

lowest frequency available (modulus 1).

This register resets to $06 for a preset multiplication factor of 14.

SYNX[1:0] — Binary Tap Select BitsThese two bits select one of four binary taps. SYNX[1:0] affect the frequency multiplication factor, vari-able X according to the formula below.

SYNY[5:0] — Modulo Counter Rate Select BitsThese six bits select one of 64 binary values that affect the frequency multiplication factor, variable Yaccording to the formula below.

WhereX = the value represented by bits SYNX[1:0]Y = the value represented by bits SYNY[5:0]

7.2 Main Timer

The main timer consists of the timer prescaler, the free-running counter, and the capture/compare unit.The timer prescaler selects one of four division rates and drives the free-running 16-bit counter. Thecapture/compare unit has three channels for input capture, four channels for output compare, and onechannel that can be configured as a fourth input capture or a fifth output compare. Timer channels con-figured for input capture (ICx) cause the current value of the free-running counter to be latched into aninput capture register (TICx) when a pulse edge is detected on the corresponding pin. Channels con-figured for output compare allow a pulse to be output when the free-running counter matches a valueloaded into an output compare register (TOCx). Figure 9 shows a detailed block diagram of the timerprescaler and the capture/compare unit.

SYNR — Frequency Synthesizer Control $1037

BIT 7 6 5 4 3 2 1 BIT 0SYNX1 SYNX0 SYNY5 SYNY4 SYNY3 SYNY2 SYNY1 SYNY0

RESET: 0 0 0 0 0 1 1 0

2 Y 1+( ) 2X( )⋅ ⋅


Figure 9 Main Timer Block Diagram

EA9 CC BLOCK

PLLTO *(PLLMO ÷ 4)

16-BIT LATCH CLK

PA0/IC3

4

3

5

6

7

8

2

1

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

PORT A PIN CONTROL

OC1I

OC2I

OC3I

OC4I

I4/O5I

IC1I

IC2I

IC3I

TFLG1STATUSFLAGS

FOC1

FOC2

FOC3

FOC4

FOC5

OC1F

OC2F

OC3F

OC4F

I4/O5F

IC1F

IC2F

IC3F

PA1/IC2

PA2/IC1

PA3/OC5/IC4/OC1

PA4/OC4/OC1

PA5/OC3/OC1

PA6/OC2/OC1

PA7/OC1/PAI

I4/O5

16-BIT COMPARATOR

TOC1 (HI) TOC1 (LO)

=

16-BIT COMPARATOR

TOC2 (HI) TOC2 (LO)

=

16-BIT COMPARATOR

TOC3 (HI) TOC3 (LO)

=

16-BIT COMPARATOR

TOC4 (HI) TOC4 (LO)

=

16-BIT LATCH

TIC1 (HI) TIC1 (LO)

CLK

16-BIT LATCH

TIC2 (HI) TIC2 (LO)

CLK

16-BIT LATCH

TIC3 (HI) TIC3 (LO)

CLK

16-BIT COMPARATOR

TI4/O5 (HI) TI4/O5 (LO)

=

16-BIT FREE RUNNINGCOUNTER

TCNT (HI) TCNT (LO)9

TOI

TOF

INTERRUPT REQUESTS(FURTHER QUALIFIED BY

I BIT IN CCR)

TAPS FOR RTI,COP WATCHDOG, ANDPULSE ACCUMULATOR

PRESCALERDIVIDE BY

1, 4, 8, OR 16PR1 PR0

16-BIT TIMER BUS

OC5

IC4

TO PULSEACCUMULATOR

TMSK1INTERRUPTENABLES

CFORCFORCE OUTPUT

COMPARE

PINFUNCTIONS

* REFER TO PLL BLOCK DIAGRAM.


FOC[1:5] — Force Output CompareWrite ones to force compare(s)

0 = Not affected1 = Output x action occurs


Set bit(s) to enable OC1 to control corresponding port A pin(s). If OC1Mx is set, data in OC1Dx is outputon port A pin x upon successful OC1 compares.


Set bit(s) to enable OC1 to control corresponding port A pin(s). If OC1Mx is set, data in OC1Dx is outputto port A bit x on successful OC1 compares.


TCNT resets to $0000. In normal modes (SMOD = 0), TCNT is a read-only register.

TICx is not affected by reset.

CFORC — Timer Compare Force $100B

BIT 7 6 5 4 3 2 1 BIT 0FOC1 FOC2 FOC3 FOC4 FOC5 — — —

RESET: 0 0 0 0 0 0 0 0

OC1M — Output Compare 1 Mask $100C

BIT 7 6 5 4 3 2 1 BIT 0OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 — — —

RESET: 0 0 0 0 0 0 0 0

OC1D — Output Compare 1 Data $100D

BIT 7 6 5 4 3 2 1 BIT 0OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 — — —

RESET: 0 0 0 0 0 0 0 0

TCNT — Timer Counter $100E–$100F

BIT 15 14 13 12 11 10 9 BIT 8 TCNT (HI)BIT 7 6 5 4 3 2 1 BIT 0 TCNT (LO)

TIC1–TIC3 — Timer Input Capture $1010–$1015

$1010 BIT 15 14 13 12 11 10 9 BIT 8 TIC1 (HI)$1011 BIT 7 6 5 4 3 2 1 BIT 0 TIC1 (LO)




All TOCx register pairs reset to $FFFF.

This is a shared register and is either input capture 4 or output compare 5 depending on the state of bitI4/O5 in PACTL. Writes to TI4/O5 have no effect when this register is configured as input capture 4. TheTI4/O5 register pair resets to $FFFF.

TOC1–TOC4 — Timer Output Compare $1016–$101D

$1016 BIT 15 14 13 12 11 10 9 BIT 8 TOC1 (HI)$1017 BIT 7 6 5 4 3 2 1 BIT 0 TOC1 (LO)

$1018 BIT 15 14 13 12 11 10 9 BIT 8 TOC2 (HI)$1019 BIT 7 6 5 4 3 2 1 BIT 0 TOC2 (LO)

$101A BIT 15 14 13 12 11 10 9 BIT 8 TOC3 (HI)$101B BIT 7 6 5 4 3 2 1 BIT 0 TOC3 (LO)

$101C BIT 15 14 13 12 11 10 9 BIT 8 TOC4 (HI)$101D BIT 7 6 5 4 3 2 1 BIT 0 TOC4 (LO)

TI4/O5 — Timer Input Capture 4/Output Compare 5 $101E–$101F

BIT 15 14 13 12 11 10 9 BIT 8 TCNT (HI)BIT 7 6 5 4 3 2 1 BIT 0 TCNT (LO)

TCTL1 — Timer Control 1 $1020

BIT 7 6 5 4 3 2 1 BIT 0OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5

RESET: 0 0 0 0 0 0 0 0

Table 14 Output Compare Channel Configuration

OMx OLx Action on Successful Compare

0 0 None — Output Compare Channel (OCx) disabled

0 1 Toggle OCx output pin logic level

1 0 Drive OCx output pin low

1 1 Drive OCx output pin high

TCTL2 — Timer Control 2 $1021

BIT 7 6 5 4 3 2 1 BIT 0EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A

RESET: 0 0 0 0 0 0 0 0

Table 15 Input Capture Channel Configuration

EDGxB EDGxA Input Capture Configuration

0 0 Input Capture Channel (ICx) disabled

0 1 Capture on rising edge on ICx input pin

1 0 Capture on falling edge on ICx input pin

1 1 Capture on any edge on ICx input pin


OC1I–OC4I — Output Compare (OCx) Interrupt EnableIf the OCxI enable bit is set when a match occurs, an interrupt is generated.

0 = Interrupts from OCx channel disabled1 = Successful compares on OCx channel generate interrupts

I4/O5I — Input Capture 4/Output Compare 5 Interrupt EnableWhen I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit and edges on the I4/O5pin generate interrupts. When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enablebit and successful matches generate interrupts.

0 = Interrupts from IC4/OC5 channel disabled1 = Interrupts from IC4/OC5 channel enabled

IC1I–IC3I — Input Capture (ICx) Interrupt EnableIf the ICxI enable bit is set when an edge is detected on the ICx pin, an interrupt is generated.

0 = Interrupts from ICx channel disabled1 = Edges detected on ICx pin generate interrupts

NOTEBits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enablethe corresponding interrupt sources.

Clear a flag by writing a one to the appropriate bit.

OC1F–OC4F — Output Compare (OCx) Interrupt FlagIf the OCxI enable bit is set when a match occurs, the corresponding flag bit is set and an interrupt isgenerated.

0 = No match has occurred1 = A successful compare has occurred on OCx channel

I4/O5I — Input Capture 4/Output Compare 5 Interrupt EnableWhen I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit and edges (rising or fall-ing, depending on configuration) on the I4/O5 pin cause this flag to be set and an interrupt is generated.When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit and successful match-es cause this flag to be set and an interrupt generated.

0 = Interrupts from IC4/OC5 channel disabled1 = Interrupts from IC4/OC5 channel enabled

IC1I–IC3I — Input Capture (ICx) Interrupt EnableIf the ICxI enable bit is set when an edge (rising or falling, depending on configuration) is detected onthe ICx pin, an interrupt is generated.

0 = Interrupts from ICx channel disabled1 = Edges detected on ICx pin generate interrupts

TMSK1 — Timer Interrupt Mask 1 $1022

BIT 7 6 5 4 3 2 1 BIT 0OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I

RESET: 0 0 0 0 0 0 0 0

TFLG1 — Timer Interrupt Flag 1 $1023

BIT 7 6 5 4 3 2 1 BIT 0OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F

RESET: 0 0 0 0 0 0 0 0


Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset innormal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time.

TOI — Timer Overflow Interrupt EnableIf the TOI enable bit is set when the value in the timer counter register (TCNT) changes from $FFFF to$0000, an interrupt is generated.

0 = Timer overflow interrupts disabled1 = Interrupts are generated each time TCNT rolls over to $0000

RTII — Real-Time Interrupt EnableIf RTII enable bit is set, interrupts are generated at the rate determined by the real-time interrupt rate(RTR[1:0]) bits in PACTL.

0 = Periodic interrupts are disabled1 = Interrupts are generated at the rate determined by RTR[1:0]

PAOVI — Pulse Accumulator Overflow Interrupt EnableIf the PAOVI enable bit is set when the pulse accumulator counter register (PACNT) changes from$FFFF to $0000 an interrupt is generated.

0 = PCNT overflow interrupts are disabled1 = Interrupts are generated each time PCNT rolls over to $0000

PAII — Pulse Accumulator Input Edge Interrupt EnableIf the PAII enable bit is set when an edge (rising or falling, depending on configuration) is detected onthe pulse accumulator input pin (PA7/PAI), an interrupt is generated.

0 = Interrupts from edges on PAI pin are disabled1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration)


PR[1:0] — Timer Prescaler Select


BIT 7 6 5 4 3 2 1 BIT 0TOI RTII PAOVI PAII — — PR1 PR0

RESET: 0 0 0 0 0 0 0 0

Table 16 Main Timer Prescaler Selection

PR1 PR0 Prescaler Selected

0 0 ÷1

0 1 ÷4

1 0 ÷8

1 1 ÷16


TOF — Timer Overflow Interrupt FlagIf the TOI enable bit is set when the timer counter register (TCNT) changes from $FFFF to $0000, thisflag is set and an interrupt is generated.

0 = TCNT has not rolled over since either the TOF flag bit was last cleared or the TOI enable bitwas set.

1 = TCNT has rolled over to $0000

RTIF — Real-Time Interrupt FlagIf RTII enable bit is set, this flag is set and an interrupt is generated periodically at the rate determinedby the real-time interrupt rate (RTR[1:0]) bits in PACTL.

0 = No periodic interrupt has occurred since either the RTIF flag bit was last cleared or when theRTII enable bit was set

1 = A periodic interrupt has occurred

PAOVF — Pulse Accumulator Overflow Interrupt FlagIf the PAOVI enable bit is set when the pulse accumulator counter register (PCNT) rolls over to $0000,this flag is set and an interrupt is generated.

0 = PCNT has not rolled over since either the PAOVF flag bit was last cleared or the PAOVI enablebit was set.

1 = PCNT has rolled over to $0000

PAIF — Pulse Accumulator Input Edge Interrupt FlagIf the PAII enable bit is set when an edge is detected on the pulse accumulator input pin (PA7/PAI), thisflag is set and an interrupt is generated.

0 = No edge has been detected on the PAI pin1 = An edge (rising or falling, depending on configuration) has been detected on the PAI pin



Bit 7 — Not ImplementedAlways reads zero

PAEN — Pulse Accumulator EnableRefer to 7.4 Pulse Accumulator.

PAMOD — Pulse Accumulator Mode SelectRefer to 7.4 Pulse Accumulator.

PEDGE — Pulse Accumulator Input Edge SelectRefer to 7.4 Pulse Accumulator.


BIT 7 6 5 4 3 2 1 BIT 0TOF RTIF PAOVF PAIF — — — —

RESET: 0 0 0 0 0 0 0 0

PACTL — Pulse Accumulator Control $1026

BIT 7 6 5 4 3 2 1 BIT 0— PAEN PAMOD PEDGE — I4/O5 RTR1 RTR0

RESET: 0 0 0 0 0 0 0 0



I4/O5 — Input Capture 4/Output Compare 5 Select0 = Interrupts from edges on PAI pin are disabled1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration)

RTR[1:0] — Real-Time Interrupt Rate Select

ADPU — A/D Converter Power upRefer to 9 Analog-to-Digital Converter

CSEL — Clock Select0 = A/D and EEPROM use the system E clock1 = A/D and EEPROM use internal RC clock

IRQE — IRQ Select Edge-Sensitive OnlyRefer to 5 Resets and Interrupts


CME — Clock Monitor Enable0 = Clock monitor disabled; slow clock can be used.1 = Slow or stopped clocks cause COP failure reset.


CR[1:0] — COP Timer Rate SelectRefer to 5 Resets and Interrupts

Table 17 Real-Time Interrupt Rates

Rate RTI Rate Selected

RTR[1:0] Selected E = 1.0 MHz E = 2.0 MHz E = 3.0 MHz

0 0 213 ÷ E 8.192 ms 4.096 ms 2.731 ms

0 1 214 ÷ E 16.384 ms 8.192 ms 5.461 ms

1 0 215 ÷ E 32.768 ms 16.384 ms 10.923 ms

1 1 216 ÷ E 65.536 ms 32.768 ms 21.845 ms




Table 18 COP Timer Rate Selection

CR[1:0]Rate

SelectedPeriod Length

E = 1.0 MHz E = 2.0 MHz E = 3.0 MHz

0 0 215 ÷ E 32.768 ms 16.384 ms 10.923 ms

0 1 217 ÷ E 131.072 ms 65.536 ms 43.691 ms

1 0 219 ÷ E 524.288 ms 262.140 ms 174.76 ms

1 1 221 ÷ E 2.097 s 1.049 s 699.05 ms


7.3 Real-Time Interrupt

The real-time interrupt (RTI) function can generate interrupts at different fixed periodic rates. Theserates are a function of the MCU oscillator frequency and the value of the software-accessible controlbits, RTR1 and RTR0. These bits determine the rate at which interrupts are requested by the RTI sys-

tem. The RTI system is driven by an E divided by 213 rate clock compensated so that it is independentof the timer prescaler. The RTR1 and RTR0 control bits select an additional division factor. RTI is setto its fastest rate by default out of reset and can be changed at any time.

TOF — Timer Overflow Interrupt FlagRefer to 7.2 Main Timer

RTIF — Real-Time Interrupt FlagIf RTII enable bit is set, this flag is set and an interrupt is generated periodically at the rate determinedby the real-time interrupt rate (RTR[1:0]) bits in PACTL.

0 = No periodic interrupt has occurred since either the RTIF flag bit was last cleared or the RTIIenable bit was set

1 = A periodic interrupt has occurred

PAOVF — Pulse Accumulator Overflow Interrupt FlagRefer to 7.4 Pulse Accumulator

PAIF — Pulse Accumulator Input Edge Interrupt FlagRefer to 7.4 Pulse Accumulator


Table 19 Real-Time Interrupt Rates (Period Length)

Period Length Period Length


0 0 213 ÷ E 8.192 ms 4.096 ms 2.731 ms

0 1 214 ÷ E 16.384 ms 8.192 ms 5.461 ms

1 0 215 ÷ E 32.768 ms 16.384 ms 10.923 ms

1 1 216 ÷ E 65.536 ms 32.768 ms 21.845 ms

Table 20 Real-Time Interrupt Rates (Frequency)

Maximum Maximum Interrupt Frequency

RTR[1:0] Frequency Possible E = 1.0 MHz E = 2.0 MHz E = 3.0 MHz

0 0 213 ÷ E 122.070 Hz 244.141 Hz 366.211 Hz

0 1 214 ÷ E 61.035 Hz 122.070 Hz 183.105 Hz

1 0 215 ÷ E 30.518 Hz 61.035 Hz 91.553 Hz

1 1 216 ÷ E 15.258 Hz 30.518 Hz 45.776 Hz



RESET: 0 0 0 0 0 0 0 0




PAEN — Pulse Accumulator EnableRefer to 7.4 Pulse Accumulator

PAMOD — Pulse Accumulator Mode SelectRefer to 7.4 Pulse Accumulator

PEDGE — Pulse Accumulator Input Edge SelectRefer to 7.4 Pulse Accumulator


I4/O5 — Input Capture 4/Output Compare 5 SelectRefer to 7.2 Main Timer

RTR[1:0] — Real-Time Interrupt Rate Select

7.4 Pulse Accumulator

M68HC11-family MCUs have an 8-bit counter within the timing system that can be configured for eventcounting or for gated time accumulation. The counter (PACNT) can be read or written at any time.

The port A bit 7 I/O pin can be configured to act as a clock in event counting mode and edges on thepulse accumulator input pin cause the counter (PACNT) to increment. When the pulse accumulator isconfigured for time accumulation, an edge on the pulse accumulator input pin enables a free-runningclock (E divided by 64) that drives PACNT in gated time accumulation mode. Refer to Figure 10.



RESET: 0 0 0 0 0 0 0 0

Table 21 Real-Time Interrupt Rates

Rate RTI Rate Selected


0 0 213 ÷ E 8.192 ms 4.096 ms 2.731 ms

0 1 214 ÷ E 16.384 ms 8.192 ms 5.461 ms

1 0 215 ÷ E 32.768 ms 16.384 ms 10.923 ms

1 1 216 ÷ E 65.536 ms 32.768 ms 21.845 ms


Figure 10 Pulse Accumulator Block Diagram



PAEN — Pulse Accumulator Enable0 = Periodic interrupts are disabled1 = Interrupts are generated at the rate determined by RTR[1:0]

PAMOD — Pulse Accumulator Mode Select0 = PCNT overflow interrupts are disabled1 = Interrupts are generated each time PCNT rolls over to $0000



RESET: 0 0 0 0 0 0 0 0

EA9 PLS ACC BLOCK

PED

GE

PAM

OD

PAEN

PACTL CONTROL

INTERNALDATA BUS

PACNT 8-BIT COUNTERPA7/PAI/OC1

INTERRUPTREQUESTS

PAIF

PAO

VF

TFLG2 INTERRUPT STATUS

PAO

VI

PAII

PAOVF

PAOVI

PAIF

PAII

TMSK2 INT ENABLES

1

2

OVERFLOW

ENABLE

DISABLEFLAG SETTING

CLOCK

PAI EDGE

PAEN

PAEN

2:1MUX

OUTPUTBUFFER

INPUT BUFFERAND

EDGE DETECTOR

FROMMAIN TIMER OC1

DATABUS

MCU PIN

PLLTO ÷ 64 CLOCK *(FROM MAIN TIMER)

FROM DATA DIRECTIONBIT FOR PORT A PIN 7

* REFER TO TIMER AND PLL BLOCK DIAGRAMS.


PEDGE — Pulse Accumulator Input Edge Select0 = Interrupts from edges on PAI pin are disabled1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration)


I4/O5 — Input Capture 4/Output Compare 5 SelectRefer to 7.2 Main Timer.

RTR[1:0] — Timer Prescaler SelectRefer to 7.3 Real-Time Interrupt.


TOI — Timer Overflow Interrupt EnableRefer to 7.2 Main Timer.

RTII — Real-Time Interrupt EnableRefer to 7.3 Real-Time Interrupt.

PAOVI — Pulse Accumulator Overflow Interrupt EnableIf the PAOVI enable bit is set when the pulse accumulator counter register (PACNT) changes from$FFFF to $0000 an interrupt is generated.

0 = PCNT overflow interrupts are disabled1 = Interrupts are generated each time PCNT rolls over to $0000

PAII — Pulse Accumulator Input Edge Interrupt EnableIf the PAII enable bit is set when an edge (rising or falling, depending on configuration) is detected onthe pulse accumulator input pin (PA7/PAI), an interrupt is generated.

0 = Interrupts from edges on PAI pin are disabled1 = Edges detected on PAI pin generate interrupts (rising or falling, depending on configuration)


PR[1:0] — Timer Prescaler SelectRefer to 7.2 Main Timer.

PACNT — Pulse Accumulator Counter $1027

BIT 7 6 5 4 3 2 1 BIT 0BIT 7 6 5 4 3 2 1 BIT 0

Can be read and written, unaffected by reset.


BIT 7 6 5 4 3 2 1 BIT 0TOI RTII PAOVI PAII — — PR1 PR0

RESET: 0 0 0 0 0 0 0 0


TOF — Timer Overflow Interrupt FlagRefer to 7.2 Main Timer.

RTIF — Real-Time Interrupt FlagRefer to 7.3 Real-Time Interrupt.

PAOVF — Pulse Accumulator Overflow Interrupt FlagIf the PAOVI enable bit is set when the pulse accumulator counter register (PCNT) rolls over to $0000,this flag is set and an interrupt is generated.

0 = PCNT has not rolled over since either the PAOVF flag bit was last cleared or when the PAOVIenable bit was set.

1 = PCNT has rolled over to $0000

PAIF — Pulse Accumulator Input Edge Interrupt FlagIf the PAII enable bit is set when an edge is detected on the pulse accumulator input pin (PA7/PAI), thisflag is set and an interrupt is generated.

0 = No edge has been detected on the PAI pin1 = An edge (rising or falling, depending on configuration) has been detected on the PAI pin




RESET: 0 0 0 0 0 0 0 0


8 Serial Communications Interface The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is anindependent serial I/O subsystem in MC68HC(7)11EA9 MCUs. The registers and control bits used inprevious M68HC11 SCI systems have been rearranged and new features added. New or enhanced fea-tures include the following:

• A 13-bit modulus prescaler that allows greater baud rate control• A new idle mode detect, independent of preceding serial data• A receiver active flag• Hardware parity for both transmitter and receiver

The enhanced baud rate generator is shown in the following diagram. Refer to the table of SCI baudrate control values for standard values.

Figure 11 SCI Baud Generator Circuit Diagram

13-BIT COUNTER

13-BIT COMPARE

SCBDH/L SCI BAUD CONTROL

INTERNALPHASE 2 CLOCK

(PH2)

= ÷ 2SYNCHRONIZE

WITH PH2

÷ 16

RECEIVERBAUD RATE

CLOCK

TRANSMITTERBAUD RATE

CLOCK

SCI BAUD CLOCKEXTAL ÷ 2, IF MCS = 04XCLK ÷ 2, IF MCS = 1 RESET

EA9 BAUD GEN BLOCK


Figure 12 SCI Transmitter Block Diagram

EA9 SCI TX BLOCK

FENF

OR

IDLE

RD

RF

TCTDR

E

SCSR1 SCI STATUS 1

SBK

RW

U

RE

TEILIE

RIE

TCIE

TIE

SCCR2 SCI CONTROL 2

TRANSMITTERCONTROL LOGIC

TCIE

TC

TIE

TDRE

SCI RxREQUESTS

SCI INTERRUPTREQUEST

INTERNALDATA BUS

PIN BUFFERAND CONTROL

H (8) 7 6 5 4 3 2 1 0 L

10 (11) - BIT Tx SHIFT REGISTER

DDD1

PD1TxD

SCDRL Tx/Rx DATA LOW

TRAN

SFER

Tx

BUFF

ER

SHIF

T EN

ABLE

JAM

EN

ABLE

PREA

MBL

E—JA

M 1

s

BREA

K—JA

M 0

s

(WRITE ONLY)

FORCE PINDIRECTION (OUT)

SIZE

8/9

WAK

E

MLOO

PS

SCCR1 SCI CONTROL 1

TRANSMITTERCLOCK

(FROM MODULUS BAUDRATE GENERATOR)

PARITYGENERATOR

ILT

PE PT

SCDRH Tx/Rx DATA HIGH

01234567

R8 T8 ——————$x076

$x077

WO

MS

PF


Figure 13 SCI Receiver Block Diagram

EA9 SCI RX BLOC

SCDRL Tx/Rx DATA LOW

SCDRH Tx/Rx DATA HIGH

01234567

R8 T8 ——————$x076

$x077

FENF

OR

IDLE

RD

RF

TCTDR

E

SCSR1 SCI STATUS 1SB

K

RW

U

RE

TEILIE

RIE

TCIE

TIE

SCCR2 SCI CONTROL 2

WAK

E

MWO

MS

LOO

PS

WAKEUPLOGIC

RIE

OR

ILIE

IDLE

SCI TxREQUESTS

SCI INTERRUPTREQUEST INTERNAL

DATA BUS

PIN BUFFERAND CONTROL

DDD0

PD0RxD

STO

P

(8) 7 6 5 4 3 2 1 0

10 (11) - BITRx SHIFT REGISTER

(READ ONLY)

SCCR1 SCI CONTROL 1

RIE

RDRF

STAR

T

MSB ALL ONES

DATARECOVERY

÷16

RWU

M

RE(DISABLES

PIN DRIVER)

RECEIVERCLOCK

(FROM MODULUSBAUD RATE

GENERATOR)

ILT

PE PT

PARITYDETECT

PF

RAF

SCSR2 SCI STATUS 2


BTST — Baud Register Test (TEST)Factory test only

BSPL — Baud Rate Counter Split (TEST)Factory test only


SBR[12:0] — SCI Baud Rate Select Bits

Use the following formula to calculate SCI baud rate. Refer to the table of baud rate control values forexample rates:

SCI baud rate = EXTAL ÷ (32 • BR)

where BR is the contents of SBR[12:0] in SCBDH,L (BR = 1, 2, 3 ... 8191 decimal, or BR = $0001,$0002, $0003 ... $1FFF hexadecimal)

BR = 0 disables the baud rate generator.

SCBDH, SCBDL — SCI Baud Rate Select High, SCI Baud Rate Select Low $1028, $1029

BIT 7 6 5 4 3 2 1 BIT 0$1028 BTST BSPL — SBR12 SBR11 SBR10 SBR9 SBR8 High

RESET: 0 0 0 0 0 0 0 0$1029 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Low

RESET: 0 0 0 0 0 1 0 0

Table 22 Baud Rate Selection

Target Crystal Frequency (XTAL)

Baud 8 MHz 12 MHz 16 MHz

Rate Dec Value Hex Value Dec Value Hex Value Dec Value Hex Value

110 2272 $08E0 3409 $0D51 4545 $11C1

312 156 78 2500 $09C4 3333 $0D05

300 833 $0341 1250 $04E2 1666 $0682

600 416 $01A0 625 $0271 833 $0341

1200 208 $00D0 312 $0138 416 $01A0

2400 104 $0068 156 $009C 208 $00D0

4800 52 $0034 78 $004E 104 $0068

9600 26 $001A 39 $0027 52 $0034

19.2K 13 $000D 20 $0014 26 $001A

38.4K — — — — 13 $000D


LOOPS — SCI LOOP Mode Enable0 = SCI transmit and receive operate normally1 = SCI transmit and receive are disconnected from TxD and RxD pins, and transmitter output is

fed back into the receiver input

WOMS — Wired-Or Mode Option for PD[1:0] (See also DWOM bit in SPCR.)0 = TxD and RxD operate normally1 = TxD and RxD are open drains if operating as an output


M — Mode (Select Character Format)0 = Start, 8 data bits, 1 stop bit1 = Start, 9 data bits, 1 stop bit

WAKE — Wake-Up by Address Mark/Idle0 = Wake-up by IDLE line recognition1 = Wake-up by address mark (most significant data bit set)

ILT — Idle Line Type0 = Short (SCI counts consecutive ones after start bit)1 = Long (SCI counts ones only after stop bit)

PE — Parity Enable0 = Parity disabled1 = Parity enabled

PT — Parity Type0 = Parity even (even number of ones causes parity bit to be zero, odd number of ones causes par-

ity bit to be one)1 = Parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity

bit to be one)

TIE — Transmit Interrupt Enable0 = TDRE interrupts disabled1 = SCI interrupt requested when TDRE status flag is set

TCIE — Transmit Complete Interrupt Enable0 = TC interrupts disabled1 = SCI interrupt requested when TC status flag is set

RIE — Receiver Interrupt Enable0 = RDRF and OR interrupts disabled1 = SCI interrupt requested when RDRF flag or the OR status flag is set

SCCR1 — SCI Control Register 1 $102A

BIT 7 6 5 4 3 2 1 BIT 0LOOPS WOMS — M WAKE ILT PE PT

RESET: 0 0 0 0 0 0 0 0

SCCR2 — SCI Control Register 2 $102B

BIT 7 6 5 4 3 2 1 BIT 0TIE TCIE RIE ILIE TE RE RWU SBK

RESET: 0 0 0 0 0 0 0 0


ILIE — Idle Line Interrupt Enable0 = IDLE interrupts disabled 1 = SCI interrupt requested when IDLE status flag is set

TE — Transmitter Enable0 = Transmitter disabled1 = Transmitter enabled

RE — Receiver Enable0 = Receiver disabled1 = Receiver enabled

RWU — Receiver Wake-Up Control0 = Normal SCI receiver1 = Wake-up enabled and receiver interrupts inhibited

SBK — Send Break0 = Break generator off1 = Break codes generated as long as SBK = 1

TDRE — Transmit Data Register Empty FlagSet if transmit data can be written to SCDR; if TDRE = 0, transmit data register is busy. Cleared bySCSR1 read with TDRE set, followed by SCDR write.

0 = Transmit data register contains data and is busy1 = Transmit data register is empty and SCDR can be written

TC — Transmit Complete FlagSet if transmitter is idle (no data, preamble, or break transmission in progress). Cleared by SCSR1 readwith TC set, followed by SCDR write.

0 = Transmitter is busy1 = Transmitter is idle and SCDR can be written

RDRF — Receive Data Register Full FlagSet if a received character is ready to be read from SCDR. Cleared by SCSR1 read with RDRF set,followed by SCDR read.

IDLE — Idle Line Detected FlagOnce cleared, IDLE is set again until the RxD line has been active and becomes idle once more. IDLEflag is inhibited when RWU = 1. Set if the RxD line is idle. Cleared by SCSR1 read with IDLE set, fol-lowed by SCDR read.

OR — Overrun Error FlagSet if a new character is received before a previously received character is read from SCDR. Clearedby SCSR1 read with OR set, followed by SCDR read.

NF — Noise Error FlagSet if majority sample logic detects anything other than a unanimous decision. Cleared by SCSR1 readwith NF set, followed by SCDR read.

FE — Framing ErrorSet if a zero is detected where a stop bit was expected. Cleared by SCSR1 read with FE set, followedby SCDR read.

SCSR1 — SCI Status Register 1 $102C

BIT 7 6 5 4 3 2 1 BIT 0TDRE TC RDRF IDLE OR NF FE PF

RESET: 0 0 0 0 0 0 0 0


PF — Parity Error FlagSet if received data has incorrect parity. Cleared by SCSR1 read with PE set, followed by SCDR read.


RAF — Receiver Active Flag (Read only)0 = The receiver circuitry is idle1 = A character is being received

R8 — Receiver Bit 8Ninth serial data bit received when SCI is configured for nine data bit operation (M = 1).

T8 — Transmitter Bit 8Ninth serial data bit transmitted when SCI is configured for nine data bit operation (M = 1).


R/T[7:0] — Receiver/Transmitter Data Bits 7 to 0SCI data is double buffered in both directions.

SCSR2 — SCI Status Register 2 $102D

BIT 7 6 5 4 3 2 1 BIT 0— — — — — — — RAF

RESET: 0 0 0 0 0 0 0 0

SCDRH, SCDRL — SCI Data High, SCI Data Low $102E, $102F

BIT 7 6 5 4 3 2 1 BIT 0$102E R8 T8 — — — — — — High$102F R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 Low


9 Analog-to-Digital ConverterThe analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution technique toconvert analog signals to digital values. The MC68HC(7)11EA9 A/D converter system, a four-channelmultiplexed-input successive-approximation converter, is accurate to ±1 least significant bit (LSB). Itdoes not require external sample and hold circuits because of the type of charge-redistribution tech-nique used.

Dedicated pins VRH and VRL provide the reference supply voltage inputs.

A multiplexer allows the single A/D converter to select one of 16 analog signals.

Figure 14 A/D Block Diagram

EA9 A/D BLOCK

PE0AN0

PE1AN1

PE2AN2

PE3AN3

PE4AN4

PE5AN5

PE6AN6

PE7AN7

ANALOGMUX

8-BIT CAPACITIVE DACWITH SAMPLE AND HOLD

SUCCESSIVE APPROXIMATIONREGISTER AND CONTROL

ADCTL A/D CONTROL

CB

CC

CD

MU

LT

SCAN

CC

F

CA

ADR1 A/D RESULT 1 ADR2 A/D RESULT 2 ADR3 A/D RESULT 3 ADR4 A/D RESULT 4

RESULT REGISTER INTERFACE

RESULT

INTERNALDATA BUS

VRH

VRL


Figure 15 A/D Conversion Sequence

Figure 16 Electrical Model of an A/D Input Pin (Sample Mode)

MSB4

CYCLES

E CLOCK

WR

ITE

TO A

DC

TL BIT 62

CYC

BIT 52

CYC

BIT 42

CYC

BIT 32

CYC

BIT 22

CYC

BIT 12

CYC

LSB2

CYCEND

12 E CYCLES

SAMPLE ANALOG INPUT SUCCESSIVE APPROXIMATION SEQUENCE

2CYC

CONVERT FOURTHCHANNEL

AND UPDATE ADR4

CONVERT THIRDCHANNEL

AND UPDATE ADR3

CONVERT SECONDCHANNEL

AND UPDATE ADR2

CONVERT FIRSTCHANNEL

AND UPDATE ADR1

SET

CC

F FL

AG

REP

EAT

SEQ

UEN

CE

IF S

CAN

= 1

ECYCLES

1289664320

EA9 A/D CONVERSION TIM

EA9 ANALOG INPUT PIN

ANALOGINPUT

PIN

400 nAJUNCTIONLEAKAGE

< 2 pF+ ~20 V– ~0.7 V

~20 pFDAC

CAPACITANCE

VRL

DIFFUSION ANDPOLY COUPLER

< 4 K½

INPUTPROTECTION

DEVICE

*THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.

*


CCF — Conversions Complete FlagSet after an A/D conversion cycle is completed. CCF is cleared by a write to ADCTL.

0 = The A/D converter is currently performing a conversion sequence1 = The A/D converter has completed a conversion, placed the result in the appropriate result reg-

ister and is currently idle


SCAN — Continuous Scan Control0 = Do four conversions and stop1 = Convert four channels in selected group continuously

MULT — Multiple Channel/Single Channel Control0 = Convert single channel selected1 = Convert four channels in selected group

CD–CA — Channel Select D through A

ADCTL — A/D Control/Status $1030

BIT 7 6 5 4 3 2 1 BIT 0CCF — SCAN MULT CD CC CB CA

RESET: I 0 I I I I I I

Table 23 A/D Converter Channel Select Control Bits

Channel Select Control Bits Channel Result in ADRx if

CD CC CB CA Signal MULT = 1

0 0 0 0 AN0 ADR1

0 0 0 1 AN1 ADR2

0 0 1 0 AN2 ADR3

0 0 1 1 AN3 ADR4

0 1 0 0 AN4 ADR1

0 1 0 1 AN5 ADR2

0 1 1 0 AN6 ADR3

0 1 1 1 AN7 ADR4

1 0 0 0 Reserved —




1 1 0 0 VRH* ADR1

1 1 0 1 VRL* ADR2

1 1 1 0 (VRH)/2* ADR3

1 1 1 1 Reserved ADR4


ADPU — A/D Converter Power-Up0 = A/D converter disabled and powered down1 = A/D converter is enabled and powered on

CSEL — Clock Select0 = A/D and EEPROM use the system E clock1 = A/D and EEPROM use internal RC clock

IRQE — IRQ Select Edge-Sensitive OnlyRefer to 5 Resets and Interrupts.


CME — Clock Monitor EnableRefer to 5 Resets and Interrupts.


CR[1:0] — COP Timer Rate SelectRefer to 5 Resets and Interrupts.

ADR1–ADR4 — A/D Results $1031–$1034

$1031 BIT 7 6 5 4 3 2 1 BIT 0 ADR1

$1032 BIT 7 6 5 4 3 2 1 BIT 0 ADR2

$1033 BIT 7 6 5 4 3 2 1 BIT 0 ADR3

$1034 BIT 7 6 5 4 3 2 1 BIT 0 ADR4

Table 24 Analog Input to 8-Bit Result Translation

Bit 7 6 5 4 3 2 1 Bit 0

% (1) 50% 25% 12.5% 6.25% 3.12% 1.56% 0.78% 0.39%

VOLTS (2) 2.5 1.250 0.625 0.3125 0.1562 0.0781 0.0391 0.0195

(1) % of VRH – VRL (2) Volts for VRL = 0; VRH = 5.0 V





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Technical Summary 8-Bit Microcontrollers7)11ea9.pdf · • Available in 52-Pin Plastic Leaded Chip...

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