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Teacher:Robert Dick Office:L477 Tech Email:dickrp...
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Advanced Digital Logic Design – EECS 303 http://ziyang.eecs.northwestern.edu/eecs303/ Teacher: Robert Dick Office: L477 Tech Email: [email protected] Phone: 847–467–2298
Transcript of Teacher:Robert Dick Office:L477 Tech Email:dickrp...
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Advanced Digital Logic Design – EECS 303
http://ziyang.eecs.northwestern.edu/eecs303/
Teacher: Robert DickOffice: L477 TechEmail: [email protected]: 847–467–2298
http://ziyang.eecs.northwestern.edu/eecs303/
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Outline
1. Implementation technologies
2. Homework
2 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Section outline
1. Implementation technologiesReview of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
3 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
5:32 decoder/demultiplexer
5 :32Decoder
Subs ys tem
\EN
S4 S3 S2 S1 S0
.
.
..
\Y31
\Y0
2Y2
1Y1
1Y0
1Y3
1Y2
2Y1
2Y0
2Y3
1G
1B
1A
139
2G
2B
2A
S4
S3
G1
G2A
G2B
CC
BB
AA
Y7
Y6
Y5
Y4
Y1
Y0
Y3
Y2
138
G1
G2A
G2B
CC
BB
AA
Y7
Y6
Y5
Y4
Y1
Y0
Y3
Y2
138
G1
G2A
G2B
CC
BB
AA
Y7
Y6
Y5
Y4
Y1
Y0
Y3
Y2
138
G1
G2A
G2B
CC
BB
AA
Y7
Y6
Y5
Y4
Y1
Y0
Y3
Y2
138
\EN
S2
S1
S0
S2
S1
S0
S2
S1
S0
S2
S1
S0
31
30
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5
4
3
2
1
0
\Y
\Y
4 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
5:32 decoder/demultiplexer implementation details
Why is G1 connected to an inverted active-low enable signal?
Why are 2A, 2B, and 2G not connected on the 74139 part?
What would happen if this design were used and the parts wereTTL (I don’t expect you to know this one already)?
How about CMOS?
5 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Section outline
1. Implementation technologiesReview of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
6 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Tally circuit example
Given n-input circuit
Count number of 1s in input
I1 Zero One
0 1 01 0 1
7 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Tally circuit example
I1 Zero One
0 1 01 0 1
Can implement using logic gates
One
Zero
8 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Tally circuit example
I1 Zero One
0 1 01 0 1
Can implement using TGs
"0"
Zero
II11
One"0"
"1"
9 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Tally circuit example
I1 Zero One
0 1 01 0 1
Can implement using TGs
Zero
One
"0"
"0"
"1"
II11
10 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
11 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
11 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
11 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
"0"
Zero
II11
One"0"
"1"
11 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
12 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
12 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
12 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
"0"
"1"
II11
12 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
4-input tally
I1 I2 Zero One Two0 0 1 0 00 1 0 1 01 0 0 1 01 1 0 0 1
13 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
4-input tally
I1 I2 Zero One Two0 0 1 0 00 1 0 1 01 0 0 1 01 1 0 0 1
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
14 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
4-input tally
I1 I2 Zero One Two0 0 1 0 00 1 0 1 01 0 0 1 01 1 0 0 1
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
15 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
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"0"
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II11
One"0"
"1"
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One
II22
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"0"
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One"0"
"1"
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"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
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II11
One"0"
"1"
"0"
Zero
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II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
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One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
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II22
"0" Two
"0"
Zero
II11
One"0"
"1"
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One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
"0"
Zero
II11
One"0"
"1"
"0"
Zero
One
II22
"0" Two
16 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
TG tally circuit
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
Zero
One
"0"
"0"
"1"
II11
Zero
One
"0"
II22
Two"0"
17 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Section outline
1. Implementation technologiesReview of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
18 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
ROMs, FPGAs, and multi-level minimization
Programmable read-only memories (PROMs)
Field-programmable gate arrays (FPGAs)
Programmable devices for prototyping
19 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Programmable read-only memories (PROMs)
2-D array of binary values
Input: Address
Output: Word
20 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
PROM
Dec
00 n− 1
Address
2 −1n
00
+5V +5V +5V +5V
Word Line 0011
Word Line 1010
Bit Lines
jj
ii
21 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Implementing logic with PROMs
F0 = A B C + A B C + A B C
F1 = A B C + A B C + A B C
F2 = A B C + A B C + A B C
F3 = A B C + A B C + A B C
22 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Truth table
A B C F3 F2 F1 F00 0 0 0 1 0 00 0 1 0 1 1 10 1 0 0 0 1 00 1 1 1 0 0 01 0 0 1 1 0 11 0 1 0 0 0 11 1 0 1 0 0 01 1 1 0 0 1 0
23 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Truth table
A B C F3 F2 F1 F00 0 0 0 1 0 00 0 1 0 1 1 10 1 0 0 0 1 00 1 1 1 0 0 01 0 0 1 1 0 11 0 1 0 0 0 11 1 0 1 0 0 01 1 1 0 0 1 0
Address
23 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Truth table
A B C F3 F2 F1 F00 0 0 0 1 0 00 0 1 0 1 1 10 1 0 0 0 1 00 1 1 1 0 0 01 0 0 1 1 0 11 0 1 0 0 0 11 1 0 1 0 0 01 1 1 0 0 1 0
Word
23 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
PROM suitable for implementing example
8 words x4 bits
addresses
outputs
24 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Memory composition
2764 EPROM
8K x 8
2764
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
O0
O1
O2
O3
O4
O5
O6
O7
OE
CS
PGM
VPP
A10
A11
A12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
O0
O1
O2
O3
O4
O5
O6
O7
OE
CS
PGM
VPP
A10
A11
A12
25 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Memory composition
++++
2764
A0A1
A2A3A4
A5A6A7A8
A9
O0
O1O2O3
O4O5O6
O7
OE
CS
P GM
VP P
A10A11A12
2764
A0A1
A2A3A4
A5A6A7A8A9
O0
O1O2O3O4O5O6
O7
OE
CS
P GM
VP P
A10A11A12
2764
A0A1
A2A3
A4A5A6A7
A8A9
O0O1O2O3O4O5O6O7
OECS
P GM
VP P
A10A11A12
2764
A0A1
A2A3A4
A5A6A7
A8
A9
O0O1O2O3
O4O5O6
O7
OECS
P GM
VP P
A10A11
A12
++ ++
A13
/OE
A12:A0
D7:D0D15:D8
U3 U2
U1 U0
++++
2764
A0A1
A2A3A4
A5A6A7A8
A9
O0
O1O2O3
O4O5O6
O7
OE
CS
P GM
VP P
A10A11A12
2764
A0A1
A2A3A4
A5A6A7A8A9
O0
O1O2O3O4O5O6
O7
OE
CS
P GM
VP P
A10A11A12
2764
A0A1
A2A3
A4A5A6A7
A8A9
O0O1O2O3O4O5O6O7
OECS
P GM
VP P
A10A11A12
2764
A0A1
A2A3A4
A5A6A7
A8
A9
O0O1O2O3
O4O5O6
O7
OECS
P GM
VP P
A10A11
A12
++ ++
A13
/OE
A12:A0
D7:D0D15:D8
U3 U2
U1 U0
16K x 16
Chip select
26 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Memory composition
++++
2764
A0A1
A2A3A4
A5A6A7A8
A9
O0
O1O2O3
O4O5O6
O7
OE
CS
P GM
VP P
A10A11A12
2764
A0A1
A2A3A4
A5A6A7A8A9
O0
O1O2O3O4O5O6
O7
OE
CS
P GM
VP P
A10A11A12
2764
A0A1
A2A3
A4A5A6A7
A8A9
O0O1O2O3O4O5O6O7
OECS
P GM
VP P
A10A11A12
2764
A0A1
A2A3A4
A5A6A7
A8
A9
O0O1O2O3
O4O5O6
O7
OECS
P GM
VP P
A10A11
A12
++ ++
A13
/OE
A12:A0
D7:D0D15:D8
U3 U2
U1 U0
++++
2764
A0A1
A2A3A4
A5A6A7A8
A9
O0
O1O2O3
O4O5O6
O7
OE
CS
P GM
VP P
A10A11A12
2764
A0A1
A2A3A4
A5A6A7A8A9
O0
O1O2O3O4O5O6
O7
OE
CS
P GM
VP P
A10A11A12
2764
A0A1
A2A3
A4A5A6A7
A8A9
O0O1O2O3O4O5O6O7
OECS
P GM
VP P
A10A11A12
2764
A0A1
A2A3A4
A5A6A7
A8
A9
O0O1O2O3
O4O5O6
O7
OECS
P GM
VP P
A10A11
A12
++ ++
A13
/OE
A12:A0
D7:D0D15:D8
U3 U2
U1 U0
16K x 16Chip select
26 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
PLA/PAL vs. PROM
PLA
Takes advantage of don’t-cares
Good at random logic
Good when product terms shared
PAL
More area-efficient for certain designs
OR-plane can’t be programmed, usually no sharing
27 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
PLA/PAL vs. PROM
PROM
Design trivial
Can’t take advantage of don’t-cares
Area-inefficient
Product/sum terms not shared
28 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Section outline
1. Implementation technologiesReview of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
29 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Field-programmable gate arrays (FPGAs)
PLAs
10–100 gate equivalent
FPGAs
AlteraActelXilinx100–1,000,000 gate equivalent
30 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Altera EPLDs
Each has from 8–48 macrocells
Macrocell behavior controlled with EPROM bits
Can be used sequentially
Has synchronous and asynchronous modes
31 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Altera erasable programmable logic devices (EPLDs)
Composed of many macrocells – 8 product term AND/OR array withprogrammable MUXs
C lk
MUX
Output
MUXQQ
F/B
MUX
Invert
Contro l
AND
ARRAY
pad
Programmab le po larity
I/O P in
Seq. Log ic
B lock
Programmab le feedback
32 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Multiple array matrix (MAX)
Altera macrocells quite limited
Can’t share product terms between macrocells
Workaround: Connect together macrocells with programmableinterconnect
33 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Multiple array matrix (MAX)
Array
8 Fixed Inputs
52 I/O P ins
8 LABs
16 Macroce lls /LAB
32 Expanders /LAB
EPM5128:
LAB A LAB H
LAB B LAB G
LAB C LAB F
LAB D LAB E
P
I
AA
Log ic
Array
B locks
(s im ilar to
macroce lls )
Globa l Routing :
Programmab le
Interconnect
34 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
MAX expander terms
Macroce ll
ARRAYI/O
Block
Expander
ProductTerm
ARRAY
I
NN
PP
UU
TT
SS
P
I
AA
I/O Pad
I/O Pad
35 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
MAX expander terms
Macroce ll
P− Term s
Expander
P− Term s
Expander product terms shared among all macrocells
36 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Altera 22V10 PAL
00AS YNCHRONOUS RE S E T(TO ALL RE GIS TE RS )
23AR
88132176220264308352396
44
22
22
OUTP UTLOGIC
MACROCE LL
P − 5810R − 5811
528572616660704748792836
484
880
440
21
33
OUTP UTLOGIC
MACROCE LL
P − 5812
R − 5813
10561100114411881232127613201364
1012
1408
924
968
1452
20
44
OUTP UT
LOGICMACROCE LL
P − 5814R − 5815
16721716176018041848189219361980
1628
2024
1496
1584
2068
1540
2112
19
55
OUTP UTLOGIC
MACROCE LL
P − 5816R − 5817
23762420246425082552259626402684
2332
2728
2156
2288
2772
22442200
28162860
11
11
00
00
11
00
00
11
DD QQ
QQS P
1100
5808
PP
RR
5809
1100 44 88 12 16 20 24 28 32 36 40
INCREMENT
FIRSTFUSENUMBERS
15
99
OUTP UTLOGIC
MACROCE LLL
P − 5824R − 5825
49725016506051045148519252365280
4928
5324
4884
17
77
OUTP UTLOGIC
MACROCE LLL
P − 5820R − 5821
38283872391639604004404840924136
3784
4180
3652
3740
4224
3696
4268
16
88
OUTP UTLOGIC
MACROCE LLL
P − 5822R − 5823
44444488453245764620466447084752
4400
4796
4312
4356
4840
18
66
OUTP UTLOGIC
MACROCE LLL
P − 5818R − 5819
31243168321232563300334433883432
3080
3476
2904
3036
3520
29922948
35643608
14
10
OUTP UTLOGIC
MACROCE LLL
P − 5826R − 5827
54125456550055445588563256765720
5368
11
5764
13
S YNCHRONOUSP RE S E T
00 44 88 12 16 20 24 28 32 36 40INCREMENTT
37 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Altera 22V10 PAL
Many product terms per output
Latches and MUXs associated with outputs
22 IO pins
10 may be used as outputs
38 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Actel programmable gate arrays
Rows of programmable logic blocks
Rows of interconnect
Columns of interconnect
Attach to rows using antifuses
39 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Actel programmable gate arrays
Each combinational logic block has 8 inputs, 1 output
No built-in sequential elements
Build flip-flops using logic blocks
40 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Actel logic block
2:1 MUX
D0
D1
S OA
2:1 MUX
D2
D3
S OB
2:1 MUX
S 0
YY
S 1
Modified 4:1 MUX
41 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Actel logic block
2:1 MUX
"0"
RR
2:1 MUX
"1"
SS
2:1 MUX QQ
"0"
Cross-couple for sequential use
42 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Actel programmable gate arrays
IO buffers, programming & test logic
IO buffers, programming & test logic
IO b
uf.
, p
rog
. &
test
log
ic
IO b
uf.
, p
rog
. &
test
log
ic
Logic modules
Wiring tracks
43 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Actel interconnect
Log ic Module
Horizontal
Track
Vertical
Track
Anti− fuse
44 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Antifuse routing
Build long routing lines from short segments
45 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Actel routing example
Log ic Modu le
Log ic Modu leLog ic Modu le
Output
Input
Input
Minimize number of antifuse hops for critical path
2-3 hops for most interconnections
46 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx logic cell arrays (LCAs)
CMOS static RAM
Run-time programmable
Serial shift-register based programming
Program on power-up (external PROM)
47 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx LCA components
Configurable logic blocks (CLBs)
IO blocks (IOBs)
Wiring channels
48 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx LCAs
IOB IOB IOB IOB
CLB CLB
CLB CLB
IOB
IO
BIO
BIO
B
W iring Channe ls
49 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx LCA features
Inputs
Input variables
Tri-state (high-Z) enable bit for output
Output clocks
50 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx LCA features
Output the input bit
Contains internal flip-flops for inputs and outputs
Fast and slow outputs available, e.g., 5 ns vs. 30 ns
Slower option limits slew rateLower noiseLower power consumption
51 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx LCA
DD QQ
OUT
INV
TS
INV
OUTPUT
S OURCE
S LEW
RATE
PAS S IVE
PULLUP
MUX
RR
DDQQ
RR
Vcc
PAD
Output
Buffer
TTL or CMOS
Input Buffer
Globa l ResetClocks
Enable
Output
Out
Direct In
Reg is tered In
Program Contro lled Options
52 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx CLB
2 flip-flops
General function of 4 variables
2 non-general functions of 5 variables
Certain special-case functions of 6 variables
Global reset
Clock
Clock enable
Independent input, DIN
53 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx CLB
Com b inationa l
Func tion
Generator
DD RD
QQ
CEMux
DD RD
QQCE
Mux
Mux
Mux
Mux
A
B
C
D
EE
Q1
Q2
Res e t
DIN
Clock
Clock
Enab le
FF
GG
XX
YY
54 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Function generator
Function
of 5
Variables
FF
GG
Mux
Mux
AA
BB
CC
DD
EE
Q1
Q2Two constrained functions of five variables
55 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Function generator
Func tion
o f 4
Variab les
FF
Mux
Mux
AA
BB
CC
DD
EE
Q1
Q2
Mux
Func tion
o f 4
Variab les
GG
Mux
Mux
AA
BB
CC
DD
EE
Q1
Q2
Mux
Two arbitrary functions of four variables
56 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Function generator
Func tion
o f 4
Variab lesEE
Mux
Mux
AA
BB
CC
DD
Q1
Q2
Func tion
o f 4
Variab les
Mux
Mux
AA
BB
CC
DD
Q1
Q2
Mux
FF
GG
Certain limited functions of 6 variables
57 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
PARITY5 CLB cost example
Determine whether the number of 1s is even or odd
F = A � B � C � D � EImplement using 1 CLB
58 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
2-bit comparator CLB cost example
A B = C D or A B > C D
GT = A C + A B D + B C D
EQ = A B C D + A B C D + A B C D + A B C D
Only 1 CLB required
59 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Majority CLB cost example
High whenever dn/2e outputs are high
CLB
5− input Majority Circuit
CLB
CLB
CLB
7− input Majority Circuit
60 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Large parity CLB cost example
2 levels allow up to 25 inputs
CLB
CLB
9 Input Parity Log ic
61 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
4-bit adder CLB cost example
Full adder, 4 CLB delays to final carry out (CO), 4 CLBs
CLB
A0 B0 Cin
S 0
CLB
A1 B1
S 1
CLB
A2 B2
C1S 2
CLB
A3 B3
C2S 3 C0Cout
62 Robert Dick Advanced Digital Logic Design
-
Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
4-bit adder CLB cost example
Composition from 2 2-bit adders give 2 CLB delay, 6 CLB cost
S 0
S 1
C2
A1 B1 CinA0 B0
CLBS 2
S 3
Cout
A3 B3 A2 B2
CLB
63 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx interconnect
Short direct connections
Global long lines
Horizontal/vertical long lines
Switching matrix connections
64 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx interconnect
Hierarchical routing organization
Some designs are constrained by routing resources
Can use logic CLBs to control routing
Substantial communication power consumption
65 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Xilinx interconnect
Interconnect
Direct Connections
Globa l Long Line
Horizonta l/Vertica l
Long Lines
Sw itch ing Matrix
Connections
XX
YY
CLB3
AA
DD
DIBBCC
KK
EE RR
CE
XX
YY
CLB1
AA
DD
DIBBCC
KK
EE RR
CEXX
YY
CLB0
AA
DD
DIBBCC
KK
EE RR
CE
Direc t
Connec tions
Horizonta l
Long Line
Vertica l
Long LinesGloba l
Long Line
Switch ing
Matrix
Horizonta l
Long Line
XX
YY
CLB2
AA
DD
DIBBCC
KK
EE RR
CE
66 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Example Xilinx parts
Parameter XC4024 XC3195 XC2018
Number of FFs 2,560 1,320 174Number of IOs 256 176 74Number of logic inputs per CLB 9 5 4Function generators per CLB 3 2 2Fast carry logic yes no noNumber of logic outputs per CLB 4 2 2RAM bits 32,768 0 0
67 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Dynamic reconfiguration
Serial configuration slow
Parallelize
Full reconfiguration slow
Partial reconfiguration
Reconfiguration slow
Use configuration cache
68 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
FPGA application examples
Prototyping
Constant coefficient multiplication
Direct HW implementation of problem instance, e.g.,
3SATDesign rule checking (DRC)
69 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Prototype designs
Discrete packages
SlowError-prone
Custom layout requires circuit fabrication
SlowExpensive for small runsCan’t be changed
70 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Programmable devices in prototyping
Multiplexers (MUXs) and demultiplexers (DMUXs)
Wiring them up is tedious and error-prone
Programmable array logic (PAL) and programmable logic array(PLA)
Fuses blown, write-once
Generic array logic (GAL)
Electrically reprogrammable
71 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Programmable devices in prototyping
Programmable read-only memories (PROMs)
Inefficient for implementing random logicWrite-once
Erasable programmable read-only memories (EPROMs)
Can be erasedErasure slow (UV)Expensive package window
72 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Programmable devices in prototyping
Electrically erasable programmable read-only memories(EEPROMs)
Erasure fastPackaging less expensivePotential for in-circuit erasure
Field-programmable gate arrays (FPGAs) are ideal
If market size small, ship FPGAs
In-circuit programming practical
73 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Section outline
1. Implementation technologiesReview of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
74 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
DeMorgan’s Law for CMOS
(A + B) = A B
(AB) = A + B
A + B = A B
AB = A + B
75 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
DeMorgan’s Law for CMOS
OR is the same as NAND with complemented inputs
AND is the same as NOR with complemented inputs
NAND is the same as OR with complemented inputs
NOR is the same as AND with complemented inputs
76 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
DeMorgan’s Law for OR/NAND
A A B B A + B (A B ) A + B (AB)
0 1 0 1 0 0 1 10 1 1 0 1 1 1 11 0 0 1 1 1 1 11 0 1 0 1 1 0 0
77 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
DeMorgan’s Law for AND/NOR
A A B B A B (A + B ) A B (A + B)
0 1 0 1 0 0 1 10 1 1 0 0 0 0 01 0 0 1 0 0 0 01 0 1 0 1 1 0 0
78 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
AND/OR → NAND/NOR
A
B
C
D
79 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
AND/OR → NAND/NOR
A
B
C
D
A
B
C
D
AND
AND
OR
80 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
AND/OR → NAND/NOR
A
B
C
D
AND
AND
OR
A
B
C
D
NAND
NAND
NAND
81 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
AND/OR → NAND/NOR
A
B
C
D
NAND
NAND
NAND
A
B
C
D
NAND
NAND
NAND
82 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
AND/OR/NOT network to NAND/NOR
=
=
=
=
83 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Outline
1. Implementation technologies
2. Homework
84 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Homework
Review for midterm exam on Thursday
Will post solutions to homework tonight
Responsible for all reading, assignments, labs
85 Robert Dick Advanced Digital Logic Design
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Implementation technologiesHomework
Review
Two-level transformations and minimization
Multi-level minimization
Design with various implementation technologies
86 Robert Dick Advanced Digital Logic Design
Implementation technologiesReview of MUX compositionSteering logicROMsFPGAsTransformations for CMOS
Homework
