Advanced Digital Logic Design – EECS...
Transcript of Advanced Digital Logic Design – EECS...
Advanced Digital Logic Design – EECS 303
http://ziyang.eecs.northwestern.edu/eecs303/
Teacher: Robert DickOffice: L477 TechEmail: [email protected]: 847–467–2298
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Outline
1. Sequential elements
2. Finite state machine design
3. Homework
2 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Section outline
1. Sequential elementsIntroductionReset/set latchesClocking conventionsD flip-flop
3 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Flip-flop introduction
Stores, and outputs, a value
Puts a special clock signal in charge of timing
Allows output to change in response to clock transition
Timing and sequential circuits
4 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Introduction to sequential elements
Feedback and memory
Memory
Latches
5 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Feedback and memory
Feedback is the root of memory
Can compose a simple loop from NOT gates
However, there is no way to switch the value
6 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Feedback and memory
Feedback is the root of memory
Can compose a simple loop from NOT gates
However, there is no way to switch the value
6 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
TG and NOT-based memory
Can break feedback path to load new value
However, potential for timing problems
7 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Section outline
1. Sequential elementsIntroductionReset/set latchesClocking conventionsD flip-flop
8 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Reset/set latch
R
R
S
S
Q
Q
Q
9 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Reset/set timing
100
Reset Hold Set Reset Set Race
R
S
Q
Q
Unstable state Unstable state
10 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
RS latch state diagram
01
0010
0001
1111
10
10 01
11
1001
00
output=Q Qinput=R S
11 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Clocking terms
Input
Clock
T su
T h
Clock – Rising edge, falling edge, high level, low level, period
Setup time: Minimum time before clocking event by which inputmust be stable (TSU)
Hold time: Minimum time after clocking event for which inputmust remain stable (TH)
Window: From setup time to hold time
12 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Gated RS latch
S
ENB
R
Q
Q
13 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Gated RS latch
S
R
ENB
Q
Q
14 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Memory element properties
Type Inputs sampled Outputs validUnclocked latch Always LFTLevel-sensitive latch Clock high LFT
(TSU to TH) around falling clock edgeEdge-triggered flip-flop Clock low-to-high transition Delay from rising edge
(TSU to TH) around rising clock edge
15 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Section outline
1. Sequential elementsIntroductionReset/set latchesClocking conventionsD flip-flop
16 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Clocking conventions
D Q
CLK
D
Active−high transparent
Q
CLK
Active−low transparent
Negative (falling) edge
D Q
CLKCLK
D Q
Positive (rising) edge
17 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Timing for edge and level-sensitive latches
D
Clk
Q edge
Q level
18 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Latch timing specifications
Minimum clock width, TW
Usually period / 2
Low to high propegation delay, PLH
High to low propegation delay, PHL
Worst-case and typical
19 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Latch timing specifications
Example, negative (falling) edge-triggered flip-flop timing diagram
T su
20 ns
T h
5 ns
T su
20 ns
T h
5 ns
T w
20 ns
T plh
C » Q 27 ns 15 ns
T phl
C » Q 25 ns 14 ns
T plh
D » Q 27 ns 15 ns
T phl
D » Q 16 ns 7 ns
D
Clk
Q
20 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
FF timing specifications
Minimum clock width, TW
Usually period / 2
Low to high propagation delay, PLH
High to low propagation delay, PHL
21 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
FF timing specifications
Example, positive (rising) edge-triggered flip-flop timing diagram
D
Clk
Q
T su
20 ns
T h
5 ns
T w
25 ns
T plh
25 ns 13 ns
T su
20 ns
T h
5 ns
T phl
40 ns 25 ns
22 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
RS latch states
S R Q+ Q + Notes
0 0 Q Q0 1 0 11 0 1 01 1 1 1 unstable
23 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
JK latch
R−S
latch
Use output feedback to ensure that RS 6= 11Q+ = Q K + Q J
24 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
JK latch
J K Q Q+
0 0 0 0hold
0 0 1 1
0 1 0 0reset
0 1 1 0
1 0 0 1set
1 0 1 1
1 1 0 1toggle
1 1 1 0
25 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
JK race
100 Set Reset Toggle
Race Condition
26 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Section outline
1. Sequential elementsIntroductionReset/set latchesClocking conventionsD flip-flop
27 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Falling edge-triggered D flip-flop
Use two stages of latches
When clock is high
First stage samples input w.o. changing second stageSecond stage holds value
When clock goes low
First stage holds value and sets or resets second stageSecond stage transmits first stage
Q+ = D
One of the most commonly used flip-flops
28 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Falling edge-triggered D flip-flop
DD
lk=
RR
SS
00
00
DD
DDDD
=1
DD
C
Clock high
29 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Falling edge-triggered D flip-flop
Holds D when
clock goes low
Holds D when
clock goes low
Q
Q
DD
Clk=1
RR
SS
00
00
DD
DDDD
=
DD
Clock switchingInputs sampled on falling edge, outputs change after falling edge
30 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Falling edge-triggered D flip-flop
?
Clk=
RR
SS
D
0
DDDD
=
RR
SS
DD
0
D
Clock low
31 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Edge triggered timing
Positive edge−
t riggered FF
Negative edge−
t riggered FF
100
32 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
RS clocked latch
Storage element in narrow width clocked systems
Dangerous
Fundamental building block of many flip-flop types
33 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
JK flip-flop
Versatile building block
Building block for D and T flip-flops
Has two inputs resulting in increased wiring complexity
Don’t use master/slave JK flip-flops
Ones or zeros catching
Edge-triggered varieties exist
34 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
D flip-flop
Minimizes input wiring
Simple to use
Common choice for basic memory elements in sequential circuits
35 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Toggle (T) flip-flops
State changes each clock tick
Useful for building counters
Can be implemented with other flip-flops
JK with inputs highD with XOR feedback
36 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Asynchronous inputs
How can a circuit with numerous distributed edge-triggeredflip-flops be put into a known state
Could devise some sequence of input events to bring the machineinto a known state
ComplicatedSlowNot necessarily possible, given trap states
Can also use sequential elements with additional asynchronousreset and/or set inputs
37 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Latch and flip-flop equations
RS
Q+ = S + R Q
D
Q+ = D
38 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
IntroductionReset/set latchesClocking conventionsD flip-flop
Latch and flip-flop equations
JK
Q+ = J Q + K Q
T
Q+ = T ⊕ Q
39 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Outline
1. Sequential elements
2. Finite state machine design
3. Homework
40 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Section outline
2. Finite state machine designRegular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
41 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Sequential FSM design example
We’ll walk through the design of an example finite state machine(FSM)
Some of the stages will be covered in more detail in later lectures
I want you to have a high-level understanding of our overall goalbefore covering every detail of FSM synthesis
42 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Regular expressions
Naturally express control
However, no simple direct HW implementation
We want to get to sequential logic
Need to go though other stages first
43 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Regular expressions
Can be expressed with regular expressions, examples
Accept the empty string, ε
Accept nothing, ∅Accept 0 or 11, (0 + 11)
Accept anything starting with 1 and one or more 0 and endingwith 0 or 10, 10+(0 + 10)
Accept anything starting with zero or more 0010 or 1 and endingwith 1, (0010 + 1)∗1
44 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Section outline
2. Finite state machine designRegular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
45 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Nondeterministic finite state automata (NFA)
State graph
Multiple states can be active at the same time
Some states Accept
The automata accepts if any accepting states are active
46 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
0
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
0 1
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
0 1
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
0 1 1
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
0 1 1 1
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
NFA
a
b c d e
hgf
i j k
0 1 1 1
ε
ε
1
0
0
1
ε
ε
1ε
ε
1 1
(101+01+ ε)(11)+
47 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Section outline
2. Finite state machine designRegular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
48 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Deterministic finite state automata (DFA)
NFAs require multiple states to be simultaneously active
Can’t represent this with conventional logic state variables
Need to convert to deterministic representation
49 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
a
b
f
i
abfi
ε
ε
ε
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
a
b
f
c
ji
cj
abfi
ε
ε
1
1
ε
1
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
d
a
b
f
c d
ji
cj
abfi
0
ε
ε
1 0
1
ε
1
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
d
a
b
f
c d
j
ei
i
e
cj
abfi
0
ε
ε
1 0
1
1
ε
ε1
1
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
d
j
a
b
f
c d
j
ei
i
e
cj
abfi
0 1
ε
ε
1 0
1
1
ε
ε1
1
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
d
j
a
b
f
c d
j
ei
i k
e
kicj
abfi
0 1
ε
ε
1 0
1
1
ε
1
ε
ε1
1
1
11
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
d
j
a
b
f
c d
j
ei
i
g
k
e
kicj
abfi
g
0 1
ε
ε
1 0
1
1
ε
0
1
ε
ε1
1
1
11
0
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
d
j
a
b
f
c d
j
ei
i
g
k
e
h
ki
hi
cj
abfi
g
0 1
ε
ε
1 0
1
1
ε
0
1
ε
ε1
1ε
1
1
1
1
1
0
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA
d
j
a
b
f
c d
j
ei
i
g
k
e
h
ki
hi
cj
abfi
g
0 1
ε
ε
1 0
1
1
1
ε
0
1
ε
ε1
1ε
1
1
1
1
1
0
(101+01+ ε)(11)+
50 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA to more explicit FSM
d
kicj
abfi
g hi
j
ei
11
01
1
1
1
1
10
(101+01+ ε)(11)+
51 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA to more explicit FSM
z d
kicj
abfi
g hi
j
ei
11
01
1
1
1
1
10
(101+01+ ε)(11)+
51 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA to more explicit FSM
z d
kicj
abfi
g hi
j
ei
10
11
01
1
1
1
1
10
(101+01+ ε)(11)+
51 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA to more explicit FSM
z d
kicj
abfi
g hi
j
ei
0
0
0
0
0
0
10
11
01
1
1
1
1
10
(101+01+ ε)(11)+
51 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Section outline
2. Finite state machine designRegular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
52 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
DFA to FSM
DFA may only accept or reject
Simple to convert Moore FSM
Add explicit output values to states
53 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Moore block diagram
combinational logic
sequential elements
combinational logic
feedback
inputs
outputs
54 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Mealy block diagram
combinational logic
sequential elements
outputs
inputs
feedback
55 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Moore FSMs
0
0
1
1
1
00 1
D/1
A/0 B/0
C/0
56 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Section outline
2. Finite state machine designRegular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
57 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Introduction to state reduction
s+
s 0 1 Q
A A B 0B C B 0C A B 0D A A 1
58 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Introduction to state reduction
s+
s 0 1 Q
A A B 0B C B 0C A B 0D A A 1
58 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Introduction to state reduction
s+
s 0 1 q
AC AC B 0B AC B 0D AC AC 1
59 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Introduction to state reduction
s+
s 0 1 q
AC AC B 0B AC B 0D AC AC 1
59 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Introduction to state reduction
s+
s 0 1 q
AC AC B 0B AC B 0D AC AC 1
59 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State assignment
s+
s 0 1 q
ABC ABC ABC 0D ABC ABC 1
Only two adjacent states, state assignment is trivialHowever, good to consider output, q
60 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State assignment
s+
s 0 1 q
ABC ABC ABC 0D ABC ABC 1
Only two adjacent states, state assignment is trivial
However, good to consider output, q
60 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State assignment
s+
s 0 1 q
ABC ABC ABC 0D ABC ABC 1
Only two adjacent states, state assignment is trivialHowever, good to consider output, q
60 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State variable functions
s+
s 0 1 q
0 0 0 01 0 0 1
s+(s) = 0q(s) = s
61 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State variable functions
s+
s 0 1 q
0 0 0 01 0 0 1
s+(s) = 0
q(s) = s
61 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State variable functions
s+
s 0 1 q
0 0 0 01 0 0 1
s+(s) = 0q(s) = s
61 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Mealy FSMs
1/X
1/0
0/0
0/0
0/1
1/0
1/1
0/1
CD
BA
62 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Mealy tabular form
s+/qs 0 1
A D/0 B/XB C/1 B/0C A/0 B/1D C/1 C/0
63 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
Mealy to Moore conversion
1
0
1
1
00
1
1
0
0
0
01
1
1/X
1/0
0/0
0/0
0/1
1/0
0/1
1/1
A/0
C/1
B/X
D/0
B/0
B/1
C/0
BA
D C
64 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State variable combinational synthesis
q plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
Separate sequential and combinational portions of circuit
Conduct standard logic synthesis
65 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State variable combinational synthesis
q plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
Separate sequential and combinational portions of circuit
Conduct standard logic synthesis
65 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
State variable combinational synthesis
q plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
q
clock
plain old combinational logic
D flip−flops
Separate sequential and combinational portions of circuit
Conduct standard logic synthesis
65 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Regular expressionsNondeterministic finite state automataDeterministic finite state automataFinite state machinesState equations and minimization
FSM design summary
Specify requirements in natural form – regular expression or NFA
Converting from NFA to DFA is straightforward
Converting from DFA to FSM is straightforward
Minimize the number of states using compatible states, classsets, and binate covering
Assign values to states to minimize logic complexity
Allow only adjacent or path transitions for asynchronousmachines
Optimize implementation of state and output functions
66 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Outline
1. Sequential elements
2. Finite state machine design
3. Homework
67 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Recommended reading
M. Morris Mano and Charles R. Kime. Logic and ComputerDesign Fundamentals. Prentice-Hall, NJ, third edition, 2004
Chapter 7
Chapter 6
68 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Video controller repair lab
Design a finite state machine based on an English problemspecification
The design problem isn’t very difficult
Going from a real-world problem to a formal representation maybe difficult
Be careful not to use too many state variables!!!
Could easily turn it from a 6–hour lab to a 12–hour lab
69 Robert Dick Advanced Digital Logic Design
Sequential elementsFinite state machine design
Homework
Next lecture
More detail and examples on FSM design and optimization
70 Robert Dick Advanced Digital Logic Design